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TEXAS INSTRUMENTS TAS5112 handbook

1. vs FREQUENCY 1 RL 6Q TC 75 C Po 50 W 0 1 Po 10 W Po 1W 0 01 0 001 20 100 1k 10k 20k f Frequency Hz Figure 1 TOTAL HARMONIC DISTORTION NOISE VS OUTPUT POWER 10 RL 6Q Tc 75 C 1 0 1 0 01 100m 1 10 Po Output Power W Figure 3 100 Noise Amplitude dBr Po Output Power W TEXAS INSTRUMENTS www ti com NOISE AMPLITUDE VS FREQUENCY RL 6 2 FFT 60 dB Tc 75 C TAS5026 Front End Device 0 2 4 6 8 10 12 14 16 18 20 22 f Frequency kHz Figure 2 OUTPUT POWER VS H BRIDGE VOLTAGE 0 4 8 12 16 20 24 28 32 VDD Supply Voltage V Figure 4 3 TEXAS Po Output Power W INSTRUMENTS www ti com TAS511 2 SLES048C JULY 2003 REVISED MARCH 2004 SYSTEM OUTPUT STAGE EFFICIENCY POWER LOSS vs vs OUTPUT POWER OUTPUT POWER 100 11 90 10 L f 1k
2. THD NOISE vs OUTPUT POWER THD NOISE vs FREQUENCY 1 1 a RL 69 a RL 69 Tc 75 C d Tc 75 C o o E Po 50 W 5 5 E 0 1 2 2 E 2 a a Po 10W o 2 01 t E E I 001 8 8 e e 1 1 z z Q Q I SS m m 0 01 0 001 100m 1 10 100 20 100 1k 10k 20k Po Output Power W f Frequency Hz Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments A semiconductor products and disclaimers thereto appears at the end of this data sheet PurePath Digital and PowerPAD are trademarks of Texas Instruments Other trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products Copyright 2004 Texas Instruments Incorporated conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters 3 TEXAS INSTRUMENTS TAS511 2 www ti com SLES048C JULY 2003 REVISED MARCH 2004 A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam during Ae GENERAL INFORMATION Terminal Assignment The TAS5112 is offered in a thermally enhanced 56 pin TSSOP DFD thermal pad is on the top
3. ing Plane AO 0 10 PINS 4073260 B 08 03 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions include mold flash or protrusion D The package thermal performance may be enhanced by attaching an external heatsink to the thermal pad This pad is electrically and thermally connected to the backside of the die and possibly selected leads E Falls within JEDEC MO 153 PowerPAD is a trademark of Texas Instruments 17 MECHANICAL DATA DFD R PDSO G PowerPAD PLASTIC SMALL OUTLINE PACKAGE DIE DOWN 48 PIN SHOWN ing Plane Thermal Pad See Note D a 0 10 PINS NOTES All linear dimensions are in millimeters This drawing is subject to change without notice A B C Body dimensions include mold flash or pro
4. 3 TEXAS DES TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 Terminal Functions iia FUNCTION 1 DESCRIPTION NAME NO BST A 31 P High side bootstrap supply BST external capacitor to OUT A required BST B 42 P High side bootstrap supply BST external capacitor to OUT B required BST C 43 P HS bootstrap supply BST external capacitor to OUT C required BST D 54 P HS bootstrap supply BST external capacitor to OUT D required DGND 23 P Digital I O reference ground DREG 16 P Digital supply voltage regulator decoupling pin capacitor connected to GND DREG RTN 12 P Digital supply voltage regulator decoupling return pin DVDD 25 P I O reference supply input 3 3 V GND 1 2 22 24 P Power ground 27 28 29 36 37 48 49 56 GREG 3 26 P Gate drive voltage regulator decoupling pin capacitor to REG GND GVDD 30 55 P Voltage supply to on chip gate drive and digital supply voltage regulators M1 TSTO 15 Mode selection pin M2 14 l Mode selection pin M3 13 Mode selection pin OTW 4 O Overtemperature warning output open drain with internal pullup resistor OUT_A 34 35 O Output half bridge A OUT_B 38 39 O Output half bridge B OUT_C 46 47 O Output half bridge C OUT_D 50 51 O Output half bridge D PVDD_A 32 33 P Power supply input for half bridge A PVDD_B 40 41 P Power supply input for half bridge B PVDD_C 44 45 P Powe
5. TAS5112DFD Ww TEXAS C9 NSTRUMENTS e TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 DIGITAL AMPLIFIER POWER STAGE IGITAL FEATURES APPLICATIONS 50 W per Channel BTL Into 6 Q Stereo DVD Receiver 95 dB Dynamic Range With TAS5026 EE Less Than 0 1 THD N 1 W RMS Into 6 Q 9 Cto Component ystems Less Than 0 2 THD N 50 W RMS into 6 Q PESCE TON ER EEN The TAS5112 is a high performance integrated stereo Self Protecting Design Undervoltage digital amplifier power stage designed to drive 6 Q Overtemperature and Short Conditions With speakers at up to 50W per channel The device Error Reporting incorporates Tl s PurePath Digital technology and is Internal Gate Drive Supply Voltage Regulator used with a digital audio PWM processor TAS50XX and EMI Compliant When Used With a simple passive demodulation filter to deliver high quality Recommended System Design high efficiency true digital audio amplification The efficiency of this digital amplifier is typically 90 reducing the size of both the power supplies and heatsinks needed Overcurrent protection overtemperature protection and undervoltage protection are built into the TAS5112 safeguarding the device and speakers against fault conditions that could damage the system
6. SD forced high 1 Normal operation 1 SD is pulled high when RESET is asserted low independent of chip state i e protection mode This is desirable to maintain compatibility with some TI PWM front ends Temperature Warning Pin OTW The OTW pin gives a temperature warning signal when temperature exceeds the set limit The pin is of the open drain type with an internal pullup resistor to DVDD Ow esmenm Junction temperature higher than 125 C Junction temperature lower than 125 C Overall Reporting The SD pin together with the OTW pin gives chip state information as described in Table 1 Table 1 Error Signal Decoding Overtemperature error OTE Overtemperature warning OTW a o Overcurrent OC or undervoltage UVP error Normal operation no errors warnings Chip Protection The TAS5112 protection function is implemented in a closed loop with for example a system controller and TI PWM processor The TAS5112 contains three individual systems protecting the device against error conditions All of the error events covered result in the output stage being set in a high impedance state Hi Z for maximum protection of the device and connected equipment 12 TEXAS INSTRUMENTS www ti com The device can be recovered by toggling RESET low and then high after all errors are cleared Overcurrent OC Protection The device has individual forward current protection on both hig
7. The output configuration mode is selected by shorting the M3 pin to DREG or DGND according to Table 3 TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 Table 3 Output Mode Selection M3 OUTPUT MODE o Bridge tied load output stage BTL APPLICATION INFORMATION DEMODULATION FILTER DESIGN The PurePath Digital amplifier outputs are driven by heavy duty DMOS transistors in an H bridge configuration These transistors are either off or fully on which reduces the DMOS transistor on state resistance R DMOSon and the power dissipated in the device thereby increasing efficiency The result is a square wave output signal with a duty cycle that is proportional to the amplitude of the audio signal It is recommended that a second order LC filter be used to recover the audio signal For this application EMI is considered important therefore the selected filter is the full output type shown in Figure 11 TAS51xx Output A utpu YYY e e R cia Load rL 9 V c2 C1B Output B L Figure 11 Demodulation Filter The main purpose of the output filter is to attenuate the high frequency switching component of the PurePath Digital amplifier while preserving the signals in the audio band Design of the demodulation filter affects the performance of the power amplifier significantly As a result to ensure proper operation of the overcurrent OC protection circuit and
8. fully charge the BST capacitor Within this time RESET must be kept low After approximately 1 ms the back end bootstrap capacitor is charged RESET can now be released if the modulator is powered up and streaming valid PWM signals to the back end PWM xP Valid means a switching PWM signal which complies with the frequency and duty cycle ranges stated in the Recommended Operating Conditions A constant HIGH dc level on the PWM xP is not permitted because it would force the high side MOSFET ON until it eventually ran out of BST capacitor energy and might damage the device An unknown state of the PWM output signals from the modulator is illegal and should be avoided which in practice means that the PWM processor must be powered up and initialized before RESET is de asserted HIGH to the back end POWERING DOWN For power down of the back end an opposite approach is necessary The RESET must be asserted LOW before the valid PWM signal is removed When PWM processors are used with TI PurePath Digital amplifiers the correct timing control of RESET and PWM xP is performed by the modulator PRECAUTION The TAS5112 must always start up in the high impedance Hi Z state In this state the bootstrap BST capacitor is precharged by a resistor on each PWM output node to ground See the system configuration This ensures that the back end is ready for receiving PWM pulses indicating either HIGH or LOW side turnon after RESET
9. is de asserted to the back end With the following pulldown resistor and BST capacitor size the charge time is C 233nF R2 47 KQ RxCx5 775 5 us After GVDD has been applied it takes approximately 800 us to fully charge the BST capacitor During this time RESET must be kept low After approximately 1 ms the back end BST is charged and ready RESET can now be released if the PWM modulator is ready and is streaming valid PWM signals to the back end Valid PWM signals are switching PWM signals with a frequency between 350 400 kHz A constant HIGH level on the PWM would force the high side MOSFET ON until it eventually ran out of BST capacitor energy Putting the device in this condition should be avoided 11 TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 In practice this means that the DVDD to PWM processor front end should be stable and initialization should be completed before RESET is de asserted to the back end CONTROL UO Shutdown Pin SD The SD pin functions as an output pin and is intended for protection mode signaling to for example a controller or other front end device The pin is open drain with an internal pullup resistor to DVDD The logic output is as shown in the following table a combination of the device state and RESET input DESCRIPTION 8b RESET fo o 1 Device in protection mode i e UVP and or OC and or OT error 0 o Pa A Device set high impedance Hi Z
10. 6 Q 8X fs 384 kHz unless otherwise noted TYPICAL OVER TEMPERATURE SYMBOL PARAMETER TEST CONDITIONS Tcase Ta 40 C MIN TYP Ta 25 C age UNITS MAx INPUT OUTPUT PROTECTION Set the DUT in normal operation mode with all the protections enabled Sweep GVDD up and down Monitor SD output Record the GREG reading when SD is triggered OTW Overtemperature warning 125 C Typ junction temperature Overtemperature error junction temperature OC Overcurrent protection OC Overcurrent protection See Notet See Notet 1 STATIC DIGITAL SPECIFICATION PWM AP PWM BP M1 M2 M3 SD OTW V Undervoltage protection uvp G limit GVDD VIH High level input voltage VIL Low level input voltage 0 8 V Max 10 Leakage Input leakage current 1 m Lo m ve OTW SHUTDOWN SD Internally pull up R from OTW SD to DVDD Low level output VoL Low level output voltage Ilo 4mA ssid 4 mA UE T optimize device performance and prevent overcurrent OC protection tripping the demodulation filter must be EEA with SE care atte Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors for optimal performance It is also important to consider PCB design and layout for optimum performance of the TAS5112 It is recommended to follow the TAS5112F2EVM S N 112 design and layout guidelines for best performance x TEXAS N
11. ECOMMENDED OPERATING CONDITIONS MA UNIT DVDD Digital supply 1 Relative to DGND 3 3 3 6 a Supply for internal gate drive and logic GVDD PPPI g Relative to GND 16 295 30 5 regulators PVDD Hatroridgssuppy Roae w GND Areosa 0 95 308 V Ee 1 j It is recommended for DVDD to be connected to DREG via a 100 Q resistor ELECTRICAL CHARACTERISTICS PVDD X 29 5 V GVDD 29 5 V DVDD connected to DREG via a 100 Q resistor T 6 Q 8X fg 384 kHz unless otherwise noted TYPICAL OVER TEMPERATURE SYMBOL PARAMETER TEST CONDITIONS ST Tan40 Ta 25 C pes EE Ea Bd UNITS n AC PERFORMANCE BTL Mode 1 kHz RL 8 Q THD 0 2 RL 8 Q THD 10 AES17 Output power RL 6 Q THD 0 2 m S AES17 filter 1 kHz yp RL 2 6 Q THD 10 AES17 filter 1 kHz Po 1 W channel RL 6 Q AES17 filter Total harmonic distortion Po 10 W channel RL 6 Q noise AES17 filter THD N f 1 kHz A weighted AES17 filter lo 1 mA PVDD 18 V 30 5 V lo 1 2 mA PVDD 18 V 30 5 V GVDD supply current fs 384 kHz no load 50 IVGDD operating duty cycle operating OUTPUT STAGE MOSFETs Forward on resistance Ron LS low side Ty 25 C IE Forward on resistance Ron HS high side Ty 25 C sl Voltage regulator 3 TEXAS TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS PVDD_x 29 5 V GVDD 29 5 V DVDD connected to DREG via a 100 Q resistor iB
12. Hz E RL 6Q2 E 80 Hr Tc 75 C o c 2 70 E 1 7 VG 6o 3 S 4 6 50 o 5 p 5 2 a 5 40 o 5 4 E 30 3 2 10 1 0 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Po Output Power W Po Output Power W Figure 5 Figure 6 OUTPUT POWER AMPLITUDE VS VS CASE TEMPERATURE FREQUENCY 3 0 2 5 2 0 1 5 a RL 69 0 5 E 0 0 amp 0 5 E 1 0 RL 80 1 5 S 2 0 2 5 3 0 0 20 40 60 80 100 120 140 10 100 1k 10k 50k Tc Case Temperature C f Frequency Hz Figure 7 Figure 8 TEXAS TAS5112 NSTRUMENTS SLES048C JULY 2003 REVISED MARCH 2004 ON STATE RESISTANCE VS JUNCTION TEMPERATURE 200 190 180 170 160 150 140 ron On State Resistance mQ 130 120 0 10 20 30 40 50 60 70 80 90 100 Ty Junction Temperature C Figure 9 d TEXAS INSTRUMENTS www ti com THEORY OF OPERATION POWER SUPPLIES The power device only requires two supply voltages GVDD and PVDD_X GVDD is the gate drive supply for the device regulated internally down to approximately 12 V and decoupled with regards to board GND on the GREG pins through an external capacitor GREG powers both the low side and high side via a bootstrap step up conversion The bootstrap supply is charged after the first low side turn on pulse Internal digital core voltage DREG is also derived from GVDD and regulated down by internal circuit
13. It is assumed that the thermal grease is 0 002 inch thick and that it is similar in performance to Wakefield Type 126 thermal grease It is important that the thermal grease layer is lt 0 002 inches thick and that thermal pads or tape are not used in the pad to heatsink interface due to the high power density that results in these extreme power cases Table 4 Case 1 2 x 50 W Unclipped Into 6 Both Channels in Same IC 1 Power to load per channel 50 W unclipped Power dissipation 10 2 C note 2 x channel dissipation Ss Geer EE 1 This case represents a stereo system with only one package See Case 2 and Case 2A if doing a full power 2 channel test in a multichannelsystem Delta T inside package Table 5 Case 2 2 x 50 W Unclipped Into 6 Channels in Separate Packages 1 WEE Ambient temperature 25 C System RgJA 19 C W 1 In this case the power is separated into two packages Note that this allows a considerably smaller heatsink because twice as much area is available for heat transfer through the thermal grease For this reason separating the stereo channels into two ICs is recommended in full power stereo tests made on multichannel systems Power to load per channel Power dissipation Delta T inside package Delta T through thermal grease Required heatsink thermal resistance Junction temperature TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 Table 6 Case 2A 2 x 60 W Unclip
14. S TAS5000 Digital Audio PWM Processor data manual TI SLAS270 True Digital Audio Amplifier TAS5001 Digital Audio PWM Processor data sheet TI SLESO009 True Digital Audio Amplifier TAS5010 Digital Audio PWM Processor data sheet TI SLAS328 True Digital Audio Amplifier TAS5012 Digital Audio PWM Processor data sheet TI SLESO06 TAS5026 Six Channel Digital Audio PWM Processor data manual TI SLES041 TAS5036A Six Channel Digital Audio PWM Processor data manual TI SLES061 TAS3103 Digital Audio Processor With 3D Effects data manual TI SLES038 Digital Audio Measurements application report T SLAA114 PowerPAD Thermally Enhanced Package technical brief TI SLMAO02 System Design Considerations for True Digital Audio Power Amplifiers application report Tl SLAA117 3 TEXAS INS S E TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 MECHANICAL DATA DFD R PDSO G PowerPAD PLASTIC SMALL OUTLINE PACKAGE DIE DOWN 48 PIN SHOWN Thermal Pad See Note D
15. STRUMENTS TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 SYSTEM CONFIGURATION USED FOR CHARACTERIZATION Gate Drive Power Supply External Power Supply H Bridge Power Supply TAS5112DFD GND 1 uF GVDD BST_D 100 nF PVDD_D LPCB LYYY PVDD_D 100 nF ERR RCVY OUT D FA PWM AP 1 OUT D 10 uH PWM AM 1 o GND 470 nF VALID 1 GND OUT C TU MH ENNYN OUT_C 100 nF PVDD_C 100 nF nj e Y Y Y e o PWM PROCESSOR PVDD_C LPCB ica TAS5026 BST C 1000uF BST B PVDD B LPCB FA PWM_AP 2 PVDD_B 100 nF PWM AM 2 e H OUT B Ze VALID 2 OUT B 10 uH GND 470 nF GND 100 Q OUT_A 10 uH Z Tog nr ndi 100 nF PVDD_A ES Y YYv e PVDD A L PCB BST_A 1000 uF 1 uF m GVDD gt GND 100 nF Lpcp TRACK IN THE PCB 1 0 mm wide and 50 mm long Tvottage Suppressor Diode 1SMA33CAT TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE OF TAS5112 EVM WITH TAS5026 PWM PROCESSOR THD N Total Harmonic Distortion Noise 96 THD N Total Harmonic Distortion Noise TOTAL HARMONIC DISTORTION NOISE
16. autorecovery timing is set by counting PWM input cycles i e the timing is relative to the switching frequency The AR system is common to both half bridges 35 TEXAS INSTRUMENTS www ti com Timing and Function The function of the autorecovery circuit is as follows 1 An error event occurs and sets the protection latch output stage goes Hi Z 2 The counter is started 3 After n 2 cycles the protection latch is cleared but the output stage remains Hi Z identical to pulling RESET low 4 After n cycles operation is resumed identical to pulling RESET high n 512 Error Protection Latch Shutdown T Autorecovery cwm Ce 3 Figure 10 NN sec Latching Shutdown on All Errors PMODE1 In latching shutdown mode all error situations result in a power down output stage Hi Z Re enabling can be done by toggling the RESET pin All Protection Systems Disabled PMODE2 In PMODE2 all protection systems are disabled This mode is purely intended for testing and characterization purposes and thus not recommended for normal device operation MODE Pins Selection The protection mode is selected by shorting M1 M2 to DREG or DGND according to Table 2 Table 2 Protection Mode Selection Mi M2 PROTECTION MODE Lo o Autorecovery after errors PMODE 0 fo 1 Latching shutdown on all errors PMODE 1 1 0 All protection systems disabled PMODE 2
17. customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs
18. h side and low side power stage FETs The OC protection works only with the demodulation filter present at the output See Demodulation Filter Design in the Application Information section of the data sheet for design constraints Overtemperature OT Protection A dual temperature protection system asserts a warning signal when the device junction temperature exceeds 125 C The OT protection circuit is shared by all half bridges Undervoltage UV Protection Undervoltage lockout occurs when GVDD is insufficient for proper device operation The UV protection system protects the device under power up and power down situations The UV protection circuits are shared by all half bridges Reset Function The function of the reset input is twofold Reset is used for re enabling operation after a latching error event Reset is used for disabling output stage switching mute function The error latch is cleared on the falling edge of reset and normal operation is resumed when reset goes high PROTECTION MODE Autorecovery AR After Errors PMODEO In autorecovery mode PMODEO the TAS5112 is self supported in handling of error situations All protection systems are active setting the output stage in the high impedance state to protect the output stage and connected equipment However after a short time the device autorecovers i e operation is automatically resumed provided that the system is fully operational The
19. meet the device THD N specifications the selection of the inductors used in the output filter must be considered according to the following The rule is that the inductance should remain stable within the range of peak current seen at maximum output power and deliver at least 5 uH of inductance at 15 A If this rule is observed the TAS5112 does not have distortion issues due to the output inductors and overcurrent conditions do not occur due to inductor saturation in the output filter 13 TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 Another parameter to be considered is the idle current loss in the inductor This can be measured or specified as inductor dissipation D The target specification for dissipation is less than 0 05 In general 10 uH inductors suffice for most applications The frequency response of the amplifier is slightly altered by the change in output load resistance however unless tight control of frequency response is necessary better than 0 5 dB it is not necessary to deviate from 10 uH The graphs in Figure 12 display the inductance vs current characteristics of two inductors that are recommended for use with the TAS5112 INDUCTANCE VS CURRENT FB1310A L Inductance AH 0 5 10 15 Current A Figure 12 Inductance Saturation The selection of the capacitor that is placed across the output of each inductor C2 in Figure 11 is simple To complete the outp
20. ped Into 6 Channels in Separate IC Packages 1 Power to load per channel 60 W 1096 THD Power dissipation per channel 6 1 C note 2 x Delta T inside package channel dissipation OIN 350 EC NOC 1 In this case the power is also separated into two packages but overdriving causes clipping to 10 THD In this case the high power requires extreme care in attachment of the heatsink to ensure that the thermal grease layer is lt 0 002 inches thick Note that this power level should not be attempted with both channels in a single IC because of the high power density through the thermal grease layer A Thermal 8 20 mm Pad 7 20 mm Vv 3 90 mm NW 2 98 mm gt 15 TAS5112 SLESO48C JULY 2003 REVISED MARCH 2004 CLICK AND POP REDUCTION TI modulators feature a pop and click reduction system that controls the timing when switching starts and stops Going from nonswitching to switching operation causes a spectral energy burst to occur within the audio bandwidth which is heard in the speaker as an audible click for instance after having asserted RESET LH during a
21. r supply input for half bridge C PVDD_D 52 53 P Power supply input for half bridge D PWM_AM 20 l Input signal negative half bridge A PWM_AP 21 Input signal positive half bridge A PWM_BM 18 Input signal negative half bridge B PWM_BP 17 Input signal positive half bridge B PWM_CM 10 Input signal negative half bridge C PWM_CP 11 Input signal positive half bridge C PWM_DM 8 Input signal negative half bridge D PWM_DP 7 Input signal positive half bridge D RESET_AB 19 Reset signal active low RESET CD 9 l Reset signal active low SD_AB 6 O Shutdown signal for half bridges A and B active low SD_CD 5 O Shutdown signal for half bridges C and D active low 1 input O Output P Power d TEXAS INSTRUMENTS TAS511 2 www ti com SLES048C JULY 2003 REVISED MARCH 2004 FUNCTIONAL BLOCK DIAGRAM BST_A eREG gt PVDD A gd 4 Gate Drive H PWM_AP PWM Timing QUT A A Oo Receiver Control Gate Drive k GND ME RESET BST B oo cree gt gt PVDD_B Gate Drive PWM_BP PWM OUT_B Timing Receiver Control To Protection Blocks OT Protection UVP DREG_RTN DREG_RTN P3 This diagram shows one channel d TEXAS INSTRUMENTS TAS5112 www ti com SLES048C JULY 2003 REVISED MARCH 2004 R
22. ry to 3 3 V The gate driver regulator can be bypassed for reducing idle loss in the device by shorting GREG to GVDD and directly feeding in 12 0 V This can be useful in an application where thermal conduction of heat from the device is difficult PVDD X is the H bridge power supply pin Two power pins exists for each half bridge to handle the current density It is important that the circuitry recommendations around the PVDD X pins are followed carefully both topology and layout wise For topology recommendations see the Typical System Configuration section Following these recommendations is important for parameters like EMI reliability and performance POWERING UP RN i gt 1ms Se D NOTE PVDD should not be powered up before GVDD During power up when RESET is asserted LOW all MOSFETs are turned off and the two internal half bridges are in the high impedance state Hi Z The bootstrap capacitors supplying high side gate drive are not charged at this point To comply with the click and pop scheme and use of non TI modulators it is recommended to use a Akti pulldown resistor on each PWM output node to ground TAS5112 SLES048C JULY 2003 REVISED MARCH 2004 This precharges the bootstrap supply capacitors and discharges the output filter capacitor see the Typical TAS5112 Application Configuration section After GVDD has been applied it takes approximately 800 us to
23. shown as follows DFD PACKAGE TOP VIEW GND 1 GND GND 2 GVDD GREG 3 BST_D OTW 4 PVDD_D SD_CD 5 PVDD_D SD_AB 6 OUT_D PWM_DP 7 OUT_D PWM_DM 8 GND RESET_CD GND PWM_CM OUT_C PWM_CP OUT_C DREG_RTN PVDD C M3 PVDD C M2 BST C M1 BST B DREG PVDD B PWM BP PVDD B PWM BM OUT B RESET AB OUT B PWM AM GND PWM AP GND GND OUT A DGND OUT A GND PVDD A DVDD PVDD A GREG BST A GND GVDD GND GND storage or handling to prevent electrostatic damage to the MOS gates ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted 1 TAS5112 UNITS DVDD TO DGND 0 3 V to 4 2 V GVDD TO GND 33 5 V PVDD X TO GND dc voltage 33 5 V PVDD X TO GND spike voltage 2 OUT X TO GND dc voltage 33 5 V OUT X TO GND spike voltage 2 BST X TO GND dc voltage 48V BST X TO GND spike voltage 2 GREG TO GND 3 14 2 V id RESET M1 M2 M3 SD L03 V to DVDD 0 3 V Maximum operating junction 40 C to 150 C temperature Ty Storage temperature 40 C to 125 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to
24. system start up To make this system work properly the following design rules must be followed when using the TAS5112 back end Therelative timing between the PWM AP M x signals and their corresponding VALID x signal should not be skewed by inserting delays because this increases the audible amplitude level of the click The output stage must start switching from a fully discharged output filter capacitor Because the output stage prior to operation is in the high impedance state this is done by having a passive pulldown resistor on each speaker output to GND see Typical System Configuration Other things that can affect the audible click level The spectrum of the click seems to follow the speaker impedance vs frequency curve the higher the impedance the higher the click energy Crossover filters used between woofer and tweeter in a speaker can have high impedance in the audio band which should be avoided if possible Another way to look at it is that the speaker impulse response is a major contributor to how the click energy is shaped in the audio band and how audible the click will be The following mode transitions feature click and pop reduction sar mg Normal 1 Mute Yes Mute Normal Yes Normal 1 gt CEN Error recovery Normal 1 Yes Normal 1 Hard Reset Hard Reset Normal Yes 1 Normal switching 16 10 TEXAS INSTRUMENTS www ti com REFERENCE
25. ted from the exposed pad area and the thermal grease manufacturers area thermal resistance expressed in C in W The area thermal resistance of the example thermal grease with a 0 002 inch thick layer is about 0 1 C in2 W The approximate exposed pad area is as follows 56 pin HTSSOP 0 045 in Dividing the example thermal grease area resistance by the surface area gives the actual resistance through the thermal grease for both ICs inside the package 56 pin HTSSOP 2 27 C W The thermal resistance of thermal pads is generally considerably higher than a thin thermal grease layer Thermal tape has an even higher thermal resistance Neither pads nor tape should be used with either of these two packages A thin layer of thermal grease with careful clamping of the heatsink is recommended It may be difficult to achieve a layer 0 001 inch thick or less so the modeling below is done with a 0 002 inch thick layer which may be more representative of production thermal grease thickness Heatsink thermal resistance is generally predicted by the heatsink vendor modeled using a continuous flow dynamics CFD model or measured Thus for a single monaural IC the system Reja Doc thermal grease resistance heatsink resistance Table 4 Table 5 and Table 6 indicate modeled parameters for one or two TAS5112 ICs on a single heatsink The final junction temperature is set at 110 C in TEXAS INSTRUMENTS www ti com all cases
26. the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum ratedconditions for extended periods may affect device reliability 2 The duration of voltage spike should be less than 100 ns 3 GREG is treated as an input when the GREG pin is overdriven by GVDD of 12 V ORDERING INFORMATION PACKAGE DESCRIPTION 0 C to 70 C TAS5112DFD 56 pin small TSSOP 1 For the most current specification and package information refer to our Web site at www ti com PACKAGE DISSIPATION RATINGS RoJC RJA PACKAGE LEW CCW 56 pin DAD TSSOP 1 The TAS5112 package is thermally enhanced for conductive cooling using an exposed metal pad area It is impractical to use the device with the pad exposed to ambient air as the only heat sinking of the device For this reason ReJA a system parameter that characterizes the thermal treatment is provided in the Application Information section of the data sheet An example and discussion of typical system RJA values are provided in the Thermal Information section This example provides additional information regarding the power dissipation ratings This example should be used as a reference to calculate the heat dissipation ratings for a specific application TI application engineering provides technical support to design heatsinks if needed
27. trusion D 4073260 B 08 03 The package thermal performance may be enhanced by attaching an external heatsink to the thermal pad This pad is electrically and thermally connected to the backside of the die and possibly selected leads E Falls within JEDEC MO 153 PowerPAD is a trademark of Texas Instruments 45 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with
28. ut filter use a 0 47 uF capacitor with a voltage rating at least twice the voltage applied to the output stage PVDD This capacitor should be a good quality polyester dielectric such as a Wima MKS2 047ufd 100 10 or equivalent In order to minimize the EMI effect of unbalanced ripple loss in the inductors 0 1 uF 50 V SMD capacitors X7R or better C1A and C1B in Figure 11 should be added from the output of each inductor to ground 14 TEXAS INSTRUMENTS www ti com THERMAL INFORMATION The thermally augmented package provided with the TAS5112 is designed to be interfaced directly to heatsinks using a thermal interface compound for example Wakefield Engineering type 126 thermal grease The heatsink then absorbs heat from the ICs and couples it to the local air If the heatsink is carefully designed this process can reach equilibrium and heat can be continually removed from the ICs Because of the efficiency of the TAS5112 heatsinks can be smaller than those required for linear amplifiers of equivalent performance Roja is a system thermal resistance from junction to ambient air As such it is a system parameter with roughly the following components Duc the thermal resistance from junction to case or in this case the metal pad Thermal grease thermal resistance Heatsink thermal resistance Rejc has been provided in the General Information section The thermal grease thermal resistance can be calcula
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TEXAS INSTRUMENTS TAS5112 handbook

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