FAIRCHILD 74LCX240 handbook
Contents
1. V CC sq O OPEN tuth Test Switch TEST C BOE OTN i R te7L gt PLZ ds ipzi ipi z 6V at Vcc 3 3 4 0 3V Vcc x2at Vcc 2 5 0 2V Figure 1 AC Test Circuit C includes probe and jig capacitance DATA IN x pxx DATA V OUT mo Waveform for Inverting and Non Inverting Functions CONTROL IN CLOCK OUTPUT Propagation Delay Pulse Width and t Waveforms OUTPUT Mcr CONTROL mi AN tPZH Puz V OUT mo Vy 3 STATE Output Low Enable and Disable Times for Logic Symbol 3 3V 0 3V OUTPUT 166 CONTROL mi T PzL PLZ DATA p OUT mo 3 STATE Output High Enable and Disable Times for Logic CONTROL INPUT CLEAR Setup Time Hold Time and Recovery Time for Logic Vou 90 90 ANY OUTPUT VoL trise and tran Vcc 2 7M 2 5V t 0 2V sjndjno pue sjnduj ju amp J9 o AG YUM JOALIG eurq 49gng e320 eBeyoA MoT OrZXO Tr Vo 0 3V Vo 0 3V Vo 0 15V Vau 03V Xep 09V Vag 0 15V Figure 2 Waveforms Input Characteristics f 1MHz t t 3ns 1994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 6 Schematic Diagram Generic for LCX Family input stage P2 Data Lg I I l I I I VoD l i N2 ii C input stage crolM gt Output P4 D6 N P Enable bugs I I I I I I N4 I I I I I I 3i s nd n o pue sjnduj 3ueJ9Jo AG YM JAG eur1 19g2. 5 5V Increase in Icc per Input 2 3 3 6 Vin Vcc 0 6V Note 4 Outputs disabled or 3 STATE only AC Electrical Characteristics TA 40 C to 85 C R 5000 Voc 3 3V 0 3V Vcc 2 7V Veco 2 5V t 0 2V C 50pF Symbol Parameter Min Note Vog 0 2 NINI N gt Nj NI amp NM OJN 5 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction either HIGH to LOW tosuL or LOW to HIGH tosL Hj 01994 Fairchild Semiconductor Corporation 74LCX240 Rev 1 6 0 4 www fairchildsemi com sjnd3no pue sjnduj ju amp J9 o AG YYM JOALIG eurq 49gng 6320 eBeyoA o1 OrZXO r4 Dynamic Switching Characteristics TA 25 C Symbol Veo V Typical un V Quiet Output Dynamic Peak V 9 9 Cr 50pF Vy 3 3V Vy 0V V OLP OL L IH IL V Quiet Output Dynamic Valley V d amp 50pF Viu 3 3V Vy 0V V OLV OL L IH IL Capacitance Input Capacitance Vcc Open V OV or Vec Output Capacitance Veco 3 3V V OV or Vec ES PF Power Dissipation Capacitance Vcc 3 3V V OV or Vec f 10MHz 1994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 5 s nd no pue sjnduj ju amp J9 o AG YYM J9Auq eurq 499ng e320 eBeyjoA moT OrZXO Tr AC Loading and Waveforms Generic for LCX Family
3. 6 772 s nd no pue sjnduj ju amp J9 o AG YYM JOALIG eurq 49gng 6320 eBeyoA o1 OrZXO Tr fs ES aaa FAIRCHILD SSS SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such trademarks ACEx FPS PDP SPM SupreMOS Build it Now FRFET Power220 SyncFET CorePLUS Global Power Resource POWEREDGE SYSTEM GENERAL CROSSVOLT Green FPS Power SPM The Power Franchise CTL Green FPS e Series PowerTrench the Current Transfer Logic GTO Programmable Active Droop P ENS EcoSPARK i Lo QFET TinyBoost EZSWITCH IntelliMAX es TM TinyBuck m ISOPLANAR QT Optoelectronics TinyLogic MegaBuck Quiet Series TINYOPTO MICROCOUPLER RapidConfigure TinyPower Fairchild MicroFET SMART START TinyPWM Fairchild Semiconductor MicroPak SPM TinyWire FACT Quiet Series MillerDrive STEALTH uSerDes FACT Motion SPM SuperFET UHC FAST OPTOLOGIC SuperSOT 3 Ultra FRFET FastvCore OPTOPLANAR SuperSOT 6 UniFET FlashWriter i SuperSOT 8 VCX EZSWITCH and FlashWriter are trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHE
4. AJ TYPE II 5 3mm Wide 74LCX240MSA MSA20 20 Lead Shrink Small Outline Package SSOP JEDEC MO 150 5 3mm Wide 74LCX240MTC MTC20 20 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Device also available in Tape and Reel Specify by appending suffix letter X to the ordering number OIN packages are lead free per JEDEC J STD 020B standard 1994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 sjnd3no pue s ndu 3u amp J9Jo AG YYM JOALIG eurq 49gng V720 eBeyoA o1 OrZXO Tr Connection Diagram Logic Diagram Pin Description PinNames Description Pins 12 14 16 18 L Z Outputs H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance 1994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 2 s nd no pue sjnduj 3u amp J9 o AG YYM J9Auq eurq 499ng e320 eBeyoA o1 OrZXO Tr Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended In addition extended exposure to stresses above the recommended operating conditions may affect device reliability The absolute maximum ratings are stress ratings only Symbol Parameter v Supply Voltage DC Input Voltage DC Output Voltage Output in 3 STATE Output in HIGH or LO
5. R NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support which a are intended for surgical implant into the body or device or system whose failure to perform can be b support or sustain life and c whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system or to affect its safety or effectiveness provided in the labeling can be reasonably expected to result in a significant injury of the user PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition This datasheet contains the design specifications for product Advance Information Formative or In Design development Specifi
6. W State 2 dk DC Input Diode Current Vj lt GND DC Output Diode Current Vo gt Vcc de DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Note 2 lg Absolute Maximum Rating must be observed CC VI Vo lik lok loc Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications Fairchild does not recommend exceeding them or designing to absolute maximum ratings PO n ov Vcc Supply Voltage Data Retention Input Voltage Vo Output Voltage 3 STATE HIGH or LOW State lon lo Output Current Vec 3 0V 3 6V Vec 2 7V 3 0V Vcc 2 3V 2 7V Note 3 Unused inputs must be held HIGH or LOW They may not float 01994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 3 sjnd3no pue sjnduj ju amp J9 o AG YPM JOALIG eurq 49gng e320 eBeyoA o1 OrZXO Tr DC Electrical Characteristics TA 40 C to 85 C e Ema are 35 fonza HIGH Level Output Voltage lou 100pA 23 low BmA 37 foam 239 86 lou 24mA LOW Level Output Voltage 23 2 3 0 loj 24mA Input Leakage Current 2 3 3 6 O0 lt V lt 5 5V Power Off Leakage Current o Vi or Vo 5 5V 3 mis lec Quiescent Supply Current 2 3 3 6 Vi Vcc or GND 6V V Vg
7. cations may change in any manner without notice This datasheet contains preliminary data supplementary data will be Preliminary First Production published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design This datasheet contains final specifications Fairchild Semiconductor No Identification Needed Full Production reserves the right to make changes at any time without notice to improve the design This datasheet contains specifications on a product that has been Obsolete Not In Production discontinued by Fairchild Semiconductor The datasheet is printed for reference information only Rev 133 1994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 12 sjnd3no pue sjnduj 3ueJ9Jo AG YM JeAlg eur1 19ging 6320 eBeyjoA MOT OFZXD1PZ
8. d no pue sjnduj juesajol AG YYM J9ALIG eurq 49gng e320 eBeyoA o1 OrZXO Tr Physical Dimensions Continued eU i 20 anna Ooni 4 4t0 1 8 be 2 27 de oe E B 065 10 ALL LEAD TIPS PIN 1 IDENT LAND PATTERN RECOMMENDATION SEE DETAIL A 42 R0 09ni DIMENSIONS ARE IN MILLIMETERS 0 8 NOTES A CONFORMS TO JEDEC REGISTRATION MO 153 VARIATION AC S I REF NOTE 6 DATE 7 93 N s BM PLANE B DIMENSIONS ARE IN MILLIMETERS BM C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLDS FLASH AND TIE BAR EXTRUSIONS DETAIL A D DIMENSIONS AND TOLERANCES PER ANSI Y14 5M 1982 MT C20REV D1 Figure 6 20 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http llwww fairchildsemi comlpackagingl 1994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 11 44
9. ea FAIRCHILD E SEMICONDUCTOR January 2008 74LCX240 Low Voltage Octal Buffer Line Driver with 5V Tolerant Inputs and Outputs Features General Description B SV tolerant inputs and outputs The LCX240 is an inverting octal buffer and line driver m 2 3V 3 6V Vcc specifications provided designed to be employed as a memory address driver W 6 5ns tpp max Vcc 3 3V 10pA Icc max clock driver and bus oriented transmitter or receiver The aw 3 ep device is designed for low voltage 2 5V or 3 3V Vcc COME ugn mpegange i and outha applications with capability of interfacing to a 5V signal B Supports live insertion withdrawal environment t B 24mA output cue Nice 3 0V The LCX240 is fabricated with an advanced CMOS tech B Implements proprietary noise EMI reduction circuitry nology to achieve high speed operation while maintain II Latch up performance exceeds 500mA ing CMOS low power dissipation m ESD performance Human body model gt 2000V Machine model gt 200V Note 1 To ensure the high impedance state during power up or down OE should be tied to Vcc through a pull up resistor the minimum value or the resistor is determined by the current sourcing capability of the driver Ordering Information Order Package Number Number Package Description 74LCX240WM M20B 20 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide 74LCX240SJ M20D 20 Lead Small Outline Package SOP EI
10. gng e320 eBeyoA o1 OrZXO Tr Physical Dimensions Continued 7 2 0 30 0 68 TYP 9 12 a aa imma 5 58 5 30 30 i 1 10 1 77 TYP ALL LEAD TIPS d 1 PIN 1 IDENT Cv 02 C A 8 0 65 TYP 0 45 TYP LAND PATTERN RECOMMENDATIONS oo MINIT 1 75 0 04 TEE i 0 13 0 08 s LL 022 08 l DIMENSIONS ARE IN MILLIMETERS GAGE PLANE NOTES 0 25 0 8 A CONFORMS TO JEDEC REGISTRATION MO 150 VARIATION AE DATE 1 94 i B DIMENSIONS ARE IN MILLIMETERS 0 75 0 2 C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS 1 25 D DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 SEATING PLANE DETAIL A MSAPOREVB Figure 5 20 Lead Shrink Small Outline Package SSOP JEDEC MO 150 5 3mm Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http llwww fairchildsemi comlpackagingl 01994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 10 s n
11. ing 6320 Beyo MOT OFZXD1PZ 1994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 7 Physical Dimensions 10 65 7 60 10 00 7 40 PIN ONE H 9 INDICATOR 35 025 C BJA LAND PATTERN RECOMMENDATION 2 65 MAX SEATING PLANE NOTES UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC RO 10 MS 013 VARIATION AC ISSUE E B ALL DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D CONFORMS TO ASME Y14 5M 1994 E LANDPATTERN STANDARD SOIC127P1030X265 20L DETAIL A F DRAWING FILENAME MKT M20BREV3 SCALE 2 1 SEATING PLANE Figure 3 20 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http llwww fairchildsemi comlpackagingl 01994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 8 sjnd3no pue sjnduj 3u amp J9 o AG YYM JOALIG eu
12. rq 49gng e320 Heyo oA MoT OrZXO r4 Physical Dimensions Continued 12 020 10 5 940 10 1 2 9 10 i 2 13 TYP f o2 c 8 A i 7 ALL LEAD TIPS as 1 27 os L 0 6 TYP LAND PATTERN RECOMMENDATION PIN 1 IDENT ALL LEAD TIPS SEE DETAIL A 2 1 MAX t TRE nE J E 1 27 TYP L 0 35 0 5 t DIMENSIONS ARE IN MILLIMETERS GAGE PLANE NOTES amp 8 0 25 A CONFORMS TO EIAJ EDR 7320 REGISTRATION ESTABLISHED IN DECEMBER 1998 B DIMENSIONS ARE IN MILLIMETERS NE C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD d FLASH AND TIE BAR EXTRUSIONS 0 60 0 15 SEATING PLANE DETAIL A M20DREVC Figure 4 20 Lead Small Outline Package SOP EIAJ TYPE II 5 3mm Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http llwww fairchildsemi comlpackagingl 1994 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX240 Rev 1 6 0 9 s nd no pue sjnduj ju amp J9 o AG YYM JOALIG eurq 49
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FAIRCHILD 74LCX240 handbook