FAIRCHILD 74LCX125 handbook
Contents
1. 5 0 0 1 0 43 TYP 4 8 HAHA HAM 4 4 0 1 d j PIN 1 IDENT s EINEN ALL LEAD TIPS Hm f DETAIL A TS ics 0 1 C FON ee FL E 0 09 0 20 d m IPTE MINNS 0 130 A 12 00 TOP amp BOTTOM R0 09 min GAGE PLANE SEATING PLANE R0 09min NOTES x A CONFORMS TO JEDEC REGISTRATION MO 153 0 VARIATION AB REF NOTE 6 B DIMENSIONS ARE IN MILLIMETERS DETAIL A C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D DIMENSIONING AND TOLERANCES PER ANSI Y14 5M 1982 E LANDPATTERN STANDARD SOP65P640X110 14M F DRAWING FILE NAME MTC14REV6 Figure 6 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http lIwww fairchildsemi comlpackagingl 01995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 12 s nd n o pue sjnduj 3ueJ9Jo AG YM Jong peny abeo Mo SZLXD1bZ2. fs ES aaa FAIRCHILD SSS SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such trademarks ACEN FPS PDP SPM SupreMOS Build it Now FRFET Power220 SyncFET CorePLUS Global Power Resource POWEREDGE SYSTEM GENERAL CROSSVOLT Green FPS Power SPM The Power Franchise CTL Green FPS e Series PowerTrench the Current Transfer Logic GTO Programmable Active Droop P ENS EcoSPARK i Lo QFET TinyBoost EZSWITCH IntelliMAX es TM TinyBuck m ISOPLANAR QT Optoelectronics TinyLogic MegaBuck Quiet Series TINYOPTO d MICROCOUPLER RapidConfigure TinyPower Fairchild MicroFET SMART START TinyPWM Fairchild Semiconductor MicroPak SPM TinyWire FACT Quiet Series MillerDrive STEALTH uSerDes FACT Motion SPM SuperFET UHC FAST OPTOLOGIC SuperSOT 3 Ultra FRFET FastvCore OPTOPLANAR SuperSOT 6 UniFET FlashWriter i SuperSOT 8 VCX EZSWITCH and FlashWriter are trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT
3. 3ueJ9 o AG YM Jong peny abeo o SZLXOTYL AC Loading and Waveforms Generic for LCX Family Voc O OPEN O GND tp7L gt PLZ tpz ipi z 6V at Vcc 3 3 4 0 3V Vcc x2at Vcc 2 5 0 2V Figure 1 AC Test Circuit C includes probe and jig capacitance Vec GND K Veni toxx Jon DATA V QUT mo Waveform for Inverting and Non Inverting Functions CONTROL IN CLOCK OUTPUT Propagation Delay Pulse Width and t Waveforms OUTPUT m Mee CONTROL mi sis tPZH Puz V OUT mo Vy 3 STATE Output Low Enable and Disable Times for Logic Symbol 3 3V 0 3V OUTPUT Ces CONTROL mi T tPzL PLZ DATA p OUT mo 3 STATE Output High Enable and Disable Times for Logic CONTROL INPUT CLEAR Setup Time Hold Time and Recovery Time for Logic Vou 90 90 ANY OUTPUT 10 VoL trise and trai Vcc s nd n pue sjnduj 3ueJ9 o AG uj Jong peny abeo o GZLXD1bZ Vo 0 3V Vo 0 3V Vo 0 15V Wisen Mee Vop 018V Figure 2 Waveforms Input Characteristics f 1MHz t t 3ns 01995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 6 Schematic Diagram Generic for LCX Family input stage P2 Data Lg I I I I I I VoD I z N2 a C input stage crolM gt Output P4 D6 N P Enable bugs N4 sjnd3no pue sjnduj juesajolL AG YUM Jong penH abeo MO7 GZL
4. ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support which a are intended for surgical implant into the body or device or system whose failure to perform can be b support or sustain life and c whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system or to affect its safety or effectiveness provided in the labeling can be reasonably expected to result in a significant injury of the user PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition This datasheet contains the design specifications for product Advance Information Formative or In Design development Specifications may change in any manner without notice This datasheet contains preliminary data
5. SSSI FAIRCHILD Bee ee eae SEMICONDUCTOR February 2008 74LCX125 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs Features General Description E 5V tolerant inputs and outputs The LCX125 contains four independent non inverting m 2 3V 3 6V Vcc specifications provided buffers with 3 STATE outputs The inputs tolerate volt ages up to 7V allowing the interface of 5V systems to 3V E 6 0ns tpp max Vcc 3 3V 10pA Icc max B Power down high impedance inputs and outputs B Supports live insertion withdrawal The 74LCX125 is fabricated with an advanced CMOS B 24mA output drive Vcc 3 0V technology to achieve high speed operation while main l l inode taining CMOS low power dissipation B Implements proprietary noise EMI reduction circuitry B Latch up performance exceeds JEDEC 78 conditions m ESD performance Human body model gt 2000V Machine model gt 100V B Leadiess DQFN package systems Note 1 To ensure the high impedance state during power up or down OE should be tied to Vcc through a pull up resistor the minimum value of the resistor is determined by the current sourcing capability of the driver Ordering Information Package Order Number Number Package Description 74LCX125M M14A 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow 74LCX125SJ M14D 14 Lead Small Outline Package SOP EIAJ TYPE II 5 3mm Wide 7ALCX125BQX MLP14A 14 Terminal Depopulated Qu
6. XOTvZ 1995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 7 Tape and Reel Specification Tape Format for DQFN Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status Trailer Hub End 75 Typ Empty Tape Dimensions inches millimeters 4 0 0 1 2 00 0 05 1 55 0 05 A d EX D 0 30 0 05 T Ko r aam e 7 H a SECTION AA DIMENSIONS ARE IN MILLIMETERS NOTES unless otherwise specified 1 Cummulative pitch for feeding holes and cavities chip pockets not to exceed 0 008 0 20 over 10 pitch span 2 Smallest allowable bending radius 3 Thru hole inside cavity is centered within cavity 4 Tolerance is 0 002 0 05 for these dimensions on all 12mm tapes 5 Ao and Bo measured on a plane 0 120 0 30 above the bottom of the pocket 6 Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier 7 Pocket position relative to sprocket hole measured as true position of pocket Not pocket hole 8 Controlling dimension is millimeter Diemension in inches rounded sjndjno pue s nduj 3ueJ9 o AG YM Jong peny abe o SZLXD1bZ Reel Dimensions inches millimeters _ W1 Measured at Hub W2 max Measured at Hub si lt x qm Dia C Dia A za CMM 48 he a acter eer con LER g Dia N max amp min y See detail AA DETAIL AA Umesm a 8 5 w w
7. ad Very Thin Flat Pack No Leads DQFN JEDEC MO 241 2 5 x 3 0mm Wide 74LCX125MTC MTC14 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Note 2 DQFN package available in Tape and Reel only Device also available in Tape and Reel Specify by appending suffix letter X to the ordering number OIN packages are lead free per JEDEC J STD 020B standard 1995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 s nd n o pue sjnduj 3ueJ9 o AG YM Jong peny abeo Mo SZLXOTYL Connection Diagrams Logic Symbol Pin Assignments for SOIC SOP and TSSOP IEEE IEC m A OE M OE Ag Ay Og OE E A ki 0 LE GND Az OE Top View Pad Assignments for DQFN Truth Table H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial Top Through View Pin Description PinNames Description Output Enable Inputs Outputs 01995 Fairchild Semiconductor Corporation 74LCX125 Rev 1 7 0 2 www fairchildsemi com s nd n o pue s nduj 3ueJ9 o AG YM Jong peny abeo Mo SZLXOTYL Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended In addition extended exposure to stresses above the recommended operating conditions may affect device reliability T
8. comlpackagingl 01995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 9 s nd n o pue s nduj 3ueJ9 o AG YM Jong peny abeo Mo SZLXD1bZ Physical Dimensions Continued e ES 8 7 2 13 TYP l Umm deg imd L H Lu TYP ALL LEAD TIPS PIN 1 IDENT LAND PAITERN RECOMMENDATION ALL LEAD TIPS SEE DETAIL A 1 80 1 0 15 0 05 0 15 0 25 E DIMENSIONS ARE IN MILLIMETERS GAGE PLANE NOTES 0 25 A CONFORMS TO EIAJ EDR 73520 REGISTRATION ESTABLISHED IN DECEMBER 1998 B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS 0 60 0 15 SEATING PLANE DETAIL A M14DREVC Figure 4 14 Lead Small Outline Package SOP EIAJ TYPE II 5 3mm Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http llwww fairchildsemi comlpackagingl 01995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 10 s
9. he absolute maximum ratings are stress ratings only w Jocimputvorage DC Output Voltage Is OwmtnHGHolOWSmeU ik DCmpiDedeCureV eOND OO b DC Output Diode Current Vo GND Vo gt Vcc de DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Note 3 lg Absolute Maximum Rating must be observed CC VI Vo lik lok loc Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications Fairchild does not recommend exceeding them or designing to absolute maximum ratings NEED noD 0n Vcc Supply Voltage Data Retention Input Voltage Vo Output Voltage HIGH or LOW State 3 STATE Lou feat Output Current Vec 3 0V 3 6V Vec 2 7V 3 0V Vcc 2 3V 2 7V Note 4 Unused inputs must be held HIGH or LOW They may not float 01995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 3 s nd n o pue s nduj 3ueJ9 o AG YM Jong peny abeo Mo SZLXD1bZ DC Electrical Characteristics TA 40 C to 85 C Parameter Conditions HIGH Level Input Voltage Les 19 s nd n pue sjnduj 3ueJ9 o AG uj Jong peny abeo o SZLXD1bZ HIGH Level Output Voltage lou 100pA lou 2 12mA 3 loy 2 18mA LOW Level Output Voltage lo 100pA 2 l
10. nd n o pue sjnduj 3ueJ9Jo AG YM Jong peny abeo Mo SZLXD1bZ Physical Dimensions Continued 1 4 SEES DX SOOO MI SSSR Ge BOSS QPS 0 50 TYP GE CONSA 2 50 pU A x 3 50 SE MAX xy 0 15 0 90 2 6 2X 9 15 C TOP VIEW 0 50 es Lan TYP RECOMMENDED LAND PATTERN iio oss h B o 18 0 30 s nd n o pue s nduj 3ueJ9 o AG YM Jong peny abeo Mo SZLXD1bZ x00 DEE BOTTOM VIEW NOTES A CONFORMS TO JEDEC REGISTRATION MO 241 VARIATION AA B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 MLP14ArevA Figure 5 14 Terminal Depopulated Quad Very Thin Flat Pack No Leads DQFN JEDEC MO 241 2 5 x 3 0mm Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http www fairchildsemi com packaging 1995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 11 Physical Dimensions Continued
11. oL 8mA 2 lo 12mA 3 1 3 3 T 0 0 lg 2 16mA lo 24mA 0 lt Vis 55V 2 3 3 6 0xVg x 5 5V V Viu or Vu Power Off Leakage Current Eo Vi or Vo 5 5V lcc Quiescent Supply Current 2 3 3 6 V Vcc or GND 3 6V V Vo lt 5 5V Increase in Icc per Input 2 3 3 6 Vin Vec 0 6V Note 5 Outputs disabled or 3 STATE only Input Leakage Current loz 3 STATE Output Leakage AC Electrical Characteristics TA 40 C to 85 C R 5000 Symbol Parameter Ven kel Output Output skew 10 Note 6 Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction either HIGH to LOW tosuL or LOW to HIGH oe ul 1995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 4 Dynamic Switching Characteristics TA 25 C Symbol Veo V Typical m V Quiet Output Dynamic Peak V 9 9 Cr 50pF Vy 3 3V Vy 0V V OLP OL L IH IL V Quiet Output Dynamic Valley V d amp 50pF Viu 3 3V Vu 0V V OLV OL L IH IL Capacitance Input Capacitance Vec Open V OV or Vec Output Capacitance Vec 3 3V V OV or Mee ESO pF Power Dissipation Capacitance Vec 3 3V Vj OV or Vec f 10MHz 1995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 5 s nd n o pue s nduj
12. supplementary data will be Preliminary First Production published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design This datasheet contains final specifications Fairchild Semiconductor No Identification Needed Full Production reserves the right to make changes at any time without notice to improve the design This datasheet contains specifications on a product that has been Obsolete Not In Production discontinued by Fairchild Semiconductor The datasheet is printed for reference information only Rev 133 01995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 13 sjnd3no pue sjnduj juesajol AG YUM Jong penH eDe3oA MO7 GZLXOTvZ
13. w 13 0 330 0 0 059 1 50 0 512 13 00 0 795 20 20 2 165 55 00 0 488 12 4 0 724 18 4 01995 Fairchild Semiconductor Corporation www fairchildsemi com 74LCX125 Rev 1 7 0 8 Physical Dimensions JOULU 5 60 Judd 1 70 Ju DIN ONE 8 INDICATOR 0 51 H 0 35 LAND PATTERN RECOMMENDATION 0 25 c B A SEE DETAIL A 1 50 1 25 p 0 25 0 25 m NOTES UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC 0 50 MS 012 VARIATION AB ISSUE C 0 25 X 43 B ALL DIMENSIONS ARE IN MILLIMETERS RO 10 l C DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS D LANDPATTERN STANDARD 0 36 SOIC127P600X145 14M E DRAWING CONFORMS TO ASME Y14 5M 1994 F DRAWING FILE NAME M14AREV13 SEATING PLANE DETAIL A SCALE 20 1 Figure 3 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http llwww fairchildsemi
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FAIRCHILD 74LCX125 handbook