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TEXAS INSTRUMENTS PCI4410 GHK/PDV handbook

1. Enable asynchronous priority requests OHCI Lynx TSB12LV22 compatible This reserved field will not be assigned in PCI4410 follow on products since this bit location loaded by the serial ROM from the enhancements field corresponds to HCControl programPhyEnable in open HCI register space Reserved These bits return 0 when read ENAB INSERT IDLE R W Enable insert idle OHCI Lynx TSB12LV22 compatible 1 ENAB ACCEL R Enable acceleration enhancements OHCI Lynx TSB12LV22 compatible 0 RSVD Reserved This bit returns 0 when read 8 15 8 22 Subsystem Access Identification Register The subsystem access identification register is used for system and option card identification purposes The contents of this register are aliased to subsystem identification register at address 2Ch See Table 8 19 for a complete description of the register contents Bit 31 so 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 peru o o lo lo o fofo o fo o o o o o 0 Bit 15 14 13 12 11 10 9 8 7 6 5 a j 3 2 j 1 0 Name Subsystemaccessident icaton pem o o o o o o o ofjo o o ol o o o o Register Subsystem access identification Type Read Write Offset F8h Default 0000 0000h Table 8 19 Subsystem Access Identification Register SIGNAL TYPE FUNCTION 31 16 SUBDEV ID Subsystem device ID This field indicates the subsystem device ID SUBVEN ID Subsystem ven
2. 9 26 9 32 Asynchronous Request Filter High Register 9 27 9 33 Asynchronous Request Filter Low Register 9 29 9 34 Physical Request Filter High Register a 9 30 9 35 Physical Request Filter Low Register nananana 9 32 9 36 Physical Upper Bound Register Optional Register 9 32 9 37 Asynchronous Context Control Register 9 33 9 38 Asynchronous Context Command Pointer Register 9 34 9 39 Isochronous Transmit Context Control Register 9 35 9 40 Isochronous Transmit Context Command Pointer Register 9 36 9 41 Isochronous Receive Context Control Register 9 37 9 42 Isochronous Receive Context Command Pointer Register 9 38 9 43 Isochronous Receive Context Match Register 9 39 Electrical Characteristics wa EER RE rrr rn DEERE 10 1 10 1 Absolute Maximum Ratings Over Operating Temperature Ranges 10 1 10 2 Recommended Operating Conditions lusus 10 2 10 3 Electrical Characteristics Over Recommended Operating Conditions unless otherwise noted 10 3 vii 10 4 PCI Clock Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free Air Temperature 10 4 10 5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free Air Temperature 11 Mech
3. Register Next item pointer Type Read only Offset Ath Default 00h 4 27 4 41 Power Management Capabilities Register This register contains information on the capabilities of the PC Card function related to power management Both PCI4410 CardBus bridge functions support DO D1 D2 and D3 power states See Table 4 16 for a complete description of the register contents mi as a ujea a r s s AE SE ANENE Power management capabilities Powermanagementcapabilties ooo Type Aw R R JR n JR Jn JR ny n Rn n n HR J RR pea 1 1 ri e fs ts tt foto fo fs Ts fo fo fof Register Power management capabilities Type Read Write Read only Offset A2h Default FE31h Table 4 16 Power Management Capabilities Register SIGNAL TYPE FUNCTION PME support This 5 bit field indicates the power states from which the PCI4410 device functions may assert PME A 0 zero for any bit indicates that the function cannot assert the PME signal while in that power state These five bits return 11111b when read Each of these bits is described below PME SUPPORT Bit 15 defaults to the value 1 indicating the PME signal can be asserted from the D3cold state This bit is R W because wake up support from D3cold is contingent on the system providing an auxiliary power source to the Vcc terminals If the system designer chooses not to provide an auxiliary power source to the Vcc terminals for D3cold wake up support then BIOS should w
4. CBCARD 16BITCARD PWRCYCLE READY IREQ CINT Bit 6 indicates the current status of READY IREQ CINT at the PC Card interface 0 READY IREQ CINT low 1 READY IREQ CINT high CardBus card detected Bit 5 indicates that a CardBus PC Card is inserted in the socket This bit is not updated until another card interrogation sequence occurs card insertion 16 bit card detected Bit 4 indicates that a 16 bit PC Card is inserted in the socket This bit is not updated until another card interrogation sequence occurs card insertion Power cycle Bit 3 indicates that the status of each card powering request This bit is encoded as 0 Socket powered down default 1 Socket powered up CCD2 Bit 2 reflects the current status of CCD2 at the PC Card interface Changes to this signal during card interrogation are not reflected here 0 CCD2 low PC Card may be present 1 CCD2 high PC Card not present CCD1 Bit 1 reflects the current status of CCD1 at the PC Card interface Changes to this signal during card interrogation are not reflected here 0 CCD1 low PC Card may be present 1 CCD1 high PC Card not present CSTSCHG Bit 0 reflects the current status of CSTSCHG at the PC Card interface 0 CSTSCHG low 1 CSTSCHG high CDETECT2 6 5 6 4 Socket Force Event Register The socket force event register is used to force changes to the socket event register see Section 6 1 and the socket present state register
5. 0000 GPIO 0100 IRQ4 1000 CAUDPWM 1100 2 LED SKT ee MFUNGO didi 0001 GPOO 0101 IRQ5 1001 IRQ9 1101 IRQ13 0010 INTA 0110 ZVSTAT 1010 IRQ10 1110 2 GPE 0011 IRQ3 0111 ZVSELO 1011 IRQ11 1111 IRQ15 4 33 Retry Status Register The retry status register enables the retry timeout counters and displays the retry expiration status The flags are set when the PC14410 retries a PCI or CardBus master request and the master does not return within 219 PCI clock cycles The flags are cleared by writing a 1 to the bit These bits are expected to be incorporated into the PCI command PCI status and bridge control registers by the PCI SIG See Table 4 10 for a complete description of the register contents et 7 e j s 4 2 1 90 Retry status me we Aw w E A ac A AGC A ew lo o o lo po fo po Register Retry status Type Read only Read Write Read Write to Clear Offset 90h Default COh Table 4 10 Retry Status Register SIGNAL TYPE FUNCTION PCI retry timeout counter enable Bit 7 is encoded 7 PCIRETRY R W 0 PCI retry counter disabled 1 PCI retry counter enabled default CardBus retry timeout counter enable Bit 6 is encoded CBRETRY 0 CardBus retry counter disabled 1 CardBus retry counter enabled default 54 RSVD R Reserved Bits 5 and 4 return Os when read CardBus target retry expired Write a 1 to clear bit 3 3 TEXP CB R C 0 Inactive default 1 Re
6. 8 12 Power Management Extension Register Lsssuu 8 13 PCI Miscellaneous Configuration Register 8 14 Link Enhancement Control Register is EE Ee ee ee ee ee 8 15 Subsystem Access Identification Register 8 16 GPIO Control Register is SEER HER EER EERDER E ERA ERR DERE ES 8 17 Open HCI Register Map 9 1 OHGI Version Register 1 sse sacr e ou ADA hab odo KERS de na E 9 4 GUID ROM REQ qua sagas EER ER da a Re RR E qp 9 5 Asynchronous Transmit Retries Register 9 6 CSR Control Register cepssmpss ns tres ris DE BE GE ER DA S Eh ER QUA ONE 9 8 Configuration ROM Header Register 9 9 Bus Options Register es sen xe RRERERERERRERREREYRREERREEd ER RE 9 10 Configuration ROM Mapping Register 9 12 Posted Write Address Low Register is EE aaa 9 12 Posted Write Address High Register 9 13 Host Controller Control Register 9 14 Self ID Count MEGISIEN sos od ERK pa si EE ante bdo eh borane 9 15 ISO Receive Channel Mask High Register 4 9 16 ISO Receive Channel Mask Low Register EE a 9 17 Interrupt Event Register 9 18 Interrupt Mask Register 2a iss es I dr RD RED RR when 9 19 Isochronous Transmit Interrupt Event Register 9 20 Isochronous Receive Interrupt Event Register 9 21 Fairness Control Register sue sext ed str ERAS ES PA VERLA SEE 9 22 Link Contr
7. TI memory indicator This bit returns 0 indicating the TI extension registers are mapped into system TI MEM memory space Tl PF TI extension register prefetch This bit returns O indicating the TI extension registers are B nonprefetchable 8 7 8 11 PCI Subsystem Identification Register The PCI subsystem identification register is used for subsystem and option card identification purposes This register can be initialized from the serial EEPROM or can be written using the subsystem access register See Table 8 10 for a complete description of the register contents m s s s s les eslsleslsIlzeIsIsIsIsIsIs Dera PCI subsystem identification Name EE Gn CERCHI RE Register PCI subsystem identification Type Read Update Offset 2Ch Default 0000 0000h Table 8 10 PCI Subsystem Identification Register SIGNAL TYPE FUNCTION 31 16 OHCI SSID Subsystem device ID This field indicates the subsystem device ID OHCI SSVID Subsystem vendor ID This field indicates the subsystem vendor ID 8 12 PCI Power Management Capabilities Pointer Register The PCI power management capabilities pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides PCI4410 configuration header doublewords at 44h and 48h provide the power management registers This register is read only and returns 44h when read Be 7 6 5 4 3 2 1 0 Name PCI power mana
8. 61h Table 4 13 Diagnostic Register SIGNAL TYPE FUNCTION This bit defaults to 0 Ths bit will cause software to fail to recognize the PCI4410 when set to 1 This bit is encoded as E REA FM 0 Reads true values from the PCI vendor ID and PCI device ID registers default 1 Reads all 1s from the PCI vendor ID and PCI device ID registers 6 RSVD Reserved Bit 6 returns 0 when read CSC interrupt routing control 5 CSC RAW 0 CSC interrupts routed to PCI if EXCA 803 see Section 5 4 bit 4 1 1 CSC interrupts routed to PCI if EXCA 805 see Section 5 6 bits 7 4 0000b default In this case the setting of EXCA 803 bit 4 is a don t care Diagnostic DISCARD TIM SEL CB Set 210 reset 215 Diagnostic DISCARD TIM SEL PCI Set 210 reset 215 Asynchronous interrupt enable ASYNCINT RAW 0 CSC interrupt is not generated asynchronously 1 CSC interrupt is generated asynchronously default 4 24 4 37 Socket DMA Register 0 The socket DMA register 0 provides control over the PC Card DMA request DREQ signaling See Table 4 14 for a complete description of the register contents Socket DMA register 0 Name TE Po Jo Jo To To oe Jo Jo To To 1e To Jo Jo To jo Register Socket DMA register 0 Type Read only Read Write Offset 94h Default 0000 0000h Table 4 14 Socket DMA Register 0 SIGNAL TYPE FUNCTION RSVD R Reserved Bits 31 2 return Os when read DMA request DREQ B
9. 9 10 UND High Registar sz om p ELA E RE ESE DE a do ee ODE DE 9 11 911 GUID Low Register osse BERE EE NAG owe EER Ete Xen 9 11 9 12 Configuration ROM Mapping Register 2 00 eee 9 12 9 13 Posted Write Address Low Register LLsuus 9 12 9 14 Posted Write Address High Register 9 13 9 15 Vendor ID Register os dur od titan GG DOE DEE 9 13 9 16 Host Controller Control Register cece eee eee 9 14 9 17 Self ID Buffer Pointer Register 0 0 c eee eee 9 15 9 18 Self ID Count Register sci isses tees den eens bets RR 9 15 9 19 ISO Receive Channel Mask High Register 9 16 9 20 ISO Receive Channel Mask Low Register 9 17 9 21 Interrupt Event Register ss ses ENE WER DEE RR RR ven sine ERR 9 18 9 22 Interrupt Mask Register 9 19 9 23 Isochronous Transmit Interrupt Event Register 9 20 9 24 Isochronous Transmit Interrupt Mask Register 9 21 9 25 8 Isochronous Receive Interrupt Event Register 9 21 9 26 Isochronous Receive Interrupt Mask Register 9 22 9 27 Fairness Control Register Optional Register 9 22 9 28 Link Control Register ss ag ER ES ESEG era ph EE RE DEE ne 9 23 9 29 Node Identification Register isi EE ER eee eee eee 9 24 9 30 PHY Control Register iss EE RE RE RE ORR RE RE m 9 25 9 31 Isochronous Cycle Timer Register
10. LINKON PHY DATAO VCCL PHY_DATA1 GND PHY_DATA2 PHY_DATA3 PHY_DATA4 PHY DATAS 207 PHY DATAS 208 0 2 3 5 6 vec CY PHY RSVD CH PHY RSVD 3 PHY RSVD 4 PHY RSVD C3 5 PHY RSVD PHY RSVD C PHY RSVD c PHY RSVD c PHY RSVD C PHY DATA7 10 PHY RSVD c4 2 PHY RSVD 7 PHY RSVD Hs PHY RSVD c Figure 2 1 PCI to CardBus Terminal Diagram ZV LRCLK E ka o 3 2 N is 2 EE R 4 09 F 4 zv UV 05F zV Yi 7 ZV Y 0 ZV VSYNC ZV HREF RSVD INTB INTA VCC LED SKT RSVD VPPD1 VPPDO SUSPEND MFUNC6 MFUNCS MEUNC4 GRST MFUNC3 MFUNC2 VCC SPKROUT MFUNC1 MFUNCO RI OUT PME GND ADO AD1 AD2 AD3 AD4 ADS AD6 VCC AD7 C BEO AD8 AD9 AD10 VCCP AD11 GND AD12 AD13 AD14 AD15 C BEi 2 2 ADDR22 ADDR15 ADDR23 ADDR12 ADDR24 GND ADDR7 ADDR25 VE ADDR6 RESET ADDR5 ADDR4 VCC INPACK ADDR3 READY IREQ WAIT BVD2 SPKR BVD1 STSCHG RI LPS PHY LREQ VCC PHY_CLK PHY CTL 0 PHY CTL 1 LINKON PHY DATAO VCCL PHY DATA1 GND PHY DATA PHY DATA3 PHY DATA PHY DATAS PHY_DATA6 156 ADDR16 155 E ADDR21 PHY RSVD CL 2 PHY DATA c 10 PHY RSVD 3 154 3 WE REQ 17 GNT CJ 18 AD31 C 19 AD30 CA 20 AD29 21 GND CA 22 AD28 CJ 23 AD27 CA 24 AD26 c 25 AD25 CA 26 AD24 27 C BE3 28 VCC C 30 AD23 31 AD22 CA 32 AD21 33 VCCP 34 AD20 35
11. PRST CA 36 PCLK C 37 GND C 38 AD19 39 AD18 40 AD17 41 AD16 42 C BE2 C 43 IRDY C 45 VCC Aas TRDY C 47 DEVSEL 48 GND 6 PHY RSVD C 7 vec cf 14 PHY RSVD 15 IDSEL CH 29 FRAME 44 PHY RSVD c 4 PHY RSVD 45 PHY RSVD 38 PHY RSVD C4 9 PHY RSVD C 10 PHY RSVD 11 PHY RSVD C 12 PHY RSVD C4 13 PHY RSVD C 16 Figure 2 2 PCI to PC Card 16 Bit Terminal Diagram SES BOSE x DE w t mon Eie IT EDE Fe E Ee YE Tola oc ISI TM RT EA ER 22 292222240269lo09 o895 6648860680959RRRKRR R CEE O GUDOSSS 2999909599599 5SRNNNANANARNANSSIT 8 STOP 49 1 108 I zv UV 107 E2 zv uv 2 0 105 2 zv v 7 PERR J 50 106 2 zv uv SERR 51 PAR CH 52 ZV VSYNC ZV HREF RSVD INTB INTA VCC LED_SKT RSVD VPPD1 VPPDO SUSPEND MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 VCCI SPKROUT MFUNG1 MFUNCO RI OUT PME GND ADO AD1 AD2 AD3 AD4 AD5 AD6 vce AD7 C BEO AD8 AD9 AD10 VCCP AD11 GND AD12 AD13 AD14 ADIS C BET OOOOOOOO OOOOOOO OOOOOOO OOOOOO OOOOOOO 00000000000 0000000000 00000000000 00000000000 00000000000 00000000000 0000000000000 O O O O O O O O O O O O O 00000000000 00000000000 0000000000000 PUOUMTOICAMEZUNAC lt S 1 3 5 7 9 1 13 15 17 19 2 4 6 8 10 12 14 16 18 Figure 2 3 MicRoSTAR BGA Ball Diagram Table 2 1 shows the terminal
12. REG is used in conjunction with the DMA read IOWR or DMA write IORD strobes to transfer data RESET 167 F12 O PC Card reset RESET forces a hard reset to a 16 bit PC Card WAIT e ato Ji pm WAIT is driven by a 16 bit PC Card to extend the completion of the memory or VO cycle Write enable WE is used to strobe memory write data into 16 bit memory PC Cards WE is also used for memory PC Cards that employ programmable memory technologies DMA terminal count WE i NE is used as TC C during DMA operations to a 16 bit PC Card that supports DMA The PCI4410 asserts WE to indicate TC for a DMA read operation Write protect WP applies to 16 bit memory PC Cards WP reflects the status of the write protect switch on 16 bit memory PC Cards For 16 bit VO PC cards WP is used for the 16 bit port IOIS16 function VO is 16 bits IOIS16 applies to 16 bit VO PC Cards IOIS16 is asserted by the 16 bit PC Card when the address on the bus corresponds to an address to which the 16 bit PC Card responds and the I O port that is addressed is capable of 16 bit accesses DMA request WP can be used as the DMA request signal during DMA operations to a 16 bit PC Card that supports DMA If used then the PC Card asserts WP to indicate a request for a DMA operation VS1 179 F11 lO Voltage sense 1 and voltage sense 2 V81 and VS2 when used in conjunction with each other determine VS2 165 E13 the operating voltage of the PC Card Table 2 13 CardBus
13. RW A Slave acknowledgement S P Start stop condition Figure 3 11 Serial Bus Protocol Byte Write Figure 3 12 illustrates a byte read The read protocol is very similar to the write protocol except the RAN command bit must be set to 1 to indicate a read data transfer In addition the PCI4410 master must acknowledge reception of the read bytes from the slave transmitter The slave transmitter drives the SDA signal during read data transfers The SCL signal remains driven by the PCI4410 master Slave Address Word Address 5 ve es ea ns vel er to 1 A ur te es oa fos ee joe oo A j 1 RW Slave Address Data Byte bo b5 va os oo er bo a b7 bs os oa bo ez ba bo m P A Slave acknowledgement M Master acknowledgement S P Start stop condition Figure 3 12 Serial Bus Protocol Byte Read Figure 3 13 illustrates EEPROM interface doubleword data collection protocol Slave Address Word Address Slave Address slileli fofofo fo o JA forze os oa fes a t ino a 1 o v o Jojo fo 1 ja A H A Ao Start EE ET EN RW 0 Restart RW esre u Sege u sep u omerco wr A Slave acknowledgement M Master acknowledgement S P Start stop condition Figure 3 13 EEPROM Interface Doubleword Data Collection 3 6 3 Serial Bus EEPROM Application When the PCI bus is reset and the serial bus interface is detected the PCI4410 attempts to read th
14. W13 195 VCCCB 138 174 A12 H19 Clamp voltage for PC Card interface Matches card signaling environment 5 V or 3 3 V VCCI 79 Ro Clamp voltage for miscellaneous VO signals MFUNC GRST and SUSPEND VCCL Veer om f7 Clamp voltage for 1394 link function 34 60 M1 V6 Clamp voltage for PCI interface ZV interface SPKROUT INTA INTB LED SKT VCCP VCCDO VCCD1 VPPDO VPPD1 Table 2 6 PC Card Power Switch Terminals ET DESCRIPTION CEA VCCDO 121 M18 VCCD1 m Logic controls to the TPS2211 PC Card power interface switch to control AVCC VPPDO 87 V12 A VPPD1 ESEHET Logic controls to the TPS2211 PC Card power interface switch to control AVPP Table 2 7 PCI System Terminals NEER DESCRIPTION EE Global reset When the global reset is asserted the GRST signal causes the PCI4410 to place all output buffers in a high impedance state and reset all internal registers When GRST is asserted the device is completely in its default state For systems that require wake up from D3 GRST will normally be asserted GRST only during initial boot PRST should be asserted following initial boot so that PME context is retained when transitioning from D3 to DO For systems that do not require wake up from D3 GRST should be tied to PRST When the SUSPEND mode is enabled the device is protected from the GRST and the internal registers are preserved All outputs are placed in a high impedance state but the contents of the registers
15. ZEROWAIT R W 0 8 and 16 bit cycles have standard length default 1 8 bit cycles are reduced to equivalent of three ISA cycles 16 bit cycles are reduced to equivalent of two ISA cycles SCRATCH Scratch pad bits Bits 5 and 4 have no effect on memory window operation 3 0 STAHN RW Start address high nibble Bits 3 0 represent the upper address bits A23 A20 of the memory window start address 5 15 5 15 ExCA Memory Windows 0 4 End Address Low Byte Registers These registers contain the low byte of the 16 bit memory window end address for memory windows 0 1 2 3 and 4 The 8 bits of these registers correspond to bits A19 A12 of the end address to 7 6 8 4 3s 2 1 o0 Name ExCA memory windows 0 4 end address low Register EXCA memory window 0 end address low byte Offset CardBus socket address 812h ExCA offset 12h Register ExCA memory window 1 end address low byte Offset CardBus socket address 81Ah ExCA offset 1Ah Register ExCA memory window 2 end address low byte Offset CardBus socket address 822h ExCA offset 22h Register ExCA memory window 3 end address low byte Offset CardBus socket address 82Ah ExCA offset 2Ah Register ExCA memory window 4 end address low byte Offset CardBus socket address 832h ExCA offset 32h Type Read Write Default 00h Size One byte 5 16 ExCA Memory Windows 0 4 End Address High Byte Registers These registers contain the high nibble of the 16
16. co me ma 7 eer aos Ks for we we ws 183 rs oorsee 75 Po mo e fono er co wrunco 76 wio faso eo Pia ias vo pe er es wrunce so eo Senn 5 es is o ot fons us Kis wruncs sa em SUSPEND es mz mona 15 es oataio isa ce rena so Ps voc es wr coms i7 rie patma iso ra pay patno 200 06 vec ee 7 Table 2 4 16 Bit PC Card Signal Names Sorted Alphabetically to GHK PDV Terminal Number Continued TERM NO TERM NO TERM NO SIGNAL NAME SIGNAL NAME SIGNAL NAME SIGNAL NAME Pov GHK Pov GHK Pov GHK voo e es wen er we mcrax 120 m7 mcum ue wr voe iss ar ver ee pui zv so ma eo zv vse se via voces ma ave vez ies es oo os er vv ou co um me war us oo neuve ue we zevo 99 wis The terminals are grouped in tables by functionality such as PCI system function and power supply function see Table 2 5 through Table 2 17 The terminal numbers are also listed for convenient reference Table 2 5 Power Supply Terminals TERMINAL Me es es 6 22 38 58 74 A5 A15 E1 E11 100 126 142 H15 J5 L15 M5 Device ground terminals 162 178 203 P14 R9 W5 DESCRIPTION 14 30 46 66 91 115 134 A7 A13 B9 F17 G1 J18 L2 M14 Power supply terminal for core logic 3 3 V 150 170 186 P3 W7
17. pilota mir m ee eee miss mis M RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Cai Physical request filter low Cc a peau o o o fo fo Jo fo 1 o Jo 19 o Jo oo od o Register Physical reguest filter low Type Read Set Clear Offset 118h set register 11Ch clear register Default 0000 0000h Table 9 27 Physical Request Filter Low Register SIGNAL TYPE FUNCTION If set to 1 for local bus node number 31 then physical requests received by the PCI4410 PHYSREQRESOURCE31 from that node are handled through the physical request context If set to 1 for local bus node number 30 then physical requests received by the PCI4410 SR from that node are handled through the physical request context Bits 29 through 2 follow the same pattern If setto 1 forlocal bus node number 1 then physical requests received by the PCI4410 from Eno OER that node are handled through the physical reguest context If setto 1 for local bus node number 0 then physical requests received by the PCI4410 from PHYSREQRESOURCFO that node are handled through the physical request context 9 36 Physical Upper Bound Register Optional Register This register is an optional register and is not implemented This register is read only and returns all Os Bit 31 30 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 Physical upper bound Register Physi
18. 1 Power Supply Sequencing uis xut sn re ka webs REEN EG KA GANA sA 3 1 di VO Characteristics is ens EER ER pis BE EE DE pes KALA ERR ER 3 1 3 3 Clamping Voltages ss sis EER AGANG pa Genes cath to E RADI hen E 3 2 3 4 Peripheral Component Interconnect PCI Interface 3 2 3 4 1 POI Bus hock LOCK iis odo eX e ERE e RE e EORR KA 3 2 3 4 2 Loading Subsystem Identification 3 3 3 5 PO Gard ApBICAlIODS 5 2 021 93 BA pps Asas RA WR DER EE 3 3 3 5 1 PC Card Insertion Removal and Recognition 3 3 3 5 2 P2C Power Switch Interface TPS2211 3 4 3 5 3 Zoomed Video Support Zeie es teer REC icem 3 5 3 5 4 Ultra Zoomed Ven 3 6 3 5 5 Da STAT Terminal oie ESSEN ay PE PE RS Pain 3 6 3 5 6 Internal Ring Oscillator 3 6 3 5 7 Integrated Pullup Resistors for PC Card Interface 3 6 3 5 8 SPKROUT and CAUDPWM Usage 3 7 3 5 9 LED Socket Activity Indicators 93 ves ber nn 3 7 3 5 10 PC Card 16 Distributed DMA Support 3 8 3 5 11 PC Card 16 PC PCI DMA si speek kv a ER REY Ric 3 10 3 5 12 CardBus Socket Registers uuuuusuuu 3 10 3 6 Serial Bus InlBrfdbb iusso qot RE DES DEE EER ERR EHE NG SE 3 11 3 6 1 Serial Bus Interface Implementation 3 11 3 6 2 Serial Bus Interface Protocol 0005 3 11 3 6 3 Serial Bus EEPROM Application ssssee 3 13 3 6 4 Accessing Serial Bus Devices Through Softw
19. 17 Power Management Control Status Register SIGNAL TYPE FUNCTION PME status Bit 15 is set when the CardBus function would normally assert PME independent 15 PMESTAT R C ofthe state of bit8 PME EN Bit 15 is cleared by a writeback of 1 and this also clears the PME signal if PME was asserted by this function Writing a O to this bit has no effect Data scale This 2 bit field returns Os when read The CardBus function does not return any TRIS DATASCALE ES dynamic data as indicated by bit 4 DYN DATA PME EN DATASEL Data select This 4 bit field returns Os when read The CardBus function does not return any dynamic data as indicated by bit 4 DYN DATA PME EN PME EN PME enable When set to 1 bit 8 enables the function to assert PME When reset to 0 the assertion of PME is disabled RSVD Reserved Bits 7 5 return Os when read Dynamic data PME enable Bit 4 returns 0 when read because the CardBus function does not DIN RTA ME EN EM report dymanic data RSVD R Reserved Bits 3 2 return Os when read Power state This 2 bit field is used both to determine the current power state of a function and to set the function into a new power state This field is encoded as 00 DO PWR STATE 01 D1 10 D2 11 D3hot 4 29 4 43 Power Management Control Status Register Bridge Support Extensions The power management control status register bridge support extensions support PCI bridge specific functionality See Table 4 18 f
20. 19 4 31 4 32 4 33 4 34 4 35 4 36 4 37 4 38 4 39 4 40 4 41 4 42 4 43 444 4 45 4 46 4 47 4 48 General Control Register ses use EEUE R EES rm RE DRR e Ed pas Multifunction Routing Register s recede cR Ee PER yeh Retry Status Register Card Control Register EER ER d aate o d EES ID RR eee Device Control Register Diagnostic Register is naa BEES ARE KRRSRR ERE RLTE ER ERR E E REGE Socket DMA Register Ds si seke SEER damas Eos na nicae Socket DMA Register Capability ID Register SERE EE KANA AN eder re ER E aes Next Item Pointer Register isi RE RR eee eee eee eee ee Power Management Capabilities Register Power Management Control Status Register Power Management Control Status Register Bridge Support de ies iere dues dep wa Via AG N EER Power Management Data Register ssuuuuu General Purpose Event Status Register General Purpose Event Enable Register General Purpose Input Register aa General Purpose Output Register 5 ExCA Compatibility Registers cece eee cence eens 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 5 10 5 11 5 12 5 13 5 14 5 15 5 16 5 17 5 18 5 19 5 20 5 21 5 22 5 23 ExCA Identification and Revision Register ExCA Interface Status Register ExCA Power Control Register ExCA Interrupt and General Control Regi
21. 3 Socket Present State Register 0a 6 4 Socket Force Event Register ed es ence eee 6 6 Socket Control Register 6 7 Socket Power Management Register 6 8 Distributed DMA Registers SEI ee pr rue RR ER DEE ig RE Gem 7 1 DDMA Command Register se EE Se EE eee ee Red ee ee 7 3 DDMA Status Register die rem SEN varie EE He ECCE EORR E RE ORES E 7 3 DDMA Mode Register sucre EES eee pais mede Rr tax bes 7 4 DDMA Multichannel Mask Register 7 5 Bit Field Access Tag Descriptions 8 1 PCI Configuration Register Map SNE ENER RR hahaa aa 8 1 PCI Command Register ARE ege err feine Ber d E bate dad 8 3 POI Status Register ass EE aii NEE RERO RR IRR cR RE 8 4 xi N N N NN NN NN ch ch sch ck ch sch ad ad zk OO ON a O OD JO Oo P ob O O DNA OH ON AO Class Code and Revision ID Register 8 5 Latency Timer and Class Cache Line Size Register 8 5 Header Type and BIST Register 8 6 Open HCI Registers Base Address Register 8 6 TI Extension Base Address Register Lisuuuuu 8 7 PCI Subsystem Identification Register EE EE a 8 8 Interrupt Line and Interrupt Pin Registers 8 9 MIN GNT and MAX LAT Registers 8 9 Capability ID and Next Item Pointer Registers 8 10 Power Management Capabilities Register 8 11 Power Management Control and Status Register
22. 32 Multifunction Routing Register for configuration details Multifunction terminal 3 MFUNCS can be configured as a parallel IRQ or the serialized interrupt signal IRQSER See Section 4 32 Multifunction Routing Register for configuration details Multifunction terminal 4 MFUNCA can be configured as PCI LOCK GPI3 GPOS socket activity LED output ZV switching outputs CardBus audio PWM GPE RI OUT or a parallel IRQ See Section 4 32 Multifunction Routing Register for configuration details Serial clock SCL When VCCDO and VCCD 1 are high after a PCI reset the MFUNCA terminal provides the SCL signaling for the serial bus interface The two terminal serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset See Section 3 6 1 Serial Bus Interface Implementation for details on other serial bus applications Multifunction terminal 5 MFUNC5 can be configured as PC PCI DMA grant GPI4 GPO4 socket activity LED output ZV switching outputs CardBus audio PWM GPE or a parallel IRQ See Section 4 32 Multifunction Routing Register for configuration details Multifunction terminal 6 MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ See Section 4 32 Multifunction Routing Register for configuration details Ring indicate out and power management event output Terminal provides an output for ring indicate or PME signals Speaker output SPKROUT is the output to the host s
23. AE AE AE x J x Bit 1 um 13 12 v 10 9 8 7 toe fs Ja j 3 2 t 0 m SormeswdwweimkWh peau X x X X X x x x x Px x Xx tx x tx x Register ISO receive channel mask high Type Read Set Clear Offset 70h set register 74h clear register Default XXXX XXXXh Table 9 13 ISO Receive Channel Mask High Register SIGNAL TYPE FUNCTION KO 31 ISOCHANNEL63 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 63 30 ISOCHANNEL62 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 62 29 ISOCHANNEL61 RSC When setto 1 the PCI4410 is enabled to receive from ISO channel number 61 ISOCHANNEL60 ISOCHANNEL59 When set to 1 the PCI4410 is enabled to receive from ISO channel number 60 IW q N o H C pol n O When set to 1 the PCI4410 is enabled to receive from ISO channel number 59 26 ISOCHANNEL58 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 58 25 ISOCHANNEL57 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 57 24 ISOCHANNEL56 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 56 23 ISOCHANNEL55 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 55 ISOCHANNEL54 N N H CD When set to 1 the PCI4410 is enabled to receive from ISO channel number 54 21 ISOC
24. BE3 applies to byte 3 AD31 AD24 PCI bus parity In all PCI bus read and write cycles the PCI4410 calculates even parity across the AD31 ADO and C BE3 C BEO buses As an initiator during PCI cycles the PCI4410 outputs this parity indicator with a one PCLK delay As a target during PCI cycles the calculated parity is compared to the initiator s parity indicator A compare error results in the assertion of a parity error PERR 2 13 Table 2 9 PCI Interface Control Terminals nem DESCRIPTION fa PCI device select The PCI4410 asserts DEVSEL to claim a PCI cycle as the target device As a PCI initiator DEVSEL VO on the bus the PCI4410 monitors DEVSEL until a target responds If no target responds before timeout occurs then the PCI4410 terminates the cycle with an initiator abort PCI cycle frame FRAME is driven by the initiator of a bus cycle FRAME is asserted to indicate that a bus transaction is beginning and data transfers continue while this signal is asserted When FRAME is deasserted the PCI bus transaction is in the final data phase PCI bus grant GNT is driven by the PCI bus arbiter to grant the PCI4410 access to the PCI bus after the current data transaction has completed GNT may or may not follow a PCI bus request depending on the PCI bus parking algorithm IDSEL 29 L1 Initialization device select IDSEL selects the PCI4410 during configuration space accesses IDSEL can be connected to one of the upper 24 PC
25. Characteristics 10 1 Absolute Maximum Ratings Over Operating Temperature Rangest Supply voltage range Ve Clamping voltage range Veeep Veci Voel VOOR HEER aaa aaa Input voltage range V PC Ieri RE EN RE EN EE EE OCT Failsafe eee Miscellaneous and PHY IFE Output voltage range Vg PC III GANAS Es AE gcse hod ee eae TIE T FalliSdfG sens daa ae dor te ae eel oun ee dak oben eds Miscellaneous and PHY I F ses essen Input clamp current lik Vis 0 or Vj 5 Voc see Note 1 eee eee Output clamp current low Vo lt 0 or Va gt Voo see Note 2 ike ENG GR ais adnan o ea 20 mA Storage temperature range Teig sesse sees see RR RR EE RR e Virtual junction temperature TI TORT 0 5 V to 4 6 V gee EE 0 5 Vto 6 V 0 5 V to Vccp 0 5 V 0 5 V to Veca 0 5 V 0 5 V to Vee 0 5 V 70 5 V to Vcc 0 5 V 0 5 V to Vee 0 5 V 0 5 V to Vee 0 5 V 70 5 V to Vcc 0 5 V 0 5 V to VccA 0 5 V 0 5 V to Veg 0 5 V 0 5 V to Vcc 0 5 V 0 5 V to Vee 0 5 V 0 5 V to Vcc 0 5 V ETER OT 20 mA TT 65 to 150 C TT 150 C t Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated condition
26. Context Command Pointer Register SIGNAL TYPE FUNCTION DESCRIPTORADDRESS Contains the upper 28 bits of the address of a 16 byte aligned descriptor block Indicates the number of contiguous descriptors at the address pointed to by the descriptor address If Z is 0 it indicates that the descriptorAddress is not valid 9 34 9 39 Isochronous Transmit Context Control Register This set clear register controls options state and status for the isochronous transmit DMA contexts The n value in the following register addresses indicates the context number n 0 1 2 3 See Table 9 30 for a complete description of the register contents ERE RM Isochronous transmit context control rame RSCU RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC EE X X X X X X asana TERTE LIT context control RSC U Deut 0 o o x fo fo fof ot x Px xt xi xt xt xt x Register Isochronous transmit context control Type Read Set Clear Update Read Set Clear Read only Read Update Offset 200h 16 n set register 204h 16 n clear register Default XXXX X0XXh Table 9 30 Isochronous Transmit Context Control Register SIGNAL TYPE FUNCTION When setto 1 processing will occur such that the packet described by the first descriptor block ofthe contextistransmitted in the cycle whose number is specified in the CYCLEMATCH field of OVCLEMATCHENABLE this register The 13 bit CYCLEMATC
27. DCH 10h 14h 18h 1Ch 20h 6 1 Socket Event Register The socket event register indicates a change in socket status has occurred These bits do not indicate what the change is only that one has occurred Software must read the socket present state register see Section 6 3 for current status Each bit in this register can be cleared by writing a 1 to that bit The bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register see Section 6 4 All bits in this register are cleared by PCI reset They can be immediately set again if when coming out of PC Card reset the bridge finds the status unchanged that is CSTSCHG reasserted or card detect is still true Software must clear this register before enabling interrupts If itis not cleared when interrupts are enabled then an interrupt is generated but not masked based on any bit set See Table 6 2 for a complete description of the register contents 29 28 27 26 25 24 23 22 21 20 t9 18 i7 16 Name PO Soketevent Te n R R RJ JR RJ JR R R R R Jn JR R JR J R petan o o o jo o fo fo fo fo fo jo fo fo fo jojo et us 14 13 r2 vt 10 9 8 v e j s ja ts 2 1 fo Name o SoWeteen LEES KEER SE SE MAA AAK Wm AE N NO NE pest o po 6 ole o Je e e 5 la po po pa Te Register Socket event Type Read only Read Write to Clear Offset CardBus socket address 00h D
28. ExCA offset 1Eh 5Eh 81Eh and defaults to the flag cleared on read method 3 17 The CardBus related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register see Section 6 1 Although some of the functionality is shared between the CardBus registers and the EXCA registers software should not program the chip through both register sets when a CardBus card is functioning 3 7 8 Using Parallel IRQ Interrupts The seven multifunction terminals MFUNC6 MFUNCO implemented in the PCI4410 may be routed to obtain a subset of the ISA IRQs The IRQ choices provide ultimate flexibility in PC Card host interruptions To use the parallel ISA type IRQ interrupt signaling software must program the device control register see Section 4 35 located at PCI offset 92h to select the parallel IRQ signaling scheme See Section 4 32 Multifunction Routing Register for details on configuring the multifunction terminals A system using parallel IRQs requires a minimum of one PCI terminal INTA to signal CSC events This requirement is dictated by certain card and socket services software The MFUNC pins provide at a maximum seven different IRQs to support legacy 16 bit PC Card functions As an example suppose the seven IRQs used by legacy PC Card applications are IRQ3 IRQ4 IRQ5 IRQ9 IRQ10 IRQ11 and IRQ15 The multifunction routing register must be programmed to a value of OXOFBA5439 This routes the MFUNC
29. FUNCTION Power management data This bit field returns Os when read because the PCI4410 does not report PM DATA dynamic data Power management CSR bridge support extensions This field returns 0s because the PCI4410 does PMCSR BSE not provide P to P bridging 8 13 8 20 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCl related configuration See Table 8 17 for a complete description of the register contents Bit 31 3o 29 28 27 26 25 2a 23 22 2t 20 19 18 17 16 PCI miscellaneous configuration iscellaneous configuration Register PCI miscellaneous configuration Type Read only Read Write Offset FOh Default 0000 2400h Table 8 17 PCI Miscellaneous Configuration Register BIT SIGNAL TYPE FUNCTION 31 16 RSVD R Reserved These bits return 0s when read PME support from D3cold This bit is used to program the corresponding read only value read 15 PME D3COLD RAW from power management capabilities This bit retains state through PCI reset and D3 DO transitions 14 RSVD Reserved This bit returns 0 when read PME support This bit is used to program the corresponding read only value read from power management capabilities If wake up from the D2 power state implemented in PCI4410 is not desired then this bit may be reset to 0 to indicate to power management software that wake up from D2 is not supported This bit r
30. Link Interface Terminals FUNCTION PHY link interface control These bidirectional signals control passage of information between the PHY and link The link can only drive these terminals after the PHY has granted permission following a link request LREQ PHY link interface data These bidirectional signals pass data between the PHY and link These terminals are driven by the link on transmissions and are driven by the PHY on receptions Only DATA1 DATAO are valid for 100 Mbit speed DATA4 DATAO are valid for 200 Mbit speed and DATA7 DATAO are valid for 400 Mbit speed System clock This input provides a 49 152 MHz clock signal for data synchronization Link request This signal is driven by the link to initiate a request for the PHY to perform some service 1394 link on This input from the PHY indicates that the link should turn on Link power status LPS indicates that link is powered and fully functional Table 2 17 Zoomed Video Interface Terminals Horizontal sync to the zoomed video port Vertical sync to the zoomed video port Video data to the zoomed video port in YUV 4 2 2 format Video data to the zoomed video port in YUV 4 2 2 format 2 21 2 22 3 Feature Protocol Descriptions The following sections give an overview of the PCI4410 Figure 3 1 shows connections to the PCI4410 The PCI interface includes all address data and control signals for PCI protocol The interrupt interface includes terminals for parall
31. Memory window page 1 Memory window page 2 Memory window page 3 Memory window page 4 5 1 ExCA ldentification and Revision Register The ExCA identification and revision register provides host software with information on 16 bit PC Card support and Intel 82365SL DF compatibility This register is read only or read write depending on the setting of bit 5 SUBSYSRW in the system control register see Section 4 29 See Table 5 2 for a complete description of the register contents Bg v7 j e s j 4 3 2 1 90 Name ExCA identification and revision we 8 A AW am w AW w w peau 14 o o o o 1 o o Register ExCA identification and revision Type Read only Read Write Offset CardBus socket address 800h ExCA offset 00h Default 84h Table 5 2 ExCA Identification and Revision Register 7 6 IETYPE Interface type These bits which are hardwired as 10b identify the 16 bit PC Card support provided by the PC14410 The PCI4410 supports both VO and memory 16 bit PC cards Intel 82365SL DF revision This field stores the Intel 82365SL DF revision supported by the PCI4410 Host 3 0 365REV R W software can read this field to determine compatibility to the Intel 82365SL DF register set Writing 0010b to this field puts the controller in 82365SL mode This field defaults to 0100b upon PCI4410 reset 5 4 5 2 ExCA Interface Status Register The ExCA interface status register pro
32. PC Card Interface System Terminals E T DESCRIPTION Ek CardBus clock CCLK provides synchronous timing for all transactions on the CardBus interface All signals except CRST CCLKRUN CINT CSTSCHG CAUDIO CCD2 CCD1 CVS2 and CVS1 are CCLK sampled on the rising edge of CCLK and all timing parameters are defined with the rising edge of this signal CCLK operates at the PCI bus clock frequency but it can be stopped in the low state or slowed down for power savings CGLKRUN 184 F10 lO CardBus clock run CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency and by the PCI4410 to indicate that the CCLK frequency is going to be decreased CardBus reset CRST brings CardBus PC Card specific registers sequencers and signals to a known TRST 167 F12 state When CRST is asserted all CardBus PC Card signals are placed in a high impedance state and the PCI4410 drives these signals to a valid logic level Assertion can be asynchronous to CCLK but deassertion must be synchronous to CCLK Table 2 14 CardBus PC Card Address and Data Terminals TERMINAL HELM DESCRIPTION CardBus address and data These signals make up the multiplexed CardBus address and data bus on the CardBus interface During the address phase of a CardBus cycle CAD31 CADO contain a 32 bit address During the data phase of a CardBus cycle CAD31 CADO contain data CAD31 is the most significant bit CardBus bus commands and byte enables CC BE
33. PCI bridge secondary status register and indicates CardBus related device information to the host system This register is very similar to the PCI status register offset 06h status bits are cleared by writing a 1 See Table 4 4 for a complete description of the register contents EE AE RE AU AE BE AKA AK AE 0869s pos qos ALA Secondary status o oo Secondary status Type RCc RC RC RC ne rR R Ro R Jn R n AR R RR pea o o o fo fo fo 1110 Jo To To To To Jo To fo Register Secondary status Type Read only Read Write to Clear Offset 16h Default 0200h Table 4 4 Secondary Status Register SIGNAL TYPE FUNCTION CBPARITY Detected parity error Bit 15 is set when a CardBus parity error is detected either address or data Signaled system error Bit 14 is set when CSERR is signaled by a CardBus card The PCI4410 does not 13 CBMABORT RIC Received master abort Bit 13 is set when a cycle initiated by the PCI4410 on the CardBus bus has been terminated by a master abort Received target abort Bit 12 is set when a cycle initiated by the PCI4410 on the CardBus bus is terminated Signaled target abort Bit 11 is set by the PCI4410 when it terminates a transaction on the CardBus bus SIG_CBTA with a target abort cs SPEED SPEED ER timing These bits encode the timing of CDEVSEL and are hardwired 01b indicating that the ERE 0 asserts CB SPEED at a medium speed CardBus data parity error detected O The conditi
34. PCI clock The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA INTB INTC and INTD For details on the IRQSER protocol refer to the document Serialized IRQ Support for PCI Systems 3 7 6 SMI Support in the PCI4410 The PCI4410 provides a mechanism for interrupting the system when power changes have been made to the PC Card socket interfaces The interrupt mechanism is designed to fitinto a system maintenance interrupt SMI scheme SMI interrupts are generated by the PCI4410 when enabled after a write cycle to either the socket control register see Section 6 5 of the CardBus register set or the ExCA power control register see Section 5 3 The SMI control is programmed through three bits in the system control register see Section 4 29 These bits are SMIROUTE bit 26 SMISTATUS bit 25 and SMIENB bit 24 Table 3 9 describes the SMI control bits function Table 3 9 SMI Control BIT NAME FUNCTION SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2 SMISTAT This socket dependent bit is set when an SMI interrupt is pending This status flag is cleared by writing back a 1 SMIENB When set SMI interrupt generation is enabled If CSC SMI interrupts are selected then the SMI interrupt is sent as the CSC The CSC interrupt can be either level or edge mode depending upon the CSCMODE bit in the ExCA global control register see Section 5 22
35. Ring Oscillator The internal ring oscillator provides an internal clock source for the PCI4410 so that neither the PCI clock nor an external clock is required in order for the PCI4410 to power down a socket or interrogate a PC Card This internal oscillator operates nominally at 16 kHz and can be enabled by setting bit 27 P2CCLK of the system control register see Section 4 29 at PCI offset 80h to a 1 This function is disabled by default 3 5 7 Integrated Pullup Resistors for PC Card Interface The 1997 PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16 bit card configurations Unlike the PCI1210 1211 which required external pullup resistors the PCI4410 has integrated all of these pullup resistors on the terminalss below except for the CCLKRUN WP IOIS16 pullup resistor 3 6 SIGNAL NAME Cen em BVD1 STSCHG CSTSCHG WE OISTSJGLKRUN t This pin requires pullup but the PC11451 lacks an integrated pullup resistor 3 5 8 SPKROUT and CAUDPWM Usage SPKROUT carries the digital audio signal from the PC Card to the system When a 16 bit PC Card is configured for VO mode the BVD2 pin becomes SPKR This terminal is also used in CardBus binary audio applications and is referred to as CAUDIO SPKR passes a TTL level digital audio signal to the PCI4410 The CardBus CAUDIO signal also can pass a single amplitude binary waveform The binary audio signals from the PC Card socket is used in the PCI4410 t
36. Table 2 1 CardBus and 16 Bit PC Card Signal Names by PDV Terminal Number Continued Os oor ions 168 oam Jee 195 fico leo Mass lessa aner es ommo fezes oi 156 CCLK ADDR16 183 CSTSCHG BVD1 STSCHG RI 2 5 TERM NO A4 2 o A6 gt q A8 A10 A11 A12 A13 A14 A15 A16 B5 B7 B8 B10 B11 B12 B13 B14 B15 C5 C6 C7 C8 C9 C10 C11 C12 cia C14 C15 D1 D19 m E2 E3 E6 E7 EE E EM Es Mo LAT An A LATA AIS AR E EM P P Bo B10 Bn B12 WER 814 PS EM ce om EM EN cto EE EN EN CSS cts ELM D19 EM Es EM e 2 6 Table 2 2 CardBus and 16 Bit PC Card Signal Names by GHK Terminal Number SIGNAL NAME TERM CARDBUS 16 BIT NO PHY_DATA6 PHY_DATA6 ND GND LINKON LINKON V 0 CC CD C Oh O 2 c is O el ei CINT CAD24 ADDR2 Vc gt e O D o 8 9 GG 2 No oc PR OTL GND GND cel o eo W C lt iw SIGNAL NAME CARDBUS 16 BIT PHY_LREQ PHY_LREQ CAD29 DATA CSTSCHG BVD1 _ STSCHG RI GND INPACK G CREQ CVS2 CFRAME ADDR23 ADDR21 ADDR20 ADDR19 PHY RSVD PHY RSVD PHY RSVD PHY RSVD PHY DATA2 PHY CTL 1 LPS DATA8 WP CDEVSEL CSTOP CBLOCK PHY RSVD PHY RSVD PHY RSVD PHY RSVD PHY DATA2 We N N LPS ki gt O ine CO CCLKRUN CVS1 D PHY CTL 1 ADDR12 ADDR14 CPERR CGNT Vcc Vcc CRSVD A
37. a 64 Kbyte page and the upper 16 bits 31 16 are a page register which locates this 64 Kbyte page in 32 bit PCI VO address space Bits 31 2 are read write Bits 1 and O are read only and always return Os forcing I O windows to be aligned on a natural doubleword boundary NOTE Either the I O base or the I O limit register must be nonzero to enable any VO transactions 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VO base registers 0 1 Name lObmeregsesO i Default o VO base registers 0 1 Name EE EE EE EE EET N e o 5 po po MERE RE TE MERE AE NEAR TA AE S Register VO base registers 0 1 Type Read only Read Write Offset 2Ch 34h Default 0000 0000h 4 22 VO Limit Registers 0 1 The VO limit registers indicate the upper address of a PCI VO address range These registers are used by the PCI4410 to determine when to forward an I O transaction to the CardBus bus and when to forward a CardBus cycle to PCI The lower 16 bits of this register locate the top of the VO window within a 64 Kbyte page and the upper 16 bits are a page register that locates this 64 Kbyte page in 32 bit PCI VO address space Bits 15 2 are read write and allow the VO limit address to be located anywhere in the 64 Kbyte page indicated by bits 31 16 of the appropriate VO base on doubleword boundaries Bits 31 16 are read only and always return Os when read The page is set in the I O base register Bits 1
38. and 0 are read only and always return Os forcing I O windows to be aligned on a natural doubleword boundary Write transactions to read only bits have no effect The PCI4410 assumes that the lower 2 bits of the limit address are 1s NOTE The VO base or the VO limit register must be nonzero to enable an VO transaction imit registers 0 ame type sw mw nw Aw AW nw Aw Aw Aw ema o fo jo Register VO limit registers 0 1 Type Read only Read Write Offset 30h 38h Default 0000 0000h 4 23 Interrupt Line Register The interrupt line register communicates interrupt line routing information m p s 3s 1 To Name SSCS Hye RW RW RW RW RW Rw RW RW peau 1 4 4 j Te Register Interrupt line Type Read Write Offset 3Ch Default FFh 4 24 Interrupt Pin Register The value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode selected through bits 2 1 INTMODE field of the device control register see Section 4 35 The PCI4410 defaults to serialized PCI and ISA interrupt mode to 7 e s 4 2 Jj 1 0 Interrupt pin Name Tee R R R R R R petan o o o o o o Register Interrupt pin Type Read only Offset 3Dh Default 01h 4 13 4 25 Bridge Control Register The bridge control register provides control over various PCI4410 bridging functions See
39. and changes on these signals during this operation are not reflected in this register See Table 6 4 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Socket present state Te n R R RJ R RJ R RJ JR R RJ R R R RJ R petan o e s 14 lo 30 30 o lo be WETE RE AK AKA et as 14 13 r2 vt 30 9 8 v e j s ja da 2 1 Jo Socket present state DO Socket present state 000000 mwe n R R RJ JR RJ JR R R R R JR JR R JR J R peam 0 o fo fo fo fo fo fo fo fx fo fo fo fx fx x Register Socket present state Type Read only Offset CardBus socket address 08h Default 3000 00XXh Table 6 4 Socket Present State Register SIGNAL TYPE FUNCTION 34 YVSOCKET YV socket Bit 31 indicates whether or not the socket can supply Vcc Y Y V to PC Cards The PCI4410 does not support Y Y V Vcc therefore this bit is hardwired to 0 30 XVSOCKET XV socket Bit 30 indicates whether or not the socket can supply Vcc X X V to PC Cards The PCI4410 does not support X X V Vcc therefore this bit is hardwired to 0 3 V socket Bit 29 indicates whether or not the socket can supply Vcc 3 3 V to PC Cards The PCI4410 29 3VSOCKET does support 3 3 V Vcc therefore this bit is always set unless overridden by the socket force event register see Section 6 4 5 V socket Bit 28 indicates whether or not the socket can supply Vcc 5 V to P
40. are 70 62 59 60 61 64 65 67 68 and 69 for the PGE packaged device L11 M9 L8 K8 N9 K9 N10 L10 N11 and M11 for the GGU packaged device and W12 U10 P9 W10 V10 P10 W11 U11 P11 and R11 for the GHK packaged device SUSPEND SPKROUT RI OUT multifunction terminals MFUNCO MFUNCS and power switch control terminals Fail safe terminals are 75 117 131 and 137 for the PGE packaged device L12 D9 C6 and A4 for the GGU packaged device and L19 E13 F11 and A9 for the GHK packaged device card detect and voltage sense pins T Applies to external output buffers These junction temperatures reflect simulation conditions The customer is responsible for verifying junction temperature NOTE 3 Unused terminals input or VO must be held high or low to prevent them from floating 10 2 10 3 Electrical Characteristics Over Recommended Operating Conditions unless PC Card VOH High level output voltage PHY I F otherwise noted PARAMETER OPERATION TEST CONDITIONS PC Card V Low level output voltage OL S 4 PHY I F TTL SERR 3 state output high impedance state Output OZL output current see Note 4 terminals A 3 state output high impedance state 8 Output Vis Vect A OZH output current terminals 5 25V Vi Vccf IL Low level input current TEE V GND H Input VisVect EDE HH High level input current inal 281 uA ome sav fv veci Fail safe T For PCI pins Vj Vccp Fo
41. assignments for the 208 terminal PDV CardBus and 16 bit PC Card signal names Table 2 2 shows the terminal assignments for the 209 ball GHK CardBus and 16 bit PC Card signal names Table 2 3 shows the CardBus PC Card signal names sorted alphabetically to the GHK PDV terminal numbers Table 2 4 shows the 16 bit PC Card signal names sorted alphabetically to the GHK PDV terminal numbers 2 3 Table 2 1 CardBus and 16 Bit PC Card Signal Names by PDV Terminal Number hax cx NO mL AE S a a 2 Jemen emv nevo as Is av novo env Revo 46 vo Le qms PHY RSVD PHY RSVD PHY RSVD PHY RSVD EE C BE1 C BE1 P PHY RSVD PHY RSVD 54 ADS AD15 97 PHY RSVD PHY RSVD 55 AD14 AD14 98 PHY RSVD PHY RSVD EH AD13 AD13 po PHY_ ere PHY_ ere Em AD11 AD11 Zv Y 4 4 MCN AD29 AD29 RE C BEO C BEO ZV UM gt ZV_UV gt rx je e Le jr pw pw now non Do xs xs e ws ws 1 Ju we Ja we 5 ues anes a Dag EST ele Tanga nuo jug num lawa AD22 AD22 RI_OUT PME RI_OUT PME ZV_LRCLK ZV_LRCLK AD21 AD21 MFUNCO MFUNCO ZV_SDATA ZV_SDATA Vecp Vecp MFUNC1 MFUNC1 ZV PCLK ZV PCLK AD20 AD20 SPKROUT SPKROUT VCCDO VCCDO PRST PRST VcCI Veci VCCD1 VCCD1 AD19 AD19 GRST GRST CAD2 DATA11 AD17 AD17 MFUNC5 MFUNC5 CAD1 DATA4 AD16 AD16 MFUNC6 MFUNC6 CAD4 DATA12 C BE2 C BE2 86 SUSPEND SUSPEND CAD3 DATAS ZV HREF ZV HREF ZV VSYNC ZV VSYNC ZV_Y 0 ZV_Y 0 ZN vu AN vu ZV Y 2 N m lt D BE 5 N lt sIslaxixl 2 4
42. bit memory window end address for memory windows 0 1 2 3 and 4 The lower 4 bits of these registers correspond to bits A23 A20 of the end address In addition the memory window wait states are set in this register See Table 5 12 for a complete description of the register contents st 7 6 5 4 3 2 1 o Name ExCA memory windows 0 4 end address high byte mw mw am a A Aw w mmu o lo 9 o lo lo Register ExCA memory window 0 end address high byte Offset CardBus socket address 813h ExCA offset 13h Register ExCA memory window 1 end address high byte Offset CardBus socket address 81Bh ExCA offset 1Bh Register ExCA memory window 2 end address high byte Offset CardBus socket address 823h ExCA offset 23h Register ExCA memory window 3 end address high byte Offset CardBus socket address 82Bh ExCA offset 2Bh Register ExCA memory window 4 end address high byte Offset CardBus socket address 833h ExCA offset 33h Type Read only Read Write Default 00h Size One byte Table 5 12 ExCA Memory Windows 0 4 End Address High Byte Registers Wait state Bits 7 and 6 specify the number of equivalent ISA wait states to be added to 16 bit memory accesses The number of wait states added is equal to the binary value of these two bits RSVD R Reserved Bits 5 and 4 return Os when read ENDHN uem high nibble Bits 3 0 represent the upper address bits A23 A20 of the memory window end
43. controls the I O window 1 wait state for 8 bit VO accesses Bit 6 has no effect on 16 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 8 bit cycles have standard length default 1 8 bit cycles are reduced to equivalent of three ISA cycles ZEROWS1 VO window 1 IOIS16 source Bit 5 controls the VO window 1 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I O data transfer This bit is encoded as 0 Window data width determined by DATASIZE1 bit 4 default 1 Window data width determined by IOIS16 IOSIS16W1 VO window 1 data size Bit 4 controls the VO window 1 data size Bit 4 is ignored if bit 5 IOSIS16W1 is set This bit is encoded as DATASIZE1 RW S O Window data width is 8 bits default W 1 Window data width is 16 bits VO window 0 wait state Bit 3 controls the VO window 0 wait state for 16 bit VO accesses Bit 3 has no effect on 8 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 16 bit cycles have standard length default 1 16 bit cycles are extended by one equivalent ISA wait state WAITSTATEO VO window 0 zero wait state Bit 2 controls the VO window 0 wait state for 8 bit VO accesses Bit 2 has no effect on 16 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF Th
44. encoded as BATWARN O No battery warning condition default 1 Detected battery warning condition When a 16 bit VO card is installed bit 1 is always 0 BATDEAD RI E 5 8 5 6 ExCA Card Status Change Interrupt Configuration Register The ExCA card status change interrupt configuration register controls interrupt routing for card status change interrupts as well as masking CSC interrupt sources See Table 5 8 for a complete description of the register contents Br Jos qos EEE Name ExCA status change interrupt configuration SIGNAL TYPE FUNCTION Interrupt select for card status change Bits 7 4 select the interrupt routing for card status change interrupts 0000 CSC interrupts routed to PCI interrupts if bit 5 CSC of the diagnostic register is set to 1 see Section 4 36 In this case bit 4 CSCROUTE of the ExCA interrupt and general control register is a don t care see Section 5 4 This is the default setting 0000 No ISA interrupt routing if bit 5 CSC of the diagnostic register is set to 0 see Section 4 36 In this case CSC interrupts are routed to PCI interrupts by setting bit 4 CSCROUTE of the ExCA interrupt and general control register to 1 see Section 5 4 CSCSELECT This field is encoded as 0000 No interrupt routing default 1000 IRQ8 enabled 0001 IRQ1 enabled 1001 IRQ9 enabled 0010 SMI enabled 1010 IRQ10 enabled 0011 IRQ3 enabled 1011 IRQ11 enabled 0100 IRQ4 enabled 110
45. fast back to back transactions thus this bit FBB ENB returns 0 when read SERR ENB SERR enable When this bit is set to 1 the PCI4410 SERR driver is enabled SERR can be asserted after detecting an address parity error on the PCI bus Address data stepping control The PCI4410 does not support address data stepping and this bit is STEP ENB hardwired to 0 PERR ENB Parity error enable When this bit is set to 1 the PCI4410 is enabled to drive PERR response to parity errors through the PERR signal Memory write and invalidate enable When this bitis set to 1 the PCI4410 is enabled to generate MWI PCI bus commands If reset to O the PCI4410 will generate memory write commands instead Special cycle enable The PCI4410 does not respond to special cycle transactions This bit returns 0 when 3 SPECIAL Gad MASTER ENB Bus master enable When this bit is set to 1 the PCI4410 is enabled to initiate cycles on the PCI bus Memory response enable Setting this bit to 1 enables the PCI4410 to respond to memory cycles on the MEMORY ENE PCI bus This bit must be set to 1 to access OHCI registers IO ENB VO space enable The PCI4410 link does not implement any VO mapped functionality thus this bit returns O when read MWI ENB E VGA ENB ES VGA palette snoop enable The PCI4410 does not feature VGA palette snooping This bit returns 0 when read 8 3 8 5 PCI Status Register The PCI status register provides device information to t
46. in D3 This may be necessary to support wake on LAN or RING if the operating system is programmed to power down a socket when the CardBus controller is placed in the D3 state 3 V socket capable force 3VCAPABLE R W 0 Not 3 V capable 1 3 V capable default 5 IO16V2 Diagnostic bit This bit defaults to 1 Bus holder cell enable disable Setting bit 4 to 1 enables the bus holder cells on the 1394 link E BUS OE N an interface Default state is 0 bus holder cells disabled TEST TI test Only a 0 should be written to bit 3 Interrupt signaling mode Bits 2 and 1 select the interrupt signaling mode The interrupt signaling mode bits are encoded 00 Parallel PCI interrupts only d INTMOBE RAN 01 Parallel IRQ and parallel PCI interrupts 10 IRQ serialized interrupts and parallel PCI interrupt 11 IRQ and PCI serialized interrupts default 0 RSVD Reserved Bit 0 is reserved for test purposes Only 0 should be written to this bit 4 23 4 36 Diagnostic Register The diagnostic register is provided for internal TI test purposes In additon the diagnostic register can be used to control CSC interrupt routing enable asynchronous interrupts and alter the PCI vendor ID and device ID register fields See Table 4 13 for a complete description of the register contents BEI o pos ox p 35 x y 4 d w jJ Name J Wegen Diagnostic ma o o llo o lo to 1 1 Register Diagnostic Type Read Write Offset 93h Default
47. jJ t 0 Status E Type Ac Rc rc rc rc r r ro R R R R R R R R Bete O po 9 9 0 6 Asa 50 0 po p4 fo 5 o a Register Status Type Read Offset 06h only Read Write to Clear Default 0210h BIT SIGNAL TYPE 15 PAR ERR 11 TABT SIG DATAPAR R C FBB CAP UDF 4 4 Table 4 3 Status Register FUNCTION Detected parity error Bit 15 is set when a parity error is detected either address or data Signaled target abort Bit 11 is set by the PCI4410 when it terminates a transaction on the PCI bus with a target abort DEVSEL timing These bits encode the timing of DEVSEL and are hardwired 01b indicating that the PCI4410 asserts PCI SPEED at a medium speed on nonconfiguration cycle accesses Data parity error detected O The conditions for setting bit 8 have not been met 1 A data parity error occurred and the following conditions were met a PERR was asserted by any PCI device including the PCI4410 b The PCI4410 was the bus master during the data parity error c The parity error response bit is set in the command Fast back to back capable The PCI4410 cannot accept fast back to back transactions therefore bit 7 is hardwired to 0 User definable feature support The PCI4410 does not support the user definable features therefore bit 6 is hardwired to O 66 MHz capable The PCI4410 operates at a maximum PCLK frequency of 33 MHz therefore bit 5 is hardwired to 0 Capabilities l
48. po synchronous requestfiterhigh pea o Collette Register Asynchronous request filter high Type Read Set Clear Offset 100h set register 104h clear register Default 0000 0000h Bit 15 14 13 m2 n w0 9 8 7 e j s j 3 2 j t 0 Table 9 24 Asynchronous Request Filter High Register SIGNAL TYPE FUNCTION ASYNREQALLBUSES e all asynchronous requests received by the PCI4410 from nonlocal bus nodes are ASYNREQRESOURCE62 If set to 1 for local bus node number 62 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 61 asynchronous requests received by the PCI4410 ASYNBEQRESOURCEGI from that node are accepted If set to 1 for local bus node number 60 asynchronous requests received by the PCI4410 ASYNREORESOURCEGO from that node are accepted If set to 1 for local bus node number 59 asynchronous requests received by the PC14410 ASYNREQRESOURCES9 from that node are accepted from that node are accepted If set to 1 for local bus node number 56 asynchronous requests received by the PC14410 AS YNREQRESOURGESG from that node are accepted If set to 1 for local bus node number 55 asynchronous requests received by the PC14410 from that node are accepted If set to 1 for local bus node number 54 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 53 asynchronous
49. requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 52 asynchronous requests received by the PCI4410 from that node are accepted ASYNREQRESOURCE55 ASYNREQRESOURCE54 ASYNREQRESOURCE53 ASYNREQRESOURCE52 28 27 26 ASYNREQRESOURCES8 If set to 1 for local bus node number 58 asynchronous requests received by the PCI4410 from that node are accepted 25 ASYNREQRESOURCES7 If set to 1 for local bus node number 57 asynchronous requests received by the PCI4410 24 23 9 27 Table 9 24 Asynchronous Request Filter High Register Continued BIT SIGNAL TYPE ERLA ASYNREQRESOURCE34 RSC FUNCTION If set to 1 for local bus node number 51 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 50 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 49 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 48 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 47 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 46 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 45 asynchronous requests received by the PCI4410 fr
50. reserved registers shown in Table 7 1 are implemented as read only and return Os when read Write transactions to reserved registers have no effect Table 7 1 Distributed DMA Registers DDMA BASE TYPE REGISTER NAME ADDRESS OFFSET ES Reserved Reserved Base count o reserved LO NA Status osm serve RN m eve Request Command Reserved Reserved Ww Mask o 7 1 DDMA Current Address Base Address Register The DDMA current address base address register sets the starting base memory address of a DDMA transfer Read transactions from this register indicate the current memory address of a direct memory transfer For the 8 bit DDMA transfer mode the current address register contents are presented on AD15 ADO of the PCI bus during the address phase Bits 7 0 of the DDMA page register see Section 7 2 are presented on AD23 AD16 of the PCI bus during the address phase For the 16 bit DDMA transfer mode the current address register contents are presented on AD16 AD1 of the PCI bus during the address phase and ADO is driven to logic O Bits 7 1 of the DDMA page register see Section 7 2 are presented on AD23 AD17 of the PCI bus during the address phase and bit O is ignored 11 DDMA current address base address Name we RW RW RW RW eam 0 o o o Register DDMA current address base address Type Read Write Offset DDMA base address 00h Default 0000h Size Two byte
51. see Section 6 3 Bit 14 CVSTEST in this register must be written when forcing changes that require card interrogation See Table 6 5 for a complete description of the register contents Name Socket force event ETES ESE Low EN GE OR aw peau o o Jo fo fo fo opo jo o Register Socket force event Type Read only Write only Offset CardBus socket address OCh Default 0000 0000h Table 6 5 Socket Force Event Register SIGNAL TYPE FUNCTION 31 15 RSVD Reserved Bits 31 15 return 0s when read CVSTEST Card VS test When bit 14 is set the PCIA410 re interrogates the PC Card updates the socket present state register see Section 6 3 and enables the socket control register see Section 6 5 FYVCARD FXVCARD F3VCARD FSVCARD FBADVCCREQ Force bad Vcc request Changes to bit 9 BADVCCREQ in the socket present state register see Section 6 3 can be made by writing to bit 9 Force data lost Write transactions to bit 8 cause bit 8 DATALOST in the socket present state register to FDATALOST i be written see Section 6 3 Force YV card Write transactions to bit 13 cause bit 18 YVCARD in the socket present state register to be written see Section 6 3 When set this bit disables the socket control register see Section 6 5 Force XV card Write transactions to bit 12 cause bit 12 XVCARD in the socket present state register to be written see Section 6 3 When set this bit disables the socket control register
52. see Section 6 5 Force 3 V card Write transactions to bit 11 cause bit 11 SVCARD in the socket present state register to be written see Section 6 3 When set this bit disables the socket control register see Section 6 5 Force 5 V card Write transactions to bit 10 cause bit 10 BVCARD in the socket present state register to be written see Section 6 3 When set this bit disables the socket control register see Section 6 5 FNOTACARD Force not a card Write transactions to bit 7 cause bit 7 NOTACARD in the socket present state register to be written see Section 6 3 RSVD Reserved Bit 6 returns 0 when read FCBCARD Force CardBus card Write transactions to bit 5 cause bit 5 CBCARD in the socket present state register to be written see Section 6 3 les 16 bit card Write transactions to bit 4 cause bit 4 16BITCARD in the socket present state register EIE be written see Section 6 3 Force power cycle Write transactions to bit 3 cause bit 3 PWREVENT in the socket event register to be FPWRCYCLE written see Section 6 1 and bit 3 PWRCYCLE in the socket present state register is unaffected see Section 6 3 2 FCDETECT2 w Force CCD2 Write transactions to bit 2 cause bit 2 CD2EVENT in the socket event register to be written see Section 6 1 and bit 2 CDETECT2 in the socket present state register is unaffected see Section 6 3 FCDETECT1 Force CCD1 Write transactions to bit 1 cause bit 1 CD1EVENT in th
53. state of a corresponding bit in the general purpose event enable register 4 31 4 46 General Purpose Event Enable Register The general purpose event enable register contains bits that are setto enable a GPE signal The GPE signalis driven until the corresponding status bit is cleared and the event is serviced The GPE can only be signaled if one of the multifunction terminals MFUNC6 MFUNCO is configured for GPE signaling See Table 4 20 for a complete description of the register contents Bit 15 14 13 12 n t0 9 8 7 J e 5 j a ds 2 jJ t 0 General purpose event enable po Generarpuposeeventenabie Type Rw R r R jew R n few R BR R Rw AW RW Rw RW pem 0 o fo fo fo Jo o To Jo To To To To Jo To Tol Register General purpose event enable Type Read only Read Write Offset AAh Default 0000h Table 4 20 General Purpose Event Enable Register SIGNAL TYPE FUNCTION PC card socket ZV enable When bit 15 is set a GPE is signaled on a change in status of bit 6 ZVENABLE in the card control register see Section 4 34 14 12 RSVD R Reserved Bits 14 12 return Os when read PWR EN ao enable When bit 11 is set a GPE is signaled when software has changed the power state RSVD R Reserved Bits 10 and 9 return Os when read 12V Vpp request enable When bit 8 is set a GPE is signaled when software has changed the requested VPP12_EN R W Vpp level to or from 12 V for t
54. support Figure 3 3 shows terminal assignments for the TPS2211 Figure 3 4 illustrates a typical application where the PCI4410 represents the PC Card controller SHDN VPPDO VPPD1 AVCC AVCC AVCC AVPP 12V Figure 3 3 TPS2211 Terminal Assignments The PCI4410 also includes support for the Maxim 1602 and Micrel MIC2562A single channel CardBus power switches Application of these power switches would be similar to that of the TPS2211 Maxim is a trademark of Maxim Integrated Products Inc 3 4 Power Supply PC14410 PCMCIA Controller Figure 3 4 TPS2211 Typical Application 3 5 3 Zoomed Video Support The zoomed video ZV port on the PCI4410 provides an internally buffered 16 bit ZV PC Card data path This internal routing is programmed through the card control register offset 91h bits 5 and 6 Figure 3 5 summarizes the zoomed video subsystem implemented in the PCI4410 and details the bit functions found in the card control register When ZV PORT ENABLE is enabled the zoomed video output terminals are enabled and allow the PCI4410 to route the zoomed video data However no data is transmitted unless ZVENABLE offset 91h bit 6 is enabled If ZVENABLE is set to low then the ZV output port drives a logic 0 on the PCI4410 s ZV bus Zoomed Video Subsystem Card Output Enable Logic ZV PORT_ENABLE eo PC Card PC Card 23 7 ZVENABLE Note ZVSTAT must b
55. terminals as illustrated in Figure 3 15 Not shown is that INTA must also be routed to the programmable interrupt controller PIC or to some circuitry that provides parallel PCI interrupts to the host PC14410 MFUNCO MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 Figure 3 15 IRQ Implementation Power on software is responsible for programming the multifunction routing register to reflect the IRQ configuration of a system implementing the PCI4410 See Section 4 32 Multifunction Routing Register for details on configuring the multifunction terminals The parallel ISA type IRQ signaling from the MFUNC6 MFUNCO terminals is compatible with those input directly into the 8259 PIC The parallel IRQ option is provided for system designs that require legacy ISA IRQs Design constraints may demand more MFUNC6 MFUNCO IRQ terminals than the PCI4410 makes available 3 7 4 Using Parallel PCI Interrupts Parallel PCI interrupts are available in parallel PCI interrupt mode parallel IRQ and parallel PCI interrupt mode or serialized IRQ and parallel PCI interrupt mode 3 7 5 Using Serialized IRQSER Interrupts The serialized interrupt protocol implemented in the PCI4410 uses a single terminal to communicate all interrupt status information to the host controller The protocol defines a serial packet consisting of a start cycle multiple interrupt indication cycles and a stop cycle All data in the packet is synchronous with the
56. the register contents 29 29 27 26 25 24 23 22 21 20 19 18 17 16 Class code and revision ID Name lass code and revision ID fee R R RJ JR R RJ JR R R RJ JR R RJR R JR eta o o o oft ft to fo fo fo lo Jo fo lo lo ol et 15 14 13 2 t 10 eee Class code and revision ID po Glass code andrevision ID fee R R R JR R R JR R R RJ JR R RJR R R pea o o o 1 To o Jo Jo Jo Jo o Jo od o To Register Class code and revision ID Type Read only Offset 08h Default 0C00 1001h Table 8 5 Class Code and Revision ID Register SIGNAL TYPE FUNCTION BASECLASS ue This field returns OCh when read which broadly classifies the function as a serial bus SUBCLASS Sub class This field returns 00h when read which specifically classifies the function as controlling an IEEE1394 serial bus 15 8 PGMIF Programming interface This field returns 10h when read which indicates that the programming model is compliant with the 1394 OHCI specification 7 0 CHIPREV Silicon revision This field returns the silicon revision of the PCI4410 8 7 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the PCI4410 See Table 8 6 for a complete description of the register contents Bit 15 14 13 m2 ft 10 9 amp 5 v j e
57. we nos s Des pemn RR room Jo w _ voo leo Cre never fosa n ran ran wie os rs aos aos us as laos wi _ wrunco Jeu Cro FOME RrourBwE ue won aon ven wrunca uruvcs Pes fave lawa ue we we a wr wwe lawe vs ime II 2 7 Table 2 3 CardBus PC Card Signal Names Sorted Alphabetically to GHK PDV Terminal Number SIGNAL NAME Ri Noa SIGNAL NAME SIGNAL NAME SIGNAL NAME EE pow Tank SGNAL NAME Tee Toc Pov Tank we n uw oon wo pw mer Fre poc roer a vo we feaa us Gr onsvo 101 es Pv pamo 20 56 wx ss ve fenos va Gre cse ve ev povoar 20 eer is se us ears we cra ostop s eis ev pama 204 Fo ae sr Re o ier es csrscus ies eo Pav pamo 205 55 as ss Pe feas ier e14 over 17e em pay pam 207 cs wo si won ise ora oevset allemol wu s vs ws 2 ee eno 6 e ovas 2 6 x ss Re es we su ow s ws Prso a eer we 2 we omo ver co eno va ro Prso 7 Fa ow n N3 aas vee ro eno ies Pra p nsvo s F2 moe a ne es ies es eno mo ws ev ev s os aw a Ki ees as vw wm s via loor 75 Po aos a foower ur re ws es oe rs o Pi axe 20 foowes ws sz eos co mi sean als joao ar ow ouk ie oio wrunco 76 wio SUSPE
58. 0 IRQ12 enabled 0101 IRQ5 enabled 1101 IRQ13 enabled 0110 IRQ6 enabled 1110 IRQ14 enabled Register ExCA card status change interrupt configuration 7 4 0111 IRQ7 enabled 1111 IRQ15 enabled Offset CardBus socket address 805h ExCA offset 05h 1 Enables interrupts on CD1 or CD2 line changes Default 00h Ready enable Bit 2 enables disables a low to high transition on PC Card READY to generate a host READYEN interrupt This interrupt source is considered a card status change This bit is encoded as Type Read Write Table 5 8 ExCA Card Status Change Interrupt Configuration Register Card detect enable Bit 3 enables interrupts on CD1 or CD2 changes This bit is encoded as CDEN 0 Disables interrupts on CD1 or CD2 line changes default 0 Disables host interrupt generation default 1 Enables host interrupt generation Battery warning enable Bit 1 enables disables a battery warning condition to generate a CSC interrupt This bit is encoded as EAN 0 Disables host interrupt generation default 1 Enables host interrupt generation Battery dead enable Bit O enables disables the generation of a CSC interrupt for a battery dead contition BATDEADEN 16 bit memory PC card or assertion of the STSCHG signal 16 bit VO PC card 0 Disables host interrupt generation default 1 Enables host interrupt generation 5 9 5 7 ExCA Address Window Enable Register The ExCA address window enable register enables dis
59. 10 1110 2 GPE 0011 IRQ3 0111 ZVSELO 1011 IRQ11 1111 2 IRQ15 Multifunction terminal 3 configuration These bits control the internal signal mapped to the MFUNCS terminal as follows 0000 RSVD 0100 IRQ4 1000 IRQ8 1100 IRQ12 0001 IRQSER 0101 IRQ5 1001 IRQ9 1101 IRQ13 as follows MFUNC4 MFUNCS3 0010 IRQ2 0110 IRQ6 1010 IRQ10 1110 IRQ14 0011 IRQ3 0111 IRQ7 1011 IRQ11 1111 IRQ15 Multifunction terminal 2 configuration These bits control the internal signal mapped to the MFUNC2 terminal as follows 0000 GPI2 0100 IRQ4 1000 CAUDPWM 1100 RI OUT Ha MFUNG 0001 GPO2 0101 IRQ5 1001 IRQ9 1101 2 D3 STAT 0010 PCREQ 0110 ZVSTAT 1010 IRQ10 1110 GPE 0011 IRQ3 0111 ZVSELO 1011 IRQ11 1111 IRQ7 4 20 R W R W R W R W AN Table 4 9 Multifunction Routing Register Continued Multifunction terminal 1 configuration These bits control the internal signal mapped to the MFUNC1 terminal as follows NOTE When the serial bus mode is implemented by pulling up the VCCDO and VCCD1 terminals the MFUNC1 terminal provides the SDA signaling 7 4 MFUNC1 R W 0000 GPI1 0100 IRQ4 1000 CAUDPWM 1100 LED_SKT 0001 GPO1 0101 IRQ5 1001 IRQ9 1101 IRQ13 0010 D3 STAT 0110 ZVSTAT 1010 IRQ10 1110 2 GPE 0011 IRQ3 0111 ZVSELO 1011 IRQ11 1111 2 IRQ15 Multifunction terminal 0 configuration These bits control the internal signal mapped to the MFUNCO terminal as follows
60. 2 P2C Power Switch Interface TPS221 1 for details The PCI4410 serial bus interface is compatible with various IC and SMBus components 3 6 1 Serial Bus Interface Implementation The PCI4410 defaults to the serial bus interface are disabled To enable the serial interface a pullup resistor must be implemented on the VCCDO and VCCD1 terminals and the appropriate pullup resistors must be implemented on the SDA and SCL signals that is the MFUNC1 and MFUNCA terminals The PC14410 implements a two pin serial interface with one clock signal SCL and one data signal SDA When pullup resistors are provided on the VPPDO and VPPD1 terminals the SCL signal is mapped to the MFUNCA terminal and the SDA signal is mapped to the MFUNC1 terminal The PCI4410 drives SCL at nearly 100 kHz during data transfers which is the maximum specified frequency for standard mode 12C The serial EEPROM must be located at address AOh Figure 3 8 illustrates an example application implementing the two wire serial bus Vcc Serial ji EEPROM PC14410 VCCDO PETENDA b Vcc VCCD1 SCL SDA e Figure 3 8 Serial EEPROM Application Some serial device applications may include PC Card power switches ZV source switches card ejectors or other devices that may enhance the user s PC Card experience The serial EEPROM device and PC Card power switches are discussed in the sections that follow 3 6 2 Serial Bus Interface Protocol The
61. 24 Isochronous Transmit Interrupt Mask Register This set clear register is used to enable the isochTx interrupt source on a per channel basis Reads from either the set register or the clear register always return IsoXmitlntMask In all cases the enables for each interrupt event align with the event register bits detailed in Table 9 17 m Tat ao 29 28 27 26 25 24 05 02 01 20 09 48 47 15 Name O Bevowesvammiempimask Isochronous transmit interrupt mask ER EE EE EE EE EE EE ololo olo floloflo x x x x x x x x aa or Isochronous transmit interrupt mask Type Read Set Clear Read only Offset 98h set register 9Ch clear register Default 0000 00XXh 9 25 Isochronous Receive Interrupt Event Register This set clear register reflects the interrupt state of the isochronous receive contexts An interrupt is generated on behalf of an isochronous receive context if an INPUT command completes and its interrupt bits are set to 1 Upon determining that the IntEvent isochRx interrupt has occurred software can check this register to determine which context s caused the interrupt The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register The only mechanism to resetthe bits in this register to Oisto write a 1 to the corresponding bit in the clear register See Table 9 18 for a complete description ofthe register cont
62. 26 16 return Os when read BUSNUMBER This number is used to identify the specific 1394 bus the PCI4410 belongs to when multiple 1394 compatible buses are connected via a bridge This number is the physical node number established by the PHY during self identification It is NODENUMBER automatically set to the value received from the PHY after the self identification phase If the PHY sets the nodeNumber to 63 then software should not set ContextControl run for either of the AT DMA contexts 9 24 9 30 PHY Control Register This register is used to read or write a PHY register See Table 9 22 for a complete description of the register contents Bit 31 30 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 PHY control Dx pe Lx px E x X a fis fia fio o fes pie fe fa te feto To PHY control emu mu a R am aw ww am Aw EL GG Register PHY control Type Read Write Update Read Update Read only Offset ECh Default XXXX OXXXh Table 9 22 PHY Control Register BIT SIGNAL TYPE FUNCTION This bit is cleared to O by the PCI4410 when either bit 15 rdReg or bit 14 wrReg is set to 1 This bit is set 31 RDDONE i e to 1 when a register transfer is received from the PHY 30 28 RSVD R Reserved Bits 30 28 return Os when read 27 24 RDADDR RU This is the address of the register most recently received from the PHY 23 16 RDDATA RU This field is the conten
63. 3 CC BEO are multiplexed on the same CardBus terminals During the address phase of a CardBus cycle CC BE3 CC BEO define the bus command During the data phase this 4 bit bus is used as byte enables The byte enables determine which byte paths ofthe full 32 bit data bus carry meaningful data CC BEO applies to byte 0 CAD7 CADO CC BE1 applies CC BEO to byte 1 CAD15 CAD8 CC BE2 applies to byte 2 CAD23 CAD16 and CC BE3 applies to byte 3 CAD31 CAD24 CardBus parity In all CardBus read and write cycles the PCI4410 calculates even parity across the CAD and CC BE buses As an initiator during CardBus cycles the PCI4410 outputs CPAR with a one CCLK delay As atarget during CardBus cycles the calculated parity is compared to the initiator s parity indicator a compare error results in a parity error assertion 2 19 Table 2 15 CardBus PC Card Interface Control Terminals AEN DESCRIPTION XE SM caunio nm ES 0 ERES audio CAUDIO is a digital input signal from a PC Card to the system speaker The PCI4410 EN the binary audio mode and outputs a binary signal from the card to SPKROUT CardBus lock CBLOCK is used to gain exclusive access to a target CCD1 123 L19 CardBus detect 1 and CardBus detect 2 CCD1 and CCD2 are used in conjunction with CVS1 and CCD2 185 AQ CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type CardBus device select The PCI4410 asserts CDEVSEL to claim a Car
64. 410 offers two mechanisms to load a read only value into the subsystem registers The first mechanism relies upon the system BIOS providing the subsystem ID value The default access mode to the subsystem registers is read only but can be made read write by setting bit 5 SUBSYSRW in the system control register see Section 4 29 at PCI offset 80h When this bit is set the BIOS can write a subsystem identification value into the registers at PCI offset 40h The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register are limited to read only access This approach saves the added cost of implementing the serial electrically erasable programmable ROM EEPROM In some conditions such as in a docking environment the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM The PC14410 loads the data from the serial EEPROM after a reset of the primary bus Note that the SUSPEND input gates the PCI reset from the entire PCI4410 core including the serial bus state machine see Section 3 8 4 Suspend Mode for details on using SUSPEND The PC14410 provides a two line serial bus host controller that can interface to a serial EEPROM See Section 3 6 Serial Bus Interface for details on the two wire serial bus controller and applications 3 5 PC Card Applications This section describes the PC Card interfaces of the PCI4410 Card insertion removal and r
65. 5 17 5 17 ExCA Memory Windows 0 4 Offset Address Low Byte Registers These registers contain the low byte of the 16 bit memory window offset address for memory windows 0 1 2 3 and 4 The 8 bits of these registers correspond to bits A19 A12 of the offset address to 7 6 8 a 3s 2 1 90 Name ExCA memory windows 0 4 offset address low Register ExCA memory window 0 offset address low byte Offset CardBus socket address 814h ExCA offset 14h Register ExCA memory window 1 offset address low byte Offset CardBus socket address 81Ch ExCA offset 1Ch Register ExCA memory window 2 offset address low byte Offset CardBus socket address 824h ExCA offset 24h Register ExCA memory window 3 offset address low byte Offset CardBus socket address 82Ch ExCA offset 2Ch Register ExCA memory window 4 offset address low byte Offset CardBus socket address 834h ExCA offset 34h Type Read Write Default 00h Size One byte 5 18 ExCA Memory Windows 0 4 Offset Address High Byte Registers These registers contain the high 6 bits of the 16 bit memory window offset address for memory windows 0 1 2 3 and 4 The lower 6 bits of these registers correspond to bits A25 A20 of the offset address In addition the write protection and common attribute memory configurations are set in this register See Table 5 13 for a complete description of the register contents st 7 6 5 4 3 2 1 o Name ExCA memor
66. 8h set register 7Ch clear register Default XXXX XXXXh Table 9 14 ISO Receive Channel Mask Low Register SIGNAL TYPE FUNCTION ISOCHANNEL31 When set to 1 the PCI4410 is enabled to receive from ISO channel number 31 ISOCHANNEL30 When set to 1 the PCI4410 is enabled to receive from ISO channel number 30 is EE Bits 29 through 2 follow the same pattern ISOCHANNEL1 When set to 1 the PCI4410 is enabled to receive from ISO channel number 1 o ISOCHANNELO When set to 1 the PCI4410 is enabled to receive from ISO channel number 0 9 17 9 21 Interrupt Event Register This set clear register reflects the state of the various PCIA410 interrupt sources The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register The only mechanism to reset the bits in this register to 0 is to write a 1 to the corresponding bit in the clear register See Table 9 15 for a complete description of the register contents m sIs s s z s 3 12125121277125 am Wempmem ee n 5 A A A 85v Jasco Jasco Jasco Jasco Jasco Jasco Jasco A Jasco scu besar o x 9 9 9 x X X X X X x X 5 x m usw pn 39 9 5 17 5 5 L5 3 12 12 T wm mim ee A A 5 A A A ASOU ASCU nu AU Jaso faso asou Jaso Jasco Jesoo Demo o o 5 5 o X X X x TX AE AE AE AE 1 Register Interrupt ev
67. ABLE and 17 LINKENABLE are 1 the OHCI driver can APHYENHANCEENABLE RSC set this bit to 1 to use all p1394a enhancements When bit 23 PROGRAMPHYENABLE is O the software does not change PHY enhancements or the APHYENHANCEENABLE bit 21 20 RSVD R Reserved Bits 21 and 20 return Os when read 19 LPS RSC This bit is used to control the link power status Software must set this bit to 1 to permit the link PHY communication A O prevents link PHY communication This bitis used to enable 1 or disable 0 posted writes Software should change this bit only 18 POSTEDWRITEENABLE oe when bit 17 LINKENABLE is 0 This bit is cleared to 0 by a hardware reset or software reset Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset This bit is necessary 17 LINKENABLE RSC to keep other nodes from sending transactions before the local system is ready When this bit is cleared the PCI4410 is logically and immediately disconnected from the 1394 bus no packets are received or processed and no packets are transmitted When this bit is set to 1 all PCI4410 states are reset all FIFO s are flushed and all OHCI registers are set to their hardware reset values unless otherwise specified PCI registers are SNS RSCU not affected by this bit This bit remains setto 1 while the soft reset is in progress and reverts back to 0 when the reset has completed RSVD R Reserved Bits 15 0 return Os when read NOBYTESWAP
68. AE AE 8 6 BEA AK AE OER Power management capabilities po o Power management capabilites Type RU Ru ru ru ru R A R Ri A rR PR aR A RT OR pea o 1 fo fo fs fo fo fofofofs fofofot Register Power management capabilities Type Read Update Offset 46h Default 6411h Table 8 14 Power Management Capabilities Register FUNCTION PME support from D3cojq When this bit is set to 1 the PCI4410 generates a PME wake event from D3cold This bit state is dependent upon PCI4410 Vaux implementation and may be configured by host software using the PCI miscellaneous configuration register PME support This four bit field indicates the power states from which the PCI4410 may assert PME These four bits return a value of 1100b by default indicating that PME may be asserted from the D3hot and D2 power states Bit 13 may be modified by host software using the PCI miscellaneous configuration register D2 support This bit returns a 1 when read indicating that the PCI4410 supports the D2 power state D1 support This bit returns a 0 when read indicating that the PCI4410 does not support the D1 power state Dynamic data support This bit returns a O when read indicating that the PCI4410 does not report dynamic power consumption data Reserved These bits return Os when read Device specific initialization This bit returns O when read indicating that the PCI4410 does not require special initialization
69. AKE RSU a Geet will reset this bit to O on every descriptor fetch T DEAD RU The PCIA410 sets this bit to 1 when it encounters a fatal error and resets the bit to O when software resets the RUN bit to 0 ACTIVE The PC14410 sets this bit to 1 when it is processing descriptors 9 8 RSVD R Reserved Bits 9 and 8 return Os when read This field indicates the speed at which a packet was received or transmitted and only contains meaningful information for receive contexts This field is encoded as 7 5 SPD RU 000b 100 Mbits sec 001b 200 Mbits sec 010b 400 Mbits sec All other values are reserved 4 0 EVENTCODE RU This field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully 9 33 9 38 Asynchronous Context Command Pointer Register This register contains a pointer to the address of the first descriptor block that the PCI4410 will access when software enables the context by setting the ContextControl run bit to 1 See Table 9 29 for a complete description of the register contents epee ee eee ER A e Lf Asynchronous context command pointer EE Asynchronous context command pointer lc pea x x x x x x x x xix x ixix ixIxIix Register Asynchronous context command pointer Type Read Write Update Offset 19Ch ATRQ 1ACh ATRS 1CCh ATRQ 1ECh ATRS Default XXXX XXXXh Table 9 29 Asynchronous
70. AME MEANING R Read Field may be read by software WwW Write Field may be written by software to any value Set Field may be set to 1 by a write of 1 Writes of 0 have no effect Field may be reset to 0 by a write of 1 Writes of 0 have no effect 8 1 PCI Configuration Registers The PCI4410 link function configuration header is compliant with the PCI specification as a standard header Table 8 2 illustrates the PCI configuration header which includes both the predefined portion of the configuration space and the user definable registers The registers that are labeled reserved are read only returning 0 when read and are not applicable to the link function or have been reserved by the PCI specification for future use Table 8 2 PCI Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command Class code Revision ID 08h Open HCI registers base address TI extension registers base address 14h Reserved 1Ch Reserved N Pam Subsystem ID Subsystem vendor ID aQ Reserved Reserved Capabilites pointer Reserved ag aa ma lug ar 8 1 Table 8 2 PCI Configuration Register Map Continued REGISTER NAME OFFSET Link enhancements F4h Subsystem ID alias Subsystem vendor ID alias GPIO3 GPIO2 GPIO1 GPIOO 8 2 Vendor ID Register This 16 bit read only register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device The vendor ID assig
71. Addresses Used for PC PCI DMA 3 10 CardBus Socket Registers EE EE cece cece eee ee Ee ee ee 3 11 Registers and Bits Loadable Through Serial EEPROM 3 14 Interrupt Mask and Flag Registers 3 16 PC Card Interrupt Events and Description 3 17 Rees ROET N NO HE OR N EE OE E 3 19 Power Management Registers iis ccc ee Re ee eee eee 3 23 PCI Configuration Registers Functions 0 and1 4 1 Command REGISTE ioon spes dues doute DS coa Dan iced 4 3 Status BBUISII gia Ee RE RE e HERE ER GA RS A E GU E EECH AE 4 4 Secondary Status Register 00 0 c cece eee eee eee 4 8 Bridge Control Register spams ou EER ida cec SEKR aw beg 4 14 System Control Register EE ER ee eee ees 4 17 General Status Register ass pesos orb eba e se AP Orada eax 4 19 General Control Register si EES ME ee eroe P ck EE 4 19 Multifunction Routing Register iss cece eee ee Re eee 4 20 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 5 2 Retry Status Register ii ak NEE DER EKS p BANANAS ABA NAE 4 21 Gard Control Register 41 24a Terus be trei tidied orate edis 4 22 Device Control Register 4 23 Diagnostie Register asi Pared e dados Ve EORR SEE HR 4 24 Socket DMA Register 0 spams Er erer EE DEE EE AE REPE EE ETE 4 25 Socket DMA Register 1 4 26 Power Management Capabilities Register 4 28 Power Management Co
72. B3 1 When the bridge function is programmed to D hot its secondary bus e PCI clock will be stopped B2 Default RSVD R Reserved Bits 5 0 return 0s when read 4 44 Power Management Data Register The power management data register returns Os when read because the CardBus functions do not report dynamic data Name Power management data Tee R j R R j R R R R J R pea o o o o o oo o o Register Power management data Type Read only Offset A7h Default 00h 4 30 4 45 General Purpose Event Status Register The general purpose event status register contains status bits that are set by different events The bits in this register andthe corresponding GPE are cleared by writing a 1 to the corresponding bit location See Table 4 19 for a complete description of the register contents Bit 15 14 t3 12 n 10 9 8 7 J e s ja da j 2 Jj t J 0 General purpose event status po Generahpurpose event status Tye RC R R R RC R R Ro R A R Ro Rc Rc Rc rc Detam 0 o fo fo fo fo fo fo fo fo fo fo fo fo fo fo Register General purpose event status Type Read only Read Write to Clear Offset A8h Default 0000h Table 4 19 General Purpose Event Status Register eo SIGNAL TYPE FUNCTION PC card ZV status Bit 15 is set on a change in status of bit 6 ZVENABLE in the card control register see mene Section 4 34 14 12 RSVD Res
73. C Card applications See Table 5 4 and Table 5 5 for a complete description of the register contents Be N o 7 d e s 4 s 2 1 o ExCA power control Name PKC power control S O mwe ew R RW w w R w RW peam 0 o o o o o o o Register ExCA power control Type Read only Read Write Offset CardBus socket address 802h ExCA offset 02h Default 00h Table 5 4 ExCA Power Control Register 82365SL Support SIGNAL TYPE FUNCTION Card output enable Bit 7 controls the state of all of the 16 bit outputs on the PCI4410 This bit is encoded as i SES iid O 16 bit PC Card outputs disabled default 1 16 bit PC Card outputs enabled 6 RSVD R Reserved Bit 6 returns 0 when read Auto power switch enable This bit is enabled by bit 7 of the system control register see Section 4 29 5 AUTOPWRSWEN R W O Automatic socket power switching based on card detects is disabled 1 Automatic socket power switching based on card detects is enabled PC Card power enable CAPWREN 0 Vcc Vpp1 Vpp2 No connection 1 Vcc is enabled and controlled by bit 2 ExCAPower of the system control register see Section 4 29 Vpp4 and Vppo are controlled according to bits 1 0 EXCAVPP field 3 2 RSVD R Reserved Bits 3 and 2 return Os when read PC Card Vpp power control Bits 1 and 0 are used to request changes to card Vpp The PCIA410 ignores this field unless Vcc to the socket is enabl
74. C Card signals describes the function for 16 bit memory I O cards and CardBus For example READY IREQ CINT includes READY for 16 bit memory cards IREQ for 16 bit I O cards and CINT for CardBus cards The 16 bit memory card signal name is first with the I O card signal name second enclosed in parentheses The CardBus signal name follows after a forward double slash The 1997 PC Card Standard describes the power up sequence that must be followed by the PCI4410 when an insertion event occurs and the host requests that the socket Voc and Vpp be powered Upon completion of this power up sequence the PCI4410 interrupt scheme can be used to notify the host system see Table 3 8 denoted by the power cycle complete event This interrupt source is considered a PCI4410 internal event because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface 3 7 2 Interrupt Masks and Flags Host software may individually mask or disable most of the potential interrupt sources listed in Table 3 8 by setting the appropriate bits in the PCI4410 By individually masking the interrupt sources listed software can control those events that cause a PCI4410 interrupt Host software has some control over the system interrupt the PCI4410 asserts by programming the appropriate routing registers The PCI4410 allows host software to route PC Card CSC and PC Card functional interrupts to separate
75. C Cards The PCI4410 28 5VSOCKET does support 5 V Vcc therefore this bitis always set unless overridden by the socket force event register see Section 6 4 27 14 RSVD R_ Reserved Bits 27 14 return Os when read YVCARD R YV card Bit 13 indicates whether or not the PC Card inserted in the socket supports Vcc Y Y V XVCARD R XV card Bit 12 indicates whether or not the PC Card inserted in the socket supports Vee X X V 3VCARD R 3 V card Bit 11 indicates whether or not the PC Card inserted in the socket supports Vcc 3 3 V 5VCARD R 5 V card Bit 10 indicates whether or not the PC Card inserted in the socket supports Vcc 5 V Bad Vcc request Bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage O Normal operation default BADVCCREQ 1 Invalid Vcc request by host software Data lost Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did DATALOST not terminate properly or because write data still resides in the PCI4410 O Normal operation default 1 Potential data loss due to card removal Not a card Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket This bit is not 7 NOTACARD updated until a valid PC Card is inserted into the socket O Normal operation default 1 Unrecognizable PC Card detected 6 4 Table 6 4 Socket Present State Register Continued SIGNAL TYPE FUNCTION
76. Control linkEnable bit is set to 1 0 Cycle master capable IEEE1394 bus management field Must be valid when HCControl linkEnable bit is set to 1 8 7 3 R W 3 CMC R W 2 ISC RW Isochronous support capable IEEE1394 bus management field Must be valid when HCControl linkEnable bit is set to 1 Bus manager capable IEEE 1394 bus managementfield Must be valid when HCControl linkEnable bit 2 BMC RW is set to 1 2 PMC RW IEEE1394 bus management field Must be valid when HCControl linkEnable bit is set to 1 26 24 RSVD R Reserved Bits 26 24 return O when read Cycle master clock accuracy in parts per million IEEE1394 bus management field Must be valid when 23 16 CYC CEK ACC RW HCControllinkEnable bit is set to 1 IEEE 1394 bus management field Hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation This value max rec bytes must be 512 or greater and is calculated by 2 max rec 1 Software may change max rec however this field must be valid at any time the HCControl linkEnable bit is set to 1 A received block write request packet with a length greater than max rec bytes may generate an ack type error This field is not affected by a soft reset and defaults to a value indicating 2048 bytes on hard reset 11 8 RSVD R Reserved Bits 11 8 return Os when read Generation counter This field is incremented if any portion of the configuration ROM has
77. DATA RSC PROGRAMPHYENABLE RC 4 9 17 Self ID Buffer Pointer Register This register points to the 2 Kbyte aligned base address of the buffer in host memory where the self ID packets will be stored during bus initialization Bits 31 11 are read write accessible 29 29 27 26 25 2a 23 22 21 20 19 18 17 16 wm Sb apan peram o o o o o fofo po fo fo oe el of of ee et 15 14 13 12 n 10 9 8 7 e jJ 5 1a 2 t j 0 Self ID buffer pointer po BD butter pointer Hye Rw Rw mw Rw Rw R a R n n JR JR Jen JR R J R pea o o Jo o o o o o o jo o o o o of e Register Self ID buffer pointer Type Read only Read Write Offset 64h Default 0000 0000h 9 18 Self ID Count Register This register keeps a count of the number of times the bus self ID process has occurred flags self ID packet errors and keeps a count of the amount of self ID data in the self ID buffer See Table 9 12 for a complete description of the register contents m a 80 29 28 27 26 25 24 28 22 21 eds el 7 ie Name Self ID count Type RU R R R R BR R R Ru Ry By RU RU FRU RU RU emm x fo fo fofototototxtxtxtxtx txt xt x et 15 14 13 12 vt 10 9 8 7 6 5 Name Self ID count me n AR A A A AU AU AU RU AU Tw peau o o o o o fo o o fo o jo Register Self ID
78. DDMAcmmad mme a R a J m R mp m peas o o o o o o o o Register DDMA command Type Read only Read Write Offset DDMA base address 08h Default 00h Size One byte Table 7 2 DDMA Command Register SIGNAL TYPE FUNCTION RSVD R Reserved Bits 7 3 return Os when read DDMA controller enable Bit 2 enables and disables the distributed DMA slave controller in the PCI4410 and defaults to the enabled state 2 DMAEN EA 0 DDMA controller enabled default 1 DDMA controller disabled RSVD R Reserved Bits 1 and 0 return 0s when read 7 5 DDMA Status Register The DDMA status register indicates the terminal count and DMA request DREQ status See Table 7 3 for a complete description of the register contents pg 7 e j s j 4 2 1 90 Name DDMA status PMSA ooo we R R R R R R R J R peat o o o j o o o o o Register DDMA status Type Read only Offset DDMA base address 08h Default 00h Size One byte Table 7 3 DDMA Status Register SIGNAL TYPE FUNCTION Channel request In the 8237 bits 7 4 indicate the status of DREQ of each DMA channel In the PCI4410 7 4 DREQSTAT these bits indicate the DREQ status of the single socket being serviced by this register All four bits are set to 1 when the PC Card asserts DREQ and are reset to O when DREQ is deasserted The status of bit O MASKBIT in the DDMA
79. DDR18 CC BE1 ADDR8 VOC C PHY RSVD PHY RSVD PHY RSVD PHY RSVD PHY RSVD PHY RSVD PHY RSVD PHY RSVD CAD16 ADDR17 CPAR ADDR13 CAD14 ADDR9 CAD15 IOWR CAD12 ADDR11 GNT GNT z ale m o m q E o Ss E D PHY RSVD PHY RSVD PHY RSVD PHY RSVD PHY RSVD PHY RSVD bu Ko olo in 2 Oly Ol 5 ed o GIE Po uj lt m o O TERM NO H14 H15 H17 H18 H19 2 3 5 6 J J J J J J14 J15 J17 J18 J19 K K K K K K14 K15 K17 K18 K19 1 1 2 3 5 6 L1 L2 L3 L5 L6 L14 L15 L17 L18 L19 M M M M 1 2 3 5 M6 M14 M15 SIGNAL NAME CARDBUS 16 BIT CAD13 CAD11 SS AD31 AD31 AD30 AD29 AD29 op fan 2 O O CH ITI m o N e vo EN CAD7 DATA7 AD27 AD27 AD26 AD26 AD25 AD25 AD24 AD24 D D C C C BES C BES CRSVD DATA14 CAD5 DATA6 CAD6 DATA13 CAD3 DATAS CAD4 DATA12 IDSEL IDSEL D D D D gt O n2 Go Jg N Go aN foaoe CAD2 DATA11 DATAS CDT Vee GN cc ZV_SDATA lt Q O U lt O Ojo Ol TU Table 2 2 CardBus and 16 Bit PC Card Signal Names by GHK Terminal Number Continued we veer wor m rmv mw us pev JI w we ais RE soe Jeer fee no fae fao ma EO s vr per JI s apr lao a6 aia fen v8 nos vs ape Janis re ads aos wo uno Je ww eus Jm no ow fowo vn eer or a rmwE JE Ro la wa nuno us eno ow es Woo voc Re awo awo
80. Default is 0 RSVD Reserved Bits 4 and 3 return 0 when read ET Raw Carine audio to IRQMUX When set the CAUDIO CardBus signal is routed to the corresponding LE terminal which may be configured for CAUDPWM Interrupt flag Bit 0 is the interrupt flag for 16 bit VO PC Cards and for CardBus cards Bit 0 is set when IFG RIC a functional interrupt is signaled from a PC Card interface Write back a 1 to clear this bit 0 No PC Card functional interrupt detected default 1 PC Card functional interrupt detected EXE UE Speaker out enable When bit 1 is set SPKR on the PC Card is enabled and is routed to SPKROUT The SPKROUT terminal drives data only when the socket s SPKROUTEN bitis set This bitis encoded SPKROUTEN R W as 0 SPKR to SPKROUT not enabled default 1 SPKR to SPKROUT enabled 4 22 4 35 Device Control Register The device control register is provided for PCI1130 compatibility The interrupt mode select and the socket capable force bits are programmed through this register See Table 4 12 for a complete description of the register contents at 7 6 s a a 2 1 9 Name Device control ma o 1 o o sos oo Register Device control Type Read only Read Write Offset 92h Default 66h Table 4 12 Device Control Register SIGNAL TYPE FUNCTION Socket power lock bit When this bit is set to 1 software will not be able to power down the PC Card 7 SKTPWR LOCK RAW socket while
81. E FUNCTION BIST R Built in self test The PCI4410 does not include a built in self test and this field returns 00h when read PCI headertype The PCI4410 includes the standard PCI header and this is communicated by returning 7 0 HEADER TYPE R 00h when this field is read 8 9 Open HCI Registers Base Address Register The open HCI registers base address register is programmed with a base address referencing the memory mapped OHCI control When BIOS writes all 1s to this register the value read back is FFFF F800h indicating that at least 2K bytes of memory address space are required for the OHCI registers See Table 8 8 for a complete description of the register contents Bit 31 3o 29 28 27 26 25 2a 23 22 zt 20 19 18 17 16 Name Gen HCl registers base address pem 9 s o o 9 o e oe oe eo 9 et is 14 13 uz t 10 9 8 7 e s 3 J 2 t o Name Ger HCl registers base address Hye nw Rw Rw nw aw R a Rn RJR Rn Jn JR R Pm petan o o o fo fo fo fo fo Jo Jo fo foto fo fo fo Register Open HCI registers base address Type Read only Read Write Offset 10h Default 0000 0000h Table 8 8 Open HCI Registers Base Address Register BIT SIGNAL TYPE FUNCTION 31 11 OHCIREG_PTR Open HCI register pointer Specifies the upper 21 bits of the 32 bit OHCI register base address 10 4 OHCI SZ Open HCl register size This field returns Os when rea
82. E GEMAAK AE AE AE AE 4 5 TE N PCI OHCI control Name tree R R R R R R R RT R Deta o o o fo jo o jo fof Register PCI OHCI control Type Read only Offset 40h Default 0000h 8 16 Capability ID and Next Item Pointer Registers The capability ID and next item pointer registers identify the linked list capability item and provide a pointer to the next capability item respectively See Table 8 13 for a complete description of the register contents m psej oe e e s e e name GapabyiD ang neem paner EE aa Po Jo Jo To jo 1e Jo 1e jo Too To To oe oo Register Capability ID and next item pointer Type Read only Offset 44h Default 0001h Table 8 13 Capability ID and Next Item Pointer Registers SIGNAL FUNCTION NEXT ITEM Next item pointer The PCI4410 supports only one additional capability that is communicated to the system through the extended capabilities list thus this field returns 00h when read 7 0 CAPABILITY ID Capability identification This field returns 01h when read which is the unique ID assigned by the PCI SIG for PCI power management capability 8 17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the PCI4410 related to PCI power management In summary the DO D2 and D3ho device states are supported See Table 8 14 for a complete description of the register contents LE AK BE AE AE
83. GPIO3 data bit The value written to bit 3 represents the logical value of the data driven to the MFUNC4 terminal if configured as GPO3 Read transactions return the last data value written 2 GPO2 DATA RW GPO2 data bit The value written to bit 2 represents the logical value of the data driven to the MFUNC2 terminal if configured as GPO2 Read transactions return the last data value written 1 GPO1 DATA RW GPO1 data bit The value written to bit 1 represents the logical value of the data driven to the MFUNC1 terminal if configured as GPO1 Read transactions return the last data value written GPOO DATA RW GPOO data bit The value written to bit O represents the logical value of the data driven to the MFUNCO E terminal if configured as GPOO Read transactions return the last data value written 4 34 5 ExCA Compatibility Registers The ExCA registers implemented in the PCIA410 are register compatible with the Intel 82365SL DF PCMCIA controller EXCA registers are identified by an offset value that is compatible with the legacy VO index data scheme used on the Intel 82365 ISA controller The ExCA registers are accessed through this scheme by writing the register offset value into the index register I O base and reading or writing the data register I O base 1 The I O base address used in the index data scheme is programmed in the PC Card 16 bit VF legacy mode base address register see Section 4 28 The offsets from this base address run
84. GRST global reset signal from the PCI4410 Besides gating PRST and GRST SUSPEND also gates PCLK inside the PCI4410 in order to minimize power consumption Gating PCLK does not create any issues with respect to the power switch interface in the PCI4410 This is because the PCI4410 does not depend on the PCI clock to clock the power switch interface There are two methods to clock the power switch interface in the PCI4410 e Use an external clock to the PCl4410 CLOCK terminal e Use the internal oscillator It should also be noted that asynchronous signals such as card status change interrupts and RI OUT can be passed to the host system without a PCI clock However if card status change interrupts are routed over the serial interrupt stream then the PCI clock must be restarted in order to pass the interrupt because neither the internal oscillator nor an external clock is routed to the serial interrupt state machine Figure 3 16 is a functional implementation diagram xRST xRSTIN PC14410 Core SUSPEND GNT SUSPENDIN PCLKIN PCLK Figure 3 16 Suspend Functional Implementation Figure 3 17 is a signal diagram of the suspend function SUSPEND PCLK External Terminals Internal Signals xRSTIN SUSPENDIN Figure 3 17 Signal Diagram of Suspend Function 3 8 5 Requirements for Suspend Mode The suspend mode prevents the clearing of all register contents on the asse
85. H field must match the 13 bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins Contains a 15 bit value corresponding to the lower order 2 bits of cycleSeconds and 13 bit CYCLEMATCH cycleCount field If CYCLEMATCHENABLE is set to 1 then this IT DMA context becomes enabled for transmits when the bus cycleCount value equals the CYCLEMATCH value This bit is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing The PCI4410 only changes this bit on a hardware or software reset Reserved Bits 14 and 13 return Os when read Software sets this bit to 1 to cause the PCI4410 to continue or resume descriptor processing The PCI4410 resets this bit to O on every descriptor fetch The PCI4410 sets this bit to 1 when it encounters a fatal error and resets the bit to O when software resets the RUN bit to 0 ACTIVE The PCI4410 sets this bit to 1 when it is processing descriptors Reserved Bits 9 and 8 return 0 when read Following an OUTPUT LAST command the error code is indicated in this field Possible values are ack complete evt descriptor read evt data read and evt unknown 9 35 9 40 Isochronous Transmit Context Command Pointer Register This register contains a pointer to the address of the first descriptor block that the PCI4410 will access when software enables an ISO transmi
86. HANNEL53 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 53 20 ISOCHANNEL52 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 52 19 ISOCHANNEL51 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 51 18 ISOCHANNEL50 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 50 17 ISOCHANNEL49 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 49 ISOCHANNEL48 ISOCHANNEL47 When set to 1 the PCI4410 is enabled to receive from ISO channel number 47 ISOCHANNEL46 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 46 ISOCHANNEL45 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 45 ISOCHANNEL44 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 44 ISOCHANNEL43 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 43 ISOCHANNEL42 ba n O When set to 1 the PCI4410 is enabled to receive from ISO channel number 48 alo Es ko O sk as DO Bs E E m ko O When set to 1 the PCI4410 is enabled to receive from ISO channel number 42 9 ISOCHANNEL41 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 41 8 ISOCHANNEL40 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 40 7 ISOCHANNEL39 RSC When set to 1 the PCI4410
87. I address lines on the PCI bus PCI initiator ready IRDY indicates the PCI bus initiator s ability to complete the current data phase of the IRDY VO transaction A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted Until IRDY and TRDY are both sampled asserted wait states are inserted AR parity error indicator PERR is driven by a PCI device to indicate that calculated parity does not match PEFR EET when PERR is enabled through bit 6 of the command register see Section 4 4 ae PCI bus request REQ is asserted by the PCI4410 to request access to the PCI bus as an initiator PCI system error SERR is an output that is pulsed from the PCI4410 when enabled through bit 8 of the command register see Section 4 4 indicating a system error has occurred The PCI4410 need not be the target of the PCI cycle to assert this signal When SERR is enabled in the command register this signal also pulses indicating that an address parity error has occurred on a CardBus interface support burst data transfers PCI target ready TRDY indicates the primary bus target s ability to complete the current data phase of the transaction A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted Until both IRDY and TRDY are asserted wait states are inserted PCI cycle stop signal STOP is driven by a PCI target to request the initiator to stop the current PCI bus R2 VO transaction STOP i
88. I4410 and may warrant notification of host card and socket services software for service CSC events include both card insertion and removal from PC Card sockets as well as transitions of certain PC Card signals Table 3 7 summarizes the sources of PC Card interrupts and the type of card associated with them CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket The three types of cards that can be inserted into any PC Card socket are e 16 bit memory card e 16 bit VO card e CardBus cards Table 3 7 Interrupt Mask and Flag Registers Battery conditions ExCA offset 05h 805h ExCA offset 04h 804h 16 bit BVD1 BVD2 bits 1 and O bits 1 and O memory Wait states ExCA offset 05h 805h ExCA offset 04h 804h READY bit 2 bit 2 Change in card status ExCA offset 05h 805h ExCA offset 04h 804h STSCHG bit 0 bit 0 16 bit VO Interrupt request PCI configuration offset 91h IREQ NA All 16 bit RE Ed EXCA offset 05h 805h ExCA offset 04h 804h PC Cards di COMP bit 3 bit 3 Change in card status Socket mask Socket event CSTSCHG bit 0 bit 0 Interrupt request PCI configuration offset 91h CINT Always enabled bit 0 CardBus Socket mask Socket event bit 3 bit 3 Card insertion or Socket mask Socket event removal bits 2 and 1 bits 2 and 1 Power cycle complete Functional interrupt events are valid only for 16 bit VO and CardBus cards that is the functional interrupts are not valid for 16 bit memor
89. ION ES this field reads 01h RSVD R Reserved Bits 15 8 return Os when read REVISION Minor version of the open HCI The PC14410 is compliant with the OHCI specification version 1 00 thus ie this field reads 00h 9 4 9 2 GUID ROM Register This register is used to access the serial ROM andis only applicable if the GUID ROM bits are set to 1 See Table 9 3 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 2t 20 19 18 17 16 Name O GUIDROM GUID ROM we Rsu R R A R R Rsu R Ru AU RU RU RU RU RU RU m CA EC E EN O CI CO E CO RI CO E E E rs Name PI ROM GUID ROM Register GUID ROM Type Read only Read Set Update Read Update Offset 04h Default 00XX 0000h Table 9 3 GUID ROM Register BIT SIGNAL TYPE FUNCTION 34 ADDRRESET Software sets this bit to 1 to reset the GUID ROM address to 0 When the PCI4410 completes the reset it clears this bit The PCI4410 does not automatically fill bits 23 16 RDDATA field with the oth byte 30 26 RSVD R Reserved Bits 30 26 return Os when read 25 RDSTART RSU A read of the currently addressed byte is started when this bit is set to 1 This bit is automatically cleared when the PCI4410 completes the read of the currently addressed GUID ROM byte RSVD R Reserved Bit 24 returns 0 when read 23 16 RDDATA RU This field represents the data read from the GUID ROM RSVD R Reser
90. If IRQ2 is selected by SMIROUTE then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ Data slot In a parallel ISA IRQ system the support for an active low IRQ2 is provided only if IRQ2 is routed to MFUNC1 MFUNCS or MFUNCS through the multifunction routing register see Section 4 32 3 8 Power Management Overview In addition to the low power CMOS technology process used for the PCI4410 various features are designed into the device to allow implementation of popular power saving techniques These features and techniques are discussed in this section 3 8 4 Clock Run Protocol The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI4410 CLKRUN signaling is provided through the MFUNC6 terminal Because some chipsets do not implement CLKRUN this is not always available to the system designer and alternative power saving features are provided For details on the CLKRUN protocol see the PCI Mobile Design Guide The PCI4410 does not permit the central resource to stop the PCI clock under any of the following conditions e Bit 1 KEEPCLK in the system control register see Section 4 29 is set e The PC Card 16 resource manager is busy e The PCI4410 CardBus master state machine is busy A cycle may be in progress on CardBus e The PCI4410 master is busy There may be posted data from CardBus to PCI in the PCI4410 e Interrupts are pending e The CardBus CCLK for either socket has n
91. MECLK SEE generate PME Version Bits 2 0 return 001b when read indicating that there are four bytes of general purpose power management PM registers as described in the PCI Bus Power Management Interface Specification 2 0 VERSION See system control register PCI offset 80h Section 4 29 PCIPMEN bit 23 for additional information It is recommended that the PCIPMEN bit be set by BIOS If PCIPMEN is set then VERSION bits 2 0 will return 010b indicating support for version 1 1 of the PCI Bus Power Management Interface Specification 4 28 4 42 Power Management Control Status Register The power management control status register determines and changes the current power state of the PCI4410 CardBus function The contents of this register are not affected by the internally generated reset caused by the transition from D3 to DO state All PCI EXCA and CardBus registers are reset as a result of a D er to DO state transition Tl specific registers PCI power management registers and the legacy base address register are not reset See Table 4 17 for a complete description of the register contents Bit 15 14 13 12 n 10 9 8 7 6 Name Power management control status we ac rR e n n n R ew ea n JR R PR R Rw Rw Deta o o o o fo fo fofotototoftofoftotfoto Register Power management control status Type Read only Read Write Read Write to Clear Offset A4h Default 0000h Table 4
92. N AO e I I PRA ee EIE O O O A ID EP PY M O O JO C1 I Co List of Tables Title Page CardBus And 16 Bit PC Card Signal Names by PDV Terminal Number 2 4 CardBus And 16 Bit PC Card Signal Names by GHK Terminal Number 2 6 CardBus PC Card Signal Names Sorted Alphabetically to GHK PDV Terminal Number 2 8 16 Bit PC Card Signal Names Sorted Alphabetically to GHK PDV Terminal Number si 24 oun ede hows OM AE EE OES 2 10 Power Supply Terminals 2 12 PC Card Power Switch Terminals 2 12 PC System Terminal S oco KAAU AG dnd daha DOP RES HD EE EE 2 12 PCI Address and Data Terminals EE EE EE EE ee ek ee ke ee 2 13 PCI Interface Control Terminals kis SIE 8 seein ds RR RR RET RE RE 2 14 Multifunction and Miscellaneous Terminals suus 2 15 16 Bit PC Card Address and Data Terminals 2 16 16 Bit PC Card Interface Control Terminals ss EE Ee se ee 2 17 CardBus PC Card Interface System Terminals 2 18 CardBus PC Card Address and Data Terminals 2 19 CardBus PC Card Interface Control Terminals 2 20 IEEE1394 PHY Link Interface Terminals 2 21 Zoomed Video Interface Terminals 2 21 PC Card Card Detect and Voltage Sense Connections 3 4 Distributed DMA Registers iese EE Ge eee eke ee ee Re eee 3 9 PO POI Channel Assignments ua ob AEN E e dee EROR RO EROR ORE n 3 10 VO
93. NAL TYPE FUNCTION Card ring indicate enable Bit 7 enables the ring indicate function of BVD1 RI This bit is encoded as 7 RINGEN O Ring indicate disabled default 1 Ring indicate enabled Card reset Bit 6 controls the 16 bit PC Card RESET and allows host software to force a card reset Bit 6 RESET affects 16 bit cards only This bit is encoded as 0 RESET signal asserted default 1 RESET signal deasserted Card type Bit 5 indicates the PC card type This bit is encoded as 5 CARDTYPE 0 Memory PC Card installed default 1 VO PC Card installed PCI Interrupt CSC routing enable bit When bit 4 is set high the card status change interrupts are routed to PCI interrupts When low the card status change interrupts are routed using bits 7 4 CSCSELECT field 4 CSCROUTE in the ExCA card status change interrupt configuration register see Section 5 6 This bit is encoded as 0 CSC interrupts are routed by ExCA registers default 1 CSC interrupts are routed to PCI interrupts Card interrupt select for VO PC Card functional interrupts Bits 3 0 select the interrupt routing for I O PC Card functional interrupts This field is encoded as 0000 No interrupt routing default CSC interrupts routed to PCI interrupts These bit settings along with bit 4 CSCROUTE are combined through an OR function for backwards compatibility 0001 IRQ1 enabled 0010 SMI enabled 0011 IRQ3 enabled 0100 IRQ4 enabled 0101 2 IRQ5
94. ND se wel cam D ller ws em wrunca e Pio voc er one uso xw owt fumo mo wruncs amp pn voc es wr 2 8 Table 2 3 CardBus PC Card Signal Names Sorted Alphabetically to GHK PDV Terminal Number Continued TTE SIGNAL NAME Fam eng SIGNAL NAME spy J GEK SIGNAL NAME sov ene Ncc o ms voce si wi asoma no wis avse 96 via Fico e es Voce 60 ve umm ue mz Java o ns cc iss ar vens er ve zov re wie vv ou ec ime ws vreo ee uw Jare rr es aw 99 wis 2 9 Table 2 4 16 Bit PC Card Signal Names Sorted Alphabetically to GHK PDV Terminal Number SIGNAL NAME ais EES SIGNAL NAME SIGNAL NAME SIGNAL NAME Es pov ew pov ew pow ew os 7s us wem is ve peveer s s gee aoa Fo o n ve ams 39 ria eno 6 e1 Prv parna 206 6 ma f vo aona is ri evo as ws rav Daras Lais is ss us noms ss cis eno ss ws eco 1 01 os 7 Fe annie is os eno ra ro Prv neo om Es ios es s aone 3s rs ovo no ato Prv nevo 3 Fs a sr vs aone ie e ovs fue en paso o re ius e er Anes is eva ovo Leslie o os mecs re E oue cem EE pe BVDI 183 EI E PHY RSVD 12 ne STSCHG RI Coroa E a EE E A eese RT E ma s o omes Ke om var nia renova ve v x um ies ao use
95. OOOOOQOOOOOO uOoommaortzcarazumucc z 11 13 15 1 12 14 16 1 40 MAX Seating Plane 4145273 2 B 12 98 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Micro Star BGA configuration Micro Star is a trademark of Texas Instruments Incorporated PDV S POFP G208 PLASTIC QUAD FLATPACK 0 13 NOM i murem 0 25 4 25 50 TYP 28 05 27 95 30 20 29 80 sa 0 05 MIN 0 75 0 45 Seating Plane 0 08 1 60 MAX 4087729 D 11 98 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 11 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the rightto make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standa
96. Output e e by Receiver N Figure 3 10 Serial Bus Protocol Acknowledge The PCI4410 is a serial bus master all other devices connected to the serial bus external to the PCI4410 are slave devices As the bus master the PCI4410 drives the SCL clock at nearly 100 kHz during bus cycles and places SCL in a high impedance state zero frequency during idle states Typically the PCI4410 masters byte reads and byte writes under software control Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control See Section 3 6 3 Serial Bus EEPROM Application for details on how the PCI4410 automatically loads the subsystem identification and other register defaults through a serial bus EEPROM Figure 3 11 illustrates a byte write The PCI4410 issues a start condition and sends the 7 bit slave device address and the command bit zero A 0 in the R W command bit indicates that the data transfer is a write The slave device acknowledges if it recognizes the address The word address byte is then sent by the PCI4410 and another slave acknowledgmentis expected Then the PCI4410 delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition Slave Address Word Address Data Byte 8 be b5 pa os o or bo fo A oz be os ba os bz pr oo A pr ee bs oa bs v2 bi oo P 2
97. PCI Bus Lock LOCK The bus locking protocol defined in the PCI Local Bus Specification is not highly recommended but is provided on the PCI4410 as an additional compatibility feature The PCI LOCK signal can be routed to the MFUNCA terminal via the multifunction routing register See Section 4 32 Multifunction Routing Register for details Note that the use of LOCK is only supported by PCI to CardBus bridges in the downstream direction away from the processor PCILOCK indicates an atomic operation that may require multiple transactions to complete When LOCK is asserted nonexclusive transactions can proceed to an address that is not currently locked A grant to start a transaction on the PCI bus does not guarantee control of LOCK control of LOCK is obtained under its own protocol It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions but the master wants exclusive rights to a region of memory The granularity of the lock is defined by PCI to be 16 bytes aligned The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock without interfering with nonexclusive real time data transfer such as video The PCI bus arbiter may be designed
98. RODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance or customer product design TI does not warrantor representthat any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used TI s publication of information regarding any third party s products or services does not constitute TI s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated Contents Section Title Page 1 lIhitroduclioh ies EE e ET N ER ran 1 1 1 1 Bede E ee 1 1 1 2 FOGO Pt 1 1 1 3 Related Documents iui mcd rex dou sea cade dee a eek 1 3 1 4 Ordering Information ese Ee EE ee RR EE ER Ee ek Re ee ke 1 3 2 Terminal DescriptioliS ege ska ss paba DEE ax k E HE RE DE N ARE ARE N EEN 2 1 3 Feature Protocol Descriptions iss saak kaak REK RARR AA RR AE KA 3 1 3
99. RWU RWU RWU RWU RWU Register Isochronous cycle timer Type Read Write Update Offset FOh Default XXXX XXXXh Table 9 23 Isochronous Cycle Timer Register SIGNAL TYPE FUNCTION 31 25 CYCLESECONDS This field counts seconds cycleCount rollovers modulo 128 24 12 CYCLECOUNT This field counts cycles cycleOffset rollovers modulo 8000 This field counts 24 576 MHz clocks modulo 3072 that is 125 us If an external 8 kHz clock BREED configurationis being used then CYCLEOFFSET mustbe resetto 0 at each tick ofthe external clock 9 26 9 32 Asynchronous Request Filter High Register This set clear register is used to enable asynchronous receive requests on a per node basis and handles the upper node IDs When a packet is destined for either the physical request context or the ARRQ context the source node ID is examined If the bit corresponding to the node ID is not set to 1 in this register then the packet is not acknowledged and the request is not queued The node ID comparison is done if the source node is on the same bus as the PCI4410 All nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set to 1 See Table 9 24 for a complete description of the register contents Bit 31 30 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 Asynchronous request filter high Bean o o 0 o fo fo fo fo fo fo fo foto lo lo ol Asynchronous request filter high
100. SCL and SDA signals are bidirectional open drain signals and require pullup resistors as shown in Figure 3 8 The PCI4410 supports up to 100 Kb s data transfer rate and is compatible with standard mode 12C using 7 bit addressing All data transfers are initiated by the serial bus master The beginning of a data transfer is indicated by a start condition which is signalled when the SDA line transitions to a low state while SCL is in the high state as illustrated in Figure 3 9 The end of a requested data transfer is indicated by a stop condition which is signaled by a low to high transition of SDA while SCL is in the high state as shown in Figure 3 9 Data on SDA must remain stable during the high state of the SCL signal as changes on the SDA signal during the high state of SCL are interpreted as control signals that is a start or a stop condition df c NETTES AE AN Start Stop Change of Condition Condition Data Allowed Data Line Stable Data Valid Figure 3 9 Serial Bus Start Stop Conditions and Bit Transfers Data is transferred serially in 8 bit bytes The number of bytes that may be transmitted during a data transfer is unlimited however each byte must be completed with an acknowledge bit An acknowledge ACK is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal Figure 3 10 illustrates the acknowledge protocol SCL From Master by Transmitter I SDA
101. Socket Power Management Register is EE aa 6 8 Distributed DMA DDMA Registers s esee 7 1 fl DDMA Current Address Base Address Register A 7 2 DDMA Page tement va deeg ur eh DEE BP EE HR DE ae 7 2 7 3 DDMA Current Count Base Count Register 7 2 7 4 DDMA Command Register sie se ke KGG Ded oet i REKE ENE SIL 7 3 is DDMA Status Register is carted REC px re phe epee 7 3 7 6 DDMA Request Register 7 4 7 7 DDMA Mode Register RE ke as EER Ee Re ke Re ek ee 7 4 7 8 DDMA Master Clear Register 7 5 7 9 DDMA Multichannel Mask Register 7 5 OHCI Lynx Controller Programming Model 8 1 8 1 PCI Configuration Registers a EEN eee a RR EERS NNN EEN add 8 1 8 2 Vendor ID RE isSter ee EE RE DE EE De OE gh 8 2 8 3 Device ID Register cs paa e EER RR REFER ER EER EER SERE RE Ex 8 2 8 4 POlCommand Register sain he ER EE EER RES RESP WESE cay 8 3 8 5 POI Slats REGIS naaa kam hee kerekan Sire DE n 8 4 8 6 Class Code and Revision ID Register 8 5 8 7 Latency Timer and Class Cache Line Size Register 8 5 8 8 Header Type and BIST Register eee eee eee 8 6 8 9 Open HCI Registers Base Address Register 8 6 8 10 TI Extension Base Address Register Lsuue 8 7 8 11 X PCI Subsystem Identification Register 8 8 8 12 PCI Power Management Capabi
102. Table 4 5 for a complete description of the register contents et 15 14 13 r2 vt 10 9 8 v e j s ja ts 2 1 jo Bridge control Name Bridge control Type R aR AR R R_ Rw Rw Aw Aw Aw Rw R Lola oy Low pea o o o fo fo fo 1111 oe T1 To To To Jo To Tol Register Bridge control Type Read only Read Write Offset 3Eh Default 0340h Table 4 5 Bridge Control Register SIGNAL TYPE FUNCTION RSVD Reserved Bits 15 11 return Os when read Write posting enable Enables write posting to and from the CardBus sockets Write posting enables posting of write data on burst cycles Operating with write posting disabled inhibits performance on burst cycles Note that bursted write data can be posted but various write transactions may not e POSTEN Memory window 1 type Bit 9 specifies whether or not memory window 1 is prefetchable This bit is socket dependent Bit 9 is encoded as 0 Memory window 1 is nonprefetchable 1 Memory window 1 is prefetchable default PREFETCH1 Memory window 0 type Bit 8 specifies whether or not memory window 0 is prefetchable This bit is encoded as 0 Memory window 0 is nonprefetchable 1 Memory window 0 is prefetchable default PREFETCHO PCI interrupt IREQ routing enable Bit 7 selects whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers O Functional interrupts ro
103. VAR 4 5 4 7 PCI Class Code Register asas sk En ae ee RR EE GER DR re ER EED 4 5 4 8 Cache Line Size Register EE a 4 5 4 9 Latency Timer Register iss RR Ee RE EE Ee ek ee ek eee 4 6 4 10 Header Type Register iii ss ee ss ee eke Gee ees 4 6 4 11 BIST Register CAE EEN EEN GARIE m hr E rhe e FOR ds 4 6 4 12 CardBus Socket ExCA Base Address Register 4 7 4 13 Capability Pointer Register ii ii a 4 7 4 14 Secondary Status Register 4 8 415 PCI Bus Number Register ucc EE EE DE E REDE ER RR 4 9 4 16 CardBus Bus Number Register 4 9 4 17 Subordinate Bus Number Register ii iss EE RR Re ee ke ee 4 9 4 18 CardBus Latency Timer Register 4 10 4 19 Memory Base Registers 0 1 cece eee eee 4 10 4 20 Memory Limit Registers 0 1 isses Es NEIE ENE er EA WEE SE EE ER 4 11 421 I O Base Registers 0 4 11 4 22 WO Limit Registers D 1 lose RR hr ERR rmm RR ens 4 12 4 23 Interrupt Line Register iine epp E cbr Dro a aae cn tees 4 12 4 24 Interrupt Pin Register 4 13 4 25 Bridge Control Register 4 14 4 26 Subsystem Vendor ID Register iss EE RE Se RR ed ee ke 4 15 4 27 Subsystem ID Register ii ss 0 00 cece eee ee ke 4 15 4 28 PC Card 16 Bit I F Legacy Mode Base Address Register 4 15 4 29 System Control Register capas sineira sds dd Eee dace p Eos 4 16 4 30 General Status Register eee eee eee 4
104. X X V 6 4 VCCCTRL R W 001 Reserved 101 Request Voc Y Y V 010 Request Vcc 5V 110 Reserved 011 Request Voc 3 3 V 111 Reserved RSVD R Reserved Bit 3 returns 0 when read Vpp control Bits 2 0 request card Vpp changes 000 Request power off default 100 Request Vpp X X V 2 0 VPPCTRL R W 001 Request Vpp 12 V 101 Request Vpp Y Y V 010 Request Vpp 5 V 110 Reserved 011 Request Vpp 3 3 V 111 Reserved 6 7 6 6 Socket Power Management Register This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle See Table 6 7 for a complete description of the register contents Socket power management Name Tee R R R RIR R R R RIRLR R R R R aw pea o o o o fo fo fo 10 o Jo To 10 To Jo To fo Register Socket power management Type Read only Read Write Offset CardBus socket address 20h Default 0000 0000h Table 6 7 Socket Power Management Register SIGNAL TYPE FUNCTION 31 26 RSVD R Reserved Bits 31 26 return Os when read Socket access status This bit provides information on when a socket access has occurred This bit is cleared by a read access ep GEES 0 A PC Card access has not occurred default 1 A PC Card access has occurred Socket mode status This bit provides clock mode information 24 SKTMODE O Clock is operating normally 1 Clock frequency ha
105. ables the memory and VO windows to the 16 bit PC Card By default all windows to the card are disabled The PCI4410 does not acknowledge PCI memory or VO cycles to the card if the corresponding enable bit in this register is 0 regardless of the programming of the memory or I O window start end offset address registers See Table 5 9 for a complete description of the register contents at v7 j e s 4 2 1 90 Name ExCA address window enable Tyee aw aw A Aw w AW w am Register ExCA address window enable Type Read only Read Write Offset CardBus socket address 806h ExCA offset 06h Default 00h Table 5 9 ExCA Address Window Enable Register SIGNAL TYPE FUNCTION VO window 1 enable Bit 7 enables disables VO window 1 for the PC Card This bit is encoded as IOWIN1EN R W 0 VO window 1 disabled default 1 VO window 1 enabled VO window 0 enable Bit 6 enables disables VO window 0 for the PC Card This bit is encoded as IOWINOEN R W 0 VO window 0 disabled default 1 VO window 0 enabled Reserved Bit 5 returns 0 when read Memory window 4 enable Bit 4 enables disables memory window 4 for the PC Card This bit is encoded as 0 Memory window 4 disabled default 1 Memory window 4 enabled RSVD MEMWINAEN Memory window 3 enable Bit 3 enables disables memory window 3 for the PC Card This bit is Memory window 2 enable Bit 2 enables disables memory window 2 for the PC Ca
106. access the bus management CSR registers from the host through compare swap operations This register is used to control the compare swap operation and select the CSR resource See Table 9 5 for a complete description of the register contents CSR control Register CSR control Type Read only Read Update Read Write Offset 14h Default 0000 0000h Table 9 5 CSR Control Register CSRDONE This bit is set to 1 by the PCI4410 when a compare swap operation is complete It is reset to O whenever ES this register is written CSRSEL Reserved Bits 30 2 return Os when read This field selects the CSR resource as follows 00 BUS MANAGER ID 01 BANDWIDTH AVAILABLE 10 CHANNELS AVAILABLE HI CHANNELS AVAILABLE LO 9 8 9 7 Configuration ROM Header Register This register externally maps to the first quadlet of the 1394 configuration ROM offset FFFF F000 0400h See Table 9 6 for a complete description of the register contents m I IeIsIsIzIslsisIsielIsIsIsISITvI wm CefgraknROMRee ew o o fofo o o o o o o o jo fofo fo fo Bit 1 Ji 12 n 10 9 8 7 e j 5 4 93 2 jJ 1 Configuration ROM header ear x x X x Tx TX TX 1X EX T LX LX Ex TX T3 Register Configuration ROM header Type Read Write Offset 18h Default 0000 XXXXh Table 9 6 Configuration ROM Header Register SIGNAL TYPE FUNCTION 31 24 INFO LENGTH IEEE 1394 bus mana
107. address decode Thus the window is aligned to a natural 16 byte boundary EXTMODE Extended addressing This feature is not supported by the PCI4410 and always returns a 0 Transfer size Bits 2 and 1 specify the width of the DMA transfer on the PC Card interface and are encoded as 00 Transfers are 8 bits default 2 XFERSIZE did 01 Transfers are 16 bits 10 Reserved 11 Reserved DDMA registers decode enable Enables the decoding of the distributed DMA registers based on the value of bits 15 4 DMABASE field DOME ER mala O Disabled default 1 Enabled 4 26 4 39 Capability ID Register The capability ID register identifies the linked list item as the register for PCI power management The register returns 01h when read which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value rogos qoos Ja qno PEN EE FA Bi ES Name O CabiliD we R R R R R R pea o o o o o j o Register Capability ID Type Read only Offset AOh Default 01h 4 40 Next Item Pointer Register The next item pointer register indicates the next item in the linked list of the PCI power management capabilities Because the PCI4410 functions include only one capabilities item this register returns 0s when read gu 7 e j s a s j 2 j 1 o Name PO Netempome Tee R R R j R R R R R Dea o o o o o o o o
108. ange register is cleared see Section 5 5 If this bit is a 0 then the card detect resume functionality is disabled O Card detect resume disabled default 1 Card detect resume enabled RSVD R Reserved Bits 3 and 2 return 0s when read Register configuration on card removal Bit 1 controls how the ExCA registers for the socket react to a card removal event This bit is encoded as i REGGONFIG SP O No change to ExCA registers on card removal default 1 Reset ExCA registers on card removal o RSVD R Reserved Bit 0 returns 0 when read 5 21 5 22 ExCA Global Control Register The ExCA global control register controls the PC Card socket The hostinterrupt mode bits in this register are retained for Intel 82365SL DF compatibility See Table 5 15 for a complete description of the register contents ES o 7 d e 5 4 s 2 1 o ExCA global control YY Ha ne 8 A A J w aw Aw Aw AW Demo o o o po po fo o Register ExCA global control Type Read only Read Write Offset CardBus socket address 81Eh ExCA offset 1Eh Default 00h Table 5 15 ExCA Global Control Register SIGNAL TYPE FUNCTION RSVD R Reserved Bits 7 5 return Os when read This bit has no assigned function Level edge interrupt mode select Bit 3 selects the signaling mode for the PCI4410 host interrupt This bit is encoded as S INTMODE S O Host interrupt is edge mode default 1 Host interrupt is level mod
109. anical Information sse nnn m IR mm hm 11 1 viii Figure List of Illustrations Title Page PCI to CardBus Terminal Diagram 2 1 PCI to PC Card 16 Bit Terminal Diagram 2 2 MicroStar BGA Ball Diagram 2 3 PCI4410 System Block Diagram ennan n nnana 3 1 3 State Bidirectional Butter 3 2 TPS2211 Terminal Assignments iis amid ue m 3 4 TPS2211 Typical Application usse eek GARAGE 3 5 Zoomed Video Subsystem 3 5 Sample Application of SPKROUT and CAUDPWM 3 7 Two sample LED GI puma nkaka hahahhaha Ere Pe DE DE E 3 8 Serial EEPROM Application sie use ee ER REK DEE De RR ER FER ERE 3 11 Serial Bus Start Stop Conditions and Bit Transfers 3 12 Serial Bus Protocol Acknowledge 3 12 Serial Bus Protocol Byte Write se SIE nes RE ag ED BANGAG NG one 3 13 Serial Bus Protocol Byte Head 3 13 EEPROM Interface Doubleword Data Collection 3 13 EEPROM Data Format 4s invests ER RE SR GE GR LENG KENA SR SE RE dene be 3 15 RQ lay 01 CPP AA AA 3 18 Suspend Functional Implementation a 3 20 Signal Diagram or Suspend Function iii VEE paw oes Rx Rn 3 21 Ri OUT Functional Diagram x x cr tis pex hup e EEN 3 22 ExCA Register Access Through VO uie es pama ana n nn 5 1 ExCA Register Access Through Memory aaa 5 1 Accessing CardBus Socket Registers Through PCI Memory 6 1 kk da kl do d dig d ep dh NOT OR WO
110. are 3 15 3 7 Programmable Interrupt Subsystem aa 3 15 3 7 1 PC Card Functional and Card Status Change Interrupts 3 16 3 7 2 Interrupt Masks and Flags 3 17 3 7 3 Using Parallel IRQ Interrupts 3 18 3 7 4 Using Parallel PCI Interrupts EEN EEN EEN hahaa 3 18 3 7 5 Using Serialized IRQSER Interrupts 3 18 3 7 6 SMI Support in the PCIA410 SEKR orn 3 19 3 8 Power Management Overview 3 19 3 8 1 Clock Run Protocol sea zx Reha nb ee ER EAR 3 19 3 8 2 CardBus PC Card Power Management 3 19 3 8 3 16 Bit PC Card Power Management 3 20 3 8 4 Suspend Mode 3 20 3 8 5 Requirements for Suspend Mode 3 21 3 8 6 RING Indieal Ee EERDER re eds SED LA DE eens 3 21 3 8 7 PCI Power Management 3 22 3 8 8 CardBus Bridge Power Management 3 23 3 8 9 ACPI Suppott ioo EE EES EER ris RE DE DEE KG 3 23 3 8 10 Master List of PME Context Bits and Global Reset Only BIG spears e Tape ice Rene OT EE AA A S ak 3 24 4 PC Card Controller Programming Model 4 1 4 1 PCI Configuration Registers Functions 0 and 1 4 1 4 2 Vendor ID Register 3 80 re re E RR ER SEE ER AR DEE REFS 4 2 4 3 Device EE RR bain e ER vale d ios pan DESEN ees 4 2 4 4 Command Register ouis su OR EER ER ee ech ERE EHE 4 3 4 5 Status Register 4 4 4 6 Revision ID Register onesteari rss sd es Tess EER NA WESE DA
111. are preserved PCI bus clock PCLK provides timing for all transactions on the PCI bus All PCI signals are sampled at the PCLK 37 M6 n rising edge of PCLK PCI bus reset When the PCI bus reset is asserted PRST causes the PCI4410 to place all output buffers in a high impedance state and reset internal registers When PRST is asserted the device is completely PRST 36 M3 nonfunctional After PRST is deasserted the PCI4410 is in a default state When SUSPEND and PRST are asserted the device is protected from PRST clearing the internal registers All outputs are placed in a high impedance state but the contents of the registers are preserved Table 2 8 PCI Address and Data Terminals LER DESCRIPTION Por ome PCI address data bus These signals make up the multiplexed PCI address and data bus on the primary interface During the address phase of a primary bus PCI cycle AD31 ADO contain a 32 bit address or other destination information During the data phase AD31 ADO contain data PCI bus commands and byte enables These signals are multiplexed on the same PCI terminals During the address phase of a primary bus PCI cycle C BE3 C BEO define the bus command During the data phase this 4 bit bus is used as byte enables The byte enables determine which byte paths of the full 32 bit data bus carry meaningful data C BEO applies to byte 0 AD7 ADO C BE1 applies to byte 1 AD15 AD8 C BE2 applies to byte 2 AD23 AD16 and C
112. atus of the PCI4410 serial EEPROM circuitry This EEBUSY bit is set during the loading of the subsystem ID value 0 Serial EEPROM circuitry is not busy default 1 Serial EEPROM circuitry is busy 4 31 General Control Register The general control register provides top level PCI arbitration control See Table 4 8 for a complete description of the register contents General control Register General control Type Read Only Read Write Offset 86h Default 00h Table 4 8 General Control Register ra mag R Remek iramumoswenmad S 2 wo Rm Reserved Bi 2rewms Owren OO OSS Controls top level PCI arbitration 00 1394 open HCI priority 1 0 ARB_CTRL RW 01 CardBus priority 10 Fair round robin 11 Reserved fair round robin 4 19 4 32 Multifunction Routing Register The multifunction routing register is used to configure the MFUNCO MFUNCS6 terminals These terminals may be configured for various functions All multifunction terminals default to the general purpose input configuration This register is intended to be programmed once at power on initialization The default value for this register may also be loaded through a serial bus EEPROM See Table 4 9 for a complete description of the register contents m IsIsIsIsIzIsIs IsIsIeIsIsIs w I7T m Bee we A A A A 9v v a aw ew uw Tw Tw AW AW AW a bw o o o o fo fofo fofo fofo fo oo of
113. ber and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses CardBus bus number R W Register CardBus bus number Type Read Write Offset 19h Default 00h 4 17 Subordinate Bus Number Register This register is programmed by the host system to indicate the highest numbered bus below the CardBus bus The PCI4410 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses st 7 6 5 4 3 2 1 9 Name Subordinate bus number we mw am AW am AW AW Register Subordinate bus number Type Read Write Offset 1Ah Default 00h 4 9 4 18 CardBus Latency Timer Register This register is programmed by the host system to specify the latency timer for the PC14410 CardBus interface in units of CCLK cycles When the PCIA410 is a CardBus initiator and asserts CFRAME the CardBus latency timer begins counting If the latency timer expires before the PCI4410 transaction has terminated then the PCI4410 terminates the transaction atthe end ofthe next data phase A recommended minimum value for this register is 20h which allows most transactions to be completed gu 7 6 s a s 2 j 1 o Name CardBus latency timer Hye RW RW RW RW RW Rw RW RW pea o o o j o o o o o Register CardBus latency ti
114. beyond the standard PCI configuration header before a generic class driver is able to use it Auxiliary power source Since the PCI4410 supports PME generation in the D3cold device state and requires Vaux this bit returns 1 when read PME clock This bit returns 0 when read indicating that no host bus clock is required for the PCI4410 to generate PME Power management version This field returns 001b when read indicating that the PCI4410 is compatible with the registers described in the revision 1 0 PCI Bus Power Management Specification 8 18 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function This register is not affected by the internally generated reset caused by the transition from the D3p to DO state See Table 8 15 for a complete description of the register contents ER opas 3e 3s om pow ow qp AAN KAK AE SERE AE BETER Power management control and status Type rc n R AR n n i R law n nn TR A OR Rw RW peau o o fo fo fo fo fo fo fo fo fo fo fo fo fo fo Register Power management control and status Type Read only Read Write Read Clear Offset 48h Default 0000h Table 8 15 Power Management Control and Status Register SIGNAL TYPE FUNCTION This bitis set to 1 when the PC14410 would normally be asserting the PME signal independent of the state of PME STS bit 8 PME ENB This b
115. bit The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal GPI3 DATA ES GPI3 data bit The value read from bit 3 represents the logical value of the data input from the MFUNCA terminal GPI2 DATA ES GPI2 data bit The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal GPI1 data bit The value read from bit 1 represents the logical value of the data input from the MFUNC1 1 GPI1 DATA terminal GPIO data bit The value read from bit O represents the logical value of the data input from the MFUNCO GPIO DATA termiha 4 33 4 48 General Purpose Output Register The general purpose output register is used for control of the general purpose outputs See Table 4 22 for a complete description of the register contents Bit 1 14 is r2 v 10 9 8 v fe 5 a ts feds fo General purpose output we R R JRJ RJ R RJ RJ R RJ R R Rw AW Rw Rw aw peas o o fo fo fo fo Jo To To To To To Jo foto fo Register General purpose output Type Read only Read Write Offset AEh Default 0000h Table 4 22 General Purpose Output Register SIGNAL TYPE FUNCTION RSVD Reserved Bits 15 5 return Os when read GPO4 DATA GPOA data bit The value written to bit 4 represents the logical value of the data driven to the MFUNC5 terminal if configured as GPO4 Read transactions return the last data value written GPOS DATA
116. bles an ISO receive context by setting the ContextControl run bit The n value in the following register addresses indicates the context number n 0 1 2 3 Bit 31 30 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 Isochronous receive context command pointer Register Isochronous receive context command pointer Type Read only Offset 40Ch 32 n Default XXXX XXXXh 9 38 9 43 Isochronous Receive Context Match Register This register is used to start an isochronous receive context running on a specified cycle number to filter incoming isochronous packets based on tag values and to wait for packets with a specified sync value The n value in the following register addresses indicates the context number n 0 1 2 3 See Table 9 32 for a complete description of the register contents et 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Isochronous receive context match Type RW RW RW RW R R R RW RW RW Raw RW RW RW RW Raw peut x x x x jJo olo x x x x x x x x x et 15 14 13 i2 0 00 9 8 7 6 5 22 23 2 1 90 Name Hype RW RW RW RW RW RW RW RW R RW RW RW RW R W RW rw pea x x x x x Jx x x Jo x x x x x x x Register Isochronous receive context match Type Read Write Read only Offset 410Ch 32 n Default XXXX XXXXh Tab
117. cal upper bound Type Read only Offset 120h Default 0000 0000h 9 32 9 37 Asynchronous Context Control Register This set clear register controls the state and indicates status of the DMA context See Table 9 28 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 zt 20 19 18 t7 16 Asynchronous context control Tee R R R RIR R R R RIR R R R R R R pea o o o o fo oo fo fo fo fo fo fo Jo oo do 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 it Eiers EE RES Default 0 X 0 0 X X X X X X X X Register Asynchronous context control Type Read Set Clear Update Read Set Update Read Update Read only Offset 180h setregister ATRQ 184h clear register ATRQ 1A0h set register ATRS 1A4h clear register ATRS 1COh set register ARRQ 1C4h clear register ARRQ 1EOh set register ATRS 1E4h clear register ATRS Default 0000 XOXXh Table 9 28 Asynchronous Context Control Register SIGNAL TYPE FUNCTION 31 16 RSVD R Reserved Bits 31 16 return Os when read 15 RUN RSCU This bitis set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing The PCI4410 will only change this bit on a hardware or software reset 14 13 RSVD R Reserved Bits 14 and 13 return Os when read Software sets this bit to 1 to cause the PCI4410 to continue or resume descriptor processing The PCI4410 12 W
118. change Type Read only Offset CardBus socket address 804h ExCA offset 04h Default 00h Table 5 7 ExCA Card Status Change Register SIGNAL TYPE FUNCTION RSVD Reserved Bits 7 4 return Os when read Card detect change Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card CDCHANGE interface This bit is encoded as READYCHANGE O No change detected on either CD1 or CD2 1 Change detected on either CD1 or CD2 Ready change When a 16 bit memory is installed in the socket bit 2 includes whether the source of a PCI4410 interrupt was due to a change on READY at the PC Card interface indicating that the PC Card is now ready to accept new data This bit is encoded as O No low to high transition detected on READY default 1 Detected low to high transition on READY When a 16 bit VO card is installed bit 2 is always 0 Battery dead or status change When a 16 bit memory card is installed in the socket bit 0 indicates whether the source of a PCI4410 interrupt was due to a battery dead condition This bit is encoded as 0 STSCHG deasserted default 1 STSCHG asserted Ring indicate When an VO card is installed in the socket and the PCI4410 is configured for ring indicate operation bit O indicates the status of RI Battery warning change When a 16 bit memory card is installed in the socket bit 1 indicates whether the source of a PCI4410 interrupt was due to a battery low warning condition This bit is
119. channel number specified in the IRDMA context match register is ignored When 0 the IRDMA context receives packets for that single channel Only one IRDMA context may use the IRChannelMask registers If more that one IRDMA context control register has the multiChanMode bit set to 1 then results are undefined The value of MULTICHANMODE must not be changed while ACTIVE or RUN is set to 1 Reserved Bits 27 16 return Os when read This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing The PCI4410 only changes this bit on a hardware or software reset T RU The PCI4410 sets this bit to 1 when it encounters a fatal error and resets the bit to O when software resets the RUN bit to 0 ACTIVE RU The PCI4410 sets this bit to 1 when it is processing descriptors 9 37 Table 9 31 Isochronous Receive Context Control Register Continued BIT SIGNAL TYPE FUNCTION 9 8 RSVD R Reserved Bits 9 and 8 return 0 when read This field indicates the speed at which the packet was received 000b 100 Mbits sec Wes SPD RU 001b 200 Mbits sec 010b 400 Mbits sec All other values are reserved 4 0 EVENT CODE Following an INPUT command the error code is indicated in this field 9 42 Isochronous Receive Context Command Pointer Register This register contains a pointer to the address of the first descriptor block that the PCI4410 will access when software ena
120. contiguously from 00h to 3Fh for the socket See Figure 5 1 for an EXCA I O mapping illustration PC14410 Configuration Registers Host I O Space Offset ERE Offset PC Card ooh ExCA CardBus Socket ExCA Base Address Registers 3Fh 16 Bit Legacy Mode Base Address Figure 5 1 ExCA Register Access Through VO The TI PCI4410 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space They are located through the CardBus socket ExCA base address register see Section 4 12 at memory offset 800h See Figure 5 2 for an EXCA memory mapping illustration This illustration also identifies the CardBus socket register mapping which is mapped into the same 4K window at memory offset Oh Host PC14410 Configuration Registers Memory Space S g Offset is Offset 00h CardBus Socket CardBus Socket ExCA Base Address Registers oh 16 Bit Legacy Mode Base Address Registers ME Figure 5 2 EXCA Register Access Through Memory As defined by the 82365SL DL Specification the interrupt registers in the ExCA register set control such card functions as reset type interrupt routing and interrupt enables Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI4410 to ensure that all possible PCI4410 interrupts can potentially be routed to the programmable interrupt controller The ExCA registers that are critical to the interrupt s
121. count Type Read Update Offset 68h Default X0XX 0000h Table 9 12 Self ID Count Register SIGNAL TYPE FUNCTION When this bit is 1 an error was detected during the most recent self ID packet reception The 31 SELFIDERROR RU contents of the self ID buffer are undefined This bit is cleared after a self ID reception in which no errors are detected Note that an error can be a hardware error or a host bus write error 30 24 RSVD oR Reserved Bits 30 24 return Os when read 23 16 SELFIDGENERATION oa aa field increments each time a bus reset is detected This field rolls over to 0 after 15 11 RSVD R Reserved Bits 15 11 return Os when read This field indicates the number of quadlets that have been written into the self ID buffer for the SELFIDSIZE current SELFIDGENERATION This includes the header quadlet and the self ID data This field is cleared to O when the self ID reception begins RSVD R Reserved Bits 1 and 0 return Os when read 9 19 ISO Receive Channel Mask High Register This set clear register is used to enable packet receives from the upper 32 isochronous data channels A read from either the set register or clear register returns the value of the IRChannelMaskHi register See Table 9 13 for a complete description of the register contents m 81 80 29 28 27 26 25 28 25 22 21 20 09 18 07 16 Name ISO receive channel mask high peau x x x x x x x Jx JX ERK
122. d
123. d Socket RI OUT Figure 3 18 RI OUT Functional Diagram RI from the 16 bit PC Card interface is masked by bit 7 RINGEN in the ExCA interrupt and general control register see Section 5 4 This is programmed on a per socket basis and is only applicable when a 16 bit card is powered in the socket The CBWAKE signaling to RI OUT is enabled through the same mask as the CSC event for CSTSCHG The mask bit bit 0 CSTSMASK is programmed through the socket mask register see Section 6 2 in the CardBus socket registers 3 8 7 PCI Power Management The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus The PCI bus and the PCI functions can be assigned one of four software visible power management states that result in varying levels of power savings The four power management states of PCI functions are e D0 Fully on state e D1 and D2 Intermediate states e D3 Off state Similarly bus power states of the PCI bus are BO B3 The bus power states BO B3 are derived from the device power state of the originating bridge device For the operating system OS to manage the device power states on the PCI bus the PCI function should support four power management operations These operations are Ca
124. d and indicates that the OHCI registers require a 2 Kbyte region of memory 3 OHCI PF OR OHCI register prefetch This bit returns 0 indicating the OHCI registers are nonprefetchable Open HCI memory type This field returns Os when read and indicates that the base register is 32 bits OHGI MEMTYPE ES wide and mapping can be done anywhere in the 32 bit memory space 0 OHCI MEM ES OHCI memory indicator This bit returns 0 indicating the OHCI registers are mapped into system memory space 8 6 8 10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory mapped TI extension registers See Table 8 9 for a complete description of the register contents Bit 31 30 29 28 27 26 25 2a 23 22 21 20 19 t8 17 16 TI extension base address Register Tl extension base address Type Read only Offset 14h Default 0000 0000h Table 8 9 TI Extension Base Address Register BIT SIGNAL TYPE FUNCTION 31 11 Tl EXTREG PTR o register pointer Specifies the upper 20 bits of the 32 bit TI extension register base Tl extension register size This field returns Os when read and indicates that the Tl extension registers ie require a 2 Kbyte region of memory TI memory type This field returns Os when read and indicates that the base register is 32 bits wide TEMEMTYEE and mapping can be done anywhere in the 32 bit memory space
125. d a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI Bits 31 12 of these registers are read write and allow the memory base to be located anywhere in the 32 bit PCI memory space on 4 Kbyte boundaries Bits 11 0 are read only and always return Os Write transactions to these bits have no effect Bits 8 and 9 of the bridge control register specify whether memory windows O and 1 are prefetchable or nonprefetchable The memory base register or the memory limit register must be nonzero for the PCI4410 to claim any memory transactions through CardBus memory windows that is these windows are not enabled by default to pass the first 4K bytes of memory to CardBus a 2 a 2 25 e 2 2 2 2 39 7 s Name Memory limit registers 0 1 Type RAW RW RW RW RW RW RW RW R W R W RW Deia o o o 0 o fo o o o o et 15 14 13 12 vt 10 9 8 7 6 Name Memory limit registers 0 1 Ka EE EE EE EE fo fo o 10 Jo 10 o 1 o fo o Register Memory limit registers 0 1 Type Read only Read Write Offset 20h 28h Default 0000 0000h 4 21 VO Base Registers 0 1 The VO base registers indicate the lower address of a PCI I O address range These registers are used by the PC14410 to determine when to forward an VO transaction to the CardBus bus and when to forward a CardBus cycle to the PCI bus The lower 16 bits of this register locate the bottom of the VO window within
126. d behaves identically to the GUID high register Name GUID low EEN ET N fo fo oo o o lo lo o o Register GUID low Type Read only Offset 28h Default 0000 0000h 9 12 Configuration ROM Mapping Register This register contains the start address within system memory that will map to the start address of 1394 configuration ROM for this node See Table 9 8 for a complete description of the register contents et 31 3o 29 28 27 26 25 2a 23 22 2t 20 19 18 17 16 Configuration ROM mapping Register Configuration ROM mapping Type Read only Read Write Offset 34h Default 0000 0000h Table 9 8 Configuration ROM Mapping Register SIGNAL TYPE FUNCTION If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh CONFIGROMADDR is received then the low order 10 bits of the offset are added to this register to determine the host memory address of the read request 9 0 men R jResevedBiso9 OretumOswhenread 9 13 Posted Write Address Low Register This register is used to communicate error information if a write request is posted and an error occurs while the posted data packet is being written See Table 9 9 for a complete description of the register contents Bit 31 3o 29 28 27 26 25 2a 23 22 2t 20 19 18 17 16 Posted write address low osted write address low Register Posted write address low Type Read Upda
127. d through the serial ROM interface after a PCI reset If no serial ROM is detected then these registers return a default value that corresponds to MIN GNT 3 MAX LAT 4 See Table 8 12 for a complete description of the register contents m BN ECRECRKCRECRECREERECREECRECREECRECRRSECR wm OM WERE eur o o lo o lo 1 lo 9 19 9 19 1 1 31 Registers MIN GNT and MAX LAT Type Read Update Offset 3Eh Default 0403h Table 8 12 MIN GNT and MAX LAT Registers SIGNAL FUNCTION Maximum latency The contents of this register may be used by host BIOS to assign an arbitration priority level to the PCI4410 The default for this register indicates that the PCI4410 may need to access the PCI bus as often as every 1 4 us thus an extremely high priority level is requested The contents of this field may also be loaded through the serial ROM MAX LAT Minimum grant The contents of this register may be used by host BIOS to assign a latency timer register MIN GNT value to the PCI4410 The default for this register indicates that the PCI4410 may need to sustain burst transfers for nearly 64 us thus requesting a large value be programmed in the PCI4410 latency timer register 8 9 8 15 PCI OHCI Control Register The PCI OHCI control register contains IEEE1394 Open HCI specific control bits All bits in this register are read only and return Os because no OHCI specific control bits have been implemented ENE HAAK OS
128. dBus cycle as the target device CDEVSEL 155 E17 VO Asa CardBus initiator on the bus the PCI4410 monitors CDEVSEL until a target responds If no target responds before timeout occurs then the PCI4410 terminates the cycle with an initiator abort CardBus cycle frame CFRAME is driven by the initiator of a CardBus bus cycle CFRAME is asserted CFRAME 159 E14 VO to indicate that a bus transaction is beginning and data transfers continue while this signal is asserted When CFRAME is deasserted the CardBus bus transaction is in the final data phase CONT 154 F15 CardBus bus grant CGNT is driven by the PCI4410 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed TNT P e interrupt CINT is asserted low by a CardBus PC Card to request interrupt servicing from the CardBus initiator ready CIRDY indicates the CardBus initiator s ability to complete the current data CIRDY VO phase of the transaction A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted Until CIRDY and CTRDY are both sampled asserted wait states are inserted Cal Di ES 4 io parity error CPERR reports parity errors during CardBus transactions except during special IE It is driven low by a target two clocks following that data when a parity error is detected CREG CardBus request CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator CardBus sy
129. ddress for VO windows 0 and 1 The 8 bits of these registers correspond to the lower 8 bits of the offset address and bit 0 is always 0 Be 7 6 5 4 3 2 1 0 Name ExCA VO windows 0 and 1 offset address low Register EXCA VO window 0 offset address low byte Offset CardBus socket address 836h ExCA offset 36h Register ExCA VO window 1 offset address low byte Offset CardBus socket address 838h ExCA offset 38h Type Read only Read Write Default 00h Size One byte 5 20 ExCA VO Windows 0 and 1 Offset Address High Byte Registers These registers contain the high byte of the 16 bit VO window offset address for VO windows 0 and 1 The 8 bits of these registers correspond to the upper 8 bits of the offset address Be 7 6 s 4 j 3 2 1 0 Name EXCA VO windows 0 and 1 offset address high byte Hye RW RW RW RW RW RW RW RW petan 0 o o o o o o o Register ExCA VO window 0 offset address high byte Offset CardBus socket address 837h ExCA offset 37h Register ExCA VO window 1 offset address high byte Offset CardBus socket address 839h ExCA offset 39h Type Read Write Default 00h Size One byte 5 21 ExCA VO Card Detect and General Control Register The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card removal as well as reports the status of VS1 and VS2 at the PC Card interface Se
130. dor ID This field indicates the subsystem vendor ID 8 23 GPIO Control Register The GPIO control register has the control and status bits for GPIOO GPIO1 GPIO2 and GPIO3 ports Upon reset GPIOO and GPIO1 default to bus manager contender BMC and link power status terminals respectively The BMC terminal can be configured as GPIOO by setting bit 7 DISABLE BMC to 1 The LPS terminal can be configured as GPIO1 by setting bit 15 DISABLE LPS to 1 See Table 8 20 for a complete description of the register contents Bit 31 so 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 GPIO control o 0 y GPlOcm we R R Rw nw R R Ra Rw R R Rw Aw rR R R aw GPIO control AL ME EE MA C MISI CURE Pi lolol REISER ER o po Register GPIO control Type Read only Read Write Offset FCh Default 0000 1010h Table 8 20 GPIO Control Register SIGNAL TYPE FUNCTION 31 30 RSVD R Reserved These bits return Os when read GPIO3 polarity invert This bit controls the input output polarity control of GPIO3 29 GPIO INV3 R W 0 Noninverted default 1 Inverted GPIOS enable control This bit controls the output enable for GPIOS 28 GPIO ENB3 R W 0 High impedance output default 1 Output enabled 27 25 RSVD R Reserved These bits return Os when read GPIOS data When GPIO3 output is enabled the value written to this bit represents the logical data GPIO DATAS dd driven to the GPIOS ter
131. e Interrupt flag clear mode select Bit 2 selects the interrupt flag clear mechanism for the flags in the EXCA card status change register see Section 5 5 This bit is encoded as 2 IFOMBDE SP O Interrupt flags are cleared by read of CSC register default 1 Interrupt flags are cleared by explicit writeback of 1 Card status change level edge mode select Bit 1 selects the signaling mode for the PCI4410 host interrupt for card status changes This bit is encoded as i CSCMODE iiid O Host interrupt is edge mode default 1 Host interrupt is level mode Power down mode select When bit O is setto 1 the PCI4410 is in power down mode In power down mode the PCI4410 card outputs are high impedance until an active cycle is executed on the card interface Following an active cycle the outputs are again high impedance The PC14410 still receives DMA requests PWRDWN functional interrupts and or card status change interrupts however an actual card access is required to wake up the interface This bit is encoded as O Power down mode is disabled default 1 Power down mode is enabled 5 23 ExCA Memory Windows 0 4 Page Register The upper 8 bits of a 4 byte PCI memory address are compared to the contents of this register when addresses for 16 bit memory windows are decoded Each window has its own page register all of which default to 00h By programming this register to a nonzero value host software can locate 16 bit memory windows i
132. e Table 5 14 for a complete description of the register contents ET qo ow 0E ow ps lotto Name ExCA VO card detect and general control me a A AW aw a A mpa a x x 0 to o o to 1 9 Register ExCA card detect and general control Type Read only Read Write Offset CardBus socket address 816h ExCA offset 16h Default XX00 0000b Table 5 14 ExCA VO Card Detect and General Control Register SIGNAL TYPE FUNCTION VS2 state Bit 7 reports the current state of VS2 at the PC Card interface and therefore does not have a default value 7 VS2STAT 0 VS low 1 VS2 high VS1 state Bit 6 reports the current state of VS1 at the PC Card interface and therefore does not have a default value VS1STAT 0 VST low 1 NEI high Software card detect interrupt If bit 3 CDEN in the ExCA card status change interrupt configuration register is set see Section 5 6 then writing a 1 to bit 5 causes a card detect card status change interrupt 5 SWCSC R W for the associated card socket If bit 3 CDEN in the ExCA card status change interrupt configuration register is cleared to 0 see Section 5 6 then writing a 1 to bit 5 has no effect A read operation of this bit always returns 0 Card detect resume enable If bit 4 is set to 1 then once a card detect change has been detected on CD1 and CD2 inputs RI OUT goes from high to low RI OUT remains low until bit O card status change in 4 CDRESUME RW the ExCA card status ch
133. e enabled through the GPIO Control Register gt ZVSTAT 19 Video Signals 4 Audio Signals Figure 3 5 Zoomed Video Subsystem 3 5 3 5 4 Ultra Zoomed Video Ultra zoomed video is an enhancement to the PCI4410 DMA engine and is intended to improve the 16 bit bandwidth for MPEG and MPEG II decoder PC Cards This enhancement allows the PCI4410 to fetch 32 bits of data from memory versus the 11XX 12XX 16 bit fetch capability This enhancement allows a higher sustained throughput to the 16 bit PC Card because the PCI4410 prefetches an extra 16 bits 32 bits total during each PCI read transaction If the PCI bus becomes busy then the PCI4410 has an extra 16 bits of data to perform back to back 16 bit transactions to the PC Card before having to fetch more data This feature is built into the DMA engine and software is not required to enable this enhancement NOTE The 11XX and 12XX series CardBus controllers have enough 16 bit bandwidth to support MPEG II PC Card decoders But it was decided to improve the bandwidth even more in the 14XX series CardBus controllers 3 5 5 D3 STAT Terminal Additional functionality for the PCI4410 versus the 12xx series is the D3 STAT D3 status pin This pin is asserted under the following two conditions both conditions must be true before D3 STAT is asserted e Function O PC Card controller and function 1 OHCI Lynx are both in Da e PME is enabled for either function 3 5 6 Internal
134. e socket event register to be written see Section 6 1 and bit 1 CDETECT 1 in the socket present state register is unaffected see Section 6 3 Force CSTSCHG Write transactions to bit 0 cause bit 0 CSTSEVENT in the socket event register to be FCARDSTS written see Section 6 1 and bit O CARDSTS in the socket present state register is unaffected see Section 6 3 6 6 Fissircano 6 5 Socket Control Register The socket control register provides control of the voltages applied to the socket and instructions for CB CLKRUN protocol The PCI4410 ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted See Table 6 6 for a complete description of the register contents Bit 21 30 29 28 27 26 25 2a 23 z2 21 20 t9 18 17 16 Socket control Register Socket control Type Read only Read Write Offset CardBus socket address 10h Default 0000 0000h Table 6 6 Socket Control Register SIGNAL TYPE FUNCTION RSVD R Reserved Bits 31 8 return Os when read CB CLKRUN protocol instructions 7 STOPCLK RW 0 CB CLKRUN protocol can only attempt to stop slow the CB clock if the socket is idle and the PCI CLKRUN protocol is preparing to stop slow the PCI bus clock 1 CB CLKRUN protocol can attempt to stop slow the CB clock if the socket is idle Vcc control Bits 6 4 request card Voc changes 000 Request power off default 100 Request Voc
135. e subsystem identification and other register defaults from a serial EEPROM The registers and corresponding bits that may be loaded with defaults through the EEPROM are provided in Table 3 6 3 13 Table 3 6 Registers and Bits Loadable Through Serial EEPROM OHCI REGISTERS LOADED OFFSET REFERENCE REGISTER REGISTER NAME BITS LOADED FROM EEPROM 0 38 MIN GNT and MAX LAT see Section 8 14 3Fh MIN GNT and aa see Section 8 14 ese sms siese fe ian identification E Section 8 s Poiacn Subsystem identication see Section 11 eves 5 Poiran Link enhancement control see Secion821 nt Ri Ep uas JJ o s PO cub righ ee Sections eo Ea Ce mo TO Link enhancement control see Section 8 21 pU EU CARDBUS REGISTERS LOADED OFFSET REFERENCE REGISTER REGISTER NAME BITS LOADED FROM EEPROM aaa o ros ienes E 5 PO System contol seo Section 4207 eo o 6 Porson System convo see Section 429 even msre s Porson General contol see Secinast Bea te O 9 Porson Multifunction outing see Section 42 Beo Multifunction e E Section 4 E Card control see Section on Figure 3 14 details the EEPROM data format This format must be followed for the PCI4410 to properly load initializations from a serial EEPROM Slave Address 1010 000 Reference 0 Word Address 00h Byte 3 0 Word Addres
136. ead Set Clear Read only Offset A8h set register ACh clear register Default 0000 000Xh 9 27 Fairness Control Register Optional Register This register provides a mechanism by which software can directthe host controller to transmit multiple asynchronous requests during a fairness interval See Table 9 19 for a complete description of the register contents Fairness control Register Fairness control Type Read only Offset DCh Default XXXX XX00h Table 9 19 Fairness Control Register BIT SIGNAL TYPE FUNCTION RSVD Reserved This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY during fairness interval PRI REQ 9 28 Link Control Register This set clear register provides the control flags that enable and configure the link core protocol portions of the PCI4410 It contains controls for the receiver and cycle timer See Table 9 20 for a complete description of the register contents et 31 20 29 28 27 26 25 2a 23 22 t 20 19 18 i7 16 Link control Do imo aa EE EE EEN a EE a Link control EECH Type r R R R R jRc msc n R AR n n R aR R RA pem o o o fo fo Tx Tx To To To Jo o To o To Register Link control Type Read Set Clear Update Read Set Clear Read only Offset EOh set register E4h clear register Default 00X0 0X00h Tab
137. eceived by the PCI4410 from that node are accepted If set to 1 for local bus node number 32 asynchronous requests received by the PCI4410 from that node are accepted 9 33 Asynchronous Request Filter Low Register This set clear register is used to enable asynchronous receive requests on a per node basis and handles the lower node IDs Other than filtering different node IDs this register behaves identically to the asynchronous request filter high register See Table 9 25 for a complete description of the register contents cl co mr ee e LRL Asynchronous request filter low reme RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 De Des pe ba bebe be pe pets pe ps pe pe Asynchronous request filter low eo 9 o AK TESE AK BU AK AE N Register Asynchronous request filter low Type Read Set Clear Offset 108h setregister 10Ch clear register Default 0000 0000h Table 9 25 Asynchronous Request Filter Low Register If set to 1 for local bus node number 31 asynchronous requests received by the PCI4410 ASYNREQRESOURCE31 from that node are accepted If set to 1 for local bus node number 30 asynchronous requests received by the PCI4410 ASYNREGRESOURCESO from that node are accepted Bits 29 through 2 follow the same pattern If setto 1 for local bus node number 1 asynchronous requests received by the PCI4410 from ASYNREQRESOURCE that node are accepted If set
138. ecognition P2C power switch interface Zoomed video support Speaker and audio applications LED socket activity indicators PC Card 16 DMA support PC Card controller programming model CardBus socket registers 3 5 4 PC Card Insertion Removal and Recognition The 1997 PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold nonpowered socket Through this interrogation card voltage requirements and interface 16 bit versus CardBus are determined The scheme uses the card detect and voltage sense signals The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface The encoding scheme is defined in the 1997 PC Card Standard and in Table 3 1 3 3 Table 3 1 PC Card Card Detect and Voltage Sense Connections CD2 CCD2 CD1 CCD1 VS2 CVS2 VS1 CVS1 KEY INTERFACE VOLTAGE V Ground Connect to CCD1 CardBus PC Card Connect to CVS2 Ground CardBus PC Card LV CardBus PC Card LV LV V V Open CardBus PC Card Open L CardBus PC Card X X V and Y Y V Connect io VS Connect to CCDA CardBus PO Card BEE HE a 3 5 2 P2C Power Switch Interface TPS2211 The PCI4410 provides a P2C PCMCIA peripheral control interface for control of the PC Card power switch The VCCD and VPPD terminals are used with the TI TPS2211 single slot PC Card power interface switch to provide power switch
139. ed that is 5 V or 3 3 V This field is encoded as 1 0 EXCAVPP RW 00 No connection default 01 Voc 10 12V 11 Reserved Table 5 5 ExCA Power Control Register 82365SL DF Support SIGNAL TYPE FUNCTION Card output enable Bit 7 controls the state of all of the 16 bit outputs on the PCI4410 This bit is encoded as 7 COE R W 0 16 bit PC Card outputs disabled default 1 16 bit PC Card outputs enabled RSVD R Reserved Bits 6 and 5 return Os when read Vcc Bits 4 and 3 are used to request changes to card Vcc This field is encoded as 00 0 V default 4 3 EXCAVCC R W 01 2 0 V reserved 10 5V 1123V RSVD R Reserved Bit 2 returns O when read Vpp Bits 1 and 0 are used to request changes to card Vpp The PCI4410 ignores this field unless Vcc to the socket is enabled This field is encoded as 1 0 EXCAVPP RAW 00 No connection default 01 Voc 10 12V 11 Reserved 5 6 5 4 ExCA Interrupt and General Control Register The ExCA interrupt and general control register controls interrupt routing for I O interrupts as well as other critical 16 bit PC Card functions See Table 5 6 for a complete description of the register contents pg 7 6 s 4 s 2 1 90 Name ExCA interrupt and general control Register ExCA interrupt and general control Type Read Write Offset CardBus socket address 803h ExCA offset 03h Default 00h Table 5 6 ExCA Interrupt and General Control Register SIG
140. efault 0000 0000h Table 6 2 Socket Event Register SIGNAL TYPE FUNCTION RSVD Reserved Bits 31 4 return Os when read 3 PWREVENT Power cycle Bit 3 is set when the PCI4410 detects that bit 3 PWRCYCLE in the socket present state register see Section 6 3 has changed state This bit is cleared by writing a 1 1 EN 2 CD2EVENT RIC CCD2 Bit 2 is set when the PCI4410 detects that bit 2 CDETECT2 in the socket present state register see Section 6 3 has changed state This bit is cleared by writing a 1 EX C CCD1 Bit 1 is set when the PCI4410 detects that bit 1 CDETECT1 in the socket present state register see Section 6 3 has changed state This bit is cleared by writing a 1 CD1EVENT CSTSCHG Bit 0 is set when bit 0 CARDSTS in the socket present state register see Section 6 3 has CSTSEVENT R changed state For CardBus cards bit 0 is set on the rising edge of CSTSCHG For 16 bit PC Cards bit 0 is set on both transitions of CSTSCHG This bit is reset by writing a 1 6 2 6 2 Socket Mask Register The socket mask register allows software to control the CardBus card events that generate a status change interrupt The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register see Section 6 1 See Table 6 3 for a complete description of the register contents Bit 21 30 29 28 27 26 25 2a 23 z2 21 20 19 18 17 16 Socket mask Regi
141. el PCI parallel ISA and serialized PCI and ISA signaling Miscellaneous system interface terminals include multifunction terminals SUSPEND RI OUT PME power management control signal and SPKROUT 1394 Ports OHCI PHY Interface PCI Bus PCI4410 PC Card TPS2211 Power Switch Controller PC Card Interface Figure 3 1 PCI4410 System Block Diagram 3 1 Power Supply Sequencing The PCI4410 contains 3 3 V VO buffers with 5 V tolerance requiring a core power supply and clamp voltages The core power supply is always 3 3 V The clamp voltages can be either 3 3 V or 5 V depending on the interface The following power up and power down sequences are recommended The power up sequence is 1 Apply 3 3 V power to the core 2 Assert GRST to the device to disable the outputs during power up Output drivers must be powered up in the high impedance state to prevent high current levels through the clamp diodes to the 5 V supply 3 Apply the clamp voltage The power down sequence is 1 Use GRST to switch outputs to a high impedance state 2 Remove the clamp voltage 3 Remove the 3 3 V power from the core 3 2 VO Characteristics Figure 3 2 shows a 3 state bidirectional buffer Section 10 2 Recommended Operating Conditions provides the electrical characteristics of the inputs and outputs NOTE The PCI4410 meets the ac specifications of the 1997 PC Card Standard and the PCI Local Bus Specification T
142. en to the GPIO1 terminal Disable bus manager contender BMC This bit configures this terminals as bus master contender or GPIOO 0 BMC default 1 GPIOO Reserved This bit returns 0 when read GPIOO polarity invert When bit 7 DISABLE BMC is set to 1 this bit controls the input output polarity control of for GPIOO O Non inverted default 1 Inverted GPIOO enable control When DISABLE BMC bitis setto 1 this bit controls the output enable for GPIOO O High impedance output 1 Output enabled default Reserved These bits return Os when read GPIOO data When the DISABLE BMC bitis setto 1 and GPIOO output is enabled the value written to this bit represents the logical data driven to the GPIOO terminal 9 Open HCI Registers The open HCI registers defined by the EEE1394 Open HCI Specification are memory mapped into a 2 Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space These registers are the primary interface for controlling the PCI4410 IEEE1394 link function This section provides the register interface and bit descriptions There are several set and clear register pairs in this programming model which are implemented to solve various issues with typical read modify write control registers There are two addresses for a set clear register RegisterSet and RegisterClear See Table 9 1 for a register listing A 1 written to RegisterSet causes the corres
143. enabled 3 0 INTSELECT 0100 IRQ6 enabled 0111 IRQ7 enabled 1000 IRQ8 enabled 1001 IRQ9 enabled 1010 IRQ10 enabled 1011 IRQ11 enabled 1100 IRQ12 enabled 1101 IRQ13 enabled 1110 IRQ14 enabled 1111 IRQ15 enabled 5 7 5 5 ExCA Card Status Change Register The ExCA card status change register controls interrupt routing for I O interrupts as well as other critical 16 bit PC Card functions The register enables these interrupt sources to generate an interrupt to the host When the interrupt source is disabled the corresponding bit in this register always reads 0 When an interrupt source is enabled the corresponding bit in this register is set to indicate that the interrupt source is active After generating the interrupt to the host the interrupt service routine must read this register to determine the source of the interrupt The interrupt service routine is responsible for resetting the bits in this register as well Resetting a bit is accomplished by one of two methods a read of this register or an explicit writeback of 1 to the status bit The choice of these two methods is based on bit 2 interrupt flag clear mode select in the ExCA global control register see Section 5 22 See Table 5 7 for a complete description of the register contents jee v j e s 4 s j 2 j 1 9 Name ExCA card status change Eee 1 Jm n p m OE DE E RO pea o o o o o oo o o Register EXCA card status
144. enerate fast back to back transactions therefore bit 9 returns O when read System error SERR enable Bit 8 controls the enable for the SERR driver on the PCI interface SERR can be asserted after detecting an address parity error on the PCI bus Both bits 8 and 6 must be set for the SERR EN R W PCIA4410 to report address parity errors 0 Disable SERR output driver default 1 Enable SERR output driver 7 STEP EN Address data stepping control The PCI4410 does not support address data stepping therefore bit 7 is hardwired to 0 Parity error response enable Bit 6 controls the PCI4410 s response to parity errors through PERR Data parity errors are indicated by asserting PERR whereas address parity errors are indicated by asserting PERR EN R W SERR O PCI4410 ignores detected parity error default 1 PCI4410 responds to detected parity errors VGA palette snoop When bit 5 is set to 1 palette snooping is enabled that is the PCI4410 does not respond 5 VGA EN HA to palette register writes and snoops the data When bit 5 is O the PCI4410 treats all palette accesses like all other accesses Memory write and invalidate enable Bit 4 controls whether a PCI initiator device can generate memory 4 MWI EN write and Invalidate commands The PCI4410 controller does not support memory write and invalidate commands It uses memory write commands instead therefore this bit is hardwired to 0 3 SPECIAL Special cycles Bit 3 controls whethe
145. ent Type Read Set Clear Update Offset 80h set register 84h clear register returns IntEvent and IntMask when read Default XXXX OXXXh Table 9 15 Interrupt Event Register BIT SIGNAL TYPE FUNCTION Co RSVD R Reserved Bit 31 returns 0 when read 30 VENDORSPECIFIC R 29 27 RSVD R 6 PHYREGRCVD RSCU CYCLETOOLONG Vendor defined Reserved Bits 29 27 return Os when read The PCI4410 has received a PHY register data byte which can be read from the PHY control register n2 If LinkControl cycleMaster is setto 1 this indicates that over 125 us elapsed between the start of sending a cycle start packet and the end of a subaction gap LinkControl cycleMaster is cleared by this event n2 q This event occurs when the PCIA410 encounters any error that forces it to stop operations on any or all of its subunits for example when a DMA context sets its dead bit to 1 While UNRECOVERABLEERROR is set to 1 all normal interrupts for the context s that caused this interrupt are blocked from being set to 1 UNRECOVERABLEER ROR CYCLEINCONSISTENT RSCU A cycle start was received that had an isochronous cycleTimer seconds and isochronous 23 cycleTimer count different from the value in the CycleTimer register A lost cycle is indicated when no cycle_start packet is sent received between two successive cycleSynch events A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap a
146. ents 29 28 27 26 25 24 23 22 21 20 19 Isochronous receive interrupt event Isochronous receive interrupt event Name EE EE EE EE EE EE EE EE EE Po Jo Jo To ol oe 10 1e To Te Jo To T TT ee ree Isochronous receive interrupt event Type Read Set Clear Read only Offset AOh set register A4h clear register returns IsoRecvEvent and IsoRecvMask when read Default 0000 000Xh Table 9 18 Isochronous Receive Interrupt Event Register SIGNAL TYPE FUNCTION RSVD R Reserved These bits return Os when read ISORECV3 RSC Isochronous receive channel 3 caused the isochRx interrupt ISORECV2 RSC Isochronous receive channel 2 caused the isochRx interrupt ISORECV1 RSC Isochronous receive channel 1 caused the isochRx interrupt o ISORECVO RSC Isochronous receive channel O caused the isochRx interrupt 9 21 9 26 Isochronous Receive Interrupt Mask Register This set clear register is used to enable the isochRx interrupt source on a per channel basis Reads from either the set register or the clear register always return IsoRecvIntMask In all cases the enables for each interrupt event align with the event register bits detailed in Table 9 18 Isochronous receive interrupt mask Name lohonowsreoeweintemuptmask EE EE R Rsc Rsc Rsc Rsc po lo NE URE AE AE Jj ow olo e NE BESK ee S Register Isochronous receive interrupt mask Type R
147. erved Bits 14 12 return Os when read Power change status Bit 11 is set when software has changed the power state of the socket A change 11 PWR STS R C NE ik in either Vcc or Vpp for the socket causes this bit to be set RSVD R Reserved Bits 10 and 9 return Os when read VPP12 STS R C 12 V Vpp request status Bit 8 is set when software has changed the requested Vpp level to or from 12 V for the PC Card socket RSVD R Reserved Bits 7 5 return Os when read GP14 Status Bit 4 is set on a change in status of the MFUNC5 terminal input level This bit does not depend 4 GP4 STS R C is N upon the state of a corresponding bit in the general purpose event enable register GPI3 Status Bit 3 is set on a change in status of the MFUNCA terminal input level This bit does not depend 3 GP3 STS R C ne i upon the state of a corresponding bit in the general purpose event enable register GPI2 Status Bit 2 is set on a change in status of the MFUNC2 terminal input level This bit does not depend 2 GP2_STS R C baa upon the state of a corresponding bit in the general purpose event enable register GPI1 Status Bit 1 is set on a change in status of the MFUNC1 terminal input level This bit does not depend 1 GP1 STS R C Ges upon the state of a corresponding bit in the general purpose event enable register GPIO Status Bit O is set on a change in status of the MFUNCO terminal input level This bit does not depend GPO STS R C MS i upon the
148. etains state through PCI reset and D3 DO transitions PME SUPPORT D2 12 11 RSVD Reserved These bits return 0s when read D2 support This bit is used to program the corresponding read only value read from power management capabilities If the D2 power state implemented in PCIA410 is not desired then 10 D2 SUPPORT SI this bit may be reset to 0 to indicate to power management software that D2 is not supported This bit retains state through PCI reset and D3 DO transitions 9 5 RSVD Reserved Bits 9 5 return Os when read When bit 4 is set to 1 the OSCI function returns indeterminate data instead of signaling target 4 DISABLE PCI TARGET ABORT abort The default 0 allows the OSCI function to signal target abort 3 RSVD Reserved This bit defaults to 0 2 DISABLE SCLKGATE When this bit is set to 1 the internal SCLK runs identically with the chip input 1 DISABLE PCIGATE When this bit is set to 1 the internal PCI clock runs identically with the chip input When this bit is set to 1 the PCI clock is always kept running through the CLKRUN protocol KEER When reset to 0 the PCI clock may be stopped using CLKRUN 8 21 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM if present After these bits are set to 1 their functionality is enabled only if the APHYENHANCEENABLE bit bit 22 in the host controller control regi
149. ext If set to 1 for local bus node number 53 then physical requests received by the PC14410 from that node are handled through the physical request context If set to 1 for local bus node number 52 then physical requests received by the PCI4410 Fi EE AUG EE Fee from that node are handled through the physical request context If set to 1 for local bus node number 51 then physical requests received by the PCI4410 FHYSREGRESOBBOSSI RSC from that node are handled through the physical request context If set to 1 for local bus node number 50 then physical requests received by the PC14410 PAYSREQRESOURCESO RSG from that node are handled through the physical request context PHYSREQRESOURCE53 bel n Table 9 26 Physical Request Filter High Register Continued HEES IERE EE N NELLA Ee id NELLA Ee median EE AA EE 9 31 9 35 Physical Request Filter Low Register This set clear register is used to enable physical receive requests on a per node basis and handles the lower node IDs When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers then the node ID comparison is done again with this register If the bit corresponding to the node ID is not setto 1 in this register then the request is handled by the asynchronous request context instead of the physical request context See Table 9 27 for a complete description of the register contents
150. fect 8 Reserved Reserved Ww Bec The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed after the PC Card is inserted and interrogated These steps include setting the proper DREQ signal assignment setting the data transfer width and mapping and enabling the DDMA register set As discussed above this is done through socket DMA register 0 and socket DMA register 1 The DMA register set is then programmed similarly to an 8237 controller and the PCI4410 awaits a DREQ assertion from the PC Card requesting a DMA transfer DMA writes transfer data from the PC Card to PCI memory addresses The PCI4410 accepts data 8 or 16 bits at a time depending on the programmed data width and then requests access to the PCI bus by asserting its REQ signal Once the PCI bus is granted in an idle state the PCI4410 initiates a PCI memory write command to the current memory address and transfers the data in a single data phase After terminating the PCI cycle the PCI4410 accepts the next byte s from the PC Card until the transfer count expires DMA reads transfer data from PCI memory addresses to the PC Card application Upon the assertion of DREQ the PCI4410 asserts REQ to acquire the PCI bus Once the bus is granted in an idle state the PCI4410 initiates a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data depending on the programmed data w
151. fter the cycleSynch eventor if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start CYCLELOST may be set to 1 either when a lost cycle occurs or when logic predicts that it will occur N CYCLELOST 21 CYCLE64SECONDS RSCU 0 CYCLESYNCH RSCU Indicates that the 7th bit of the cycle second counter has changed Indicates that a new isochronous cycle has started and is set to 1 when the low order bit of the cycle count toggles Er N gt 15 10 8 BUSRESET RSCU SELFDCOMPLETE RSCU RSVD R Indicates the PHY requests an interrupt through a status transfer Reserved Bit 18 returns 0 when read Indicates that the PHY chip has entered bus reset mode A self ID packet stream has been received It is generated at the end of the bus initialization process This bit is turned off simultaneously when IntEvent busReset is turned on Reserved Bits 15 10 return Os when read Table 9 15 Interrupt Event Register Continued Isochronous receive DMA interrupt Indicates that one or more isochronous receive contexts have generated an interrupt This is not a latched event it is the OR ing of all bits in isoRecvIntEvent and isoRecvIntMask The isoRecvlntEvent register indicates which contexts have interrupted Isochronous transmit DMA interrupt Indicates that one or more isochronous transmit contexts have generated an interrupt This is not a latched event it is the OR in
152. g of all bits in isoXmitIntEvent and isoXmitintMask The isoXmitlntEvent register indicates which contexts have interrupted Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor s xferStatus and resCount fields have been updated Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor s xferStatus and resCount fields have been updated Asynchronous receive response DMA interrupt This bit is conditionally set to 1 upon completion of an ARRS DMA context command descriptor Asynchronous receive request DMA interrupt This bit is conditionally set to 1 upon completion of an ARRQ DMA context command descriptor Asynchronous response transmit DMA interrupt This bit is conditionally set to 1 upon completion of an ATRS DMA command Asynchronous request transmit DMA interrupt This bit is conditionally set to 1 upon completion of an ATRQ DMA command 9 22 Interrupt Mask Register This set clear register is used to enable the various PCI4410 interrupt sources Reads from either the set register or the clear register always return IntMask In all cases except masterlntEnable bit 31 the enables for each interrupt event align with the event register bits detailed in Table 9 15 See Table 9 16 for a complete description of the register contents et 31 3 20 28 27 26 25 24 23 22 21 20 19 18 17 16 Name dmemp
153. gement capabilities pointer Register PCI power management capabilities pointer Type Read only Offset 34h Default 44h 8 8 8 13 Interrupt Line and Interrupt Pin Registers The interrupt line and interrupt pin registers are used to communicate interrupt line routing information See Table 8 11 for a complete description of the register contents Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Interrupt line and interrupt pin we R R R R R R R R Rw Rw Rw aw rw RW aw rw peas o o fo fo fo fofts fofofofofofofofo fo Registers Interrupt line and interrupt pin Type Read only Read Write Offset 3Ch Default 0200h Table 8 11 Interrupt Line and Interrupt Pin Registers SIGNAL TYPE FUNCTION Interrupt pin register This register returns 01h or 02h when read indicating that the PC14410 link function 15 8 INTR_PIN signals interrupts on the INTA or INTB terminal respectively If TIE_INTB_INTA offset 80h bit 29 is setto 1 then INTR_PIN byte reads 0000 0001b which indicates the OHCI function is signaling on INTA Interrupt line register This register is programmed by the system and indicates to the software which DIERE interrupt line the PCI4410 INTA is connected to 8 14 MIN GNT and MAX LAT Registers These registers are used to communicate to the system the desired setting of the latency timer register If a serial ROM is detected then the contents of this register are loade
154. gement field Must be valid when HCControl linkEnable bit is set to 1 23 16 CRC LENGTH IEEE1394 bus management field Must be valid when HCControl linkEnable bit is set to 1 IEEE1394 bus management field Must be valid at any time the HCControl linkEnable bit is set to 1 15 0 ROM CRC VALUE RAW Theresetvalue is undefined if no serial ROM is present If a serial ROM is present then this field is loaded from the serial ROM 9 8 Bus ldentification Register This register externally maps to the first quadlet in the Bus Info Block and contains the constant 3133 3934h which is the ASCII value of 1394 Bus identification Name EE to EE NEK a Lilo AE RE AE ecpor por po EC Register Bus identification Type Read only Offset 1Ch Default 3133 3934h 9 9 Bus Options Register This register externally maps to the second quadlet of the Bus Info Block See Table 9 7 for a complete description of the register contents Bit 31 3o 29 28 27 26 25 2a 23 22 2t 20 19 18 17 16 Bus options Type RW RW Raw Rw Raw R R R RW RW RW RW R W RW RW FRI peau x x x x o o o fo x xX x x TOT TT us options Register Bus options Type Read only Read Write Offset 20h Default X0XX AOX2h Table 9 7 Bus Options Register BIT SIGNAL TYPE FUNCTION 1 IRMG Isochronous resource manager capable IEEE1394 bus management field Must be valid when HC
155. gh eight multifunction terminals These terminals present a system with options in PC PCI DMA PCI LOCK and parallel interrupts PC Card activity indicator LEDs and other platform specific signals ACPI compliant general purpose events may be programmed and controlled through the multifunction terminals and an ACPI compliant programming interface is included for the general purpose inputs and outputs The PCI4410 is compliant with the latest PC Bus Power Management Specification and provides several low power modes which enable the host power system to further reduce power consumption The PC Card CardBus Controller and EEE 1394 Host Controller Device Class Specifications required for Microsoft OnNow power management are supported Furthermore an advanced complementary metal oxide semiconductor CMOS process achieves low system power consumption Unused PC14410 inputs must be pulled to a valid logic level using a 43 kQ resistor 1 2 Features The PCI4410 supports the following features e Ability to wake from D3hot and D3cold e Fully compatible with the Intel 430TX Mobile Triton II chipset e A208 pin low profile QFP PDV or 209 ball MICROSTAR BGA ball grid array GHK package Intel is a trademark of Intel Corporation Microsoft OnNow is a trademark of Microsoft Corporation MicroStar BGA is a trademark of Texas Instruments Incorporated 3 3 V core logic with universal PCI interfaces compatible with 3 3 V and 5 V PCI signaling e
156. h bits 29 28 24 21 20 16 15 13 12 8 7 5 4 0 Global unique ID low high OHCI function PCI offset 24h 28h bits 31 0 ExCA identification and revision register ExCA offset 00h bits 7 0 ExCA card status change register ExCA offset 804h bits 3 0 ExCA global control register ExCA offset 1Eh bits 3 0 4 PC Card Controller Programming Model This section describes the PCI4410 PCI configuration registers that make up the 256 byte PCI configuration header for each PCI4410 function As noted some bits are global in nature and are accessed only through function 0 4 1 PCI Configuration Registers Functions 0 and 1 The PCI4410 is a multifunction PCI device and the PC Card controller is integrated as PCI functions O and 1 The configuration header is compliant with the PC Local Bus Specification as a CardBus bridge header and is PC 99 compliant as well Table 4 1 shows the PCI configuration header which includes both the predefined portion of the configuration space and the user definable registers Table 4 1 PCI Configuration Registers Functions 0 and 1 Power management Power management data control status register Power management control status A4h bridge support extensions General purpose event enable General purpose event status General purpose output General purpose input BOh FCh 4 1 4 2 Vendor ID Register This 16 bit register contains a value allocated by the PCI SIG special interest gro
157. h PCI and CB CLKRUN protocols 1 KEEPCLK R W O Allows normal functioning of both CLKRUN protocols default B d 1 Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols RI OUT PME multiplex enable 0 RI_OUT and PME are both routed to the RI_OUT PME terminal If both are enabled at the same time then RI OUT has precedence over PME 1 Only PME is routed to the RI OUT PME terminal 4 30 General Status Register The general status register provides the general device status information The status ofthe serial EEPROM interface is provided through this register See Table 4 7 for a complete description of the register contents Register General status Type Read UpdateRead only Read Clear Offset 85h Function 0 Default 00h Table 4 7 General Status Register SIGNAL TYPE FUNCTION RSVD R Reserved Bits 7 3 return 0s when read Serial EEPROM detect Serial EEPROM is detected by sampling a logic high on SCL while PRST is low When this bit is set the serial ROM is detected This status bit is encoded as 2 SCHERER 0 EEPROM not detected default 1 EEPROM detected Serial EEPROM data error status This bit indicates when a data error occurs on the serial EEPROM 1 DATAERR RIC interface This bit may be set due to a missing acknowledge This bit is cleared by a writeback of 1 0 No error detected default 1 Data error detected Serial EEPROM busy status This bit indicates the st
158. he card socket Reserved Bits 7 5 return Os when read GPI4 enable When bit 4 is set a GPE is signaled when there has been a change in status of the MFUNC5 terminal input level if configured as GPIA GPI3 enable When bit 3 is set a GPE is signaled when there has been a change in status of the MFUNC4 terminal input level if configured as GPIS GPI2 enable When bit 2 is set a GPE is signaled when there has been a change in status of the MFUNC2 terminal input if configured as GPI2 GPI1 enable When bit 1 is set a GPE is signaled when there has been a change in status of the MFUNC1 terminal input if configured as GPI1 GPIO enable When bit 0 is set a GPE is signaled when there has been a change in status of the MFUNCO terminal input if configured as GPIO 4 32 4 47 General Purpose Input Register The general purpose input register provides the logical value of the data input from the GPI terminals MFUNCS MFUNCA and MFUNC2 MFUNCO See Table 4 21 for a complete description of the register contents Bit 1 ta vs m2 m 10 9 8 v je js ja la 2 y o0 General purpose input Tee R R R R R R RR RIA RR RR RR peas o o o jo o o o o o oJjo x x x xl x Register General purpose input Type Read only Offset ACh Default 00XXh Table 4 21 General Purpose Input Register SIGNAL TYPE FUNCTION RSVD R Reserved Bits 15 5 return Os when read GPI4 DATA EX GPI4 data
159. he host system Bits in this register may be read normally A bit in the status register is reset when a 1 is written to that bit location a 0 written to a bit location has no effect All bit functions adhere to the definitions in the PCI Local Bus Specification PCI bus status is shown through each function See Table 8 4 for a complete description of the register contents Bit 15 14 13 m2 m t0 9 8 7 e ts a j 3 2 j 1 0 PCI status Type RcU RCU RCU Rey RCU A R Ru R A AR R JR R J A Ry emu 9 oo o o 9 o o 9o 9 3 o o o po Register PCI status Type Read only Read Clear Update Offset 06h Default 0210h Table 8 4 PCI Status Register BIT SIGNAL TYPE FUNCTION 15 PAR ERR RCU Detected parity error This bitis set to 1 when a parity erroris detected either address or data parity errors Signaled system error This bitis setto 1 when SERR is enabled and the PCI4410 signaled a system error SYS_ERA to the host Received master abort This bitis setto 1 when a cycle initiated by the PC14410 on the PCI bus has been MABORT terminated by a master abort Received target abort This bit is set to 1 when a cycle initiated by the PCI4410 on the PCI bus is TABORI BER terminated by a target abort Signaled target abort This bitis setto 1 by the PCI4410 when it terminates a transaction on the PCI bus TABORI SIG with a target abort DEVSEL tim
160. high byte register 0 WP is 0 PC Card is read write 1 WP is 1 PC Card is read only Card detect 1 Bit 2 indicates the status of CD1 at the PC Card interface Software may use this and bit 3 CDETECT2 to determine if a PC Card is fully seated in the socket 0 CD1 is 1 No PC Card is inserted 1 CD1 is 0 PC Card is at least partially inserted Battery voltage detect When a 16 bit memory card is inserted the field indicates the status of the battery voltage detect signals BVD1 BVD2 at the PC Card interface where bit 1 reflects the BVD2 status and bit 0 reflects BVD1 00 Battery dead 01 Battery dead 10 Battery low warning 11 Battery good When a 16 bit I O card is inserted this field indicates the status of SPKR bit 1 and STSCHG bit 0 at the PC Card interface In this case the two bits in this field directly reflect the current state of these card outputs CDETECT1 BVDSTAT D E Card detect 2 Bit 3 indicates the status of CD2 at the PC Card interface Software may use this and bit 2 CDETECT1 to determine if a PC Card is fully seated in the socket 2 GBETEGTS 0 CD2 is 1 No PC Card is inserted 1 CD2 is 0 PC Card is at least partially inserted D 5 5 5 3 ExCA Power Control Register The ExCA power control register provides PC Card power control Bit 7 COE ofthis register controls the 16 bit output enables on the socket interface and can be used for power management in 16 bit P
161. ial EEPROM until an end of list indicator is read Three reserved bytes are stuffed to maintain eight byte data structures Note the eight byte data structure is important to provide correct addressing per the doubleword read format shown in Figure 3 13 In addition the reference offsets must be loaded in the EEPROM in sequential order that is 01h 02h O3h 04h If the offsets are not sequential then the registers may be loaded incorrectly 3 6 4 Accessing Serial Bus Devices Through Software The PCI4410 provides a programming mechanism to control serial bus devices through software The programming is accomplished through a doubleword of PCI configuration space at offset BOh 3 7 Programmable Interrupt Subsystem Interrupts provide a way for VO devices to let the microprocessor know that they require servicing The dynamic nature of PC Cards and the abundance of PC Card VO applications require substantial interrupt support from the PCI4410 The PCI4410 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards The ExCA register set provides interrupt control for some 16 bit PC Card functions and the CardBus socket register set provides interrupt control for the CardBus PC Card functions The PCI4410 is therefore backward compatible with existing interrupt control register defini
162. idth After terminating the PCI cycle the data is passed onto the PC Card After terminating the PC Card cycle the PCI4410 requests access to the PCI bus again until the transfer count has expired The PC14410 target interface acts normally during this procedure and accepts VO reads and writes to the DDMA registers While a DDMA transfer is in progress and the host resets the DMA channel the PCI4410 asserts TC and ends the PC Card cycle s TC is indicated in the DDMA status register see Section 7 5 At the PC Card interface the PCI4410 supports demand mode transfers The PCI4410 asserts DACK during the transfer unless DREQ is deasserted before TC TC is mapped to the OE PC Card terminal for DMA write operations and is mapped to the WE PC Card terminal for DMA read operations The DACK signal is mapped to the PC Card REG signal in all transfers and the DREQ terminal is routed to one of three options which is programmed through socket DMA register 0 3 9 3 5 11 PC Card 16 PC PCI DMA Some chip sets provide a way for legacy VO devices to do DMA transfers on the PCI bus In the PC PCI DMA protocol the PCI4410 acts as a PCI target device to certain DMA related VO addresses The PCI4410 PCREQ and PCGNT signals are provided as a point to point connection to a chipset supporting PC PCI DMA The PCREQ and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals respectively See Section 4 32 Multifunction Routing Register for details on co
163. ied for Open Drain VCCP OE d Figure 3 2 3 State Bidirectional Buffer NOTE Unused pins input or VO must be held high or low to prevent them from floating 3 3 Clamping Voltages The clamping voltages are set to match whatever external environment the PCI4410 is interfaced with 3 3 V or 5 V The I O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals The core power supply is always 3 3 V and is independent of the clamping voltages For example PCI signaling can be either 3 3 V or 5 V and the PCI4410 must reliably accommodate both voltage levels This is accomplished by using a 3 3 V VO buffer that is 5 V tolerant with the applicable clamping voltage applied If a system designer desires a 5 V PCI bus then Vccp can be connected to a 5 V power supply The PC14410 requires four separate clamping voltages because it supports a wide range of features The four voltages are listed and defined in Section 10 2 Recommended Operating Conditions 3 4 Peripheral Component Interconnect PCI Interface The PC14410 is fully compliant with the PCI Local Bus Specification The PCI4410 provides all required signals for PCI master or slave operation and may operate in either a 5 V or 3 3 V signaling environment by connecting the Vccp terminals to the desired voltage level In addition to the mandatory PCI signals the PCI4410 provides the optional interrupt signal INTA 3 4 4
164. ignaling are the ExCA interrupt and general control register see Section 5 4 and the ExCA card status change interrupt configuration register see Section 5 6 Access to VO mapped 16 bit PC Cards is available to the host system via two ExCA VO windows These are regions of host VO address space into which the card VO space is mapped These windows are defined by start end and offset addresses programmed in the ExCA registers described in this section VO windows have byte granularity Access to memory mapped 16 bit PC Cards is available to the host system via five EXCA memory windows These are regions of host memory space into which the card memory space is mapped These windows are defined by start end and offset addresses programmed in the ExCA registers described in this section Table 5 1 identifies each ExCA register and its respective ExCA offset Memory windows have 4 Kbyte granularity Table 5 1 ExCA Registers and Offsets CARDBUS SOCKET ExCA REGISTER NAME ADDRESS OFFSET Ed HEX HEX EECH EE REECH HEES HEES HEES HEES 5 2 Table 5 1 EXCA Registers and Offsets Continued CARDBUS SOCKET ExCA REGISTER NAME ADDRESS OFFSET din P uad HEX en Memory window 2 start address low byte 820 20 Reserved 826 Reserved 827 Memory window 3 start address low byte 828 Reserved 82bE Reserved 82F Memory window 4 start address low byte Reserved Reserved Reserved Reserved Reserved Reserved Memory window page 0
165. incremented 7 6 G R W h since the prior bus reset 0 R MAX REC RSVD Reserved Bits 5 3 return Os when read Link speed This field returns 010 indicating that the link speeds of 100 200 and 400 Mbits s are 2 LNK SPD supported 9 10 GUID High Register This register represents the upper quadlet in a 64 bit global unique ID GUID which maps to the third quadlet in the Bus Info Block This register contains node vendor ID and chip ID hi fields This register initializes to Os on a hardware reset which is an illegal GUID value If a serial ROM is detected then the contents of this register are loaded through the serial ROM interface after a PCI reset At that point the contents of this register cannot be changed If no serial ROM is detected then this register may be written once to set the value of this register At that point the contents of this register cannot be changed Fs s ze els lerlslslsIlsIsIsIsIs wm ob ed ne T8T8T8T8 T5 T5 RA LALA Ap ALALA peram o o o o o po fo po fo 9 1 9 oo o gm w w w w w we lslsiz1isislislslsisle Name GUID high EE E ESE E Po to e 19 9 19 9 19 19 1919 15 Register GUID high Type Read only Offset 24h Default 0000 0000h 9 11 GUID Low Register This register represents the lower quadlet in a 64 bit global unique ID GUID which maps to chip ID lo in the Bus Info Block This register initializes to Os on a hardware reset an
166. ing These bits encode the timing of DEVSEL and are hardwired 01b indicating that the SSES PC14410 asserts this signal at a medium speed on non configuration cycle accesses Data parity error detected This bit is set to 1 when the following conditions have been met a PERR was asserted by any PCI device including the PCI4410 b The PC14410 was the bus master during the data parity error c The parity error response bit is set to 1 in the command register Fast back to back capable The PCI4410 cannot accept fast back to back transactions thus this bit is FBB CAP R hardwired to O B R UDF supported The PCI4410 does not support the user definable features thus this bit is hardwired to 0 66 MHz capable The PCI4410 operates at a maximum PCLK frequency of 33 MHz therefore this bit is 66MHZ R k hardwired to 0 5 4 CAPLIST R Capabilities list This bit returns 1 when read and indicates that capabilities additional to standard PCI are implemented The linked list of PCI power management capabilities is implemented in this function DATAPAR RCU T o D RSVD Reserved These bits return Os when read L 8 8 6 Class Code and Revision ID Register This read only register categorizes the PCI4410 as a serial bus controller OCh controlling an IEEE1394 bus 00h with an OHCI programming model 10h Furthermore the TI chip revision is indicated in the lower byte See Table 8 5 for a complete description of
167. is As in distributed DMA the PC Card terminal mapped to DREQ must be configured through socket DMA register O see Section 4 37 The data transfer width is a function of channel number and the DDMA slave registers are not used When a DREQ is received from a PC Card and the channel has been granted the PCI4410 decodes the VO addresses listed in Table 3 4 and performs actions dependent upon the address Table 3 4 VO Addresses Used for PC PCI DMA DMA VO ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE When the PC PCI DMA is used as a PC Card 16 DMA mechanism it may not provide the performance levels of DDMA however the design of a PCI target implementing PC PCI DMA is considerably less complex No bus master state machine is required to support PC PCI DMA because the DMA control is centralized in the chipset This DMA scheme is often referred to as centralized DMA for this reason 3 5 12 CardBus Socket Registers The PCI4410 contains all registers for compatibility with the PC Card Standard release 7 These registers exist as the CardBus socket registers and are listed in Table 3 5 Table 3 5 CardBus Socket Registers Reserved Reserved Socket power management 20h 3 6 Serial Bus Interface 20h The PCI4410 provides a serial bus interface to load subsystem identification and select register defaults through a serial EEPROM and to provide a PC Card power switch interface alternative to P2C See Section 3 5
168. is bit is encoded as 0 8 bit cycles have standard length default 1 8 bit cycles are reduced to equivalent of three ISA cycles ZEROWSO VO window 0 IOIS16 source Bit 1 controls the VO window 0 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I O data transfer This bit is encoded as O Window data width is determined by DATASIZEO bit O default 1 Window data width is determined by IOIS16 IOSIS16WO O Window data width is 8 bits default 1 Window data width is 16 bits VO window 0 data size Bit O controls the VO window 0 data size Bit O is ignored if bit 1 IOSIS16WO is DATASIZEO R set This bit is encoded as 5 9 ExCA VO Windows 0 and 1 Start Address Low Byte Registers These registers contain the low byte of the 16 bit I O window start address for VO windows 0 and 1 The 8 bits of these registers correspond to the lower 8 bits of the start address Be 7 6 s a 3 2 1 0 Name ExCA VO windows 0 and 1 start address low Register EXCA VO window 0 start address low byte Offset CardBus socket address 808h ExCA offset 08h Register ExCA VO window 1 start address low byte Offset CardBus socket address 80Ch ExCA offset OCh Type Read Write Default 00h Size One byte 5 10 ExCA VO Windows 0 and 1 Start Address High Byte Registers These registers contain the high byte of the 16 bit VO window start address for I O windows 0 a
169. is enabled to receive from ISO channel number 39 6 ISOCHANNEL38 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 38 5 ISOCHANNEL37 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 37 Er 6 Table 9 13 ISO Receive Channel Mask High Register Continued SIGNAL TYPE FUNCTION ISOCHANNEL36 When set to 1 the PCI4410 is enabled to receive from ISO channel number 36 ISOCHANNEL35 When set to 1 the PCI4410 is enabled to receive from ISO channel number 35 2 ISOCHANNEL34 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 34 1 ISOCHANNEL33 RSC When set to 1 the PCI4410 is enabled to receive from ISO channel number 33 0 ISOCHANNEL32 When set to 1 the PCI4410 is enabled to receive from ISO channel number 32 9 20 ISO Receive Channel Mask Low Register This set clear register is used to enable packet receives from the lower 32 isochronous data channels See Table 9 14 for a complete description of the register contents et 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name ISO receive channel mask low eut X X X X x X X x x X X X X x x x et 15 14 13 i2 1 00 9 8 7 6 5 22 23 2 1 90 Name ISOrecevechamelmasklow SS S y OO peut x X X X x X X x XIX tx x Ix tx x X Register ISO receive channel mask low Type Read Set Clear Offset 7
170. ist Bit 4 returns 1 when read This bit indicates that capabilities in addition to standard PCI capabilities are implemented The linked list of PCI power management capabilities is implemented in this function Reserved Bits 3 0 return Os when read 4 6 Revision ID Register The revision ID register indicates the silicon revision of the PCI4410 pec T r qc Y 5 pL 4 Lr c q v Jj o Revision ID Name Revision S me R R j R R j R R j R R pem o o o j o o o o 1 Register Revision ID Type Read only Offset 08h Default 01h 4 7 PCI Class Code Register The class code register recognizes the PCI4410 as a bridge device 06h and CardBus bridge device 07h with a 00h programming interface fen aso zr 2 s ws v ss s 5 5 4 8 o 8 8 IF T6 8 T4 T8 T4 T T9 Name T ed wees Seems Pewammnomete rise Te TR TR TR 8S S RTRTR TR TR 8 IE ST TR S T8 8 8 8 8 8 8 eun o olo lolol 1 1o To lolo To T9 13 12 E119 1o To T9 19 T9 T9 to Register PCI class code Type Read only Offset 09h Default 060700h 4 8 Cache Line Size Register The cache line size register is programmed by host software to indicate the system cache line size B T e ed a cup p uw Name Cachelinesize RW R W R W R W R W R W R W Register Cache line size Type Read Write Offset OCh Default 00h 4 9 Latency Timer Register The latency timer
171. it is cleared by a writeback of 1 and this also clears the PME signal driven by the PCI4410 Writing a O to this bit has no effect 4 9 DYN CTRL nos data control This bit field returns Os when read because the PCI4410 does not report dynamic PME ENB R W PMEenable This bit enables the function to assert PME If the bit is reset to 0 assertion of PME is disabled 5 RSVD DYN DATA RSVD PWR STATE Reserved These bits return Os when read Dynamic data This bit returns 0 when read because the PCI4410 does not report dynamic data e y b Reserved These bits return Os when read Power state This two bit field is used to set the PCI4410 device power state and is encoded as follows 00 Current power state is DO Current power state is D1 10 Current power state is D2 11 Current power state is D3hot 8 19 Power Management Extension Register The power management extension register provides extended power management features not applicable to the PCI4410 thus it is read only and returns 0 when read See Table 8 16 for a complete description of the register contents LE AE pou AA AE RE AE RE HURK Ge a saxum Power management extension Powermanagementextension Tee R R R R RRnR R R R R RJ RJ RJ RJ R le pea o o 0 fo fo fo fo fo fo Jo fo fo fo fo fo fo Register Power management extension Type Read only Offset 4Ah Default 0000h Table 8 16 Power Management Extension Register SIGNAL
172. its 1 and 0 indicate which pin on the 16 bit PC Card interface acts as DREQ during DMA transfers This field is encoded as 00 Socket not configured for DMA default 10 DREREIN bya 01 DREQ uses SPKR 10 DREQ uses IOIS16 11 DREQ uses INPACK 4 25 4 38 Socket DMA Register 1 The socket DMA register 1 provides control over the distributed DMA DDMA registers and the PCI portion of DMA transfers The DMA base address locates the DDMA registers in a 16 byte region within the first 64K bytes of PCI VO address space See Table 4 15 for a complete description of the register contents NOTE 32 bit transfers are not supported the maximum transfer possible for 16 bit PC Cards is 16 bits Socket DMA register 1 Name SocketDMAregisterT Hype RAW RW RAW Raw Raw RW RW RAW Raw RW RW RW B RAW RIW pw pest oo o 9 9 o n To o o po po Deo Ts Register Socket DMA register 1 Type Read only Read Write Offset 98h Default 0000 0000h Table 4 15 Socket DMA Register 1 SIGNAL TYPE FUNCTION 31 16 RSVD Reserved Bits 31 16 return Os when read DMA base address Locates the socket s DMA registers in PCI VO space This field represents a 16 bit PCI 15 4 DMABASE RAW VO address The upper 16 bits of the address are hardwired to 0 forcing this window to within the lower 64K bytes of VO address space The lower 4 bits are hardwired to O and are included in the
173. j s a da fo Latency timer and class cache line size peut o o o o fo fo fo fo fo 1 o o o oo ol Register Latency timer and class cache line size Type Read Write Offset OCh Default 0000h Table 8 6 Latency Timer and Class Cache Line Size Register SIGNAL TYPE FUNCTION PCI latency timer The value in this register specifies the latency timer for the PCI4410 in units of PCI clock cycles When the PC14410 is a PCI bus initiator and asserts FRAME the latency timer begins Tn ENS nia counting from zero If the latency timer expires before the PCI4410 transaction has terminated then the PCI4410 terminates the transaction when its GNT is deasserted 70 CACHELINE SZ RW Cache line size This value is used by the PC14410 during memory write and invalidate memory read line and memory read multiple transactions 8 5 8 8 Header Type and BIST Register The header type and BIST register indicates that this function is part of a multifunction device and has a standard PCI header type and no built in self test See Table 8 7 for a complete description of the register contents et 15 14 13 2 t 10 9 8 7 e J s j 3 2 t fo Header type and BIST Tee RIRIR R R RIR RIR RIR R R R R R peau o o o To To To To To To To To To To To oo Register Header type and BIST Type Read only Offset OEh Default 0000h Table 8 7 Header Type and BIST Register SIGNAL TYP
174. le 16 bit memory PC Card data output during host memory read cycles DMA terminal count OE is used as terminal count TC during DMA operations to a 16 bit PC Card that supports DMA The PCI4410 asserts OE to indicate TC for a DMA write operation 2 17 Table 2 12 16 Bit PC Card Interface Control Terminals Continued EE DESCRIPTION Ready The ready function is provided by READY when the 16 bit PC Card and the host socket are configured for the memory only interface READY is driven low by the 16 bit memory PC Cards to indicate thatthe memory card circuits are busy processing a previous write command READY is driven high when the 16 bit memory PC Card is ready to accept a new data transfer command Interrupt request IREQ is asserted by a 16 bit I O PC Card to indicate to the host that a device on the 16 bit I O PC Card requires service by the host software IREQ is high deasserted when no interrupt is requested Attribute memory select REG remains high for all common memory accesses When REG is asserted access is limited to attribute memory OE or WE active and to the VO space IORD or IOWR active Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information DMA acknowledge REG is used as a DMA acknowledge DACK during DMA operations to a 16 bit PC Card that supports DMA The PCI4410 asserts REG to indicate a DMA operation
175. le 9 20 Link Control Register SIGNAL TYPE FUNCTION 31 23 RSVD R Reserved Bits 31 23 return Os when read When this bit is 1 the cycle timer uses an external source CYCLEIN to determine when to roll CYCLESOURCE over the cycle timer When this bit is 0 the cycle timer rolls over when the timer reaches 3072 cycles of the 24 576 MHz clock 125 us When this bit is set to 1 and the PHY has notified the PCIA410 that it is root the PCI4410 generates a cycle start packet every time the cycle timer rolls over based on the setting of bit 22 CYCLESOURCE When this bit is 0 the OHCILynx accepts received cycle start packets to maintain synchronization with the node which is sending them This bit is automatically reset to 0 when the cycleTooLong event occurs and cannot be set to 1 until the IntEvent cycleTooLong bit is cleared CYCLEMASTER When this bit is 1 the cycle timer offset counts cycles of the 24 576 MHz clock and rolls over at CYCLETIMERENABLE the appropriate time based on the settings of the above bits When this bit is 0 the cycle timer offset does not count Reserved Bits 19 11 return Os when read RCVPHYPKT When this bit is 1 the receiver accepts incoming PHY packets into the AR request context if the AR request context is enabled This does not control receipt of self identification packets RCVSELFID When this bit is 1 the receiver accepts incoming self identification packets Before setting this bitto 1 softwa
176. le 9 32 Isochronous Receive Context Match Register Cem sew me mmm S S m mes mw ibi set men hi conto wil match on ISO receive packets wih a tag fedor tio s tase raw fists set men hi cortex wil match on ISO receive packets wi a tag ferdof 106 al mer TAW siiis se men hi context wil match on ISO receive packets pair m taco RW fists set men this cortex wil match on ISO receive packets pair a2 men Reserved ts 27 25 rum Oswheneead DD Contains a 13 bit value corresponding to the 13 bit cycleCount field in the cycleStart packet If 24 12 CYCLEMATCH cycleMatchEnable is set then this context is enabled for receives when the bus cycleCount value equals the cycleMatch value This 4 bit field is compared to the sync field of each iso packet for this channel when the command BET gen SE descriptor s w field is set to 11b Reserved Bit 7 returns 0 when read filtered according to TAGO TAG2 and TAG3 without any additional restrictions If clear this context will match on isochronous receive packets as specified in the TAGO 3 bits with no additional restrictions CHANNELNUMBER EE field indicates the isochronous channel number for which this IR DMA context accepts If this bit and bit 29 TAG1 are set then packets with tag 01b are accepted into the context if the two most significant bits of the packets sync field are 00b Packets with tag values other than 01b are 9 39 9 40 10 Electrical
177. le mode select 10 Block mode select 11 Reserved Address increment decrement The PCI4410 uses bit 5 to select the memory address in the DDMA current address base address register to increment or decrement after each data transfer This is in accordance 5 INCDEC with the 8237 use of this register bit and is encoded as follows O Addresses increment default 1 Addresses decrement Auto initialization 4 AUTOINIT O Auto initialization disabled default 1 Auto initialization enabled Transfer type Bits 3 and 2 select the type of direct memory transfer to be performed A memory write transfer moves data from the PCI4410 PC Card interface to memory and a memory read transfer moves data from memory to the PCI4410 PC Card interface The field is encoded as 3 2 XFERTYPE 00 No transfer selected default 01 Write transfer 10 Read transfer 11 Reserved RSVD R Reserved Bits 1 and 0 return Os when read 7 4 7 8 DDMA Master Clear Register The DDMA master clear register resets the DDMA controller and all DDMA registers BE pom qw ow pow qp EE py 5 m 3 Name PMA masterclear ma il OE EE AE SE e Register DDMA master clear Type Write only Offset DDMA base address ODh Default 00h Size One byte 7 9 DDMA Multichannel Mask Register The PCI4410 uses only the least significant bit of this register to mask the PC Card DMA channel The PCI4410 sets the mask bit to 1 when the PC Card is removed Host
178. ledge or ack data error is received from the target node R W The MAXATREQRETRIES field tells the asynchronous transmit DMA request unit how MAXATREQRETRIES many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack data error is received from the target node 9 4 CSR Data Register This register is used to access the bus management CSR registers from the host through compare swap operations This register contains the data to be stored in a CSR if the compare is successful 29 28 27 26 25 24 23 22 21 20 19 CSR data Name Type R R R R R R R R R R R Defaut o o 0 o o o Jo o jo o o et 15 14 13 12 t1 10 9 8 7 6 5 Name CSR data we R R IRTI TAT T T EE TARTE peat o o o o o o o fo o o Jj o Register CSR data Type Read only Offset OCh Default 0000 0000h 9 5 CSR Compare Register This register is used to access the bus management CSR registers from the host through compare swap operations This register contains the data to be compared with the existing value of the CSR resource Defaut o et 15 14 13 12 t 10 9 8 7 e j 5 j 3 J 2 t fo CSR compare EE EE EE Ee EE Po Jo Jo To o oe To 1e To 1e Jo To To eo To ol Register CSR compare Type Read only Offset 10h Default 0000 0000h 9 6 CSR Control Register This register is used to
179. lities Pointer Register 8 8 8 13 Interrupt Line and Interrupt Pin Registers 8 9 8 14 MIN ONT and MAX LAT Register 8 9 8 15 PCI OHCI Control Register site Ki REKE Sie KNA ERR EE N be 8 10 8 16 Capability ID and Next Item Pointer Registers 8 10 8 17 Power Management Capabilities Register 8 11 8 18 Power Management Control and Status Register 8 12 8 19 Power Management Extension Register 8 13 8 20 PCI Miscellaneous Configuration Register 8 14 8 21 Link Enhancement Control Register RR Re ee ke 8 15 8 22 Subsystem Access ldentification Register 8 16 8 23 GPIO Control Register ist sg Een PRE tweed ade a ben RE bene xe 8 17 Open HCI Registers i s scole s or e ARR ARE MER ERE RA IE E Re RE Rs 9 1 9 1 OHGI Version Register ss sis verna TE SERERE VERE REA oak 9 4 9 2 GUID ROM Register x ous iere p Ede eet d Scc GA ee 9 5 9 3 Asynchronous Transmit Retries Register 9 6 10 9 4 Com Data Fenisiese EER RES ietie eo IRR ERE E Ed ERE RUE 9 7 9 5 CSR Compare Register esse vy pk er RE RE ER SE wed weed ens 9 7 96 CSR Control Register ss ROES SKREDE EE AR OS BEE EE EE SUE 9 8 9 7 Configuration ROM Header Register 9 9 9 8 Bus Identification Register 23 eegen berg Eer RE RP RETE RE 9 9 9 9 Bus Options Register hee Ee FERAS EER DANE bee DR eax 9 10
180. mer Type Read Write Offset 1Bh Default 00h 4 19 Memory Base Registers 0 1 The memory base registers indicate the lower address of a PCI memory address range These registers are used by the PCI4410 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI Bits 31 12 of these registers are read write and allow the memory base to be located anywhere in the 32 bit PCI memory space on 4 Kbyte boundaries Bits 11 0 are read only and always return Os Write transactions to these bits have no effect Bits 8 and 9 of the bridge control register see Section 4 25 specify whether memory windows 0 and 1 are prefetchable or nonprefetchable The memory base register or the memory limit register must be nonzero for the PCI4410 to claim any memory transactions through CardBus memory windows that is these windows are not enabled by default to pass the first 4K bytes of memory to CardBus 29 28 27 26 25 24 23 22 21 20 19 Memory base registers 0 1 ame ee nw AW AW mw iw am am Aw mw AW a Detur o po po to Ce Kai aT MEEN BLES o o o po po Register Memory base registers 0 1 Type Read only Read Write Offset 1Ch 24h Default 0000 0000h 4 20 Memory Limit Registers 0 1 The memory limit registers indicate the upper address of a PCI memory address range These registers are used by the PCI4410 to determine when to forwar
181. minal RSVD R Reserved These bits return Os when read GPIO2 polarity invert This bit controls the input output polarity control of GPIO2 O Noninverted default 1 Inverted GPIO2 enable control This bit controls the output enable for GPIO2 O High impedance output default 1 Output enabled GPIO INV2 GPIO ENB2 driven to the GPIO2 terminal Disable link power status LPS This bit configures this terminal as 0 LPS default 1 GPIO1 Reserved This bit returns 0 when read GPIO1 polarity invert When DISABLE LPS bit is set to 1 this bit controls the input output polarity control of GPIO1 0 Noninverted default 1 Inverted RSVD R Reserved These bits return Os when read GPIO DATA2 RW GPIO2 data When GPIO2 output is enabled the value written to this bit represents the logical data o 8 17 B SIGNAL TYPE IT 12 GPIO ENB1 R 1 9 R JN 1 RSVD JN 8 GPIO DATA1 R DISABLE BMC RSVD R 6 5 GPIO INVO R W 4 GPIO ENBO R W 3 1 RSVD R 0 R GPIO DATAO AN 8 Table 8 20 GPIO Control Register Continued FUNCTION GPIO1 enable control When the DISABLE_LPS bit is set to 1 this bit controls the output enable for GPIO1 O High impedance output 1 Output enabled default Reserved These bits return Os when read GPIO1 data When the DISABLE LPS bit is set to 1 and GPIO1 output is enabled the value written to this bit represents the logical data driv
182. multichannel mask register see Section 7 9 has no effect on these bits Channel terminal count The 8327 uses bits 3 0 to indicate the TC status of each of its four DMA channels Inthe PCIA410 these bits report information about a single DMA channel therefore all four of these register 3 0 TC bits indicate the TC status of the single socket being serviced by this register All four bits are set to 1 when the TC is reached by the DMA channel These bits are reset to 0 when read or when the DMA channel is reset 7 3 7 6 DDMA Request Register The DDMA request register requests a DDMA transfer through software Any write to this register enables software requests and this register is to be used in block mode only et 7 e j s j s j 2 4 o Name DDMA request Register DDMA request Type Write only Offset DDMA base address 09h Default 00h Size One byte 7 7 DDMA Mode Register The DDMA mode register sets the DDMA transfer mode See Table 7 4 for a complete description of the register contents gu 7 e j s j a s j 2 j 1 o Name DDMA mode we am w AW am sw Aw A A Register DDMA mode Type Read only Read Write Offset DDMA base address OBh Default 00h Size One byte Table 7 4 DDMA Mode Register SIGNAL TYPE FUNCTION Mode select The PCI4410 uses bits 7 and 6 to determine the transfer mode 00 Demand mode select default 7 6 DMAMODE 01 Sing
183. n any 1 of 256 16 Mbyte regions in the 4 Gbyte PCI address space These registers are only accessible when the ExCA registers are memory mapped that is these registers cannot be accessed using the index data VO scheme et 7 e j s j s j 2 t o ExCA memory windows 0 4 page Register ExCA memory windows 0 4 page Type Read Write Offset CardBus socket address 840h 841h 842h 843h 844h Default 00h 5 22 6 CardBus Socket Registers The 1997 PC Card Standard requires a CardBus socket controller to provide five 32 bit registers that report and control socket specific functions The PCI4410 provides the CardBus socket ExCA base address register see Section 4 12 to locate these CardBus socket registers in PCI memory address space Each socket has a separate base address register for accessing the CardBus socket registers see Figure 6 1 Table 6 1 gives the location of the socket registers in relation to the CardBus socket ExCA base address The PCI4410 implements an additional register at offset 20h that provides power management control for the socket Host PC14410 Configuration Registers Memory Space ia g Offset YER Offset 00h CardBus Socket CardBus Socket ExCA Base Address Registers Soh 16 Bit Legacy Mode Base Address Registers N EN B Figure 6 1 Accessing CardBus Socket Registers Through PCI Memory Table 6 1 CardBus Socket Registers soe Ig Socket control 10h 00h 04h 08h
184. nd 1 The 8 bits of these registers correspond to the upper 8 bits of the start address Be 7 6 5 4 3 2 1 0 Name ExCA VO windows 0 and 1 start address high byte Hye RW RW RW RW RW RW RW RW petan 0 o o o o o o o Register ExCA VO window 0 start address high byte Offset CardBus socket address 809h ExCA offset 09h Register ExCA VO window 1 start address high byte Offset CardBus socket address 80Dh ExCA offset ODh Type Read write Default 00h Size One byte 5 11 ExCA VO Windows 0 and 1 End Address Low Byte Registers These registers contain the low byte of the 16 bit VO window end address for VO windows 0 and 1 The 8 bits of these registers correspond to the lower 8 bits of the end address Be 7 j e s 4 j 2 1 90 Name ExCA VO windows 0 and 1 end address low Register ExCA I O window 0 end address low byte Offset CardBus socket address 80Ah ExCA offset OAh Register ExCA VO window 1 end address low byte Offset CardBus socket address 80Eh ExCA offset OEh Type Read Write Default 00h Size One byte 5 12 ExCA VO Windows 0 and 1 End Address High Byte Registers These registers contain the high byte of the 16 bit VO window end address for VO windows 0 and 1 The 8 bits of these registers correspond to the upper 8 bits of the end address Be 7 e s 4 3 2 1 0 Name ExCA VO windows 0 and 1 end addres
185. ned to Texas Instruments is 104Ch Bit 15 t 13 m2 f v0 9 8 7 e j s 4 3 Name Vendor ID EET EEN fo fo jo 11 o jo Jo lo o Register Vender ID Type Read only Offset OOh Default 104Ch 8 3 Device ID Register This 16 bit read only register contains a value assigned to the PCI4410 by Texas Instruments The device identification for the PCI4410 OHCI controller function is 8017h Bit is 14 13 uz t 10 9 8 7 j e s 3 2 t o Device ID Name vice mwe R R RJ JR R R R R R RJR R RJR R R petan o Jo o o ojo o ojo o o 1 j Register Device ID register Type Read only Offset 02h Default 8017h 8 4 PCI Command Register The command register provides control over the PCI4410 link interface to the PCI bus All bit functions adhere to the definitions in the PCI Local Bus Specification as seen in the following bit descriptions See Table 8 3 for a complete description of the register contents LE AE AE AE AE AE AA AA E 6 6 AE AK AE 4 OE N PCI command oo POlemmad we R R R R R R aR Rw R RW R RW R aw Rrw pea o o 0 fo fo fo fo fo Jo fo fo fo fo fo fo fo Register PCI command Type Read only Read Write Offset 04h Default 0000h Table 8 3 PCI Command Register BIT SIGNAL TYPE FUNCTION 15 10 RSVD Reserved These bits return Os when read Fast back to back enable The PCI4410 will not generate
186. nfiguring the multifunction terminals Under the PC PCI protocol a PCI DMA slave device such as the PCI4410 requests a DMA transfer on a particular channel using a serialized protocol on PCREQ The VO DMA bus master arbitrates for the PCI bus and grants the channel through a serialized protocol on PCGNT when it is ready for the transfer The VO cycle and memory cycles are then presented on the PCI bus which performs the DMA transfers similarly to legacy DMA master devices PC PCI DMA is enabled for each PC Card 16 slot by setting bit 19 CDREQEN in the respective system control register see Section 4 29 On power up this bit is reset and the card PC PCI DMA is disabled Bit 3 CDMA EN of the system control register is a global enable for PC PCI DMA and is set at power up and never cleared if the PC PCI DMA mechanism is implemented The desired DMA channel for each PC Card 16 slot must be configured through bits 18 16 CDMACHAN field in the system control register The channels are configured as indicated in Table 3 3 Table 3 3 PC PCI Channel Assignments SYSTEM CONTROL REGISTER DMA CHANNEL CHANNEL TRANSFER DATA WIDTH BIT 18 BIT 17 BIT16 amp o o Channel 0 8 bit DMA transfers og o 4 Channel 1 8 bit DMA transfers Do 5 o Gendt 2 OMA vansters Do 5 poemas et MA rantes 3 0 o Ghameis nous Do 0 5 cremas 16 ROMA raters OS Geng 16 OMA raters OG oer 1GBRDMA rans
187. ntrol Status Register 4 29 Power Management Control Status Register Bridge Support Extensions 4 30 General Purpose Event Status Register 4 31 General Purpose Event Enable Register iss ei ss se de se 4 32 General Purpose Input Register 4 33 General Purpose Output Register 4 34 ExCA Registers and Offsets is EE Ee ee eee 5 2 ExCA Identification and Revision Register 5 4 ExCA Interface Status Register 5 5 ExCA Power Control Register 82365SL Support 5 6 ExCA Power Control Register 82365SL DF Support 5 6 ExCA Interrupt and General Control Register 5 7 ExCA Card Status Change Register ii ss ee se ee ee sed ee ee 5 8 ExCA Card Status Change Interrupt Configuration Register 5 9 ExCA Address Window Enable Register ssluuuses 5 10 ExCA VO Window Control Register 5 11 ExCA Memory Windows 0 4 Start Address High Byte Registers 5 15 ExCA Memory Windows 0 4 End Address High Byte Registers 5 17 ExCA Memory Windows 0 4 Offset Address High Byte Registers 5 19 ExCA VO Card Detect and General Control Register 5 21 ExCA Global Control Register scene rr m RR NAL 5 22 CardBus Socket Registers i nude haah AA RE PEERS 6 1 Socket Event Register St AR e EE Eb a TEES AREE AREE RES 6 2 Socket Mask Register is Ee EE RE de ee eee ees 6
188. nvironments Mix and match 5 V 3 3 V 16 bit PC Cards and 3 3 V CardBus Cards Single PC Card or CardBus slot with hot insertion and removal Burst transfers to maximize data throughput on the PCI bus and the CardBus bus Parallel PCI interrupts parallel ISA IRQ and parallel PCI interrupts serial ISA IRQ with parallel PCI interrupts and serial ISA IRQ and PCI interrupts Serial EEPROM interface for loading subsystem ID and subsystem vendor ID Pipelined architecture allows greater than 130M bps sustained throughput from CardBus to PCI and from PCI to CardBus Interface to parallel single slot PC Card power interface switches like the TIM TPS2211 Up to five general purpose l Os Programmable output select for CLKRUN Five PCI memory windows and two UO windows available to the 16 bit PC Card socket Two I O windows and two memory windows available to the CardBus socket Exchangeable Card Architecture ExCA compatible registers are mapped in memory and VO space Intel 82365SL DF and 82365SL register compatible Distributed DMA DDMA and PC PCI DMA 16 Bit DMA on the PC Card socket Ring indicate SUSPEND PCI CLKRUN and CardBus CLKRUN Socket activity LED pins PCI bus lock LOCK Advanced submicron low power CMOS technology Internal ring oscillator OHCI link function designed to EEE 1394 Open Host Controller Interface OHCI Specification Implements PCI burst transfers and deep FIFOs to tolerate large host latency Supports physical write p
189. o circuits shown in Figure 3 7 can be implemented to provide LED signaling It is left for the board designer to implement the circuit that best fits the application The LED activity signals are valid when a card is inserted powered and not in reset For PC Card 16 the LED activity signal is pulsed when READY IREQ is low For CardBus cards the LED activity signal is pulsed if CFRAME CIRDY or CREQ is active Current Limiting R 500 0 PC14410 LED v Na Current Limiting r a Rs Application 500 2 Specific Delay mM PCI4410 EE 1 v Figure 3 7 Two Sample LED Circuits As indicated the LED signals are driven for a period of 64 ms by a counter circuit To avoid the possibility of the LED appearing to be stuck when the PCI clock is stopped the LED signaling is cut off when the SUSPEND signal is asserted when the PCI clock is to be stopped during the clock run protocol or when in the D2 or D1 power state If any additional socket activity occurs during this counter cycle then the counter is reset and the LED signal remains driven If socket activity is frequent at least once every 64 ms then the LED signal remains driven 3 5 10 PC Card 16 Distributed DMA Support The PC14410 supports a distributed DMA slave engine for 16 bit PC Card DMA support The distributed DMA DDMA slave register set provides the programmability necessary for the slave DDMA engine Table 3 2 provides the DDMA
190. o produce SPKROUT This output is enabled by bit 1 SPKROUTEN in the card control register see Section 4 34 Older controllers support CAUDIO in binary or PWM mode but use the same pin SPKROUT Some audio chips may not support both modes on one pin and may have a separate pin for binary and PWM The PCI4410 implementation includes a signal for PWM CAUDPWM which can be routed to a MFUNC terminal Bit 2 AUD2MUX located in the card control register is programmed to route a CardBus CAUDIO PWM terminal to CAUDPWM See Section 4 32 Multifunction Routing Register for details on configuring the MFUNC terminals Figure 3 6 illustrates a sample application using SPKROUT and CAUDPWM System Core Logic BINARY SPKR SPKROUT PC14410 CAUDPWM PWM SPKR Speaker Subsystem Figure 3 6 Sample Application of SPKROUT and CAUDPWM 3 5 93 LED Socket Activity Indicators The socket activity LEDs are provided to indicate when a PC Card is being accessed The LED SKT signal can be routed to the multifunction terminals and is also provided on a dedicated pin LED SKT When configured for LED output this terminal outputs an active high signal to indicate socket activity See Section 4 32 Multifunction Routing Register for details on configuring the multifunction terminals The LED signal is active high and is driven for 64 ms durations When the LED is not being driven high it is driven to a low state Either of the tw
191. of PME context bits Global reset GRST is used only on the initial boot up of the system after power up It places the PCI4410 in its default state and requires BIOS to configure the device before becoming fully functional PCI reset PRST now has dual functionality based on whether PME is enabled or not If PME is enabled then PME context is preserved If PME is not enabled then PRST acts the same as a normal PCI reset Please see the master list of PME context bits in Section 3 8 10 e Power source in D3cold if wake up support is required from this state Because Voc is removed in D3cola an auxiliary power source must be supplied to the PCI4410 Vcc pins Consult the PC 14xx Implementation Guide for D3 Wake Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for further information 3 8 9 ACPI Support The Advanced Configuration and Power Interface ACPI Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver The PCI4410 offers a generic interface that is compliant with ACPI design rules Two doublewords of general purpose ACPI programming bits reside in PCI4410 PCI configuration space at offset A8h The programming model is broken into status and control functions In compliance with ACPI the top level event status and enable bits reside in the general purpose event status see Section 4 45 and general purpose event enable see Section 4 46
192. ol Register is EES ESRA DE Eg EE Ended ipid 9 23 Node Identification Register 9 24 PHY Control Register uu kka KARERA vb oa ce SO RR EO o CR DE RIG de 9 25 Isochronous Cycle Timer Register 9 26 Asynchronous Request Filter High Register 9 27 Asynchronous Request Filter Low Register ss Es es see 9 29 Physical Request Filter High Register 9 30 Physical Request Filter Low Register 9 32 Asynchronous Context Control Register 9 33 Asynchronous Context Command Pointer Register 9 34 Isochronous Transmit Context Control Register 9 35 Isochronous Receive Context Control Register 9 37 Isochronous Receive Context Match Register 9 39 xiii xiv 1 Introduction The Texas Instruments PCI4410 is an integrated single socket PC Card controller and IEEE 1394 Open HCI host controller This high performance integrated solution provides the latest in both PC Card and IEEE 1394 technology 1 1 Description The PCI4410 is a dual function PCI device compliant with PCI Local Bus Specification 2 2 Function O provides the independent PC Card socket controller compliant with the 1997 PC Card Standard The PCI4410 provides features that make it the best choice for bridging between the PCI bus and PC Cards and supports either 16 bit or CardBus PC Cards in the socket powered at 5 V or 3 3 V as required All card signals a
193. om that node are accepted If set to 1 for local bus node number 44 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 43 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 42 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 41 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 40 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 39 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 38 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 37 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 36 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 35 asynchronous requests received by the PCI4410 from that node are accepted If set to 1 for local bus node number 34 asynchronous requests received by the PCI4410 from that node are accepted ASYNREQRESOURCE33 ASYNREQRESOURCE32 mec RSC 9 28 If set to 1 for local bus node number 33 asynchronous requests r
194. ons for setting bit 8 have not been met CB DPAR 1 A data parity error occurred and the following conditions were met a CPERR was asserted on the CardBus interface b The PCI4410 was the bus master during the data parity error c The parity error response bit is set in the bridge control Fast back to back capable The PCI4410 cannot accept fast back to back transactions therefore bit 7 User definable feature support The PCI4410 does not support the user definable features therefore bit 6 CB UDF is hardwired to 0 5 CB66MHZ 66 MHz capable The PCI4410 CardBus interface operates at a maximum CCLK frequency of 33 MHz therefore bit 5 is hardwired to 0 RSVD R Reserved Bits 4 0 return Os when read 4 8 4 15 PCI Bus Number Register This register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI4410 is connected The PCI4410 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses m 7 s 1 03 WEER EE we mw Aw AW w ww AW Register PCI bus number Type Read Write Offset 18h Default 00h 4 16 CardBus Bus Number Register This register is programmed by the host system to indicate the bus number of the CardBus bus to which the PC14410 is connected The PCI4410 uses this register in conjunction with the PCI bus num
195. or gm o a 163 n HET WE o 7 e WE afa a WENA o C Wysig mmu o o o o o 9 fofo fofo To T9 T9 T 9 T9 Register Multifunction routing Type Read only Read Write Offset 8Ch Default 0000 0000h Table 4 9 Multifunction Routing Register SIGNAL TYPE FUNCTION 31 28 RSVD Bits 31 28 return Os when read Multifunction terminal 6 configuration These bits control the internal signal mapped to the MFUNC6 terminal as follows 0000 RSVD 0100 IRO4 1000 IRQ8 1100 IRQ12 0001 CLKRUN 0101 IRQ5 1001 IRQ9 1101 IRQ13 0010 IRQ2 0110 IRQ6 1010 IRQ10 1110 IRQ14 0011 IRQ3 0111 IRQ7 1011 IRQ11 1111 IRQ15 Multifunction terminal 5 configuration These bits control the internal signal mapped to the MFUNCS terminal as follows 0000 GPI4 0100 IRQ4 1000 CAUDPWM 1100 LED SKT 0001 GPO4 0101 D3 STAT 1001 IRQ9 1101 Diagnostic setup OHCI test 27 24 MFUNC6 0010 PCGNT 0110 ZVSTAT 1010 2 IRQ10 1110 2 GPE MFUNC5 0011 IRQ3 0111 ZVSELO 1011 IRQ11 1111 2 IRQ15 Multifunction terminal 4 configuration These bits control the internal signal mapped to the MFUNCA terminal NOTE When the serial bus mode is implemented by pulling up the VCCDO and VCCD1 terminals the MFUNCA terminal provides the SCL signaling 0000 GPI3 0100 IRQ4 1000 CAUDPWM 1100 RI OUT 0001 GPO3 0101 2 IRQ5 1001 IRQ9 1101 LED SKT 0010 PCI LOCK 0110 ZVSTAT 1010 2 IRQ
196. or a complete description of the register contents gu 7 e j s j s j 2 1 0o Name Power management control status register bridge support extensions Type R RW R R R R R J R peas 1 4 o o o oo j o o Register Power management control status register bridge support extensions Type Read only Offset A6h Default COh Table 4 18 Power Management Control Status Register Bridge Support Extensions SIGNAL TYPE FUNCTION BPCC Enable Bus power clock control enable This bit returns 1 when read This bit is encoded as O Bus power clock control is disabled 1 Bus power clock control is enabled default 7 BPCC EN A 0 indicates that the bus power clock control policies defined in the PCI Bus Power Management Interface Specification are disabled When the bus power clock control enable mechanism is disabled the bridge s power management control status register power state field see Section 4 42 bits 1 0 cannot be used by the system software to control the power or the clock of the bridge s secondary bus A 1 indicates that the bus power clock control mechanism is enabled B2 B3 support for D3hot The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot This bitis only meaningful if bit7 BPCC EN isa 1 This bitis encoded B2 B3 Rw 3 0 When the bridge is programmed to D3hot its secondary bus will have its power removed
197. or enable bits See Section 5 5 ExCA Card Status Change Register and Section 5 2 ExCA Interface Status Register for the status bits for this signal Status change STSCHG is used to alert the system to a change in the READY write protect or battery voltage dead condition of a 16 bit VO PC Card Ring indicate RI is used by 16 bit modem cards to indicate a ring detection Battery voltage detect 2 BVD2 is generated by 16 bit memory PC Cards that include batteries BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card Both BVD1 and BVD2 are high when the battery is good When BVD2 is low and BVD1 is high the battery is weak and should be replaced When BVD1 is low the battery is no longer serviceable and the data in the memory PC Card is lost See Section 5 6 ExCA Card Status Change Interrupt Configuration Register for enable bits See Section 5 5 ExCA Card Status Change Register and Section 5 2 ExCA Interface Status Register for the status bits for this signal Speaker SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16 bit VO interface The audio signals from cards A and B are combined by the PCI4410 and are output on SPKROUT DMA request BVD2 can be used as the DMA request signal during DMA operations to a 16 bit PC Card that supports DMA The PC Card asserts BVD2 to indicate a request for a DMA operation Card detect 1 and Card de
198. osting of up to 3 outstanding transactions OHCI link function is IEEE 1394 1995 compliant and compatible with Proposal 1394a Supports serial bus data rates of 100 200 and 400 Mbits second Provides bus hold buffers on the PHY Link I F for low cost single capacitor isolation Tl is a trademark of Texas Instruments Incorporated 1 3 Related Documents e Advanced Configuration and Power Interface ACPI Specification Revision 2 0 e PCI Bus Power Management Interface Specification Revision 1 1 e PCI Bus Power Management Interface Specification for PCI to CardBus Bridges Revision 1 e PCI Local Bus Specification Revision 2 2 e PCI Mobile Design Guide Revision 1 0 e PCli4xx Implemenation Guide for D3 Wake Up e 1997 PC Card Standard e PC 98 99 e Serialized IRQ Support for PCI Systems Revision 6 1 4 een Information ORDERINGNUMBER NUMBER VOLTAGE PACKAGE PCI4410 NEN M Card controller 3 3 V 5 V tolerant I Os 208 pin LQFP 209 ball PBGA 2 Terminal Descriptions The PC14410 is packaged in either a 209 ball GHK MICROSTAR BGA or a 208 terminal PDV package The PCI4410 is a single socket CardBus bridge with integrated OHCI link Figure 2 1 is a terminal diagram of the PDV package with PCI to CardBus signal names Figure 2 2 is a terminal diagram of the PDV package with PCI to PC Card signal names Figure 2 3 is a terminal diagram of the GHK package LPS PHY LREQ VCC PHY_CLK PHY_CTL 0 PHY_CTL 1
199. ot been stopped by the PCI4410 CCLKRUN manager The PC14410 restarts the PCI clock using the CLKRUN protocol under any of the following conditions e APC Card 16 IREQ or a CardBus CINT has been asserted e ACardBus CBWAKE CSTSCHG or PC Card 16 STSCHG RI event occurs e ACardBus attempts to start the CCLK using CCLKRUN e A CardBus card arbitrates for the CardBus bus using CREQ e A 16 bit DMA PC Card asserts DREQ 3 8 2 CardBus PC Card Power Management The PCI4410 implements its own card power management engine that can turn off the CCLK to a socket when there is no activity to the CardBus PC Card The PCI clock run protocol is followed on the CardBus CCLKRUN interface to control this clock management 3 19 3 8 3 16 Bit PC Card Power Management The COE bit 7 EXCA power control register and PWRDWN bit 0 ExCA global control register bits are provided for 16 bit PC Card power management The COE bit places the card interface in a high impedance state to save power The power savings when using this feature are minimal The COE bit will reset the PC Card when used and the PWRDWN bit will not Furthermore the PWRDWN bit is an automatic COE that is the PWRDWN performs the COE function when there is no card activity NOTE The 16 bit PC Card must implement the proper pullup resistors for the COE and PWRDWN modes 3 8 4 Suspend Mode The SUSPEND signal provided for backward compatibility gates the PRST PCI reset signal and the
200. pabilities reporting Power status reporting Setting the power state System wake up The OS identifies the capabilities of the PCI function by traversing the new capabilities list The presence of capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 CAPLIST of the status register see Section 4 5 The capabilities pointer provides access to the first item in the linked list of capabilities For the PCI4410 a CardBus bridge with PCI configuration space header type 2 the capabilities pointer is mapped to an offset of 14h The first byte of each capability register block is required to be a unique ID of that capability PCI power management has been assigned an ID of 01h The next byte is a pointer to the next pointer item in the list of capabilities If there are no more items in the list then the next item pointer should be set to 0 The registers following the next item pointer are specific to the function s capability The PCI power management capability implements the register block outlined in Table 3 10 Table 3 10 Power Management Registers REGISTER NAME OFFSET Power management capabilities Next item pointer Capability ID PMCSR bridge support extensions Power management control status CSR The power management capabilities register see Section 4 41 is a static read only registerthat provides information on the capabilities of the function related to power management The power management control sta
201. ponding bit in the set clear register to be set to 1 whereas a 0 leaves the corresponding bit unaffected A 1 written to RegisterClear causes the corresponding bit in the set clear register to be reset to O whereas a O leaves the corresponding bit in the set clear register unaffected Typically a read from either RegisterSet or RegisterClear returns the value of the set clear register However sometimes reading the RegisterClear provides a masked version of the set clear register The interrupt event register is an example of this behavior Table 9 1 Open HCI Register Map Bus identification BuslD 1Ch EE MERE Global unigue ID high GUIDHi CT Jat E EE E CCT Peseved mm Bana LGAN ROM map MEMEL Es E Posted write address high PostedWriteAddressHi eim mp Reserved 44h 4Ch 9 1 9 Table 9 1 Open HCI Register Map Continued DMA CONTEXT Self ID 2 Interrupt avent IntEventClear 84h IntMaskSet 88h Interrupt mask IntMaskClear 8Ch IsoXmitlntEventSet 90h Isochronous transmit interrupt event IsoXmitintEventClear 94h IsoXmitlntMaskSet 98h Isochronous transmit interrupt mask 9Ch Physical upper bound 120h Table 9 1 Open HCI Register Map Continued DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET ContextControlSet 180h Asynchronous Gontexkeartrel ContextControlClear 184h request transmit ATRQ Reseved 88 Command pointer CommandPt
202. progress When set bit 8 indicates an interrogation is in progress and clears when INTERROGATE interrogation completes This bit is socket dependent 0 Interrogation not in progress default 1 Interrogation in progress Auto power switch enable 7 AUTOPWRSWEN R W 0 Aa in EXCA power control register see Section 5 3 is disabled 1 Bit 5 AUTOPWRSWEN in ExCA power control register see Section 5 3 is enabled Power savings mode enable When this bit is set if a CB card is inserted idle and without a CB clock ES PWRSAVINGS then the applicable CB state machine will not be clocked Subsystem ID see Section 4 27 subsystem vendor ID see Section 4 26 EXCA identification and revision see Section 5 1 registers read write enable SUBSYSRW 0 Subsystem ID subsystem vendor ID ExCA identification and revision registers are read write 1 Subsystem ID subsystem vendor ID ExCA identification and revision registers are read only default CardBus data parity error SERR signaling enable O CardBus data parity error not signaled on PCI SERR 1 CardBus data parity eror signaled on PCI SERR PC PCI DMA enable Bit 3 enables PC PCI DMA when set if MFUNCO MFUNC6 are configured for centralized DMA CB DPAR 0 Centralized DMA disabled default 3 CDMA EN R W 1 Centralized DMA enabled ExCA power control bit Enabled by selecting the 82365SL mode 2 ExCAPower R W 0 Enables 3 3 V 1 Enables 5 V Keep clock This bit works wit
203. r Register Vendor ID Type Read only Offset 40h Default 0000 0000h 9 13 T ki 9 16 Host Controller Control Register This set clear register pair provides flags for controlling the PCI4410 link function See Table 9 11 for a complete description of the register contents et 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Hostoonwollerconteol Host controller control kr E Ga E NCR Can Ca a BON EE EE Register Host controller control Type Read Set Clear Update Offset 50h set register 54h clear register Default X00X 0000h Table 9 11 Host Controller Control Register BIT SIGNAL TYPE FUNCTION 31 RSVD R Reserved Bit 31 returns 0 when read This bitis used to control whether physical accesses to locations outside the PC144 10 itself as well as any other DMA data accesses should be swapped RSVD R Reserved Bits 29 24 return Os when read This bit informs upper level software that lower level software has consistently configured the p1394a enhancements in the Link and PHY When this bit is 1 generic software such as the OHCI driver is responsible for configuring p1394a enhancements in the PHY and the APHYENHANCEENABLE bit in the PC14410 When this bit is 0 the generic software may not modify the p1394a enhancements in the PCI4410 or PHY and cannot interpret the setting of APHYENHANCEENABLE This bit can be initialized from serial EEPROM When bits 23 PROGRAMPHYEN
204. r 18Ch ContextControlSet 1A0h Asynchronous Context control response transmit ContextControlClear 1A4h ATRS Reserved 1A8h Command pointer CommandPtr 1ACh Reserved 1B0h 1BCh Asynchronous ContextControlSet 1COh RO Jee LE Reed EE KSA ContextControlSet 1EOh Asynchronous Context control response receive ContextControlClear 1E4h ARRS Dese Ha Command pointer CommandPtr 1ECh l GE l ContextControlSet 200h 16 n ransmit context n ontext contro B ContextControlClear 204h 4 16 n n 0 1 2 3 7 Reserved 208 fen Command pointer CommandPtr 20Ch 16 n ContextControlSet 400h 4 32 n Isochronous Context control receive context n ContextControlClear 404h 4 32 n Command pointer CommandPtr 40Ch 32 n Do Context match ContextMatch 410h 32 n 9 1 OHCI Version Register This register indicates the OHCI version support and whether or not the serial ROM is present See Table 9 2 for a complete description of the register contents Register OHCI version Type Read only Offset 00h Default 0001 0000h Table 9 2 OHCI Version Register BIT SIGNAL TYPE FUNCTION 31 25 RSVD R Reserved Bits 31 25 return Os when read GUID ROM The PC14410 sets this bit to 1 if the serial ROM is detected If the serial ROM is present then the Bus Info Block is automatically loaded on hardware reset Major version of the open HCI The PCI4410 is compliant with the OHCI specification version 1 00 thus PITIE A VERS
205. r PC Card pins Vj VeCCB For miscellaneous pins Vj VCCI tFor VO pins input leakage li and IH includes 107 leakage of the disabled output 10 3 10 4 PCI Clock Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free Air Temperature um 30 te Cycle time PCLK toyo s0 twH Pulse duration width PCLK high thigh 0 0 o twL Pulse duration width PCLK low 1 Av At Slew rate PCLK tr tf tsu Setup time PCLK active at end of PRST trst clk o lito us 10 5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free Air Temperature ALTERNATE PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT PCLK to shared signal 1 valid delay time CL 50 pF PCLK to shared signal See Note 4 invalid delay time tod Propagation delay time See Note 4 ns Non Enable time igh Impedance o cive delay O ds DIsabi time active impedance delay ime rom PCLK w __ aje DEER EE rs in Poa ime afer POLK high LTC 10 4 11 Mechanical Information The PC14410 is packaged in either a 209 ball GHK MicroStar BGA or a 208 pin PDV package The PCI4410 is a single socket CardBus bridge with an integrated OHCI link The following shows the mechanical dimensions for the GHK and PDV packages GHK S PBGA N209 PLASTIC BALL GRID ARRAY OOOOOOQOOOOOO OOOOOQOOOOO OOOOOOOOOOO OOOOQOOOO OOOOOQOOOOO OOOOOOOOOOO OOOOOQOOOOO O
206. r or not a PCI device ignores PCI special cycles The PCI4410 does not respond to special cycle operations therefore this bit is hardwired to 0 Bus master control Bit 2 controls whether or not the PCI4410 can act as a PCI bus initiator master The PC14410 can take control of the PCI bus only when this bit is set 2 MAGILEN UNY 0 Disables the PCI4410 s ability to generate PCI bus accesses default 1 Enables the PCIA410 s ability to generate PCI bus accesses Memory space enable Bit 1 controls whether or not the PCI4410 can claim cycles in PCI memory space 1 MEM EN 0 Disables the PCI4410 s response to memory space accesses default 1 Enables the PCIA410 s response to memory space accesses VO space control Bit O controls whether or not the PCI4410 can claim cycles in PCI VO space IO EN 0 Disables the PCI4410 from responding to VO space accesses default 1 Enables the PCIA410 to respond to I O space accesses 4 5 Status Register The status register provides in the status register is reset functions adhere to the defini device information to the host system Bits in this register may be read normally A bit when a 1 is written to that bit location a O written to a bit location has no effect All bit tions in the PCI Local Bus Specification PCI bus status is shown through each function See Table 4 3 for the complete description of the register contents Bit 15 14 13 12 n t0 9 8 J 7 J e 5 pats 2
207. r register See Table 9 17 for a complete description of the register contents Bit 31 3o 29 28 27 26 25 2a 23 22 2t 20 19 18 17 16 Isochronous transmit interrupt event fee R R RJ JR R R R R R RJR RJ JRJR R R petan o o o o fo fo fo fo fo fo fo fo fo fo fof Bit 15 14 13 2 ff 10 9 amp v j e s Ja da o Isochronous transmit interrupt event dsohrnoustensmitintemptevent Tye n R R n n R n R hs Asc nsc Asc Rsc Rec Rsc Aso pea o o fo fo fo fo fo fo fx fx tx txt x tx tx x Register Isochronous transmit interrupt event Type Read Set Clear Read only Offset 90h set register 84h clear register returns IsoXmitEvent and IsoXmitMask when read Default 0000 00XXh Table 9 17 Isochronous Transmit Interrupt Event Register FUNCTION 31 8 RSVD R Reserved Bits 31 8 return Os when read Isochronous transmit channel 7 caused the isochTx interrupt Isochronous transmit channel 6 caused the isochTx interrupt Isochronous transmit channel 5 caused the isochTx interrupt Isochronous transmit channel 4 caused the isochTx interrupt Isochronous transmit channel 3 caused the isochTx interrupt Isochronous transmit channel 2 caused the isochTx interrupt Isochronous transmit channel 1 caused the isochTx interrupt Isochronous transmit channel 0 caused the isochTx interrupt m c nLjo o o 9 20 9
208. rd This bit is encoded as 0 Memory window 2 disabled default 1 Memory window 2 enabled MEMWIN2EN Memory window 1 enable Bit 1 enables disables memory window 1 for the PC Card This bit is encoded as MEMWIDTER 0 Memory window 1 disabled default 1 Memory window 1 enabled Memory window O enable Bit O enables disables memory window O for the PC Card This bit is encoded as MEMWINGEN 0 Memory window 0 disabled default 1 Memory window O enabled encoded as 8 DMEMNSINSEN 0 Memory window 3 disabled default 1 Memory window 3 enabled 5 8 ExCA VO Window Control Register The ExCA I O window control register contains parameters related to VO window sizing and cycle timing See Table 5 10 for a complete description of the register contents et v e j s j a 2 1 90 Name ExCA VO window control Register ExCA l O window control Type Read Write Offset CardBus socket address 807h ExCA offset 07h Default 00h Table 5 10 ExCA VO Window Control Register SIGNAL TYPE FUNCTION VO window 1 wait state Bit 7 controls the I O window 1 wait state for 16 bit I O accesses Bit 7 has no effect on 8 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as O 16 bit cycles have standard length default 1 16 bit cycles are extended by one equivalent ISA wait state WAITSTATE1 VO window 1 zero wait state Bit 6
209. rd warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used TI s publication of information regarding any third party s products or services does not constitute TI s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporate
210. re internally buffered to allow hot insertion and removal without external buffering The PCI4410 is register compatible with the Intel 82365SL DF and 82365SL ExCA controllers The PCI4410 internal data path logic allows the host to access 8 16 and 32 bit cards using full 32 bit PCI cycles for maximum performance Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting The PCI4410 can be programmed to accept posted writes to improve bus utilization Function 1 of the PCI4410 is compatible with IEEE1394A and the latest 1394 open host controller interface OHCI specifications The chip provides the IEEE1394 link function and is compatible with data rates of 100 200 and 400 Mbits per second Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies The PCI4410 provides physical write posting and a highly tuned physical data path for SBP 2 performance Multiple cache line burst transfers advanced internal arbitration and bus holding buffers on the PHY Link interface are other features that make the PCI4410 the best in class 1394 Open HCI solution The PC14410 provides an internally buffered zoomed video ZV path This reduces the design effort of PC board manufacturers to add a ZV compatible solution and ensures compliance with the CardBus loading specifications Various implementation specific functions and general purpose inputs and outputs are provided throu
211. re must ensure that the self ID buffer pointer register contains a valid address RSVD R Reserved Bits 8 0 return Os when read 9 23 9 29 Node Identification Register This register contains the address of the node on which the OHCILynx chip resides and indicates the valid node number status The 16 bit combination of busNumber and NodeNumber is referred to as the node ID See Table 9 21 for a complete description of the register contents Bit 31 so 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 Node identification DO Nodeidentiheaton Type m Ru R A Rut R R R JR R R JR RnR JR RR m petan o o o o fo fo fo fo fo fo lo fo fo lo lo m a ww wn 3 s T5 17 L5 15 apa 12 12 1294 mm Node meu o fo 31 3 L3 13 13 L3 LX EX EX T2 T9 T Register Node identification Type Read Write Update Read Update Read only Offset E8h Default 0000 11XXh Table 9 21 Node Identification Register This bit indicates whether or not the PCI4410 has a valid node number It is reset to O when a 1394 bus reset is detected and set to 1 when the PCIA410 receives a new node number from the PHY ROOT This bit is set to 1 during the bus reset process if the attached PHY is root 29 28 RSVD Reserved Bits 29 and 28 return Os when read Ls es RT This bit is set to 1 if the PHY is reporting that cable power status is OK VP 8V 26 16 RSVD Reserved Bits
212. received packets are placed back to back to completely fill each receive buffer When resetto 0 each received packet is placed in a single buffer If the MULTICHANMODE bit is setto 1 this bit must also be setto 1 The value of BUFFERFILL must not be changed while ACTIVE or RUN is set to 1 When set to 1 received isochronous packets will include the complete 4 byte isochronous packet header seen by the link layer The end of the packet is marked with xferStatus in the first doublet and a 16 bit timeStamp indicating the time of the most recently received or sent cycleStart packet When clear the packet header is stripped from received isochronous packets The packet header if received immediately precedes the packet payload The value of isochHeader must not be changed while ACTIVE or RUN is set to 1 BUFFERFILL ISOCHHEADER When set to 1 the context begins running only when the 13 bit cycleMatch field in the contextMatch register matches the 13 bit cycleCount in the cycleStart packet The effects of CYCLEMATCHENABLE this bit however are impacted by the values of other bits in this register Once the context has become active hardware clears the CYCLEMATCHENABLE bit The value of CYCLEMATCHENABLE must not be changed while ACTIVE or RUN is set to 1 When set to 1 the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the IRChannelMaskHi and IRChannelMaskLo registers The isochronous
213. register configuration Two socket function dependent PCI configuration header registers that are critical for DDMA are the socket DMA register 0 see Section 4 37 and the socket DMA register 1 see Section 4 38 Distributed DMA is enabled through socket DMA register 0 and the contents of this register configure the PC Card 16 terminal SPKR IOIS16 or INPACK which is used for the DMA request signal DREQ The base address of the DDMA slave registers and the transfer size bytes or words are programmed through the socket DMA register 1 See the programming model and register descriptions in Section 4 for details 3 8 Table 3 2 Distributed DMA Registers DDMA TYPE REGISTER NAME BASE ADDRESS OFFSET R B d B Current address eserve age 8 NA w Reserved O R Multichannel R N A eserve iac The DDMA registers contain control and status information consistent with the 8237 DMA controller however the register locations are reordered and expanded in some cases While the DDMA register definitions are identical to those in the 8237 DMA controller of the same name some register bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment In such cases the PCI4410 implements these obsolete register bits as read only nonfunctional bits The reserved registers shown in Table 3 2 are implemented as read only and return Os when read Write transactions to reserved registers have no ef
214. register specifies the latency timer for the PCI4410 in units of PCI clock cycles When the PCI4410 is a PCI bus initiator and asserts FRAME the latency timer begins counting from zero If the latency timer expires before the PCI4410 transaction has terminated then the PCI4410 terminates the transaction when its GNT is deasserted 7 m 7 I s I s I I 3 L 2 I I s mme WEE Hye RW RW RW RW RW Rw RW RW pude o qn op o ow ng o dg N o Register Latency timer Type Read Write Offset ODh Default 00h 4 10 Header Type Register This register returns 82h when read indicating that the PCI4410 configuration spaces adhere to the CardBus bridge PCI header The CardBus bridge PCI header ranges from PCI register 0 to 7Fh and 80h FFh are user definable extension registers gu 7 e j s 4 s j 2 4 o Name Headrpe mwe R R j R R j R R j R R peam 1 o o o o o o Register Header type Type Read only Offset OEh Default 82h 4 11 BIST Register Because the PCI4410 does not support a built in self test BIST this register returns the value of 00h when read Register BIST Type Read only Offset OFh Default 00h 4 6 4 12 CardBus Socket ExCA Base Address Register The CardBus socket ExCA base address register is programmed with a base address referencing the CardBus socket registers and the memory mapped E
215. registers 3 23 The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the pending status bit The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods A hierarchical implementation would be somewhat limiting however as upstream devices would have to remain in some level of power state to report events For more information of ACPI see the Advanced Configuration and Power Interface ACPI Specification 3 8 10 Master List of PME Context Bits and Global Reset Only Bits If the PME enable bit PCI offset A4h bit 8 is asserted then the assertion of PRST will not clear the following PME context bits If the PME enable bit is not asserted then the PME context bits are cleared with PRST The PME context bits are Bridge control register PCI offset 3Eh bit 6 Power management control status register PCI offset A4h bits 15 8 ExCA power control register ExCA offset 802h bits 4 3 1 0 ExCA interrupt and general control ExCA offset 803h bits 6 5 ExCA card status change interrupt register ExCA offset 805h bits 3 0 CardBus socket event register CardBus offset 00h bits 3 0 CardBus socket mask register CardBus offset 04h bits 3 0 CardBus socket present state register CardBus offset 08h bits 13 10 7 5 0 CardBus socket control register CardB
216. rite a O to this bit PME SUPPORT Bit 14 contains the value 1 indicating that the PME signal can be asserted from D3po state Bit 13 contains the value 1 indicating that the PME signal can be asserted from D2 state Bit 12 contains the value 1 indicating that the PME signal can be asserted from D1 state Bit 11 contains the value 1 indicating that the PME signal can be asserted from the DO state D2 SUPPORT D2 support Bit 10 returns a 1 when read indicating that the CardBus function supports the D2 device power state D1 SUPPORT ES GE Bit 9 returns a 1 when read indicating that the CardBus function supports the D1 device 8 6 RSVD R Reserved Bits 8 6 return Os when read Device specific initialization Bit 5 returns 1 when read indicating that the CardBus controller function 5 DSI requires special initialization beyond the standard PCI configuration header before the generic class device driver is able to use it Auxiliary power source Bit 4 is meaningful only if bit 15 PME Support D3cold is set When bit 4 is ij AUX PWR set it indicates that support for PME in D3cojg requires auxiliary power supplied by the system by way of a proprietary delivery vehicle When bit 4 is O it indicates that the function supplies its own auxiliary power source Because the PCI4410 requires an auxiliary power supply this bit returns 1 PME clock Bit 3 returns O when read indicating that no host bus clock is required for the PCI4410 to 3 P
217. rtion of reset PRST or GRST which would require the reconfiguration of the PCI4410 by software Asserting the SUSPEND signal places the controller s PCI outputs in a high impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process GNT is asserted It is important that the PCI bus not be parked on the PCI4410 when SUSPEND is asserted because the outputs are in a high impedance state The GPIOs MFUNC signals and RI OUT signals are all active during SUSPEND unless they are disabled in the appropriate PCI4410 registers 3 8 6 Ring Indicate The RI OUT output is an important feature in power management allowing a system to go into a suspended mode and wake up on modem rings and other card events TI designed flexibility permits this signal to fit wide platform requirements RI OUT on the PCI4410 can be asserted under any of the following conditions e A 16 bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call e Apowered down CardBus card asserts CSTSCHG CBWAKE requesting system and interface wake up e A powered CardBus card asserts CSTSCHG from the insertion removal of cards or change in battery voltage levels Figure 3 18 shows various enable bits for the PCI4410 RI OUT function however it does not show the masking of CSC events See Table 3 7 for a detailed description of CSC interrupt masks and flags 3 21 PC Car
218. s 7 2 DDMA Page Register The DDMA page register sets the upper byte of the address of a DDMA transfer Details of the address represented by this register are explained in Section 7 1 DDMA Current Address Base Address Register gu 7 e s j 4 s 2 o Name o DDMApage Hye RW RW RW RW RW Rw RW RW pe e g p cec Sp ow Pt qn ol mm Register DDMA page Type Read Write Offset DDMA base address 02h Default 00h Size One byte 7 3 DDMA Current Count Base Count Register The DDMA current count base count register sets the total transfer count in bytes of a direct memory transfer Read transactions to this register indicate the current count of a direct memory transfer In the 8 bit transfer mode the count is decremented by 1 after each transfer and the count is decremented by 2 after each transfer in the 16 bit transfer mode prm pw pou ow Name DDMA current count base count Name DDMA current count base count EES EE EE EE EE EE a Register DDMA current count base count Type Read Write Offset DDMA base address 04h Default 0000h Size Two bytes 7 2 74 DDMA Command Register The DDMA command register enables and disables the DDMA controller Bit 2 DMAEN defaults to 0 enabling the DDMA controller All other bits are reserved See Table 7 2 for a complete description of the register contents gu 7 e 5 4 3 2 DDMA command Name Te
219. s 01h Byte 2 0 Word Address 02h Byte 1 0 Word Address 03h Byte 0 0 Word Address 04h RSVD Word Address 8 x n 1 Word Address 8 x n 1 1 Word Address 8 x n 1 2 Word Address 8 x n 1 3 Word Address 8 x n 1 4 RSVD RSVD Reference 1 Word Address 08h Word Address 8 x n Figure 3 14 EEPROM Data Format The byte at the EEPROM word address 00h must either contain a valid offset reference as listed in Table 3 6 or an end of list EOL indicator The EOL indicator is a byte value of FFh and indicates the end of the data to load from the EEPROM Only doubleword registers are loaded from the EEPROM and all bit fields must be considered when the EEPROM is programmed The serial EEPROM is addressed at slave address 1010000b by the PCI4410 All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address The serial EEPROM chip in the sample application circuit see Figure 3 8 assumes the 1010b high address nibble The lower three address bits are terminal inputs to the chip and the sample application shows these terminal inputs tied to GND When a valid offset reference is read four bytes are read from the EEPROM MSB first as illustrated in Figure 3 13 The address autoincrements after every byte transfer according to the doubleword read protocol Note that the word addresses align with the data format illustrated in Figure 3 14 The PCI4410 continues to load data from the ser
220. s changed 23 17 RSVD R Reserved Bits 23 17 return 0s when read CardBus clock control enable When bit 16 is set bit O CLKCTRL is enabled 16 CLKCTRLEN RAW O Clock control is disabled default 1 Clock control is enabled RSVD R Reserved Bits 15 1 return Os when read CardBus clock control This bit determines whether the CB CLKRUN protocol stops or slows the CB clock during idle states Bit 16 CLKCTRLEN enables this bit EET EA O Allows CB CLKRUN protocol to stop the CB clock default 1 Allows CB CLKRUN protocol to slow the CB clock by a factor of 16 6 8 7 Distributed DMA DDMA Registers The DMA base address programmable in PCI configuration space at offset 98h points to a 16 byte region in PCI VO space where the DDMA registers reside The names and locations of these registers are summarized in Table 7 1 These PCI4410 register definitions are identical in function but differ in location to the 8237 DMA controller The similarity between the register models retains some level of compatibility with legacy DMA and simplifies the translation required by the master DMA device when it forwards legacy DMA writes to DMA channels While the DMA register definitions are identical to those in the 8237 of the same name some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment In such cases the PCI4410 implements these obsolete register bits as read only nonfunctional bits The
221. s for extended periods may affect device reliability NOTES 1 Applies for external input and bidirectional buffers Vj gt Vc c does not apply to fail safe terminals PCI terminals are measured with respectto Vc cp instead of Voc PC Card terminals are measured with respect to Voc cp Miscellaneous signals are measured with respect to Vcc The limit specified applies for a dc condition Applies for external output and bidirectional buffers VO gt Voc does not apply to fail safe terminals PCI terminals are measured with respect to Vc cp instead of Voc PC Card terminals are measured with respect to Vc c cp Miscellaneous signals are measured with respect to Vcc The limit specified applies for a dc condition 10 2 Recommended Operating Conditions see Note 3 Vcc Core voltage Commercial V PCI VO clamp voltage ZV Port VO Commercial CCP voltage VCCCB VCCI PC Card VO clamp voltage Commercial 3 3 V PCI PC Card Vint High level input voltage PHY I F NEM EE CN TI 2a Vee V Fail safe 2 PCI PC Card Vict Low level input voltage PHY VF TIL Fail safe PCI PC Card Input voltage PHY I F TIL Fail safe PCI vof Output voltage PHY I F TIL Fail safe PCland PC Card 1 tt Input transition time tr and ty TTL and fail safe Operating ambient temperature range 0 25 70 0 Ta E t Applies to external inputs and bidirectional buffers without hysteresis t Miscellaneous terminals
222. s high byte RW R W R W R W R W R W R W Register ExCA VO window 0 end address high byte Offset CardBus socket address 80Bh ExCA offset OBh Register ExCA l O window 1 end address high byte Offset CardBus socket address 80Fh ExCA offset OFh Type Read write Default 00h Size One byte 5 13 5 13 ExCA Memory Windows 0 4 Start Address Low Byte Registers These registers contain the low byte of the 16 bit memory window start address for memory windows 0 1 2 3 and 4 The 8 bits of these registers correspond to bits A19 A12 of the start address to 7 6 8 4 s 2 1 90 Name ExCA memory windows 0 4 start address low Register ExCA memory window O start address low byte Offset CardBus socket address 810h ExCA offset 10h Register ExCA memory window 1 start address low byte Offset CardBus socket address 818h ExCA offset 18h Register ExCA memory window 2 start address low byte Offset CardBus socket address 820h ExCA offset 20h Register ExCA memory window 3 start address low byte Offset CardBus socket address 828h ExCA offset 28h Register ExCA memory window 4 start address low byte Offset CardBus socket address 830h ExCA offset 30h Type Read Write Default 00h Size One byte 5 14 ExCA Memory Windows 0 4 Start Address High Byte Registers These registers contain the high nibble of the 16 bit memory window start address for memory windows 0 1 2 3 and 4 The lower 4 bit
223. s of these registers correspond to bits A23 A20 of the start address In addition the memory window data width and wait states are set in this register See Table 5 11 for a complete description of the register contents 7 e s j 4 2 1 Name ExCA memory windows 0 4 start address high byte Hye RW RW RW RW RW RW RW RW Ba o N osp qo o4 O p xp deo p 09 Register ExCA memory window 0 start address high byte Offset CardBus socket address 811h ExCA offset 11h Register ExCA memory window 1 start address high byte Offset CardBus socket address 819h ExCA offset 19h Register ExCA memory window 2 start address high byte Offset CardBus socket address 821h ExCA offset 21h Register ExCA memory window 3 start address high byte Offset CardBus socket address 829h ExCA offset 29h Register ExCA memory window 4 start address high byte Offset CardBus socket address 831h ExCA offset 31h Type Read Write Default 00h Size One byte Table 5 11 ExCA Memory Windows 0 4 Start Address High Byte Registers SIGNAL TYPE FUNCTION Data size Bit 7 controls the memory window data width This bit is encoded as 7 DATASIZE R W 0 Window data width is 8 bits default 1 Window data width is 16 bits Zero wait state Bit 6 controls the memory window wait state for 8 and 16 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as
224. s used for target disconnects and is commonly asserted by target devices that do not Table 2 10 Multifunction and Miscellaneous Terminals NER DESCRIPTION Ger INTA 92 Vi3 O Parallel PCI interrupt INTA INTB 93 U13 O Parallel PCI interrupt INTB Lue sc 9 m2 o u o SUSPEND Ge PC Card socket activity LED indicator LED SKT provides an output indicating PC Card socket activity Multifunctionterminal 0 MFUNCO can be configured as parallel PCI interrupt INTA GPIO GPOO socket activity LED output ZV switching outputs CardBus audio PWM GPE or a parallel IRQ See Section 4 32 Multifunction Routing Register for configuration details Multifunction terminal 1 MFUNC1 can be configured as GPI1 GPO1 socket activity LED output ZV Switching outputs CardBus audio PWM GPE or a parallel IRQ See Section 4 32 Multifunction Routing Register for configuration details Serial data SDA When VCCDO and VCCD 1 are high after a PCI reset the MFUNC1 terminal provides the SDA signaling for the serial bus interface The two terminal serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset See Section 3 6 1 Serial Bus Interface Implementation for details on other serial bus applications Multifunction terminal 2 MFUNC2 can be configured as PC PCI DMA request GPI2 GPO2 ZV switching outputs CardBus audio PWM GPE RI OUT or a parallel IRQ See Section 4
225. sed for system and option card identification purposes and may be required for certain operating systems This register is read only or read write depending on the setting of bit5 SUBSYSRW in the system control register see Section 4 29 Bit ns tw vs T2 m 10 9 8 v j e js ja 3 2 1 Jj 0 Subsystem vendor ID Name Sub systemvendor ID me m Re eee ee eRe esti o oo eee e po o da e o o oo oe Register Subsystem vendor ID Type Read only Read Write if enabled by SUBSYSRW Offset 40h Default 0000h 4 27 Subsystem ID Register The subsystem ID register is used for system and option card identification purposes and may be required for certain operating systems This register is read only or read write depending on the setting of bit 5 SUBSYSRW in the system control register see Section 4 29 Bie EE ORE WE HE AE 59 s ENG PA AE ES Name Subsystem ID EE EEN fo fo fo fo Jo o jo o Jol Register Subsystem ID Type Read only Read Write if enabled by SUBSYSRW Offset 42h Default 0000h 4 28 PC Card 16 Bit VF Legacy Mode Base Address Register The PCI4410 supports the index data scheme of accessing the ExCA registers which is mapped by this register An address written to this register is the address for the index register and the address 1 is the data address Using this access method applications requiring index data ExCA access can be supported The base address can be mapped any
226. sing the DREQ signaling DREQ is selected through the socket DMA register 0 see Section 4 37 18 16 CDMACHAN MRBURSTDN 4 17 Table 4 6 System Control Register Continued SIGNAL TYPE FUNCTION Memory read burst enable upstream When bit 14 is set the PC14410 allows memory read transactions to burst upstream ii si SH O Upstream memory read burst is disabled default 1 Upstream memory read burst is enabled Socket activity status When set bit 13 indicates access has been performed to or from a PC card and is cleared upon read of this status bit o SOCACTIVE 0 No socket activity default 1 Socket activity RSVD R Reserved Bit 12 returns 1 when read Power stream in progress status bit When set bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested This bit is cleared when the power stream 11 PWRSTREAM is complete 0 Power stream is complete and delay has expired 1 Power stream is in progress Power up delay in progress status When set bit 9 indicates that a power up stream has been sent to 10 DELAYUP the power switch and proper power may not yet be stable This bit is cleared when the power up delay has expired Power down delay in progress status When set bit 10 indicates that a power down stream has been DELAYDOWN sent to the power switch and proper power may not yet be stable This bit is cleared when the power down delay has expired Interrogation in
227. software is responsible for either resetting the socket DMA controller or enabling the mask bit See Table 7 5 for a complete description of the register contents Br jT e 5 DDMA multichannel mask Name De n m m R M Rm pea o o o j o o o Register DDMA multichannel mask Type Read only Read Write Offset DDMA base address OFh Default 00h Size One byte Table 7 5 DDMA Multichannel Mask Register SIGNAL TYPE FUNCTION RSVD EN Reserved Bits 7 1 return Os when read Mask select Bit 0 masks incoming DREQ signals from the PC Card When set to 1 the socket ignores DMA MASKBIT R W requests from the card When cleared or reset to 0 incoming DREQ assertions are serviced normally 0 DDMA service provided on card DREQ 1 Socket DREQ signal ignored default 7 5 7 6 8 OHCI Lynx Controller Programming Model This section describes the internal registers used to program the link function including both PCI configuration registers and open HCl registers All registers are detailed in the same format A brief description is provided for each register followed by the register offset and a bit table describing the reset state for each register A bit description table is typically included that indicates bit signal names a detailed field description and field access tags Table 8 1 describes the field access tags Table 8 1 Bit Field Access Tag Descriptions ACCESS TAG N
228. stem error CSERR reports address parity errors and other system errors that could lead GSERR 181 B10 to catastrophic results CSERR is driven by the card synchronous to CCLK but deasserted by a weak pullup and may take several CCLK periods The PCI4410 can report CSERR to the system by assertion of SERR on the PCI interface CardBus stop CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus CSTOP 153 E18 l O transaction CSTOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers CardBus status change CSTSCHG alerts the system to a change in the card s status and is used as CardBus target ready CTRDY indicates the CardBus target s ability to complete the current data phase CTRDY 157 A16 VO of the transaction A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted until this time wait states are inserted CVS1 179 F11 CardBus voltage sense 1 and CardBus voltage sense 2 CVS1 and CVS2 are used in conjunction with CVs 165 E13 VO CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type 2 20 TERMINAL PHY CTL1 PHY CTLO PHY DATA7 PHY DATA6 PHY DATAS PHY DATA4 PHY DATAS PHY DATA2 PHY DATA1 PHY DATAO PHY LREQ LINKON 194 TERMINAL ZV HREF ZV VSYNC ZV SDATA NUMBER Pov GHK 95 8 9 Table 2 16 IEEE1394 PHY
229. ster ExCA Card Status Change Register ExCA Card Status Change Interrupt Configuration Register ExCA Address Window Enable Register se ee se ee ee ExCA VO Window Control Register EXCA VO Windows 0 and 1 Start Address Low Byte Registers EXCA VO Windows 0 and 1 Start Address High Byte Registers EXCA VO Windows 0 and 1 End Address Low Byte Registers ExCA VO Windows 0 and 1 End Address High Byte Registers ExCA Memory Windows 0 4 Start Address Low Byte Registers ExCA Memory Windows 0 4 Start Address High Byte Registers ExCA Memory Windows 0 4 End Address Low Byte Registers ExCA Memory Windows 0 4 End Address High Byte Registers ExCA Memory Windows 0 4 Offset Address Low Byte Registers ExCA Memory Windows 0 4 Offset Address High Byte Registers ExCA VO Windows 0 and 1 Offset Address Low Byte Registers ExCA VO Windows 0 and 1 Offset Address High Byte Registers ExCA Card Detect and General Control Register ExCA Global Control Register ii ss ee ke ee ee se eee ExCA Memory Windows 0 4 Page Register 6 CardBus Socket Register vi 6 1 Socket Event REGIS BRESSLER KAAR RE DR ag BA AKA 6 2 6 2 Socket Mask REISTE uirtute Tire usted Eg b Dac hdi 6 3 6 3 Socket Present State Register 6 4 6 4 Socket Force Event Register iis a 6 6 6 5 Sockel Control Register iss ese patr RR E RR RE Ed 6 7 6 6
230. ster Socket mask Type Read only Read Write Offset CardBus socket address 04h Default 0000 0000h Table 6 3 Socket Mask Register SIGNAL TYPE FUNCTION RSVD R Reserved Bits 31 4 return Os when read Power cycle Bit 3 masks bit 3 PWRCYCLE in the socket present state register see Section 6 3 from causing a status change interrupt 3 PAM SE TUNE 0 PWRCYCLE event does not cause CSC interrupt default 1 PWRCYCLE event causes CSC interrupt Card detect mask Bits 2 and 1 mask bits 1 and 2 CDETECT1 and CDETECT2 in the socket present state register see Section 6 3 from causing a CSC interrupt 00 Insertion removal does not cause CSC interrupt default eal CDMASK Y 01 Reserved undefined 10 Reserved undefined 11 Insertion removal causes CSC interrupt CSTSCHG mask Bit 0 masks bit 0 CARDSTS in the socket present state register see Section 6 3 from causing a CSC interrupt DOTSNINGIS RH 0 CARDSTS event does not cause CSC interrupt default 1 CARDSTS event causes CSC interrupt 6 3 6 3 Socket Present State Register The socket present state register reports information about the socket interface Write transactions to the socket force event register see Section 6 4 are reflected here as well as general socket interface status Information about PC Card Vcc support and card type is only updated at each insertion Also note that the PCI4410 uses CCD1 and CCD2 during card identification
231. ster offset 50h 54h see Section 9 16 is set to 1 See Table 8 18 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Link enhancement control Type R R R R RJ RJR R R R RJ R RR R R Petan 0 o o fo fo fo foto fo o o 0 0 opo o et 15 14 13 i2 0 00 9 8 7 te Pe ad s3 2 tao Name timkenhancementeontro O Type R R Rw Rw R R Rw Rw Rw R R R R RW RW R peau o o of 1 0o fo fo o o fo 10 fo fo fo fo o Register Link enhancement control Type Read only Read Write Offset F4h Default 0000 1000h Table 8 18 Link Enhancement Control Register FUNCTION Reserved These bits return O when read This bit field sets the initial AT threshold value which is used until the AT FIFO is underrun When PC14410 retries the packet it uses a 2K byte threshold resulting in store and forward operation 00 Threshold 2 Kbytes resulting in store and forward operation 01 Threshold 1 7 Kbytes default 10 Threshold 1 K 11 Threshold 512 bytes Reserved This bit returns 0 when read Enable audio music CIP timestamp enhancement When this bit is set to 1 the enhancement is enabled for audio music CIP transmit streams FMT 10h Enable DV CIP timestamp enhancement When this bit is set to 1 the enhancement is enabled for DV CIP transmit streams FMT 00h
232. system interrupts Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections When an interrupt is signaled by the PCI4410 the interrupt service routine must determine which of the events listed in Table 3 7 caused the interrupt Internal registers in the PCI4410 provide flags that report the source of an interrupt By reading these status bits the interrupt service routine can determine the action to be taken Table 3 7 details the registers and bits associated with masking and reporting potential interrupts All interrupts can be masked except the functional PC Card interrupts and an interrupt status flag is available for all types of interrupts Notice that there is not a mask bit to stop the PCI4410 from passing PC Card functional interrupts through to the appropriate interrupt scheme These interrupts are not valid until the card is properly powered and there should never be a card interrupt that does not require service after proper initialization Table 3 7 lists the various methods of clearing the interrupt flag bits The flag bits in the ExCA registers 16 bit PC Card related interrupt flags can be cleared using two different methods One method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register The selection of flag bit clearing is made by bit 2 IFCMODE in the ExCA global control register see Section 5 22 located at
233. t context by setting the ContextControl run bit to 1 The n value in the following register addresses indicates the context number n 0 1 2 3 E EM 28 27 26 25 21 20 19 18 17 16 Isochronous ad context KHEN ene Et Isochronous transmit context command pointer BEE EE RENE Type R R R RJ R R RI RI RR RI ER RI RI RYE pea x x x x x x x Px tx txt xt xt x txt x x Register Isochronous transmit context command pointer Type Read only Offset 20Ch 16 n Default XXXX XXXh 9 36 9 41 Isochronous Receive Context Control Register This set clear register controls options state and status for the isochronous receive DMA contexts The n value in the following register addresses indicates the context number n 0 1 2 3 See Table 9 31 for a complete description of the register contents Bit 31 so 28 28 27 26 25 2a 23 22 21 20 19 18 t7 16 Isochronous receive context control RSC RSCU RSC R we ascu a A mu mu mo n n su Ru Ro AU AU AU AU AU Der o o fo x 9 9 o 9 X TOC 1 LX EX TX 1 12 Register Isochronous receive context control Type Read Set Clear Update Read Set Clear Read Update Read only Offset 400h 32 n set register 404h 32 n clear register Default X000 X0XXh Table 9 31 Isochronous Receive Context Control Register SIGNAL TYPE FUNCTION When set to 1
234. te Offset 38h Default XXXX XXXXh Table 9 9 Posted Write Address Low Register BIT SIGNAL TYPE FUNCTION OFFSETLO The lower 32 bits of the 1394 destination offset of the write request that failed 9 14 Posted Write Address High Register This register is used to communicate error information if a write requestis posted and an error occurs while the posted data packet is being written See Table 9 10 for a complete description of the register contents m IsIeIsIsSIZISISI ISIZISISISISITI Name Eiere Dean x x x x x x x x x i ENE DERE E AE m uos es fe 2 4 a Posted write address high peau x x X x X x x x x x x x x Xx tx xs Register Posted write address high Type Read Update Offset 3Ch Default XXXX XXXXh Table 9 10 Posted Write Address High Register SIGNAL TYPE FUNCTION 31 16 SOURCEID This bus and node number of the node that issued the write request that failed OFFSETHI The upper 16 bits of the 1394 destination offset of the write request that failed 9 15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor unique registers The PCI4410 does not implement Texas Instruments unique behavior with regards to open HCI Thus this register is read only and returns Os when read ets 0 lan s 94 lere sek ese Ne a T UNIES NOME ON ESE SE SE SE DEE SEE ENE Lo 15191919159 191919 19 L9 L9 T9 e
235. tect 2 CD1 and CD2 are internally connected to ground on the PC Card When a PC Card is inserted into a socket CD1 and CD2 are pulled low For signal status see Section 5 2 ExCA Interface Status Register CE1 136 J14 Card enable 1 and card enable 2 CE1 and CE2 enable even and odd numbered address bytes CE1 CE2 139 H18 enables even numbered address bytes and CE2 enables odd numbered address bytes Input acknowledge INPACK is asserted by the PC Card when it can respond to an VO read cycle at the current address INPACK 171 E12 DMA request INPACK can be used as the DMA request signal during DMA operations from a 16 bit PC Card that supports DMA If it is used as a strobe then the PC Card asserts this signal to indicate a request for a DMA operation VO read IORD is asserted by the PCI4410 to enable 16 bit VO PC Card data output during host VO read cycles DMA write IORD is used as the DMA write strobe during DMA operations from a 16 bit PC Card that supports DMA The PCI4410 asserts IORD during DMA transfers from the PC Card to host memory je e VO write IOWR is driven low by the PCI4410 to strobe write data into 16 bit VO PC Cards during host Es VO write cycles IOWR 144 G18 E l l l DMA read IOWR is used as the DMA write strobe during DMA operations from a 16 bit PC Card that supports DMA The PCIA410 asserts IOWR during transfers from host memory to the PC Card m fefee Output enable OE is driven low by the PC14410 to enab
236. that node are handled through the physical request context If set to 1 for local bus node number 61 then physical requests received by the PC14410 PHYSREQRESOURCE61 RSC from that node are handled through the physical request context If set to 1 for local bus node number 60 then physical requests received by the PC14410 PrHYSREQRESOURCEGO Her from that node are handled through the physical request context If set to 1 for local bus node number 59 then physical requests received by the PCI4410 PHYSREQRESOURCE59 RSC from that node are handled through the physical request context If set to 1 for local bus node number 58 then physical requests received by the PCI4410 RE RSC from that node are handled through the physical request context If set to 1 for local bus node number 57 then physical requests received by the PC14410 PHYSREQRESOURCE57 RSC from that node are handled through the physical request context If set to 1 for local bus node number 56 then physical requests received by the PC14410 PHYSREQRESOURCES6 RSG from that node are handled through the physical request context If set to 1 for local bus node number 55 then physical requests received by the PC14410 PHYSREGBESQUHBGESS RSC from that node are handled through the physical request context If set to 1 for local bus node number 54 then physical requests received by the PCI4410 EE AR d RSG from that node are handled through the physical request cont
237. tion revision 1 1 implementation Note See power management capability register PCI offset A2h Section 4 41 VERSION bits 2 0 for additional information CardBus reserved terminals signaling When a CardBus card is inserted and bit 22 is set the RSVD CardBus terminals are driven low When this bit is 0 these signals are placed in a high impedance state 0 3 state CardBus RSVD 1 Drive Cardbus RSVD low default 22 CBRSVD Vcc protection enable 0 Vcc protection enabled for 16 bit cards default 2 VCCPROT R W 1 Vcc protection disabled for 16 bit cards Reduced zoomed video enable When this bit is enabled pins A25 A22 of the card interface for PC Card 16 cards are placed in the high impedance state This bit should not be set for normal ZV operation 2 REDUCEZV RAW This bit is encoded as O Reduced zoomed video disabled default 1 Reduced zoomed video enabled 0 Ignore DREQ signaling from PC Cards default 1 Signal DMA request on DREQ PC PCI DMA channel assignment Bits 18 16 are encoded as 0 3 8 bit DMA channels 4 PCI master not used default 5 7 16 bit DMA channels Memory read burst enable downstream When bit 15 is set memory read transactions are allowed to burst downstream O Downstream memory read burst is disabled 1 Downstream memory read burst is enabled default 1 0 PC PCI DMA card enable When bit 19 is set the PCI4410 allows 16 bit PC Cards to request PC PCI 19 CDREQEN DMA u
238. tions and new registers have been defined where required 3 15 The PCIA4410 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols To simplify the discussion of interrupts in the PCI4410 PC Card interrupts are classified as either card status change CSC or as functional interrupts The method by which any type of PCI4410 interrupt is communicated to the host interrupt controller varies from System to system The PCI4410 offers system designers the choice of using parallel PCI interrupt signaling parallel ISA type IRQ interrupt signaling or the IRQSER serialized ISA and or PCI interrupt protocol It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs as detailed in the sections that follow All interrupt signaling is provided through the seven multifunction terminals MFUNCO MFUNCS In addition PCI interrupts INTA and INTB are available on dedicated pins 3 7 1 PC Card Functional and Card Status Change Interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially defined signals on the PC Card interface Functional interrupts are generated by 16 bit VO PC Cards and by CardBus PC Cards Card status change CSC type interrupts are defined as events at the PC Card interface that are detected by the PC
239. tmask OO O O O vee LC TS A ascu Rscu Rscu Rscu ascu Rscu Rscu ascu A Rscu asou pem o x o 9 9 x X x X X x LX Lx L9 Lx Lx et 15 14 fs 2 0 0 o e 7 6 5 1a 3 12 10 Name Interrupt mask Tee R R R A A A eso ssco RU ru nscu scu ascu Jasco scu nscu em S RES CC RE de ele GC Register Interrupt mask Type Read Set Clear Update Read only Offset 88h set register 8Ch clear register Default XXXX 0XXXh Table 9 16 Interrupt Mask Register Bm SIGNAL TYPE FUNCTION When this bitis set to 1 external interrupts are generated in accordance with the IntMask register ES Mi DE ER EE meo If this bit is reset to O no external interrupts are generated 900 To Se Table 9 15 9 19 9 23 Isochronous Transmit Interrupt Event Register This set clear register reflects the interrupt state of the isochronous transmit contexts An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT LAST command completes and its interrupt bits are setto 1 Upon determining that the IntEvent isochTx interrupt has occurred software can check this register to determine which context s caused the interrupt The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register The only mechanism to reset the bits in this register to 0 is to write a 1 to the corresponding bit in the clea
240. to 1 for local bus node number 0 asynchronous requests received by the PC14410 from ASYNREQRESOURCEOQ that node are accepted 9 29 9 34 Physical Request Filter High Register This set clear register is used to enable physical receive requests on a per node basis and handles the upper node IDs When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers then the comparison is done again with this register If the bit corresponding to the node ID is not set to 1 in this register then the request is handled by the ARRQ context instead of the physical request context See Table 9 26 for a complete description of the register contents Bt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Physical request filter high peut o o o of of of of oP of o fof of of of of et 15 14 13 12 ft v0 9 j ae 7 j e s J 8 j 2 1 0 me Eieren Dean o o o o j o j o j o j o of o j o jo jo op oj o Register Physical request filter high Type Read Set Clear Offset 110h set register 114h clear register Default 0000 0000h Table 9 26 Physical Request Filter High Register SIGNAL TYPE FUNCTION PHYSREQALLBUSSES RSC e all asynchronous requests received by the PCI4410 from nonlocal bus nodes If set to 1 for local bus node number 62 then physical requests received by the PCI4410 Pi SME ORESQURCEQE RSG from
241. to support only complete bus locks using the LOCK protocol In this scenario the arbiter will not grant the bus to any other agent other than the LOCK master while LOCK is asserted A complete bus lock may have a significant impact on the performance of the video The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress The PCI4410 supports all LOCK protocol associated with PCI to PCI bridges as also defined for PCI to CardBus bridges This includes disabling write posting while a locked operation is in progress which can solve a potential 3 2 deadlock when using devices such as PCI to PCI bridges The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read This target characteristic is prohibited by the PCI Local Bus Specification and the issue is resolved by the PCI master using LOCK 3 4 2 Loading Subsystem Identification The subsystem vendor ID register see Section 4 26 and subsystem ID register see Section 4 27 make up a doubleword of PCI configuration space located at offset 40h for functions O and 1 This doubleword register is used for system and option card mobile dock identification purposes and is required by some operating systems Implementation of this unique identifier register is a PC 99 requirement The PCI4
242. tribution of interrupts signaled on the four PCI interrupt slots Bits 31 and 30 are global to all PCI4410 functions 31 30 SER STEP R W 00 INTA INTB signal in INTA INTB slots default 01 INTA INTB signal in INTB INTC slots 10 INTA INTB signal in INTC INTD slots 11 INTA INTB signal in INTD INTA slots TIE INTB INTA Tie INTB to INTA When bit 29 is set to 1 INTB is tied to INTA default is 0 DIAGNOSTIC TI diagnostic IC Test bit default is 0 Internal oscillator enable 27 OSEN R W O Internal oscillator disabled default 1 Internal oscillator enabled SMI interrupt routing Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket 26 ME PME O PC Card power change interrupts routed to IRQ2 default 1 A CSC interrupt is generated on PC Card power changes SMI interrupt status This bit is set when bit 24 SMIENB is set and a write occurs to set the socket power Writing a 1 to bit 25 clears the status eo NUS MA RG 0 SMI interrupt signaled default 1 SMI interrupt not signaled SMI interrupt mode enable When bit 24 is set and a write to the socket power control occurs the SMI 24 SMIENB RW uci interrupt signaling is enabled and generates an interrupt PCI Bus Power Management Interface Specification revision 1 1 enable 0 Use PCI Bus Power Management Interface Specification revision 1 0 implementation default PCIPMEN 1 Use PCI Bus Power Management Interface Specifica
243. try has expired RSVD R Reserved Bit 2 returns 0 when read PCI target retry expired Write a 1 to clear bit 1 1 TEXP PCI R C 0 Inactive default 1 Retry has expired o RSVD R Reserved Bit 0 returns 0 when read 4 21 4 34 Card Control Register The card control register is provided for PCI1130 compatibility RI OUT is enabled through this register See Table 4 11 for a complete description of the register contents gu 7 6 5 4 3 2 1 0 Name Card control we w w w er A AW AW AC Register Card conirol Type Read only Read Write Read Write to Clear Offset 91h Default 00h Table 4 11 Card Control Register Ring indicate output enable 7 RIENB RAW 0 Disables any routing of RI OUT signal default 1 Enables RI OUT signal for routing to the RI OUT PME terminal when bit 0 RIMUX in the System control register see Section 4 29 is set to 0 and for routing to MFUNC2 or MFUNCA Compatibility ZV mode enable When set the PC Card socket interface ZV terminals enter a EX MNE high impedance state This bit defaults to 0 ZV output port enable When bit 5 is set the ZV output port is enabled If bit 6 ZVENABLE is set then ZV ZN data from the PC Card interface is routed to the ZV output port Otherwise the ZV output port drives 5 port ENABLE DIN la stable 0 pattern on all pins When bit 5 is not set the ZV output port pins are placed in a high impedance state
244. ts of a PHY register which has been read 15 RDREG RWU This bit is set to 1 by software to initiate a read request to a PHY register and is cleared by hardware when the request has been sent The wrReg and rdReg bits must be used exclusively This bit is set to 1 by software to initiate a write request to a PHY register and is reset to 0 by hardware when the request has been sent The wrReg and rdReg bits must be used exclusively 13 12 RSVD R Reserved Bits 13 and 12 return 0 when read REGADDR R W This field is the address of the PHY register to be written or read 7 0 WRDATA R W This field is the data to be written to a PHY register and is ignored for reads WRREG 9 25 9 31 Isochronous Cycle Timer Register This read write register indicates the current cycle number and offset When the PCI4410 is cycle master this register is transmitted with the cycle start message When the PCI4410 is not cycle master this register is loaded with the data field in an incoming cycle start In the event that the cycle start message is not received the fields can continue incrementing on their own if programmed to maintain a local time reference See Table 9 23 for a complete description of the register contents Bit 31 3o 29 28 27 26 25 2a 23 22 zt 20 19 18 17 16 Isochronous cycle timer Ca T 7 Isochronous cycle timer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
245. tus register offset A4h see Section 4 42 enables control of power management states and enables monitors power management events The data register is an optional register that can provide dynamic data For more information on PCI power management see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges 3 8 8 CardBus Bridge Power Management The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in December of 1997 This specification follows the device and bus state definitions provided in the PC Bus Power Management Interface Specification published by the PCI Special Interest Group SIG The main issue addressed inthe PCI Bus Power Management Interface Specification for PClto CardBus Bridges is wake up from D3pot or D3coid without losing wake up context also called PME context The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges for D3 wake up are as follows e Preservation of device context The specification states that a reset must occur when transitioning from D3 to DO Some method to preserve wake up context must be implemented so that the reset does not clear the PME context registers e Power source in D3cold if wake up support is required from this state The Texas Instruments PCI4410 addresses these D3 wake up issues in the following manner e Two resets are provided to handle preservation
246. up and identifies the manufacturer of the PCI device The vendor ID assigned to TI is 104Ch OE AE SE AE AE RNAAK AU AK AE AGE RE AE v0 Vendor ID Name Penton EE EE EE EE EE EE EE EE Lo o o EE AE OH REM 39 g t og poe BEA AG BE N Register Vendor ID Type Read only Offset 00h Default 104Ch 4 3 Device ID Register This 16 bit register contains a value assigned to the PCI4410 by TI The device identification for the PCIA410 is AC41h Bit 15 14 13 r2 vt 10 9 8 v e j s ja da 2 1 jo Device ID Name vice Te n R R RJ JR RJ JRJ R R R RJ R R RJ R JR pem 1 Jo fs To s a be To Joe Ti To To To o To Register Device ID Type Read only Offset 02h Default AC41h 4 2 4 4 Command Register The command register provides control over the PCI4410 interface to the PCI bus All bit functions adhere to the definitions in PCI Local Bus Specification See Table 4 2 for the complete description of the register contents Bit ns um vs m2 m 10 9 8 v je 5 4 3 2 1 o0 Name Command Command Type R R R rR rR JR n aw R JRW RW B Raw Rw rw eut o o o o fo fo fo foto 10 ofofofofo to Register Command Type Read only Read Write Offset 04h Default 0000h Table 4 2 Command Register SIGNAL TYPE FUNCTION 15 10 RSVD R Reserved Bits 15 10 return Os when read FBB EN Fast back to back enable The PCI4410 does not g
247. us offset 10h bits 6 4 2 0 Global reset places all registers in their default state regardless of the state of the PME enable bit The GRST signal is gated only by the SUSPEND signal This means that assertion of SUSPEND blocks the GRST signal internally thus preserving all register contents The registers cleared by GRST are Subsystem ID subsystem vendor ID PCI offset 40h bits 31 0 PC Card 16 bit legacy mode base address register PCI offset 44h bits 31 1 System control register PCI offset 80h bits 31 24 22 14 6 3 1 0 General status register PCI offset 85h bits 2 0 General control register PCI offset 86h bits 3 1 0 Multifunction routing register PCI offset 8Ch bits 27 0 Retry status register PCI offset 90h bits 7 6 3 1 Card control register PCI offset 91h bits 7 5 2 0 Device control register PCI offset 92h bits 7 0 Diagnostic register PCI offset 93h bits 7 0 Socket DMA register 0 PCI offset 94h bits 1 0 Socket DMA register 1 PCI offset 98h bits 15 4 2 0 Power management capabilities register PCI offset A2h bit 15 General purpose event enable register PCI offset AAh bits 15 11 8 4 0 General purpose output register PCI offset AEh bits 4 0 PCI miscellaneous configuration register OHCI function PCI offset FOh bits 15 13 10 2 0 Link enhancements register OHCI function PCI offset F4h bits 13 12 9 7 2 1 GPIO control register OHCI function PCI offset FC
248. uted to PCI interrupts default 1 Functional interrupts routed to IRQ interrupts CardBus reset When bit 6 is set CRST is asserted on the CardBus interface CRST can also be asserted RW by passing a PRST assertion to CardBus 0 CRST deasserted 1 CRST asserted default W Master abort mode Bit 5 controls how the PC14410 responds to a master abort when the PCI4410 is an initiator on the CardBus interface 0 Master aborts not signaled default 1 Signal target abort on PCI Signal SERR if enabled Reserved Bit 4 returns 0 when read VGA enable Bit 3 affects how the PCI4410 responds to VGA addresses When this bit is set accesses to VGA addresses are forwarded ISA mode enable Bit 2 affects how the PCI4410 passes VO cycles within the 64 Kbyte ISA range This bitis not common between sockets When this bit is set the PCI4410 does not forward the last 768 bytes of each 1K VO range to CardBus MABTMODE A RSVD Co VGAEN ISAEN CSERR enable Bit 1 controls the response of the PCI4410 to CSERR signals on the CardBus bus 0 CSERR is not forwarded to PCI SERR 1 CSERR is forwarded to PCI SERR ES CardBus parity error response enable Bit 0 controls the response of the PCI4410 to CardBus parity errors R CSERREN CPERREN 0 CardBus parity errors are ignored 1 CardBus parity errors are reported using CPERR ER ER 4 26 Subsystem Vendor ID Register The subsystem vendor ID register is u
249. ved Bits 15 0 return Os when read 9 5 9 3 Asynchronous Transmit Retries Register This register indicates the number of times the PCI4410 will attempt a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit See Table 9 4 for a complete description of the register contents Bit 31 30 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 Asynchronous transmit retries Asynchronous transmit retries Do Asynchronous tranemitretries EE EE EE ER EG BIT SIGNAL TYPE FUNCTION The second limit field returns 0 when read because outbound dual phase retry is not 31 29 SECONDLIMIT EN implemented 28 16 CYCLELIMIT The cycle limit field returns 0 when read because outbound dual phase retry is not imple mented 15 12 RSVD R Reserved Bits 15 12 return 0 when read Register Asynchronous transmit retries Type Read only Read Write Offset 08h Default 0000 0000h Table 9 4 Asynchronous Transmit Retries Register R W The MAXPHYSRESPRETRIES field tells the physical response unit how many times to MAXPHYSRESPRETRIES attemptto retry the transmit operation for the response packet when a busy acknowledge or ack data error is received from the target node R W The MAXATRESPRETRIES field tells the asynchronous transmit response unit how many MAXATRESPRETRIES times to attempt to retry the transmit operation for the response packet when a busy ac know
250. vides information on the current status of the PC Card interface An X in the default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface See Table 5 3 for a complete description of the register contents pr J rv 6 p w s p 9 p v p ww N Name ExCA interface status EE me R R R R j R R R R petan o0 o x x x x x x Register ExCA interface status Type Read only Offset CardBus socket address 801h ExCA offset 01h Default 00XX XXXXb Table 5 3 ExCA Interface Status Register SIGNAL TYPE FUNCTION RSVD R Reserved Bit 7 returns 0 when read Card Power Bit 6 indicates the current power status of the PC Card socket This bit reflects how the ExCA power control register see Section 5 3 is programmed Bit 6 is encoded as 0 Vcc and Vpp to the socket turned off default 1 Vcc and Vpp to the socket turned on Ready Bit 5 indicates the current status of the READY signal at the PC Card interface O PC Card not ready for data transfer 1 PC Card ready for data transfer CARDPWR READY CARDWP Card write protect Bit 4 indicates the current status of WP at the PC Card interface This signal reports to the PCI4410 whether or not the memory card is write protected Furthermore write protection for an entire PCI4410 16 bit memory window is available by setting the appropriate bit in the EXCA memory window offset address
251. where in 32 bit VO space on a word boundary hence bit 0 is read only returning 1 when read See Section 5 ExCA Compatibility Registers for register offsets a Tar 80 29 28 27 26 25 20 25 22 01 20 49 48 4718 Ca TY O O mea o o o o o o o fofo o fofo po m fos 54 slee ele 1715151213 12 1231 Name PGGadi biFigeymodebaseaddes O O O OOOO U OOO E Pa LUN RR Fo o o o o lolo o o 19159191919 jo Tr Register PC Card 16 bit VF legacy mode base address Type Read only Read Write Offset 44h Default 0000 0001h 4 15 4 29 System Control Register System level initializations are performed through programming this doubleword register See Table 4 6 for a complete description of the register contents 29 28 27 26 25 24 23 22 21 z0 19 te i7 16 System control Name Seme ope Row Rw Rw Rw AM LAW mo mw mw mw mw mw mw nw mw A Default 0 System control Name Type Rw Aw A R R RB R J R Rw Rw AW rw RW AW Rw rw pea o f o rjojo o o o t o ol o o o j Register System control Type Read only Read Write Read Write to Clear Offset 80h Default 0044 9060h Table 4 6 System Control Register SIGNAL TYPE FUNCTION Serialized PCI interrupt routing step Bits 31 and 30 configure the serialized PCI interrupt stream signaling and accomplish an even dis
252. xCA register set Bits 31 12 are read write and allow the base address to be located anywhere in the 32 bit PCI memory address space on a 4 Kbyte boundary Bits 11 0 are read only returning Os when read When software writes all 1s to this register the value read back is FFFF FOOOh indicating that at least 4K bytes of memory address space are required The CardBus registers start at offset 000h and the memory mapped ExCA registers begin at offset 800h LE SE ARKA KABA OE BEK AE Ee eee Name ENE TE we aw aw aw Aw aw Paw aw aw aw Rw AW T ea ps s s Ls L5 L9 L9 L5 fo L9 GEE Pa fo fe 0 7 e s Name CardBus socket ExCA EE ENE EE AE fo fo fo fo fo fo Register CardBus socket ExCA base address Type Read only Read Write Offset 10h Default 0000 0000h 4 13 Capability Pointer Register The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides PCI header doublewords at AOh and A4h provide the power management PM registers The Socket has its own capability pointer register This register returns AOh when read Bit UNUS PT EE EE QUEUE N NE CONI GEK GN E Name Capability pointer mwe R R j R R R R R J R pea o o o o o o j Register Capability pointer Type Read only Offset 14h Default AOh 4 14 Secondary Status Register The secondary status register is compatible with the PCl to
253. y cards Furthermore card insertion and removal type CSC interrupts are independent of the card type Table 3 8 describes the PC Card interrupt events Table 3 8 PC Card Interrupt Events and Description CARD TYPE EVENT TYPE SIGNAL DESCRIPTION BVD1 STSCHG CSTSCHG A transition on BVD1 indicates a change in the Battery conditions PC Card battery conditions bi BVD1 BVD2 GEN iti indi i 16 bit BVD2 SPKR CAUDIO A transition on BVD2 indicates a change in the memory PC Card battery conditions Wait states ee A transition on READY indicates a change in the ability READY READY IREQ WCINT of the memory PC Card to accept or provide data Change in card The assertion of STSCHG indicates a status change status STSCHG BVD1 STSCHG CSTSCHG on the PC Card 16 bit VO Interrupt request EES The assertion of IREO indicates an interrupt reguest IREQ READY IREQ CINT from the PC Card Change in card The assertion of CSTSCHG indicates a status change status CSTSCHG oso ST STSCHG EE on the PC Card CardBus Interrupt request e The assertion of CINT indicates an interrupt request CINT READY REQUCINT gom the PC Card Gard inseition CDT CCDI A transition on either CD1 CCD1 or CD2 CCD2 CSC UA indicates an insertion or removal of a 16 bit or CardBus or removal CD2 CCD2 All PC Cards PC Card Power cycle An interrupt is generated when a PC Card power up CSC N A complete cycle has completed The naming convention for P
254. y windows 0 4 offset address high byte R W R W R W R W R W R W R W Register ExCA memory window 0 offset address high byte Offset CardBus socket address 815h ExCA offset 15h Register ExCA memory window 1 offset address high byte Offset CardBus socket address 81Dh ExCA offset 1Dh Register ExCA memory window 2 offset address high byte Offset CardBus socket address 825h ExCA offset 25h Register ExCA memory window 3 offset address high byte Offset CardBus socket address 82Dh ExCA offset 2Dh Register ExCA memory window 4 offset address high byte Offset CardBus socket address 835h ExCA offset 35h Type Read Write Default 00h Size One byte Table 5 13 ExCA Memory Windows 0 4 Offset Address High Byte Registers SIGNAL TYPE FUNCTION Write protect Bit 7 specifies whether write operations to this memory window are enabled This bit is encoded as O Write operations are allowed default 1 Write operations are not allowed as 0 Memory window is mapped to common memory default 1 Memory window is mapped to card attribute memory Offset address high byte Bits 5 0 represent the upper address bits A25 A20 of the memory window offset address Bit 6 specifies whether this memory window is mapped to card attribute or common memory This bit is encoded 5 19 5 19 ExCA VO Windows 0 and 1 Offset Address Low Byte Registers These registers contain the low byte of the 16 bit VO window offset a
255. ystem that can carry SPKR or CAUDIO through the PCI4410 from the PC Card interface SPKROUT is driven as the exclusive OR combination of card SPKR CAUDIO inputs Suspend SUSPEND protects the internal registers from clearing when the GRST or PRST signal is asserted See Section 3 8 4 Suspend Mode for details 2 15 TERMINAL ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDRO DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATAS DATA4 DATAS DATA2 DATA1 DATAO Table 2 11 16 Bit PC Card Address and Data Terminals r NN PC Card address 16 bit PC Card address lines ADDR25 is the most significant bit PC Card data 16 bit PC Card data lines DATA15 is the most significant bit Table 2 12 16 Bit PC Card Interface Control Terminals WT DESCRIPTION Battery voltage detect 1 BVD1 is generated by 16 bit memory PC Cards that include batteries BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card Both DVD and BVD2 are high when the battery is good When BVD2 is low and BVD1 is high the battery is weak and should be replaced When BVD1 is low the battery is no longer serviceable and the data in the BVD1 memory PC Card is lost See Section 5 6 ExCA Card Status Change Interrupt Configuration STSCHG RI Register f
256. z amp 18OCIBB52PD f TES TEXAS INSTRUMENTS PCI4410 GHK PDV PC Card and OHCI Controller Data Manual 2000 PCIBus Solutions da TEXAS INSTRUMENTS Printed in U S A 01 00 SCPS052 PCI4410 GHK PDV Data Manual PC Card and OHCI Controller Literature Number SCPS052 January 2000 P TEXAS INSTRUMENTS IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products orto discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR P

TEXAS INSTRUMENTS PCI4410 GHK/PDV handbook

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