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TEXAS INSTRUMENTS PCI1211 GGU/PGE PC CARD CONTROLLERS handbook

1. ring indicate enable Bit 7 enables the ring indicate function of BVD1 RI This bit is encoded as RINGEN 0 Ring indicate disabled default 1 Ring indicate enabled RESET CARDTYPE Card reset Bit 6 controls the 16 bit PC Card RESET and allows host software to force a card reset Bit 6 CSCROUTE affects 16 bit cards only This bit is encoded as INTSELECT 0 RESET signal asserted default 1 RESET signal deasserted Card type Bit 5 indicates the PC card type This bit is encoded as 0 Memory PC Card installed default 1 I O PC Card installed PCI Interrupt CSC routing enable bit When bit 4 is set high the card status change interrupts are routed to PCl interrupts When low the card status change interrupts are routed using bits 7 4 in the card status change interrupt configuration register This bit is encoded as 0 CSC interrupts are routed by ExCA registers default 1 CSC interrupts are routed to PCI interrupts Card interrupt select for I O Card functional interrupts Bits 3 0 select the interrupt routing for I O PC Card functional interrupts This field is encoded as 0000 No interrupt routing default CSC interrupts routed to PCI interrupts This bit setting is OR ed with ExCA bit 4 for backwards compatibility 0001 IRQ1 enabled 0010 SMI enabled 0011 IRQ3 enabled 0100 IRQ4 enabled 0101 IRQ5 enabled 0100 IRQ6 enabled 0111 IRQ7 enabled 1000 IRQ8
2. The Card standard describes the power up sequence that must be followed by the 1211 when an insertion event occurs and the host requests that the socket Vcc and Vpp be powered Upon completion of this power up sequence the 1211 interrupt scheme can be used to notify the host system see Table 13 denoted by the power cycle complete event This interrupt source is considered a PCI1211 internal event because it does not depend on a signal change at the PC Card interface but rather the completion of applying power to the socket interrupt masks and flags Host software may individually mask or disable most of the potential interrupt sources listed in Table 13 by setting the appropriate bits in the PCI1211 By individually masking the interrupt sources listed software can control those events that cause a PCI1211 interrupt Host software has some control over the system interrupt the 1211 asserts by programming the appropriate routing registers The PCI1211 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts A discussion of interrupt routing is somewhat specific to the interrupt signaling method used and is discussed in more detail in the following sections When an interrupt is signaled by the PCI1211 the interrupt service routine must determine which of the events in Table 12 caused the interrupt Internal registers in the PCI1211 provide flags that re
3. 1 1 1 0 feo Register Vendor ID Type Read only Offset 00h Default 104Ch Description This register contains a value allocated by the PCI SIG special interest group and identifies the manufacturer of the PCI device The vendor ID assigned to TI is 104Ch device ID register Bu upmiegsrv gs sqejisqe tv o Name _ _ _________ _ O 1 o 1 jopsjsjojojop ogjogyty srgyt 09 Register Device ID Type Read only Offset 02h Default AC1Eh Description This register contains a value assigned to the 1211 by TI The device identification for the 1211 is TEXAS INSTRUMENTS 44 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 command register gt 8 13 2 7 9 8 7 6 5 4 2 J t 0 ee eee e rR R few rR jew ea n R Rw pea o o o fo 0 Register Command Type Read only Read Write see individual bit descriptions Offset 04h Default 0000h Description This register provides control over the PCI1211 interface to the PCI bus All bit functions adhere to the definitions in PC Local Bus Specification Revision 2 2 See Table 17 for the complete description of the register conten
4. Receiver Figure 10 Serial Bus Protocol Acknowledge 1211 is a serial bus master all other devices connected to the serial bus external to the PCI1211 are slave devices As the bus master the PCI1211 drives the SCL clock at nearly 100 kHz during bus cycles and 3 states SCL zero frequency during idle states Typically the 1211 masters byte reads and byte writes under software control Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control Refer to serial bus EEPROM application on page 32 for details on how the 1211 automatically loads the subsystem identification and other register defaults through a serial bus EEPROM Figure 11 illustrates a byte write operation The PCI1211 issues a start condition and sends the seven bit slave device address and the command bit zero A zero in the R W command bit indicates that the data transfer is a write The slave device acknowledges if it recognizes the address If there is no acknowledgment received by the PCI1211 then an appropriate status bit is set in the serial bus control and status register The word address byte is then sent by the PCI1211 and another slave acknowledgment is expected Then the PCI1211 delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLA
5. OOOOOOQOOOOOO OOOOOOQOOOOOO OOOOOOQOOOOOO OOOO D OOOO OOOOOOQOOOOOO OOOOOOQOOOOOO OOOOOOQOOOOOO oooummorzcarszaz 123456 7 8 9 1011 1213 1 40 MAX 4073221 B 11 97 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Micro Star BGA configuration Micro Star is a trademark of Texas Instruments Incorporated 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 129 IMPORTANT NOTICE Texas Instruments and its subsidiaries reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each devi
6. 9 9 F 000 E p P 5 0 e 0 o eo B 5 9 CardBus Signals 1 2 3 4 5 6 7 8 9 10 11 12 13 D Power Switch Clamping Voltages CardBus Signals 2 GND O Interrupt and Miscellaneous PCI Signals PCI to CardBus and PCI to PC Card 16 Bit Diagram signal names and terminal assignments Signal names and their terminal assignments are shown in Table 1 through Table 4 Table 1 and Table 2 show the terminal assignments for the CardBus PC Card and Table 3 and Table 4 show the terminal assignments for the 16 bit PC Card Table 2 and Table 4 show the CardBus Card and the 16 bit PC Card terminals sorted alphanumerically by the signal name and its associated terminal number 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 1 CardBus PC Card Signal Names Sorted by BGA Terminal Numbert PIN NO PIN NO PIN NO PIN NO SIGNAL NAME SIGNAL NAME SIGNAL NAME SIGNAL NAME GGU PGE GGU PGE GGU PGE GGU PGE L4 42 GND REQ 11 CGNT CAD11 RSVD C12 CSTOP CAD10 L5 46 AD9 CAD28 C13 CPERR CAD9 6 50 Vcc 2 D1 AD27 VCCCB L7 55 02 CSERR D2 28 PCLK L8 59 OUT PME CAD26 D3 GND GND L9 63 VCCCB D4 AD29 AD19 67 MFUNC4 CAD23 D5 CCLKRUN AD18 70 SUSPEND CAD21 D6 CINT CAD7 75 CCD1 CAD19 D7 CAD25 V
7. 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 25 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 SPKROUT and CAUDPWM usage SPKROUT carries the digital audio signal from the PC Card to the system When a 16 bit PC Card is configured for I O mode the BVD2 pin becomes SPKR This terminal is also used in CardBus binary audio applications and is referred to as CAUDIO SPKR passes TTL level digital audio signal to the 1211 The CardBus CAUDIO signal also can pass a single amplitude binary waveform The binary audio signals from the PC Card socket is used in the PCI1211 to produce SPKROUT This output is enabled by the SPKROUTEN bit in the card control register Older controllers support CAUDIO in binary or PWM mode but use the same pin SPKROUT Some audio chips may not support both modes on one and may have a separate pin for binary and PWM 1211 implementation includes a signal for PWM CAUDPWM which can be routed to a MFUNC terminal The AUD2MUX bit located in the card control register is programmed to route a CardBus CAUDIO PWM terminal to CAUDPWM Refer to the multifunction routing register description on page 61 for details on configuring the MFUNC terminals Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM System Core Logic BINARY SPKR SPKROUT 1211 CAUDPWM PWM_SPKR Speaker Subsystem
8. master devices PC PCI DMA is enabled for the PC Card 16 slot by setting bit 19 in the respective system control register On power up this bit is reset and the card PC PCI DMA is disabled Bit 3 of the system control register is a global enable for PC PCI DMA and is set at power up and never cleared if the PC PCI DMA mechanism is implemented The desired DMA channel for the PC Card 16 slot must be configured through bits 18 16 in the system control register The channels are configured as indicated in Table 7 28 ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 7 PC PCI Channel Assignments SYSTEM CONTROL REGISTER So TENER a DMA CHANNEL CHANNEL TRANSFER DATA WIDTH BIT 18 BIT 17 BIT16 52 19 1291 SDi DMA anser 9 9 3 LL EE transfer 9 E transfor 9 1 1 Chame amp bit DMA transfers spo 9 emm Notused O j 51 1 5 f btoMAransers 1 1 Oo 16 bit DMA transfers As in distributed DMA the Card terminal mapped to DREQ must be configured through socket DMA register 0 The data transfer width is a function of channel number and the DDMA slave registers are not used When DREQ is received from a PC Card and the channel has been granted the PCI1211 decodes the I O addresses listed in Table 8 and perfor
9. Figure 6 Sample Application of SPKROUT and CAUDPWM LED socket activity indicators A socket activity LED indicates when PC Card is being accessed The LED_SKT signal can be routed to the multifunction terminals When configured for LED output this terminal outputs an active high signal to indicate socket activity Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals The LED signal is active high and is driven for 64 ms durations When the LED is not being driven high itis driven to a low state Either of the two circuits shown in Figure 7 can be implemented to provide LED signaling and it is left for the board designer to implement the circuit that best fits the application The LED activity signal is valid when a card is inserted powered and not in reset For PC Card 16 the LED activity signal is pulsed when READY IREQ is low For CardBus cards the LED activity signal is pulsed if CFRAME CIRDY or CREQ is active 26 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 LED socket activity indicators continued Current Limiting R 500 Q 1211 W LED Current Limiting 5000 Application Specific Delay 1211 a W LED Figure 7 Two Sample LED Circuits As indicated the LED signal is driven for 64 ms
10. _ 28 awiz wla gt A nanaaaanaaa oa gt dadaddaaaanaddlajojo lt lt lt 2 lt lt lt lt lt lt lt lt lt lt lt 2 lt lt gt gt gt gt gt LLL LaL Ll LI Ll L LLLI nm ow on no o co Pr O r e on N 1 000 rer o c NN N ANN e 122 LI LI Li LI LI LI L1 EI LL H Li Li LI LJ amp SA C QI Z QN QI 5 Be8 883 888 SSR lt lt lt lt lt lt lt lt lt lt 5 lt a LSE F 2 10 In 0 LL a PCI to CardBus Pin Diagram 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 VPPD1 VPPDO SUSPEND MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 Voc SPKROUT MFUNC1 MFUNCO OUT PME GND ADO AD1 AD2 AD3 AD4 AD5 AD6 C BEO AD8 AD9 AD10 AD11 GND AD12 AD13 AD14 AD15 C BE1 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 terminal assignments continued PGE LOW PROFILE QUAD FLAT PACKAGE BOTTOM VIEW VCCD1 VCCDO Vcc 101 D A13 IOWR IORD VCCCB 100 b A18 GND 75 B CD1 8
11. 0 RSVD Reserved Bit 0 returns 0 when read ki TEXAS INSTRUMENTS 64 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 card control register 7 e j s 46 s 2 1 Name Card control aw Aw A A Aw AW Register Card control Type Read only Read Write Read Write to Clear see individual bit descriptions Offset 91h Default 00h Description This register is provided for PCI1130 compatibility RI OUT is enabled through this register See Table 24 for a complete description of the register contents Table 24 Card Control Register SIGNAL TYPE FUNCTION Ring indicate output enable 7 RIENB R W 0 Disables any routing of RI OUT signal default 1 Enables RI OUT signal for routing to the RI OUT PME terminal when RIMUX is set to 0 or for routing to MFUNC2 4 Compatibility ZV mode enable When set the PC Card socket interface ZV terminals enter a EB ZVENABLE high impedance state These bits have no assigned function RSVD O R Reserved Bits 4 3 default to 0 2 AUD2MUX R W CardBus Audio to CAUDPWM When set the CAUDIO signal PWM is routed to the CAUDPWM signal which can be routed to a multifunction terminal Speaker out enable This bit is the enable for routing PC Card SPKR through to the SPKROUT terminal The SPKROUT terminal drives valid data only when the socket SPKROUTEN b
12. 7 e s 46 s 2 1 Revision ID Register Revision ID Type Read only Offset 08h Default 00h Description This register indicates the silicon revision of the 1211 PCI class code register fer TS TX T9 5 5 E T9 me T me IS eun o o 0 0 T9 19 1 0 19 T9 19 To To T9 T9 T9 Register PCI Class code Type Read only Offset 09h Default 060700h Description This register recognizes the PCI1211 as a bridge device 06h and CardBus bridge device 07h with a 00h programming interface cache line size register gs 7 e s 4 j 2 1 9 Name fT Cameliesge 2 Cache line size Register Cache line size Type Read Write Offset OCh Default 00h Description This register is programmed by host software to indicate the system cache line size 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 47 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 latency timer register 7 6 s 4 3 2 1 0 Latency timer R W R W R W R W R W R W R W R W Register Latency timer Type Read Write Offset ODh Default 00h Description This register specifies the latency timer for the PCI1211 in units of PCI clock cycles When the PCI1211 is a PC
13. The power management capabilities register is a static read only register that provides information on the capabilities of the function related to power management The PMCSR register enables control of power management states and enables monitors power management events The data register is an optional register that can provide dynamic data For more information on PCI power management refer to the PCI Bus Power Management Interface Specification Revision 1 0 ACPI Support The Advanced Configuration and Power Management ACPI Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver The PCI1211 offers a generic interface that is compliant with ACPI design rules Two doublewords of general purpose ACPI programming bits reside in the PCI1211 PCI configuration space at offset A8h The programming model is broken into status and control functions In compliance with ACPI the top level event status and enable bits reside in GPE STS and GPE EN registers The status and enable bits are implemented as defined by ACPI and illustrated in Figure 19 Status Bit Event input gt Event Output Enable Bit Figure 19 Block Diagram of a Status Enable Cell The status and enable bits are used to generate an event that allows the ACPI driver to call a control method associated with the pending status bit The control method can then control the hardware by manipulating the hardware control bits or by
14. Interrupt mode Bits 2 1 select the interrupt signaling mode The interrupt mode bits are encoded 00 Parallel PCI interrupts only 2 1 INTMODE R W 01 Parallel IRQ and parallel PCI interrupts 10 IRQ serialized interrupts and parallel PCI interrupt 11 IRQ and PCI serialized interrupts default Oo RSVD Reserved This bit is reserved for test purposes Only 0 should be written to this bit TEXAS INSTRUMENTS 66 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 diagnostic register 7 e j s 4 s 2 j 1 Name Diagnose _ Diagnostic mem o 3 1 o o o Jo 1 Register Diagnostic Type Read Write Offset 93h Default 61h Description This register is provided for internal TI test purposes It is a read write register but should not be accessed during normal operation See Table 26 for a complete description of the register contents Table 26 Diagnostic Register BIT SIGNAL TYPE FUNCTION 7 True value This bit defaults to 0 when read This bit is encoded as TRUE_VAL R W 0 Reads true values in PCI vendor ID and PCI device ID registers default 1 Reads all 1s in reads to the PCI vendor ID and PCI device ID registers RSVD Reserved This bit has no function CSC Interrupt Routing Control 0 CSC interrupts routed to PCI if ExCA 803 bit 4 1 1 CSC interrupts routed to PCI if EXCA 805 bits 7 4
15. _ Reserved Regest commana Ci Reserved Reserved e umemeut 9 04 Reserved Reserved Basecont count 221 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 27 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PC Card16 Distributed DMA support continued The DDMA registers contain control and status information consistent with the 8237 DMA controller however the register locations are reordered and expanded in some cases While the DDMA register definitions are identical to those in the 8237 DMA controller of the same name some register bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment In such cases the PCI1211 implements these obsolete register bits as read only nonfunctional bits The reserved registers shown in Table 6 are implemented as read only and return zeros when read Writes to reserved registers have no effect The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed after the PC Card is inserted and interrogated These steps include setting the proper DREQ signal assignment setting the data transfer width and mapping and enabling the DDMA register set As discussed above this is done through socket DMA register 0 and socket DMA register 1 The DMA register set is then programm
16. La x 106 P WE 105 P 20 104 B A14 103 5 A19 99 D 8 98H A17 97 A9 io rir S 5588 82 5 013 80 3 012 77 011 76 D3 N VPPD1 22 A15 VPPDO A23 SUSPEND A12 C MFUNC6 A24 MFUNC5 GND MFUNC4 A7 C 25 MFUNC3 VS2 c MFUNC2 VCCI RESET C SPKROUT A5 C MFUNC1 A4 C MFUNCO _ RI_OUT PME c GND CI ADO REG o AD1 AD2 A2c AD3 Aic AD4 qc AD5 GND AD6 VST Vcc READY IREQ AD7_ WAIT C C BEO BVD2 SPKR AD8 BVD1 STSCHG RI AD9 WP IOIS16 AD10 CD2 Voc AD11 DO GND D8 AD12 D1 AD13 D9 AD14 D2 AD15 D10 C BE1 ae SrELPZSRANKRARAA LI LI LI LI LI LI LI LI LI LI LI LI LI LI EI LE LI LI LI LI LI GERBSR2SRESREUDSERROS 9 r co gt OP E tc CC 2 QN zz OI LE 0 2 m PCI to PC Card 16 Bit Diagram Texas INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 terminal assignments continued GGU BALL GRID ARRAY PACKAGE BOTTOM VIEW PCI Signals Interrupt Power and Misc Switch 9 6 M o 0 k 0 Oe 3
17. Register CardBus socket ExCA registers base address Type Read only Read Write Offset 10h Default 0000 0000h Description This register is programmed with a base address referencing the CardBus socket registers and the memory mapped ExCA register set Bits 31 12 are read write and allow the base address to be located anywhere in the 32 bit PCI memory address space on 4K byte boundary Bits 11 0 are read only returning Os when read When software writes all 1s to this register the value readback is FFFF FOOOh indicating that at least 4K bytes of memory address space are required The CardBus registers start at offset O00h and the memory mapped ExCA registers begin at offset 800h capability pointer register gu v e 5 a 3 2 1 o Capability pointer ye R R R R R R R R Deta gt o0 3 0 o 0 o o Register Capability pointer Type Read only Offset 14h Default Description This register provides a pointer into the PCI configuration header where the PCI power management register block resides PCI header doublewords at AOh and A4h provide the power management PM registers The socket has its own capability pointer register This register returns AOh when read 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 49 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 secondary status register t5 fa 1
18. Rw RW RW mw RW RW RW R pea o o 1 0 Register I O base registers 0 1 Type Read only Read Write Offset 2Ch 34h Default 0000 0000h Description These registers indicate the lower address of a PCI I O address range and are used by the PCI1211 to determine when to forward an I O transaction to the CardBus bus and likewise when to forward a CardBus cycle to the PCI bus The lower 16 bits of this register locate the bottom of the I O window within a 64K byte page and the upper 16 bits 31 16 are a page register which locates this 64K byte page in 32 bit PCI I O address space Bits 31 2 are read write Bits 1 0 always return Os when read forcing I O windows to be aligned on a natural doubleword boundary NOTE Either the I O base or the I O limit register must be nonzero to enable any I O transactions 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 53 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 I O limit registers 0 1 name eu foto fo fof Register I O limit registers 0 1 Type Read only Read Write Offset 30h 38h Default 0000 0000h Description These registers indicate the upper address of a PCI I O address range and are used by the PCI1211 to determine when to forward an I O transaction to the CardBus bus and likewise when to forw
19. Socket control R a eR in nw Rw RW pee o o o 69 69 0 Register Socket conirol Type Read only Read Write see individual bit descriptions Offset CardBus socket address 10h Default 0000 0000h Description This register provides control of the voltages applied to the socket and instructions for CB CLKRUN protocol The PCI1211 ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted See Table 59 for a complete description of the register contents Table 59 Socket Control Register SIGNAL TYPE FUNCTION RSVD O R Reserved Bits 31 8 return 05 when read CB CLKRUN protocol instructions 7 STOPCLK the PCI CLKRUN protocol is preparing to stop slow the PCI bus clock default 1 CB CLKRUN protocol can attempt to stop slow the CB clock if the socket is idle 0 CB CLKRUN protocol can only attempt to stop slow the CB clock if the socket is idle and Vcc control Bits 6 4 are used to request card Voc changes 000 Request power off default 001 Reserved 010 Request Vcc 5 VCCCTRL R W 011 Request Voc 3 3 V 100 Request Voc X X V 101 Request Vcc Y Y V 110 Reserved 111 Reserved R VPPCTRL 110 POST OFFICE BOX 655303 DALLAS TEXAS 75265 Reserved Bit 3 returns 0 when read Vpp control Bits 2 0 are used to request card Vpp changes 000 Request
20. cycles see Figure 28 mom gg Seupiine FES betas Du Setup tne CET and CEZ betore ORDIOWA Iw m Fp Propagation delay time 105716 ow afer GA5 CAdvald 35 th Hold time read CDATA15 CDATAO valid after IORD high m4 0 sm tsu Setup time T CDATA15 CDATAO valid before IO IOWR low m5 m in He time GDATATS GDATAD vaia ater OWA non we 1 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 125 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 switching characteristics over recommended ranges of supply voltage and operating free air temperature miscellaneous see Figure 29 ALTERNATE PARAMETER SYMBOL Lx UNIT BVD2 low BVD2 low to SPKROUT low BVD2 low to SPKROUT low low BVD2 high to SPKROUT high t Propagation delay time ns pd pag 4 IREQ to IRQ15 IRQ3 oe 2030 STSCHG to IRQ15 IRQ3 PC Card PARAMETER MEASUREMENT INFORMATION 2 T10 gt REG 2 4 47 1 2 eT x T5 gt MEE WE OE lt T3 an 4 2 gt 4 14 5 gt 164 pp E a p WAIT J 0 4 12 CDATA15 CDATAO MEME write zur I I q T9 CDATA15 CDATAO read cts With no wait state With wait state Figure 27 PC Card Memory Cycle 35 TEXAS INSTRUMENTS 126 POST OFFICE BOX 655303 9
21. 0000b default In this case the setting of 803 bit 4 is a don t care Diagnostic DISCARD_TIM_SEL_CB Set 210 reset 215 Diagnostic DISCARD TIM SEL PCI Set 210 reset 215 ASYNCINT R W Global asynchronous interrupt enable When set to a 1 bit 0 enables the asynchronous generation of CSC interrupts socket DMA register 0 gt 3o 26 27 25 zs 22 2t zo 19 18 17 16 Socket DMA register 0 Socket DMA register 0 Register Socket DMA register 0 Type Read only Read Write see individual bit descriptions Offset 94h Default 0000 0000h Description This register provides control over the PC Card DMA request DREQ signaling See Table 27 for a complete description of the register contents 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 67 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 27 Socket DMA Register 0 SIGNAL TYPE FUNCTION RSVD OR Reserved Bits 31 2 return Os when read DMA request DREQ Bits 1 0 indicate which on the 16 bit PC Card interface will be used as DREQ during DMA transfers This field is encoded as 00 Socket not configured for DMA default T9 01 DREQ uses SPKR 10 DREQ uses 101516 11 DREQ uses INPACK socket DMA register 1 Bt 3o 28 27 26 25 2a 23 22 21 20 19 18 17 16 Socket DMA register 1 me R R RJ
22. PERR 35 TEXAS INSTRUMENTS 12 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Terminal Functions Continued PCI interface control TERMINAL PIN NUMBER FUNCTION PGE GGU PCI device select The PCI1211 asserts DEVSEL to claim a PCI cycle as the target device As a DEVSEL PCI initiator on the bus the PCI1211 monitors DEVSEL until a target responds If no target responds before timeout occurs the PCI1211 terminates the cycle with an initiator abort PCI cycle frame FRAME is driven by the initiator of a bus cycle FRAME is asserted to indicate that FRAME a bus transaction is beginning and data transfers continue while this signal is asserted When FRAME is deasserted the PCI bus transaction is in the final data phase 2n PCI bus grant GNT is driven by the PCI bus arbiter to grant the PCI1211 access to the PCI bus 2 B1 NAME GNT after the current data transaction has completed GNT may or may not follow a PCI bus request depending on the PCI bus parking algorithm IDSEL Initialization device select IDSEL selects the PCI1211 during configuration space accesses IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus PCI initiator ready IRDY indicates the PCI bus initiator s ability to complete the current data phase ofthetransaction A data phase is completed on a rising edge of PCLK where both TRDY and TRDY are ass
23. SCPS033A OCTOBER 1998 retry status register 7 e s j 46 s 2 1 o Name Retry status Tyee mw ew n R wc nm mw pee 1 1 59 o o o o o Register Retry status Type Read only Read Write Read Write to Clear see individual bit descriptions Offset 90h Default Coh Description This register enables the retry timeout counters and displays the retry expiration status The flags setwhen the 11211 retries a PCI or CardBus master request and the master does not return within 215 PCI clock cycles The flags are cleared by writing a 1 to the bit These bits are expected to be incorporated into the PCI command PCI status and bridge control registers by the PCI SIG See Table 23 for a complete description of the register contents Table 23 Retry Status Register TYPE FUNCTION PCI retry timeout counter enable Bit 7 is encoded R W 0 PCI retry counter disabled 1 PCI retry counter enabled default CardBus retry timeout counter enable Bit 6 is encoded R W 0 CardBus retry counter disabled 1 CardBus retry counter enabled default R Reserved These bits return 05 when read CardBus target retry expired Write a 1 to clear bit 3 3 TEXP_CB R WC 0 Inactive default 1 Retry has expired RSVD Reserved Bit 2 returns 0 when read PCI target retry expired Write a 1 to clear bit 1 TEXP PCI R WC 0 Inactive default 1 Retry has expired
24. The 1211 does permit the central resource to stop the PCI clock under any of the following conditions The KEEPCLK bit in the system control register is set The PC Card 16 resource manager is busy PCI1211 CardBus master state machine is busy A cycle may be in progress on CardBus PCI1211 master is busy There may be posted data from CardBus to PCI in the PCI1211 There are pending interrupts The CardBus CCLK has not been stopped by the PCI1211 PCI CCLKRUN manager The 1211 restarts the PCI clock using the clockk run protocol under any of the following conditions A PC Card 16 IREQ or a CardBus CINT has been asserted by either card A CardBus wakeup CSTSCHG or PC Card 16 STSCHG RI event occurs A CardBus card attempts to start the CCLK using CCLKRUN A CardBus card arbitrates for the CardBus bus using CREQ A 16 bit DMA PC Card asserts DREQ CardBus PC Card Power Management The 1211 implements its own card power management engine that can be used to turn off the CCLK to the socket when there is no activity to the CardBus PC Card The PCI CCLKRUN protocol is followed on the CardBus interface to control this clock management 16 Bit PC Card Power Management The COE and PWRDOWN bits in the ExCA registers are provided for 16 bit PC Card power management The COE bit three states the card interface to save power The power savings when using this feature are minimal The COE bit will res
25. 0 5 V to Veg 0 5 V Input clamp current Ij Vj lt 0 or Vi gt see Note 1 20 mA Output clamp current lox lt 0 or Vo gt Voc see Note 2 20 mA Storage temperature range Tstg 65 to 150 C Virtual junction temperature Ty 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 Applies for external input and bidirectional buffers Vj gt Vcc does not apply to fail safe terminals PCI terminals are measured with respect to Vccp instead of Vcc PC Card terminals are measured with respect to Voc cp Miscellaneous signals are measured with respect to Vcc The limit specified applies for a dc condition 2 Applies for external output and bidirectional buffers gt Vcc does not apply to fail safe terminals PCI terminals are measured with respect to Vccp instead of Vcc PC Card terminals are measured with respect to VG C cp Miscellaneous signals are measured with respect to Vc c The limit specified applies for a dc condition 35 T
26. 25 2a 23 22 zt 20 19 18 17 16 Memory limit registers 0 1 Name _ _ MemoyimtregstrsO 0 Memory limit registers 0 1 Name Hye Rn n R in Jn n PR n eem o o 9 Register Memory limit registers 0 1 Type Read only Read Write Offset 20h 28h Default 0000 0000h Description These registers indicate the upper address of a PCI memory address range and are used by the 1211 to determine when to forward a memory transaction to the CardBus bus and likewise when to forward a CardBus cycle to PCI Bits 31 12 of these registers are read write and allow the memory base to be located anywhere in the 32 bit PCI memory space 4K byte boundaries Bits 11 0 always return Os when read Writes to these bits have no effect Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable The memory base register or the memory limit register must be nonzero for the PCI1211 to claim any memory transactions through CardBus memory windows i e these windows are not enabled by default to pass the first 4K bytes of memory to CardBus I O base registers 0 1 Bin so 29 28 27 26 25 24 23 22 2t 20 19 18 17 16 I O base registers 0 1 Name Defaut 0 I O base registers 0 1 Name Hype RW
27. 4 returns 0 when read Writes to this bit have no effect m Special cycles Bit controls whether or not a PCI device ignores PCI special cycles PCI1211 does Memory write and invalidate enable Bit 4 controls whether a PCI initiator device can generate memory write and Invalidate commands The PCI1211 controller does not support memory write and invalidate SPECIAL not respond to special cycle operations therefore this bit is hardwired to 0 Bit 3 returns 0 when read Writes to this bit have no effect Bus master control Bit 2 controls whether or not the PCI1211 can act as a PCI bus initiator master The MAST EN PCI1211 can take control of the PCI bus only when this bit is set ES 0 Disables the PCI1211 s ability to generate PCI bus accesses default 1 Enables the PCI1211 s ability to generate PCI bus accesses Memory space enable Bit 1 controls whether or not the 11211 can claim cycles in PCI memory space AN AN R R 0 Disables the PCI1211 s response to memory space accesses default 1 Enables the PCI1211 s response to memory space accesses I O space control Bit 0 controls whether or not the PCI1211 can claim cycles in PCI I O space R W 0 Disables the PCI1211 from responding to I O space accesses default 1 Enables the 11211 to respond to I O space accesses 3 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 45 1211 GGU PGE PC CARD CONTROLLERS SCPS033A
28. Bits Loadable Through Serial EEPROM OFFSET PCI OFFSET REFERENCE REGISTER BITS LOADED FROM EEPROM 40h System control register 31 30 27 26 24 15 14 6 3 1 Retry status Card control device control diagnostic 31 28 24 22 19 16 15 7 6 Figure 13 details the EEPROM data format This format must be followed for the PCI1211 to properly load initializations from a serial EEPROM Any undefined condition results in a terminated load and sets the ROM_ERR bit in the serial bus control and status register 35 TEXAS INSTRUMENTS 32 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 serial bus EEPROM application continued A Slave Address 1010 000 Reference 0 Word Address 00h Byte 3 0 Word Address 01h Reference n Word Address 8 x n 1 Byte 2 0 Word Address 02h Byte 3 n Word Address 8 x n 1 1 Byte 1 0 Word Address 03h Byte 2 n Word Address 8 x n 1 2 Byte 0 0 Word Address 04h Byte 1 n Word Address 8 x n 1 3 RSVD RSVD RSVD Reference 1 Byte 0 RSVD RSVD RSVD Word Address 8 x n 1 4 Word Address 08h Word Address 8 x n r Figure 13 EEPROM Data Format The byte at the EEPROM word address 00h must either contain a valid PCI offset as listed in Table 10 or an end of list EOL indicator The EOL indicator is a byte value of FFh and indicates the end of the data to load from the EEPROM Only d
29. CCD2 low PC Card may be present CDETECT1 CARDSTS 1 CCD2 high PC Card not present CCD1 Bit 1 reflects the current status of CCD1 at the PC Card interface Changes to this signal during card interrogation are not reflected here 0 CCD1 low PC Card may be present 1 CCD1 high PC Card not present CSTSCHG Bit 0 reflects the current status of CSTSCHG at the PC Card interface 0 CSTSCHG low 1 CSTSCHG high 35 TEXAS INSTRUMENTS 108 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 socket force event register gt so 29 28 27 26 25 24 23 22 2t 20 19 18 17 16 Socket force event oo o O S S L R R RIR R RRJ R iR Jn R n peat o o o foe fo 15 14 t3 2 v0 9 8 Pez je Ps ja 2 1 0 Socket force event peut o fo fo fo Register Socket force event Type Read only Write only see individual bit descriptions Offset CardBus socket address 0Ch Default 0000 0000h Description This register is used to force changes to the socket event register and the socket present state register The CVSTEST bit in this register must be written when forcing changes that require card interro
30. CardBus card Writes to bit 5 cause the CBCARD bit in the socket present state register to be written 4 F16BITCARD W Force 16 bit card Writes to bit 4 cause the 16BITCARD bit in the socket present state register to be written 3 FPWRCYCLE W Force power cycle Writes to bit 3 cause the PWREVENT bit in the socket event register to be written and the PWRCYCLE bit in the socket present state register is unaffected 2 FCDETECT2 W Force CCD2 Writes to bit 2 cause the CD2EVENT bit in the socket event register to be written and the CDETECT2 bit in the socket present state register is unaffected 1 FCDETECT4 w Force CCD1 Writes to bit 1 cause the CD1EVENT bit in the socket event register to be written and the CDETECT1 bit in the socket present state register is unaffected FCARDSTS w Force CSTSCHG Writes to bit 0 cause the CSTSEVENT bit in the socket event register to be written and the CARDSTS bit in the socket present state register is unaffected 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 109 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 socket control register gt so 29 28 27 25 24 2s 22 2t 20 19 18 17 16 Socket control po Socket conto pea 0 0 15 14 t3 12 9 8 7 e Ps ja 3 2 1 0
31. IRQ11 Parallel ISA type 1100 LED_SKT Socket activity LED 1101 LED_SKT Socket activity LED 1110 GPE General Purpose event signal 1111 IRQ15 Parallel ISA type Multifunction terminal 4 configuration These bits control the internal signal mapped to the MFUNC4 terminal as follows NOTE When the serial bus mode is implemented by pulling up the VPPDO and VPPD1 terminals the MFUNCA terminal provides the SCL signaling 0000 GPI3 General purpose input default 0001 General purpose output 0010 LOCK PCI atomic transfer support mechanism 0011 IRQ3 Parallel ISA type 0100 IRQ4 Parallel ISA type 18 08 MPUNGA RAN 0101 IRQ5 Parallel ISA type 0110 ZVSTAT Zoom video status output 0111 ZVSELO Zoom video select output 1000 CAUDPWM PWM output of CAUDIO CardBus terminal 1001 IRQS Parallel ISA type 1010 IRQ10 Parallel ISA type 1011 IRQ11 Parallel ISA type 1100 RI OUT Ring indicate output 1101 LED SKT Socket activity LED 1110 GPE General purpose event signal 1111 IRQ15 Parallel ISA type Multifunction terminal 3 configuration These bits control the internal signal mapped to the MFUNC3 terminal as follows 0000 RSVD Reserved high impedance input default 0001 IRQSER Serial interrupt stream IRQ and optional PCI 0010 IRQ2 Parallel ISA type 0011 IRQ3 Parallel ISA type 0100 IRQ4 Parallel ISA type 0101 IRQ5 Parallel ISA type 0110 IRQ6 Parallel ISA type Lene MFUNGS RM 0111 I
32. PC Card Signal Names Sorted Alphabetically PIN NO PIN NO PIN NO AO 129 6 AD10 45 K5 D4 79 2 A1 128 D7 AD11 43 M4 D5 J10 A2 197 C7 AD12 41 D6 J12 A3 194 8 AD13 40 D7 H10 A4 121 D8 AD14 39 M3 D8 A3 A5 120 A9 AD15 38 N2 A6 118 9 AD16 26 J2 D10 B2 A7 115 B10 AD17 25 D11 K10 A8 99 E11 AD18 H4 D12 K13 A9 97 E13 AD19 H3 D13 J11 89 912 AD20 G3 D14 J13 95 11 AD 1 D15 H12 11 AD22 F1 DEVSEL L1 D13 AD23 F2 FRAME J4 C13 AD24 E2 GND D3 A12 AD25 E3 GND H2 B12 AD26 E4 GND E12 AD27 Di GND E10 AD28 D2 GND D11 AD29 D4 GND C12 AD30 GND B13 AD31 C2 GND A13 BVD1 STSCHG R 135 5 GNT B11 BVD2 SPKR 134 B5 IDSEL D10 C BEO 48 5 INPACK A10 37 IORD N8 C BE2 27 J3 IOWR K7 C BE3 12 IRDY L7 CD1 75 MFUNCO N7 CD2 MFUNC1 M7 88 MFUNC2 6 CE2 91 MFUNC3 M6 DO MFUNC4 K6 D1 MFUNCS5 M5 D2 MFUNC6 L5 D3 OE 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 PIN NO PGE GGU SIGNAL NAME PAR PCLK PERR REQ READY IREQ REG RESET RST SERR SPKROUT STOP SUSPEND TRDY Voc 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Terminal Functions The terminals are grouped in tables by functionality such as PCI system function power supply function etc The term
33. PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 power management control status register gt sa m9 12 m w0 9 e v je js ea s j 2 0 Power management control status r r n n n nw n n n Jn P R pea o o o jo jo jo 09 Register Power management control status Type Read only Read Write Read Write to Clear see individual bit descriptions Offset A4h Default 0000h Description This register determines and changes the current power state of the PCI1211 CardBus function The contents of this register are not affected by the internally generated reset caused by the transition from D3 to DO state See Table 30 for a complete description of the register contents Table 30 Power Management Control Status Register SIGNAL TYPE FUNCTION PME status Bit 15 is set when the CardBus function would normally assert PME independent 15 PMESTAT R WC of the state of the PME EN bit Bit 15 is cleared by a write back of 1 and this also clears the PME signal if PME was asserted by this function Writing a 0 to this bit has no effect Data scale This 2 bit field returns 0s when read The CardBus function does not return any 14 19 DATASCALE ES dynamic data as indicated by the DYN DATA bit 12 9 DATASEL Data select This 4 bit field returns 05 when read CardBus function does not return any dynamic data as indicated by the DYN DATA bit ES P
34. The SUSPEND input gates the PCI reset from the entire PCI1211 core including the serial bus state machine see suspend mode on page 39 for details on using SUSPEND 1211 provides a two line serial bus host controller that can be used to interface to a serial EEPROM Refer to serial bus interface on page 30 for details on the two wire serial bus controller and applications PC Card applications This section describes the PC Card interfaces of the PCI1211 Discussions are provided for Card insertion removal and recognition 2 power switch interface Zoom video support Speaker and audio applications LED socket activity indicator PC Card 16 distributed DMA support PC Card controller programming model CardBus socket registers PC Card insertion removal and recognition The 1997 PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold unpowered socket Through this interrogation card voltage requirements and interface 16 bit versus CardBus are determined The scheme uses the CD1 CD2 VS1 and VS2 signals CCD1 CCD2 CVS1 and CVS2 for CardBus The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface The encoding scheme is defined in the 1995 PC Card Standard and is shown in Table 5 Table 5 PC Card Card Detect and Voltage Sense Connections Co
35. W R W R W R W Register ExCA memory window 0 4 page Type Read Write Offset CardBus socket address 840h 841h 842h 843h 844h Default 00h Description The upper 8 bits of a 4 byte PCI memory address are compared to the contents of this register when decoding addresses for 16 bit memory windows Each window has its own page register all of which default to 00h By programming this register to a nonzero value host software can locate 16 bit memory windows in any one of 256 16M byte regions in the 4G byte PCI address space These registers are accessible only when the ExCA registers are memory mapped i e these registers can not be accessed using the index data scheme 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 103 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 CardBus socket registers The PCMCIA CardBus specification requires a CardBus socket controller to provide five 32 bit registers that report and control socket specific functions The PCI1211 provides the CardBus socket ExCA base address register PCI offset 10h to locate these CardBus socket registers in PCI memory address space Each socket has a separate base address register for accessing the CardBus socket registers see Figure 22 Table 54 gives the location of the socket registers in relation to the CardBus socket ExCA base address The 1211 implements an additional register at offset 20h that provide
36. When bit 1 is set a GPE is signaled when there has been a change in status GRIE of the MFUNC1 terminal input if configured as GPI1 Z _ A R GPIO event enable When bit 0 is set a GPE is signaled when there has been a change in status of the MFUNCO terminal input if configured as GPIO 35 TEXAS INSTRUMENTS 74 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 general purpose input register gt 14 t3 r2 v 8 Pez je ts 1 0 General purpose input me n n n R R n Jn n n JR pem o Register General purpose input Type Read only see individual bit descriptions Offset ACh Default 00XXh Description This register provides the logical value of the data input from the GPI terminals MFUNC5 MFUNC4 and MFUNC2 MFUNCO See Table 34 for a complete description of the register contents Table 34 General Purpose Input Register SIGNAL TYPE FUNCTION RSVD Reserved Bits 15 5 return Os when read Writes no effect 4 GPI4 DATA GPI4 Data Bit The value read from bit 4 represents the logical value of the data input from the MFUNCS terminal Writes have no effect 3 GPI3 DATA GPI3 Data Bit The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal Writes hav
37. a don t care This is the default setting 0000 No ISA interrupt routing if bit 5 of the diagnostic register PCI Offset 93h is set to Ob In this case CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803 to 1b This field is encoded as 0000 No interrupt routing default 0001 IRQ1 enabled 0010 enabled 0011 IRQ3 enabled 0100 IRQ4 enabled CSCSELECT 0101 IRQ5 enabled 0110 IRQ6 enabled 0111 IRQ7 enabled 1000 IRQ8 enabled 1001 IRQ9 enabled 1010 IRQ10 enabled 1011 IRQ11 enabled 1100 IRQ12 enabled 1101 IRQ13 enabled 1110 IRQ14 enabled 1111 IRQ15 enabled Card detect enable Bit 3 enables interrupts on CD1 or CD2 changes This bit is encoded as CDEN 0 Disables interrupts on CD1 or CD2 line changes default 1 Enables interrupts on CD1 or CD2 line changes READYEN 0 Disables host interrupt generation default 1 Enables host interrupt generation Battery dead enable Bit 0 enables disables a battery dead condition Card or assertion BATDEADEN R of the STSCHG signal to generate a CSC interrupt 0 Disables host interrupt generation default 1 Enables host interrupt generation Ready enable Bit 2 enables disables a low to high transition on PC Card READY to generate a host interrupt This interrupt source is considered a card status change This bit is encoded as 0 Disables host interrupt generation defa
38. a critical access to memory might be broken into several transactions but the master wants exclusive rights to a region of memory The granularity of the lock is defined by PCI to be 16 bytes aligned The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real time data transfer such as video The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol In this scenario the arbiter will not grant the bus to any other agent other than the LOCK master while LOCK is asserted A complete bus lock may have a significant impact on the performance of the video The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress The 1211 supports LOCK protocol associated with PCl to PCl bridges as also defined for PCI to CardBus bridges This includes disabling write posting while a locked operation is in progress which can solve a potential deadlock when using devices such as bridges The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read This target characteristic is prohibited by the PCI Local Bus Specification Revision 2 2 and the issue is resolved by the PCI master using LOCK loading subsystem identification The subsystem vendor ID regis
39. address for I O windows 0 and 1 The eight bits of these registers correspond to the upper eight bits of the end address 35 TEXAS INSTRUMENTS 92 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA I O window 0 and 1 end address low byte register index 0 OEh gu v 6 5 4 3 2 1 o Name ExCA window 0 and 1 end address low byte R W R W R W R W R W R W R W Register ExCA window 0 end address low byte Offset CardBus socket address 80Ah ExCA offset OAh Register ExCA window 1 end address low byte Offset CardBus socket address 80Eh ExCA offset OEh Type Read Write Default 00h Size One byte Description These registers contain the low byte of the 16 bit I O window end address for I O windows 0 and 1 The eight bits of these registers correspond to the lower eight bits of the end address ExCA window 0 and 1 end address high byte register index OBh OFh gu 7 6 5 4 3 2 1 o Name ExCA window 0 and 1 end address high byte R W R W R W R W R W R W R W Register ExCA window 0 end address high byte Offset CardBus socket address 80Bh offset OBh Register ExCA I O window 1 end address high byte Offset CardBus socket address 80Fh ExCA offset OFh Type Read Write Default 00h Size One byte Description These registers contain the high byte of the 16 b
40. by a counter circuit To avoid the possibility of the LED appearing to be stuck when the PCI clock is stopped the LED signaling is cut off when the SUSPEND signal is asserted when the PCI clock is to be stopped during the CLKRUN protocol or when in the D2 or D1 power state If any additional socket activity occurs during this counter cycle the counter is reset and the LED signal remains driven If socket activity is frequent at least once every 64 ms the LED signal remains driven PC Card16 Distributed DMA support The 1211 supports a distributed DMA slave engine for 16 bit PC Card DMA support The distributed DMA DDMA slave register set provides the programmability necessary for the slave DDMA engine Table 6 shows the DDMA register configuration Two critical PCI configuration header registers for DDMA are the socket DMA register 0 and the socket DMA register 1 Distributed DMA is enabled through socket DMA register 0 and the contents of this register configure the PC Card 16 terminal SPKR 101516 or INPACK which is used for the DMA request signal DREQ base address of the DDMA slave registers and the transfer size bytes or words are programmed through the socket DMA register 1 Refer to the PC Card controller programming model on page 43 and the accompanying register descriptions for details Table 6 Distributed DMA Registers DMA REGISTER NAME BASE ADDRESS OFFSET HEX Reserved Page
41. byte reads the word address is programmed into this register the serial bus slave address must be programmed with both the 7 bit slave address and the read write indicator bit must be set and the REQBUSY bit in the serial bus control and status register must be polled until clear Then the contents of the serial bus data register are valid read data from the serial bus interface See Table 37 for a complete description of the register contents 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 77 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 37 Serial Bus Index Register SIGNAL FUNCTION SBINDEX 1 index This bit field represents the byte address read or write transaction on the serial serial bus slave address register pe T 15 14 12 2 o Serial bus slave address Register Serial bus slave address Type Read Write Offset B2h Default 00h Description This register is for programmable serial bus byte read and write transactions To write a byte the serial bus data register must be programmed with the data the serial bus index register must be programmed with the byte address and this register must be programmed with both the 7 bit slave address and the read write indicator bit On byte reads the byte address is programmed into the serial bus index register this register must be programmed with both the 7 bit slave address and the read
42. either resetting the socket s DMA controller or reenabling the mask bit See Table 65 for a complete description of the register contents Table 65 DDMA Multichannel Mask Register SIGNAL TYPE FUNCTION RSVD OR Reserved Bits 7 1 return Os when read Mask select Bit 0 masks incoming DREQ signals from the Card When set the socket ignores DMA requests from the card When cleared or when reset incoming DREQ assertions are serviced normally 0 DDMA service provided on card DREQ 1 Socket DREQ signal ignored default MASKBIT 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 117 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 absolute maximum ratings over operating temperature ranges unless otherwise Supply voltage range VAG isses epe a RR tena RR 0 5 Vto4 V Clamping voltage range VGC VCCP sai du eR ERRARE ACE 0 5Vto6V Input voltage range V 0 5 V to Vccp 0 5 V Np CC 0 5 to Vppo 0 5 V MISO rm 0 5 to Voc 0 5 V Fall Safe eee eee eee Tee Tec Tere eee d URS 0 5 V to Vcc 0 5 V Gutput voltage Tange Ves POL nacho aca Iac n ca dee arai n 0 5 V to Vecp 0 5 V ET 0 5 to Vppo 0 5 V MISO arc rm 0 5 to Voc 0 5 V wit quis Ve babe
43. enabled 1001 IRQ9 enabled 1010 IRQ10 enabled 1011 IRQ11 enabled 1100 IRQ12 enabled 1101 IRQ13 enabled 1110 IRQ14 enabled 1111 2 IRQ15 enabled 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 87 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA card status change register index 04h 7 e s 4 s 2 1 09 Name ExCA card status change 8 pee o o o o Register ExCA card status change Type Read only see individual bit descriptions Offset CardBus socket address 804h ExCA offset 04h Default 00h Description This register controls interrupt routing for I O interrupts as well as other critical 16 bit PC Card functions This register reflects the status of PC Card CSC interrupt sources The card status change interrupt register enables these interrupt sources to generate an interrupt to the host When the interrupt source is disabled the corresponding bit in this register always reads O When an interrupt source is enabled and that particular event occurs the corresponding bit in this registeris setto indicate thatthe interrupt source is active After generating the interruptto the host the interrupt service routine must read this register to determine the source of the interrupt The interrupt service routine is responsible for resetting the bits in this register as well Res
44. includes loz leakage of the disabled output Vccp pins include VCCD0 73 and VCCD1 74 NOTES 4 and loj are not tested on SERR 35 1 and OUT 59 L8 because they are open drain outputs 5 is not tested on VCCDO 73 N13 and VCCD1 74 M13 because they are pulled down with an internal resistor 6 INSTRUMENTS 120 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PCI clock reset timing requirements over recommended ranges of supply voltage and operating free air temperature see Figure 24 and Figure 25 Cycle time PCLK H Pulse duration PCLK high L t PCI timing requirements over recommended ranges of supply voltage and operating free air temperature see Note 6 and Figures 19 and 22 ALTERNATE PARAMETER SYMBOL TEST CONDITIONS PCLK to shared signal valid delay time va Propagation delay time C 50 pF See Note 7 See Note 7 PCLK to shared signal 2 invalid delay time ny t Enable time high impedance to active delay time from t 2 i en PCLK on Disable time active to high impedance delay time from tdis PCLK toff 28 ns NOTES 6 This data sheet uses the following conventions to describe time t intervals The format is tA where subscript A indicates the type of dynamic parameter being represented One ofthe following is used propagation delay time tg delay time tg setup time a
45. indicates whether or not the PC Card inserted in the socket supports Vcc X X V Data lost Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle DATALOST did not terminate properly or because write data still resides in the PCI1211 0 Normal operation default 1 Potential data loss due to card removal Not a card Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket This bit is 7 NOTACARD not updated until a valid PC Card is inserted into the socket 0 Normal operation default 1 Unrecognizable PC Card detected READY IREQ CINT Bit 6 indicates the current status of READY IREQ CINT at the PC Card interface 0 READY IREQJ CINT low 1 READY IREQ CINT high CardBus card detected Bit 5 indicates that a CardBus PC Card is inserted in the socket This bit is not updated until another card interrogation sequence occurs card insertion 16 bit card detected Bit 4 indicates that a 16 bit PC Card is inserted in the socket This bit is not updated until another card interrogation sequence occurs card insertion CBCARD 16BITCARD EN Power cycle Bit 3 indicates that the status of each card powering request This bit is encoded as 3 PWRCYCLE 0 Socket powered down default 1 Socket powered up CCD2 Bit 2 reflects the current status of CCD2 at the PC Card interface Changes to this signal during 2 CDETECT2 card interrogation are not reflected here 0
46. investigating child status bits and calling their respective control methods A hierarchical implementation would be somewhat limiting however as upstream devices would have to remain in some level of power state to report events For more information on ACPI refer to the Advanced Configuration and Power Interface Specification at http www teleport com acpi 35 TEXAS INSTRUMENTS 42 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PC Card controller programming model This section describes the PCI1211 PCI configuration registers that make up the 256 byte PCI configuration header for each 1211 function PCI configuration registers The configuration header is compliant with the PCI specification as a CardBus bridge header and is PC98 99 compliant as well Table 16 shows the PCI configuration header which includes both the predefined portion of the configuration space and the user definable registers Table 16 PCI Configuration Registers PM data BMGs bridge Support Power management control status extensions Reserved 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 43 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 vendor ID register us 2 n o 9 te fs ist stati to Vendor ID Name fend petam o o o
47. pullup resistors must be implemented on VCCDO and VCCD1 When the interface is detected the SBDETECT bit in the system control register is set The SBDETECT bit is cleared by a write back of 1 The 1211 implements a two pin serial interface with one clock signal SCL and one data signal SDA SCL signal is mapped to the MFUNC4 terminal and the SDA signal is mapped to the MFUNC1 terminal The 1211 drives SCL at nearly 100 kHz during data transfers which is the maximum specified frequency for standard mode 126 Figure 8 illustrates an example application implementing the two wire serial bus 2 Pullup resistors are required on the SCL and SDA signals Serial Other Serial A weak 43 pullup resistor EEPROM Device is implemented on VCCDO and VCCD1 terminals to enable the serial EEPROM interface Figure 8 Serial EEPROM Application Some serial device applications may include PC Card power switches ZV source switches card ejectors or other devices that may enhance the user s PC Card experience The serial EEPROM device and PC Card power switches are discussed in the sections that follow serial bus interface protocol The SCL and SDA signals are bidirectional open drain signals and require pullup resistors as shown in Figure 8 1211 supports up to 100 kb s data transfer rate and is compatible with standard mode 12 using seven bit addressing All data trans
48. used to indicate the next item in the linked list of the PCI power management capabilities Because the PCI1211 functions include only one capabilities item this register returns 05 when read 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 69 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 power management capabilities register 15 14 t9 12 f t0 9 8 7 e s ja 3 2 1 0 Power management capabilities JR R petan o Pt s 1 tt tate topo 110 Register Power management capabilities Type Read only see individual bit descriptions Offset A2h Default 7E21h Description This register contains information on the capabilities of the PC Card function related to power management Both 1211 CardBus bridge functions support DO D2 and power states See Table 29 for a complete description of the register contents Table 29 Power Management Capabilities Register SIGNAL TYPE FUNCTION PME support This 5 bit field indicates the power states from which the PCI1211 supports asserting PME A 0 for any bit indicates that the CardBus function cannot assert PME from that power state These five bits return 01111b when read Each of these bits is described below 15 11 _ Bit 15 contains the value 0 indicating that PME cannot be asserted from D3cold state
49. write indicator bit must be set and the REQBUSY bit in the serial bus control and status register must be polled until clear Then the contents of the serial bus data register are valid read data from the serial bus interface See Table 38 for a complete description of the register contents Table 38 Serial Bus Slave Address Register SIGNAL TYPE FUNCTION 7 1 SLAVADDR R W Serial bus slave address This bit field represents the slave address of a read or write transaction on the serial interface Read write command Bit 0 indicates the read write command bit presented to the serial bus on byte read and write accesses RWEMD BAN 0 byte write access is requested to the serial bus interface 1 A byte read access is requested to the serial bus interface 35 TEXAS INSTRUMENTS 78 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 serial bus control and status register B T J s 2 9 j Name Serial bus control and status aw A R w awc Register Serial bus control and status Type Read only Read Write Read Write to Clear see individual bit descriptions Offset B3h Default 00h Description This register is used to communicate serial bus status information and select the quick command protocol The REQBUSY bit in this register must be polled during serial bus byte reads to indicate when data is valid in th
50. 033A OCTOBER 1998 socket mask register gt so 28 27 25 24 2s 22 zt 20 19 18 17 16 Socket mask pS oeketmaske 222 pea 0 0 Socket mask m jn ew mw petan o o yo Register Socket mask Type Read only Read Write see individual bit descriptions Offset CardBus socket address 04h Default 0000 0000h Description This register allows software to control the CardBus card events that generate a status change interrupt The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register See Table 56 for a complete description of the register contents Bit 15 14 t3 12 f 9 8 7 e s ja ts 2 1 0 Table 56 Socket Mask Register SIGNAL TYPE FUNCTION RSVD Reserved Bits 31 4 return Os when read Power cycle Bit 3 masks the PWRCYCLE bit in the socket present state register from causing a status change interrupt BOMINES n 0 PWRCYCLE event does not cause CSC interrupt default 1 PWRCYCLE event causes CSC interrupt R Card detect mask Bits 2 1 mask the CDETECT1 and CDETECT2 bits in the socket present state register from causing a CSC interrupt 00 Insertion removal do
51. 11h 19h 21h 29h 31h gu 7 6 5 4 3 2 1 o ExCA memory window 0 4 start address high byte R W 7 we Aw w aw Aw Aw AW AW Register ExCA memory window 0 start address high byte Offset CardBus socket address 811h ExCA offset 11h Register ExCA memory window 1 start address high byte Offset CardBus socket address 819h ExCA offset 19h Register ExCA memory window 2 start address high byte Offset CardBus socket address 821h ExCA offset 21h Register ExCA memory window 3 start address high byte Offset CardBus socket address 829h ExCA offset 29h Register ExCA memory window 4 start address high byte Offset CardBus socket address 831h ExCA offset 31h Type Read Write Default 00h Size One byte Description These registers contain the high nibble of the 16 bit memory window start address for memory windows 0 1 2 3 and 4 The lower four bits of these registers correspond to bits 23 20 of the start address In addition the memory window data width and wait states are set in this register See Table 49 for a complete description of the register contents Table 49 Memory Window 0 4 Start Address High Byte Register Index 11h 19h 21h 29h 31h SIGNAL TYPE FUNCTION Data size Bit 7 controls the memory window data width This bit is encoded as DATASIZE R W 0 Window data width is 8 bits default 1 Window data width is 16 bits R W Zero wait sta
52. 124 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 69 PC Card Address Hold Time tha 8 Bit and 16 Bit PCI Cycles TS1 0 01 WAIT STATE BITS PCLK ns Memory WS1 0 2 60 Memory WS1 1 3 90 timing requirements over recommended ranges of supply voltage and operating free air temperature memory cycles for 100 ns common memory see Note 8 and Figure 27 Lemma 1 ee gy _Setuptine CET and CEBbetoreWEOEIow Soup time before Setup time REG before WE OE low 78 299 m ips Propagation delay time WEOE owo WAT fe Pulse duration WEGE 9 Lm Hedime WEE SSCS S T Cid Lus Setup time ead CDATATS CDATAO vaid betore OE Ng th Hold time read CDATA15 CDATAO valid after OE high 79 9 nmn Cus Setup time wie CDATATS CDATAO valdbeforeWElow m o m NOTE 8 These times are dependent on the register settings associated with ISA wait states and data size They are also dependent on cycle type read write and WAIT from PC Card The times listed here represent absolute minimums the times that would be observed if programmed for zero wait state 16 bit cycles with a 33 MHz PCI clock timing requirements over recommended ranges of supply voltage and operating free air temperature
53. 1998 BIT SIGNAL TYPE FUNCTION YV socket Bit 31 indicates whether or not the socket can supply Vcc Y Y V to PC Cards The PCI1211 31 YVSOCKET does not support Y Y V Vcc therefore this bitis always reset unless overridden by the socket force event XV socket Bit 30 indicates whether or not the socket can supply Vcc V to PC Cards The PCI1211 30 XVSOCKET does not support X X V Vcc therefore this bit is always reset unless overridden by the socket force event register 5 V socket Bit 28 indicates whether or not the socket can supply Vcc 5 V to PC Cards The PCI1211 28 5VSOCKET does support 5 V Vcc therefore this bit is always set unless overridden by the socket force event register 27 14 RSVD 13 YVCARD 3VCARD R 3 V card Bit 11 indicates whether or not the PC Card inserted in the socket supports Voc 3 3 V 5VCARD 5 V card Bit 10 indicates whether or not the PC Card inserted in the socket supports Vcc 5 V Bad Vcc request Bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage 0 Normal operation default 1 Invalid Vcc request by host software Table 57 Socket Present State Register m register 3 V socket Bit 29 indicates whether or not the socket can supply Voc 3 3 V to PC Cards The PCI1211 29 3VSOCKET does support 3 3 V Vcc therefore this bit is always set unless overridden by the socket force event register XVCARD R XV card Bit 12
54. 211 allows memory read transactions to burst upstream 0 Upstream memory read burst is disabled default 1 Upstream memory read burst is enabled MRBURSTUP Socket activity status When set bit 13 indicates access has been performed to or from a PC card and is cleared upon read of this status bit This bit is socket dependent 0 No socket activity default 1 Socket activity Reserved Bit 12 returns 1 when read This is the power rail bit SOCACTIVE RSVD een 12 3 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 59 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 21 System Control Register Continued SIGNAL TYPE FUNCTION Power stream in progress status bit When set bit 11 indicates that a power stream to the power switch 11 PWRSTREAM is in progress and a powering change has been requested This bit is cleared when the power stream is complete Power up delay in progress status When set bit 9 indicates that a power up stream has been sent 10 DELAYUP to the power switch and proper power may not yet be stable This bit is cleared when the power up delay has expired Power down delay in progress status When set bit 10 indicates that a power down stream has been DELAYDOWN sent to the power switch and proper power may not yet be stable This bit is cleared when the power down delay has expired Interrogation in
55. 3 12 vt v0 9 8 7 j e Ps 4 3 2 1 0 Secondary status Tyee Awe R R R R n m R peau o o j o jo y o o jt yo ojo 060 0 Register Secondary status Type Read only Read Write to Clear see individual bit descriptions Offset 16h Default 0200h Description This register is compatible with the PCI to PCI bridge secondary status register and indicates CardBus related device information to the host system This register is very similar to the PCI status register offset 06h and status bits are cleared by writing a 1 See Table 19 for the complete description of the register contents Table 19 Secondary Status Register SIGNAL TYPE FUNCTION CBPARITY R WC Detected parity error Bit 15 is set when a CardBus parity error is detected either address or data sit d eee CB SPEED CDEVSEL timing These bits encode the timing of CDEVSEL and are hardwired 01b indicating that the PCI1211 asserts SPEED at a medium speed CardBus data parity error detected 0 The conditions for setting bit 8 have not been met 1 data parity error occurred and the following conditions were met a CPERR was asserted on the CardBus interface b The PCI1211 was the bus master during the data parity error c The parity error response bit is set in the bridge control CB DPAR R WC CBFBB CAP Fast back to back capable The PC
56. 3 R B2 B3 support for D3hot This bit returns a 1 when read RSVD R Reserved These bits return 05 when read power management data register seo 7 e 5 4 3 2 1 0 Name Power management data Register Power management data Type Read only Offset A7h Default 00h Description This register returns zeros when read since the CardBus functions do not report dynamic data TEXAS INSTRUMENTS 72 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 general purpose event status register git 1a tts r2 v wo j 9 j e je js ja 3 2 1 Power management control status we awc a AWC A A Jawe 5 wwe we Tnwc wc AWC pem o o o o o o o o o o elo o e lee Register General purpose event status Type Read only Read Write to Clear see individual bit descriptions Offset A8h Default 0000h Description This register contains status bits that are set when events occur that are controlled by the general purpose control register The bits in this register and the corresponding GPE are cleared by writing a 1 to the corresponding bit location The status bits in this register do not depend upon the state of a corresponding bit in the general purpose enable register See Table 32 for a complete description of the register contents Table 32 General Purpose Event Status Register SIGNAL
57. 998 Terminal Functions Continued CardBus PC Card interface control TERMINAL 1 0 NANE PIN NUMBER TYPE FUNCTION PGE GGU CAUDIO 134 B5 CardBus audio CAUDIO is a digital input signal from a PC Card to the system speaker The PCI1211 supports the binary audio mode and outputs a binary signal from the card to SPKROUT CBLOCK 1 vo CardBus lock CBLOCK is used to gain exclusive access to a target CardBus detect 1 and CardBus detect 2 CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type CardBus device select 1211 asserts CDEVSEL to claim a CardBus cycle as the target CDEVSEL 107 device As a CardBus initiator on the bus the 1211 monitors CDEVSEL until a target responds If no target responds before timeout occurs the 1211 terminates the cycle with an initiator abort CardBus cycle frame CFRAME is driven by the initiator of a CardBus bus cycle CFRAME is asserted to indicate that a bus transaction is beginning and data transfers continue while this signal is asserted When CFRAME is deasserted the CardBus bus transaction is in the final data phase CardBus bus grant CGNT is driven by the PCI1211 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed D6 CardBus interrupt CINT is asserted low by a CardBus PC Card to request interrupt servicing from
58. A OCTOBER 1998 ring indicate continued PC Card Socket RI OUT Figure 18 RI OUT Functional Diagram RI from the 16 bit PC Card interface is masked by the ExCA control bit RINGEN in the interrupt and general control register This is programmed on a per socket basis and is only applicable when a 16 bit card is powered in the socket The CBWAKE signaling to OUT is enabled through the same mask as the CSC event for CSTSCHG The mask bit CSTSMASK is programmed through the socket mask register in the CardBus socket registers PCI power management PCIPM The PCI power management PCIPM specification establishes the infrastructure required to let the operating system control the power of PCI functions This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus The PCI bus and the PCI functions can be assigned one of four software visible power management states that result in varying levels of power savings The four power management states of PCI functions are DO Fully on state Di and D2 Intermediate states D3 Off state Similarly bus power states of the PCI bus are The bus power states are derived from the device power state of the originating bridge device For the operating system OS to power manage the device power states on the PCI bus the PCI function should support four power management operations These operations
59. Bit 14 contains the value 1 indicating that PME can be asserted from D3po state Bit 18 contains the value 1 indicating that PME can be asserted from D2 state Bit 12 contains the value 1 indicating that PME can be asserted from D1 state Bit 11 contains the value 1 indicating that PME can be asserted from the DO state 10 D2 D2 support Bit 10 returns a 1 when read indicating that the CardBus function supports the D2 device B power state D1 CAP D1 support Bit 9 returns a 1 when read indicating that the CardBus function supports the D1 device power state 8 6 RSVD O R Reserved These bits return 000b when read Device specific initialization Bit 5 returns 1 when read indicating that the CardBus controller function require special initialization beyond the standard PCI configuration header before the generic class device driver is able to use it power source This bit returns 0 when read indicating that the function supplies its own auxiliary power source PME clock Bit 3 returns 0 when read indicating that no host bus clock is required for the PCI1211 to PMECLK generate PME Version Bits 2 0 return 001b when read indicating that there are four bytes of general purpose power 2 0 VERSION management PM registers as described in the PC Bus Power Management Interface Specification Revision 1 0 35 TEXAS INSTRUMENTS 70 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU
60. CVS1 CAD20 CVS2 CAD21 DEVSEL Voc CAD22 FRAME Voc CAD23 GND Voc CAD24 GND CAD25 GND CAD26 GND CAD27 GND CAD28 GND CAD29 GND CAD30 GND CAD31 GNT CAUDIO IDSEL CBLOCK IRDY CC BEO MFUNCO MFUNC1 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 3 16 Bit PC Card Signal Names Sorted BGA Terminal Numbert PIN NO PIN NO PIN NO PIN NO SIGNAL NAME SIGNAL NAME SIGNAL NAME SIGNAL NAME GGU PGE GGU PGE GGU PGE GGU PGE WE 92 L4 42 GND C11 106 G10 12 105 20 G11 CE2 AD9 C13 104 A14 G12 A10 D1 AD27 G13 VCCCB AD2 D2 28 H1 PCLK OUT PME D3 GND H2 GND D4 AD29 H3 AD19 MFUNC4 D5 WP IOIST6 H4 AD18 SUSPEND D6 READY IREQ D7 CD1 D7 A1 D3 D8 A4 D15 SERR 9 VS2 CET PAR AD17 AD14 AD16 AD11 C BE2 AD8 FRAME AD6 D5 AD4 BVD2 SPKR D13 GND GND D6 SPKROUT REG D14 IRDY MFUNC6 RESET VPPD1 A7 TRDY VCCD1 A23 AD12 C BET A16 AD10 AD15 A21 AD7 AD13 AD30 AD1 AD31 MFUNCO C BEO D9 MFUNC2 AD5 DO D11 AD3 BVD1 STSCHG RI GND ADO VS1 D4 MFUNC1 A2 D12 MFUNC3 DEVSEL MFUNC5 A6 STOP VPPDO GND PERR VCCDO t The PGE LQFP pin numbers are shown also 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 9 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 4 16 Bit
61. DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PC Card PARAMETER MEASUREMENT INFORMATION cD 101516 X 4 T20 gt 2 4 6 14 gt lt T18 T21 p IORD IOWR EM lt T15 gt 4 T17 gt gt 7194 WAIT MAE i T25 T26 9 CDATA15 CDATAO ___ T23 4 T24 gt CDATA15 CDATAO read E ene With no wait state With wait state Figure 28 PC Card Cycle BVD2 T27 SPKROUT IREQ lt T28 IRQ15 IRQ3 Y Figure 29 Miscellaneous PC Card Delay Times 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 127 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 MECHANICAL DATA PGE S PQFP G144 PLASTIC QUAD FLATPACK 0 13 NOM zeae 4 Gage Plana 20 20 cq 19 80 22 20 0 05 MIN 21 80 sQ Seating Plane 1 60 MAX lt 0 08 4040147 11 96 NOTES A All linear dimensions in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 TEXAS INSTRUMENTS 128 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 MECHANICAL DATA GGU S PBGA N144 PLASTIC BALL GRID ARRAY
62. Data Byte 0 Slave acknowledgement M Master acknowledgement S P Start stop condition Figure 14 EEPROM Interface Doubleword Data Collection 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 33 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 accessing serial bus devices through software 1211 provides a programming mechanism to control serial bus devices through software The programming is accomplished through a doubleword of PCI configuration space at offset BOh Table 11 illustrates the registers used to program a serial bus device through software Table 11 1211 Registers Used to Program Serial Bus Devices h BOH Serial bus dela Contains the data byte to send on write commands or the received data byte on read commands BIH bus dox The content of this register is sent as the word address on byte writes or reads This register is not used in the quick command protocol Serial bus slave Writes to this register initiate a serial bus transaction The slave device address and the RW address command selector are programmed through this register B3H Serial bus control Read data valid general busy and general error status are communicated through this register and status In addition the protocol select bit is programmed through this register B2H programmable interrupt subsystem Interrupts provide a way for I O devices to let t
63. ER 1998 PC Card cycle timing The PC Card cycle timing is controlled by the wait state bits in the Intel 82365SL DF compatible memory and I O window registers The PC Card cycle generator uses the PCI clock to generate the correct card address setup and hold times and the PC Card command active low interval This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL DF timing as possible while always slightly exceeding the Intel 82365SL DF values This ensures compatibility with existing software and maximizes throughput The PC Card address setup and hold times are a function of the wait state bits Table 66 shows address setup time in PCLK cycles and nanoseconds for I O and memory cycles Table 67 and Table 68 show command active time in PCLK cycles and nanoseconds for I O and memory cycles Table 69 shows address hold time in PCLK cycles and nanoseconds for I O and memory cycles Table 66 PC Card Address Setup Time 15 8 Bit 16 Bit PCI Cycles TS1 0 01 WAIT STATE BITS PCLK ns Memory WS1 0 2 60 Memory WS1 1 4 120 Table 67 PC Card Command Active Cycle Time 8 Bit PCI Cycles WAIT STATE BITS TS1 0 01 ws Zws PCLK ns Po o 39m io EN 720 s 959 w 3 7e Table 68 PC Card Command Active Cycle Time 16 Bit PCI Cycles WAIT STATE BITS TS1 0 01 ws zws torno e 7m io NA m Fw 3
64. EXAS INSTRUMENTS 118 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 recommended operating conditions see Note 3 OPERATION Now UNT Voc Supply voltage core Commercial 3 3 3 3 6 3 3 475 5 525 475 3 5 6 5 25 Commercial V PCI VCCI Miscellaneous clamping voltage 3 3 V Vint High level input voltage PC Card misct lt CD Pins 3 3 V 0 0 3V Ed CCP 3 3 V 0 0 325V um Lee 7j CCCB 058 Input voltage Fail safe 0 m PCCard Fail safe 0 Input transition time tr and tf Miscellaneous and fail safe Operating ambient temperature range P 0 25 70 Virtual junction temperature PF 0 25 115 t Applies to external inputs and bidirectional buffers without hysteresis Miscellaneous pins are 70 62 59 60 61 64 65 67 68 and 69 for the PGE packaged device and L11 M9 L8 K8 N9 K9 N10 L10 N11 and M11 for the GGU packaged device SUSPEND SPKROUT RI OUT multifunction terminals MFUNCO MFUNCS and power switch control pins Fail safe pins are 75 117 131 and 137 for the PGE packaged device and L12 D9 C6 and A4 for the GGU packaged device card detect and voltage sense pins CD Pins are 75 and 137 fT Applies to external output buffers These junction temperatures reflect simulation conditions The customer is responsible for verifying junction temperat
65. Extended addressing This feature is not supported by the PCI1211 and always returns a 0 DDMA registers decode enable Enables the decoding of the distributed DMA registers based on the value of DMABASE 0 Disabled default 1 Enabled Transfer size Bits 2 1 specify the width of the DMA transfer on the PC Card interface and are encoded as 00 Transfers are 8 bits default 2 1 XFERSIZE R W 01 Transfers are 16 bits 10 Reserved 11 Reserved B DDMAEN 35 TEXAS INSTRUMENTS 68 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 capability ID register 7 e s a s 2 j 1 227 R R j R R pem o o o o o Register Capability ID Type Read only Offset AOh Default 01h Description This register identifies the linked list item as the register for PCI power management The register returns 01h when read which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value next item pointer register gp v s s jJ j s 2 Name NexHempomer 2 02 Next item pointer mee mu J m R petam 0 o o o jo 0 Register Next item pointer Type Read only Offset Ath Default 00h Description This register is
66. Figure 17 is a signal diagram of the suspend function 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 39 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 suspend mode continued RST SUSPEND External Terminals Internal Signals RSTIN SUSPENDIN Figure 17 Signal Diagram of Suspend Function ring indicate The RI OUT output is an important feature in power management and is basically used so that a system can go into a suspended mode and wake up on modem rings and other card events RI OUT on the PCI1211 can be asserted under any of the following conditions A 16 bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call A powered down CardBus card asserts CSTSCHG CBWAKE requesting system and interface wake up ACSC event occurs such as insertion removal of cards battery voltage levels CSTSCHG from a powered CardBus card is indicated as a CSC event not as CBWAKE event These two RI OUT events are enabled separately Figure 15 shows various enable bits for the PCI1211 RI OUT function however it does not show the masking of CSC events See interrupt masks and flags on page 36 for a detailed description of CSC interrupt masks and flags 35 TEXAS INSTRUMENTS 40 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033
67. I bus initiator and asserts FRAME the latency timer begins counting from zero If the latency timer expires before the PCI121 1 transaction has terminated the PCI121 1 terminates the transaction when its GNT is deasserted header type register 7 6 5 4 3 2 1 90 Header type Name mwe j BR R petan o o o o o o 1 9 Register Header type Type Read only Offset OEh Default 02h Description This register returns 02h when read indicating that the PCI1211 configuration spaces adhere to the CardBus bridge PCI header The CardBus bridge PCI header ranges from PCI register to 7Fh leaving 80 is user definable extension registers BIST register Register BIST Type Read only Offset OFh Default 00h Description Because the PCI1211 does not support a built in self test BIST this register returns the value of 00h when read 35 TEXAS INSTRUMENTS 48 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 CardBus socket registers ExCA registers base address register m Ja 2 e 6 ams address 0 CardBus socket ExCA registers base address Name Hye Rw mw nuw Rw n Rn n in Jn n eam o o 0 0 0 0 0 0 0
68. I1211 cannot accept fast back to back transactions thus bit 7 is hardwired to 0 CB UDF User definable feature support The PCI1211 does not support the user definable features thus bit 6 is hardwired to 0 5 CB66MHZ 66 MHz capable The PCI1211 CardBus interface operates at a maximum CCLK frequency of 33 MHz therefore bit 5 is hardwired to 0 RSVD Reserved Bits 4 0 return Os when read 35 TEXAS INSTRUMENTS 50 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PCI bus number register m 7 2 ams 2 2 R W R W R W R W R W R W R W R W Register PCI bus number Type Read Write Offset 18h Default 00h Description This register is programmed by the host system to indicate the bus number of the PCI bus to which the 1211 is connected PCI1211 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses CardBus bus number register 7 6 s 2 o CardBus bus number Register CardBus bus number Type Read Write Offset 19h Default 00h Description This register is programmed by the host system to indicate the bus number of the CardBus bus to which the 1211 is connected The PCI1211 uses this register in conjunction with the PCI bus numbe
69. ICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 21 System Control Register SIGNAL TYPE FUNCTION Serialized PCI interrupt routing step Bits 31 30 are used to configure the serialized PCI interrupt stream signaling and accomplish an even distribution of interrupts signaled on the four PCI interrupt Slots Bits 31 30 are encoded as follows 31 30 SER STEP R W 00 INTA is signaled in the INTA IRQSER slot 01 INTA is signaled in the INTB IRQSER slot 10 INTA is signaled in the INTC IRQSER slot 11 INTA is signaled in the INTD IRQSER slot 29 27 RSVD R Reserved These bits return 05 when read SMI interrupt routing Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket 26 SMIROUTE RAY 0 PC Card power change interrupts routed to IRQ2 default 1 A CSC interrupt is generated on PC Card power changes SMI interrupt status This socket dependent bit is set when a write occurs to set the socket power and the SMIENB bit is set Writing a 1 to bit 25 clears the status 0 SMI interrupt signaled default 1 SMI interrupt not signaled SMISTATUS SMI interrupt mode enable When bit 24 is set the SMI interrupt signaling is enabled and generates an interrupt when a write to the socket power control occurs This bit defaults to 0 disabled Reserved This bit returns 0 when read CardBus reserved terminals signaling Wh
70. IROUTE SMI route This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2 SMISTAT SMI status This bit is set when an SMI interrupt is pending This status flag is cleared by writing back a 1 SMIENB SMI interrupt mode enable When set SMI interrupt generation is enabled If CSC SMI interrupts are selected then the SMI interrupt is sent as the CSC The CSC interrupt can be either level or edge mode depending upon the CSCMODE bit in the ExCA global control register If IRQ2 is selected by SMIROUTE the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ Data slot In a parallel ISA IRQ system the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC1 MFUNC3 MFUNCS6 through the multifunction routing register power management overview In addition to the low power CMOS technology process used for the PCI1211 various features are designed into the device to allow implementation of popular power saving techniques These features and techniques are discussed in this section CLKRUN protocol The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1211 CLKRUN signalling is provided through the MFUNC6 terminal Since some chipsets do not implement CLKRUN this is not always available to the system designer alternate power savings features are provided For details on the CLKRUN protocol refer to the PCI Mobile Design Guide
71. In addition the write protection and commonr attribute memory configurations are set in this register See Table 51 for a complete description of the register contents Table 51 Memory Window 0 4 Offset Address High Byte Register Index 15h 1Dh 25h 2Dh 35h Write protect Bit 7 specifies whether write operations to this memory window are enabled This bit is encoded as 0 Write operations are allowed default 1 Write operations are not allowed Bit 6 specifies whether this memory window is mapped to card attribute common memory This bit is encoded as 0 Memory window is mapped to common memory default 1 Memory window is mapped to attribute memory Offset address high byte Bits 5 0 represent the upper address bits 25 20 of the memory window offset address 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 99 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA I O window 0 and 1 offset address low byte register index 36h 38h 7 6 5 4 3 2 1 90 wowo offsetaddressiowbyte R W R W R W R W Register ExCA I O window 0 offset address low byte Offset CardBus socket address 836h ExCA offset 36h Register ExCA I O window 1 offset address low byte Offset CardBus socket address 838h ExCA offset 38h Type Read only Read Write see description Default 00h Size One byte Descri
72. JR R RJ JR RJ R RJ R R R R R R peut 0 0 0 0 15 14 t9 12 9 8 7 e Ps ja s 2 1 0 Socket DMA register 1 Name 222 SoetDMAregisteri 0 2 Hype RW RW Raw rw Raw ew fw mw RW R Rw RW Fw Detam o o 9 p 9 Register Socket DMA register 1 Type Read only Read Write see individual bit descriptions Offset 98h Default 0000 0000h Description This register provides control over the distributed DMA DDMA registers and the PCI portion of DMA transfers The DMA base address locates the DDMA registers in a 16 byte region within the first 64K bytes of PCI I O address space See Table 28 for a complete description of the register contents NOTE 32 bit transfers are not supported the maximum transfer possible for 16 bit PC Cards is 16 bits Table 28 Socket DMA Register 1 SIGNAL FUNCTION 31 16 RSVD Reserved Bits 31 16 return Os when read DMA base address Locates the socket s DMA registers in PCI I O space This field represents a 16 bit 15 4 DMABASE R W PCI I O address The upper 16 bits of the address are hardwired to 0 forcing this window to within the lower 64K bytes of I O address space The lower 4 bits are hardwired to 0 and are included in the address decode Thus the window is aligned to a natural 16 byte boundary EXTMODE
73. ME EN 4 Bit 8 enables the function to assert PME If this bit is cleared assertion of PME RSVD Reserved Bits 7 5 return Os when read 4 DYN DATA PME Dynamic data PME enable Bit 4 returns 0 when read since the CardBus function does not report dynamic data RSVD OR Reserved Bits 3 2 return 05 when read Power state This 2 bit field is used both to determine the current power state of a function and to set the function into a new power state This field is encoded as 00 DO 1 0 PWR_STATE R W 01 D1 10 D2 11 D3hot 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 71 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 power management control status register bridge support extensions 7 6 5 4 3 2 1 90 Name Power management control status register bridge support extensions w 8 R pee 1 1 59 o o o o Register Power management control status register bridge support extensions Type Read only Offset A6h Default COh Description The power management control status register bridge support extensions supports PCI bridge specific functionality See Table 31 for a complete description of the register contents Table 31 Power Management Control Status Register Bridge Support Extensions SIGNAL TYPE FUNCTION BPCC EN Bus power clock control When read bit 7 returns a 1 6 8282
74. NAL 1 0 NANE PIN NUMBER TYPE FUNCTION PGE GGU MFUNCO MFUNC1 EIE Multifunction Terminal 0 MFUNCO can be configured as parallel PCI interrupt INTA GPIO GPOO GPE socket activity LED output ZV output select CardBus audio PWM or a parallel IRQ Refer to the multifunction routing register description on page 61 for configuration details Multifunction Terminal 1 MFUNC1 can be configured as GPI1 GPO1 GPE socket activity LED output ZV output select CardBus audio PWM or a parallel IRQ Refer to the multifunction routing register description on page 61 for configuration details Serial Data SDA When the serial bus mode is implemented by pulling up the SCA and SCL terminals the MFUNC1 terminal provides the SDA signaling The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset Refer to the serial bus interface protocol description on page 30 for details on other serial bus applications Multifunction Terminal 2 MFUNC2 can be configured as PC PCI DMA Request GPI2 GPO2 socket activity LED output ZV output select CardBus audio PWM GPE RI OUT or a parallel IRQ Refer to the multifunction routing register description on page 61 for configuration details Multifunction Terminal 3 MFUNCS can be configured as a parallel IRQ or the serialized interrupt signal IRQSER Refer to the multifunction routing register description on page 61 for configuration de
75. OCTOBER 1998 status register 5 1 2 9 9 8 7 6 5 4 3 2 1 0 Status Hype Rwc Rwo Rwe awe Rn n aA R AR PR JR petam o o fo o jo 1 1 Register Status Type Read only Read Write to Clear see individual bit descriptions Offset 06h Default 0210h Description This register provides device information to the host system Bits in this register may be read normally A bit in the status register is reset when a 1 is written to that bit location a O written to a bit location has no effect All bit functions adhere to the definitions in the Local Bus Specification Revision 2 2 PCl bus status is shown through each function See Table 18 for the complete description of the register contents Table 18 Status Register SIGNAL TYPE FUNCTION PAR ERR R WC Detected parity error Bit 15 is set when a parity error is detected either address or data SYS ERR RWG pu system error Bit 14 is set when SERR is enabled and the PCI1211 signals a system error to the 13 MABORT B WC Received master abort Bit 13 is set when a cycle initiated by the PCI1211 on the PCI bus has been terminated by a master abort 12 TABT REC R wC Received target abort Bit 12 is set when a cycle initiated by the PCI1211 on the PCI bus was terminated by a target abort T TABT SIG RWG Signaled target abort Bit 11 is set by the 1211 when it terminates a transact
76. ODE bit is encoded as IFCMODE 0 Host interrupt is edge mode default 1 Host interrupt is level mode Interrupt flag clear mode select Bit 2 selects the interrupt flag clear mechanism for the flags in the EXCA card status change register This bit is encoded as 0 Interrupt flags are cleared by read of CSC register default 1 Interrupt flags are cleared by explicit write back of 1 1 Host interrupt is level mode Power down mode select When bit 0 is set to 1 the PCI1211 is in power down mode In power down mode the PCI1211 card outputs are 3 stated until an active cycle is executed on the card interface Following an active cycle the outputs are again 3 stated The PCI1211 still receives DMA requests functional interrupts and or card status change interrupts however an actual card access is required to wake up the interface This bit is encoded as 0 Power down mode is disabled default 1 Power down mode is enabled Card status change level edge mode select Bit 1 selects the signaling mode for the PCI1211 hostinterrupt for card status changes This bit is encoded as GSCMODE 0 Host interrupt is edge mode default PWRDWN 35 TEXAS INSTRUMENTS 102 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA memory window 0 4 page register Bu 7 e 5 4 3 2 1 9 Name ExCA memory window 0 4 page R W R W R W R W R
77. PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Terminal Functions Continued The interface system address and data and interface control terminals for the CardBus PC Card system are shown in the following three tables CardBus PC Card interface system TERMINAL yo NAME PIN NUMBER TYPE FUNCTION PGE GGU CardBus PC Card clock CCLK provides synchronous timing for all transactions on the CardBus interface All signals except CRST CLKRUN CINT CSTSCHG CAUDIO CCD2 and CCLK CVS2 CVS1 are sampled on the rising edge of CCLK and all timing parameters are defined with the rising edge of this signal CCLK operates at the PCI bus clock frequency but it can be stopped in the low state or slowed down for power savings CGLKRUN 136 D5 CardBus PC Card clock run COLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency and by the PCI1211 to indicate that the CCLK frequency is going to be decreased CardBus PC Card reset CRST is used to bring CardBus PC Card specific registers sequencers CRST 119 B9 and signals a known state When CRST is asserted all CardBus PC Card signals must be 3 stated and the PCI1211 drives these signals to a valid logic level Assertion be asynchronous to CCLK but deassertion must be synchronous to CCLK 35 TEXAS INSTRUMENTS 18 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Termin
78. PCII211fH v RS PC 98 99 Compliant PCI Bus Power Management Interface Specification 1 0 Compliant Advanced Configuration and Power Interface ACPI 1 0 Compliant Fully Compatible With the Intel 430TX Mobile Triton II Chipset PCI Local Bus Specification Revision 2 2 Compliant 1997 Standard Compliant 3 3 V Core Logic With Universal PCI Interfaces Compatible With 3 3 V and 5 V PCI Signaling Environments Mix and Match 5 V 3 3 V PC Card16 Cards and 3 3 V CardBus Cards Supports a Single PC Card or CardBus Slot With Hot Insertion and Removal Provides Interface to Parallel Single Slot PC Card Power Interface Switches like the TI TPS2211 Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and the CardBus Bus Supports Parallel PCI Interrupts Parallel ISA IRQ and Parallel PCI Interrupts Serial ISA IRQ With Parallel PCI Interrupts and Serial ISA IRQ and PCI Interrupts Pin to Pin Compatible with 1210 Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Pipelined Architecture Allows Greater Than 130M Bytes Per Second Throughput From CardBus to PCI and From PCI to CardBus Supports Up to Five General Purpose I Os Five PCI Memory Windows and Two I O Windows Available to the PC Card16 Socket Two I O Windows and Two Memory Windows Availab
79. PKR or CAUDIO through the 1211 from the PC Card interface SPKROUT is driven as the exclusive OR combination of card SPKR CAUDIO inputs 35 TEXAS INSTRUMENTS 14 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Terminal Functions Continued The address and data and interface control terminals for the 16 bit PC Card are shown in the following two tables 16 bit PC Card address and data TERMINAL PIN NUMBER FUNCTION GGU NAME PC Card address 16 bit PC Card address lines A25 is the most significant bit PC Card data 16 bit PC Card data lines D15 is the most significant bit 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 15 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Terminal Functions Continued 16 bit PC Card interface control TERMINAL 1 0 NANE PIN NUMBER TYPE FUNCTION PGE GGU Battery voltage detect 1 BVD1 is generated by 16 bit memory PC Cards that include batteries BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card Both BVD1 and BVD2 are kept high when the battery is good When BVD2 is low and BVD1 is high the battery is weak and should be replaced When BVD1 is low the battery is no longer serviceable BVD1 and the data in the memory PC Card is lost See ExCA card status change interrupt configuration STSCHG RI 135 regis
80. RQ7 Parallel ISA type 1000 IRQ8 Parallel ISA type 1001 IRQS Parallel ISA type 1010 IRQ10 Parallel ISA type 1011 IRQ11 Parallel ISA type 1100 IRQ12 Parallel ISA type 1101 IRQ13 Parallel ISA type 1110 IRQ14 Parallel ISA type 1111 2 IRQ15 Parallel ISA type 35 TEXAS INSTRUMENTS 62 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 22 Multifunction Routing Register Continued SIGNAL TYPE FUNCTION Multifunction terminal 2 configuration These bits control the internal signal mapped to the MFUNC2 terminal as follows 0000 2 General purpose input default 0001 GPO2 General purpose output 0010 PCREQ PC PCI centralized DMA request 0011 IRQ3 Parallel ISA type 0100 IRQ4 Parallel ISA type 0101 IRQS Parallel ISA type 0110 ZVSTAT Zoom video status output TIS MUNG 0111 ZVSELO Zoom video select output 1000 CAUDPWM PWM output of CAUDIO CardBus terminal 1001 IRQS Parallel ISA type 1010 IRQ10 Parallel ISA type 1011 IRQ11 Parallel ISA type 1100 RI_OUT Ring indicate output 1101 IRQ13 Parallel ISA type 1110 GPE General purpose event signal 1111 IRQ7 Parallel ISA type Multifunction terminal 1 configuration These bits control the internal signal mapped to the MFUNC1 terminal as follows NOTE When the serial bus mode is implemented by pulling up the VPPDO and VPPD1 terminals the MFUNC1 termin
81. S TEXAS 75265 31 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 serial bus interface protocol continued Slave Address Word Address Data Byte S fee ns ee vo oz o1 oo o A or oo os ne oo o2 os oo A or os fa os we uo e RAW A z Slave acknowledgement S P Start stop condition Figure 11 Serial Bus Protocol Byte Write Figure 12 illustrates a byte read operation The read protocol is very similar to the write protocol except the R W command bit must be set to one to indicate a read data transfer In addition the PCI1211 master must acknowledge reception of the read bytes from the slave transmitter The slave transmitter drives the SDA signal during read data transfers The SCL signal remains driven by the PCI1211 master Slave Address Word Address Data Byte S fee ns ee vo oz o1 oo v A or oo os ns oo o2 os on A or no os ne wa ez es foo m e R W A Slave acknowledgement M Master acknowledgement S P Start stop condition Figure 12 Serial Bus Protocol Byte Read serial bus EEPROM application When the PCI bus is reset and the serial bus interface is detected the PCI1211 attempts to read the subsystem identification and other register defaults from a serial EEPROM The registers and corresponding bits that may be loaded with defaults through the EEPROM are provided in Table 10 Table 10 Registers and
82. TYPE FUNCTION B WC PC card ZV Status Bit 15 is set on a change in status of the ZVENABLE bit in the PC card controller function of the PCI1211 Reserved These bits return Os when read Power change status Bit 11 is set when software has changed the power state the socket A change in either Vcc or Vpp for the socket causes this bit to be set 10 9 RSVD Reserved These bits return 0s when read eme 7 unis Thess run Oswhen ea 7s er s sts awo GPs Stats Bis set ona chang caus ofthe MFUNGH ternal eri sts awo Status Bi T seton a chang isa ofthe MFUNCTmmnal uiu ___ ssi awo GP Stats BO seton a change aa fhe MFUNGDerinl 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 73 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 general purpose event enable register 15 14 t9 12 f t0 9 8 7 e js ja 3 2 1 0 General purpose event enable r Rw n few a r n rw rw nw mw mw pee o o o 1 090 090 9 0 Register General purpose event enable Type Read only Read Write see individual bit descriptions Offset AAh Default 0000h Description This register contains bits that are set to enable a GPE signal The GPE signal is driven until the corresponding status bit is cleared and the even
83. ace The 1211 is fully compliant with the PCI Local Bus Specification Revision 2 2 The 1211 provides all required signals for PCI master or slave operation and may operate in either 5 V or 3 3 V signaling environment by connecting the Vccp terminals to the desired voltage level In addition to the mandatory PCI signals the PCI1211 provides the optional interrupt signal INTA PCI bus lock LOCK The bus locking protocol defined in the PCI specification is not highly recommended but is provided on the PCI1211 as an additional compatibility feature The PCI LOCK signal can be routed to the MFUNCA terminal via the multifunction routing register see the multifunction routing register description on page 61 for details Note that the use of LOCK is only supported by PCI to CardBus bridges in the downstream direction away from the processor PCI LOCK indicates an atomic operation that may require multiple transactions to complete When LOCK is asserted nonexclusive transactions can proceed to an address that is not currently locked A grant to start a transaction on the PCI bus does not guarantee control of LOCK control of LOCK is obtained under its own protocol It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock An agent may need to do an exclusive operation because
84. ads return the last data value written GPIO3 Data Bit The value written to bit 3 represents the logical value of the data driven to the GPOSEDATA MFUNC4 terminal if configured as GPO3 Reads return the last data value written GPO2 Data Bit The value written to bit 2 represents the logical value of the data driven to the GPO2 DATA MFUNC2 terminal if configured as GPO2 Reads return the last data value written 1 1 R W GPO 1 Data Bit The value written to bit 1 represents the logical value of the data driven to the MFUNC1 terminal if configured as GPO1 Reads return the last data value written GPOO Data Bit The value written to bit 0 represents the logical value of the data driven to the MFUNCO terminal if configured as GPOO Reads return the last data value written GPOO DATA 35 TEXAS INSTRUMENTS 76 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 serial bus data register m 7 s 2 1 ams R W R W R W R W R W R W R W R W Register Serial bus data Type Read Write Offset BOh Default 00h Description This register is for programmable serial bus byte reads and writes This register represents the data when generating cycles on the serial bus interface To write a byte this register must be programmed with the data the serial bus index register must be programmed with the byte address and th
85. al Functions Continued CardBus PC Card address and data TERMINAL PIN NUMBER FUNCTION PGE NAME PC Card address and data These signals make up the multiplexed CardBus address and data bus on the CardBus interface During the address phase of a CardBus cycle CAD31 CADO contain a 32 bit address During the data phase of a CardBus cycle CAD31 CADO contain data CAD31 is the most significant bit CardBus bus commands and byte enables CC BES CC BEO are multiplexed on the same CardBus terminals During the address phase of a CardBus cycle CC BE3 CC BEO defines the bus command CC BE2 During the data phase this 4 bit bus is used as byte enables The byte enables determine which byte paths of the full 32 bit data bus carry meaningful data CC BEO applies to byte 0 CAD7 CADO CC BE1 CC BEO applies to byte 1 CAD15 CAD8 CC BE2 applies to byte 2 CAD23 CAD16 and CC BES applies to byte CAD31 CAD24 CardBus parity In all CardBus read and write cycles the PCI1211 calculates even parity across the CAD and CC BE buses As an initiator during CardBus cycles the PCI1211 outputs CPAR with a one CCLK delay As a target during CardBus cycles the calculated parity is compared to the initiator s parity indicator a compare error results in a parity error assertion 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1
86. al provides the SDA signaling 0000 GPI1 General purpose input default 0001 GPO1 General purpose output 0010 IRQ2 Parallel ISA type 0011 IRQ3 Parallel ISA type 0100 IRQ4 Parallel ISA type MENGI RUW 0101 IRQ5 Parallel ISA type 0110 ZVSTAT Zoom video status output 0111 ZVSELO Zoom video select output 1000 CAUDPWM PWM output of CAUDIO CardBus terminal 1001 IRQS Parallel ISA type 1010 IRQ10 Parallel ISA type 1011 IRQ11 Parallel ISA type 1100 LED_SKT Socket activity LED 1101 IRQ13 Parallel ISA type 1110 GPE General purpose event signal 1111 IRQ15 Parallel ISA type Multifunction terminal 0 configuration These bits control the internal signal mapped to the MFUNCO terminal as follows 0000 GPIO General purpose input default 0001 GPOO General purpose output 0010 INTA PCI interrupt signal INTA 0011 IRQ3 Parallel ISA type 0100 IRQ4 Parallel ISA type 0101 IRQS Parallel ISA type 0110 ZVSTAT Zoom video status output oo MEUNGO iud 0111 ZVSELO Zoom video select output 1000 CAUDPWM PWM output of CAUDIO CardBus terminal 1001 IRQS Parallel ISA type 1010 IRQ10 Parallel ISA type 1011 IRQ11 Parallel ISA type 1100 LED_SKT Socket activity LED 1101 IRQ13 Parallel ISA type 1110 GPE General purpose event signal 1111 IRQ15 Parallel ISA type 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 63 1211 GGU PGE PC CARD CONTROLLERS
87. and PC Card detect 2 CD1 and CD2 are internally connected to ground on the PC Card When a PC Cardis inserted into a socket CD1 and CD2 are pulled low For signal status see interface status register Card enable 1 and card enable 2 CE1 and CE2 enable even and odd numbered address bytes CE1 enables even numbered address bytes and CE2 enables odd numbered address bytes Input acknowledge INPACK is asserted by the PC Card when it can respond to an read cycle at the current address DMA request INPACK can be used as the DMA request signal during DMA operations from a 16 bit PC Card that supports DMA If used as a strobe the PC Card asserts this signal to indicate a request for a DMA operation read IORD is asserted by the PCI1211 to enable 16 bit PC Card data output during host I O read cycles DMA write IORD is used as the DMA write_strobe during DMA operations from a 16 bit PC Card that supports DMA The PCI1211 asserts IORD during DMA transfers from the PC Card to host memory write IOWR is driven low by the PCI1211 to strobe write data into 16 bit I O PC Cards during host I O write cycles DMA read IOWR is used as the DMA write strobe during DMA operations from a 16 bit PC Card that supports DMA The 1211 asserts IOWR during transfers from host memory to the PC Card Output enable OE is driven low by the PCI1211 to enable 16 bit memory PC Card data output during host memory read cycles DMA terminal c
88. ard a CardBus cycle to PCI The lower 16 bits of this register locate the top of the I O window within a 64K byte page and the upper 16 bits are a page register which locates this 64K byte page in 32 bit PCI I O address space Bits 15 2 are read write and allow the I O limit address to be located anywhere the 64K byte page indicated by bits 31 16 of the appropriate I O base on doubleword boundaries Bits 31 16 always return Os when read The page is set in the I O base register Bits 1 0 always return Os when read forcing I O windows to be aligned on natural doubleword boundary Writes to read only bits have no effect The PCI1211 assumes that the lower 2 bits of the limit address are 15 NOTE The I O base or the I O limit register must be nonzero to enable an O transaction 35 TEXAS INSTRUMENTS 54 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 interrupt line register gu o o7 d e 5 4 J 3 2 1 9 Interrupt line R W R W R W R W R W R W R W R W a ee E E Register Interrupt line Type Read Write Offset 3Ch Default FFh Description This register is used to communicate interrupt line routing information interrupt pin register gs 7 e s 4 2 1 9 Name 7 5 Wiemptpn 22 4 Interrupt Register Interrupt pin Type Read only Offset 3Dh Default 01h Descriptio
89. are Capabilities reporting Power status reporting Setting the power state System wake up The OS identifies the capabilities of the PCI function by traversing the new capabilities list The presence of new capabilities is indicated by a 1 in the capabilities list CAPLIST bit in the status register bit 4 and providing access to a capabilities list The capabilities pointer provides access to the first item in the linked list of capabilities For the PCI1211 CardBus bridge with PCI configuration space header type 2 the capabilities pointer is mapped to an offset of 14h The first byte of each capability register block is required to be a unique ID of that capability PCI power management has been assigned an ID of 01h The next byte is a pointer to the next pointer item in the list of capabilities If there are no more items in the list the next item pointer should be set to 0 The registers following the next item pointer are specific to the function s capability The PCIPM capability implements the register block outlined in Table 15 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 41 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PCI power management PCIPM continued Table 15 Power Management Registers REGISTER NAME OFFSET Power management capabilities Next item pointer Capability ID PMCSR bridge support extensions Power management control status CSR
90. artially inserted CDETECT1 Battery voltage detect When a 16 bit memory card is inserted the field indicates the status of the battery voltage detect signals BVD1 BVD2 at the PC Card interface where bit 1 reflects the BVD2 status and bit 0 reflects BVD1 00 Battery dead 01 Battery dead 10 Battery low warning 11 Battery good When a 16 bit I O card is inserted this field indicates the status of SPKR bit 1 and STSCHG bit 0 at the PC Card interface In this case the two bits in this field directly reflect the current state of these card outputs E o BVDSTAT 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 85 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA power conirol register index 02h 7 e s 4 s 2 1 09 Name ExCA power control w A A aw Aw A Aw AW Register ExCA power control Type Read only Read Write see individual bit descriptions Offset CardBus socket address 802h ExCA offset 02h Default 00h Description This register provides PC Card power control Bit 7 of this register controls the 16 bit output enables on the socket interface and can be used for power management in 16 bit PC Card applications See Table 43 for a complete description of the register contents Table 43 Power Control Register Index 02h Card output enable Bit 7 controls the state of all of the 16 b
91. be programmed to accept fast posted writes to improve system bus utilization Multiple system interrupt signaling options are provided including parallel PCI parallel ISA serialized ISA and serialized PCI Furthermore general purpose inputs and outputs are provided for the board designer to implement sideband functions Many other features are designed into the PCI1211 such as socket activity light emitting diode LED output that are discussed in detail throughout the design specification An advanced complementary metal oxide semiconductor CMOS process achieves low system power consumption while operating at PCI clock rates up to 33 MHz Several low power modes enable the host power management system to further reduce power consumption Unused PCI1211 inputs must be pulled up using a 43 resistor 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 system block diagram A simplified system block diagram using the PCI1211 is provided below The PCI950 IRQ deserializer and the PCI930 zoomed video ZV switch are optional functions that can be used when the system requires that capability The PCI interface includes all address data and control signals for PCI protocol The 68 pin PC Card interface includes all address data and control signals for CardBus and 16 bit R2 protocols When ZV is enabled in 16 bit PC Card mode 23 of the 68 sig
92. ce is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
93. ch the card memory space is mapped These windows are defined by start end and offset addresses programmed in the ExCA registers described in this section Table 40 identifies each ExCA register and its respective ExCA offset Memory windows 4K byte granularity 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 81 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 40 ExCA Registers and Offsets PCI MEMORY ADDRESS ExCA REGISTER NAME OFFSET HEX ExCA OFFSET HEX Identification and revision 800 Interface status 801 Power control 802 Interrupt and general control 803 Card status change 804 Card status change interrupt configuration 805 Address window enable 806 O window control 807 O window 0 start address low byte 808 O window 0 start address high byte 809 1 O window 0 end address low byte 80A O window 0 end address high byte 80B window 1 start address low byte 80C O window 1 start address high byte 80D 1 O window 1 end address low byte 80E 1 O window 1 end address high byte 80F Memory window 0 start address low byte 810 Memory window 0 start address high byte 811 Memory window 0 end address low byte 812 Memory window 0 end address high byte 813 Memory window 0 offset address low byte 814 Memory window 0 offset address high byte 815 Card detect and general control 816 Reserved 817 Memory window 1 start address low byte 818 Memory windo
94. cket address 807h ExCA offset 07h Default 00h Description This register contains parameters related to I O window sizing and cycle timing See Table 48 for a complete description of the register contents Table 48 ExCA I O Window Control Register Index 07h SIGNAL TYPE FUNCTION I O window 1 wait state Bit 7 controls the I O window 1 wait state for 16 bit I O accesses Bit 7 has no effect on 8 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 16 bit cycles have standard length default 1 16 bit cycles are extended by one equivalent ISA wait state WAITSTATE1 I O window 1 zero wait state Bit 6 controls the I O window 1 wait state for 8 bit I O accesses Bit 6 has no effect on 16 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 8 bit cycles have standard length default 1 8 bit cycles are reduced to equivalent of three ISA cycles ZEROWS1 I O window 1 101516 source Bit 5 controls the I O window automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I O data transfer This bit is encoded as 0 Window data width determined by DATASIZE1 bit 4 default 1 Window data width determined by IOIS16 window 1 data size Bit 4 controls the I O window 1 data size Bit 4 is ignored if the I O window 1 IOIS16 source bit bit 5 i
95. controller PIC or to some circuitry that provides parallel PCI interrupts to the host 1211 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 Figure 15 Example of IRQ Implementation Power on software is responsible for programming the multifunction routing register to reflect the IRQ configuration of a system implementing the PCI1211 Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals The parallel ISA type IRQ signaling from the MFUNC6 MFUNCO terminals is compatible with those input directly into the 8259 PIC The parallel IRQ option is provided for system designs that require legacy ISA IRQs There may be design constraints that demand more MFUNC6 MFUNCO IRQ terminals than the PCI1211 makes available A system designer may choose to implement an IRQSER deserializer companion chip such as the Texas Instruments PCI950 To use a deserializer the MFUNCS terminal must be configured as IRQSER and connected to the deserializer which outputs all 15 ISA IRQ s and four PCI interrupts as decoded from the IRQSER stream using parallel PCI interrupts Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode parallel ISA IRQ signaling mode and when only IRQs are serialized with the IRQSER protocol The socket function interrupts are routed to INTA MFUNCO using serialized IROSER interrupts The serialized interrupt p
96. d outputs 0 Serial bus interface not detected 1 Serial bus interface detected ROMBUSY SBDETECT R WC Serial bus test When bit 2 is set the serial bus clock frequency is increased for test purposes SBTEST R W 0 Serial bus clock at normal operating frequency 100 kHz default 1 Serial bus clock frequency increased for test purposes Requested serial bus access error Bit 1 indicates when a data error occurs on the serial interface during a requested cycle and may be set due to a missing acknowledge Bit 1 is cleared by a write back of 1 REQ_ERR R WC 0 No error detected during user requested byte read or write cycle 1 Data error detected during user requested byte read or write cycle EEPROM data error status Bit 0 indicates when a data error occurs on the serial interface during the auto load from the serial bus EEPROM and may be set due to a missing acknowledge Bit 0 is also set on invalid EEPROM data formats Refer to serial bus interface on page 30 for details on EEPROM data R WC MEN 2 format Bit 0 is cleared by a write back of 1 0 No error detected during auto load from serial bus EEPROM 1 Data error detected during auto load from serial bus EEPROM ROM_ERR SIGNAL rime 6 Rsv T T sve HE 3 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 79 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA compatibility regi
97. dBus target s ability to complete the current data CTRDY phase of the transaction A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted until this time wait states are inserted 131 CardBus voltage sense 1 and CardBus voltage sense 2 CVS1 and CVS2 are used in conjunction 117 E with CCD1 and to identify card insertion and interrogate cards to determine the operating voltage and card type 35 TEXAS INSTRUMENTS 20 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 power supply sequencing 1211 contains 3 3 V I O buffers with 5 V tolerance requiring a core power supply and clamp voltage The core power supply is always 3 3 V The clamp voltage can be either 3 3 V or 5 V depending on the interface The following power up and power down sequences are recommended The power up sequence is 1 Apply 3 3 V power to the core 2 Assert PRST to the device to disable the outputs during power up Output drivers must be powered up in the high impedance state to prevent high current levels through the clamp diodes to the 5 V supply 3 Apply the clamp voltage The power down sequence is 1 Use PRST to switch outputs to a high impedance state 2 Remove the clamp voltage 3 Remove the 3 3 V power from the core I O characteristics Figure 1 shows a 3 state bidirectional buffer The recommended operating conditio
98. ddress register contents are presented on AD15 ADO of the PCI bus during the address phase Bits 7 0 of the page register are presented on AD23 AD16 of the PCI bus during the address phase For the 16 bit DDMA transfer mode the current address register contents are presented on AD16 AD1 of the PCI bus during the address phase ADO is driven to logic 0 Bits 7 1 of the page register are presented on AD23 AD17 ofthe PCI bus during the address phase and bit 0 is ignored DDMA page register 7 e s 46 s 2 1 Register DDMA page Type Read Write Offset DDMA base address 02h Default 00h Size One byte Description This register is used to set the upper byte of the address of a DDMA transfer Details of the address represented by this register are explained in DDMA current address base adaress register 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 113 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 DDMA current count base count register 12 11 DDMA current count base count Register DDMA current count base count Type Read Write Offset DDMA base address 04h Default 0000h Size Two bytes Description This register is used to set the total transfer count in bytes of a direct memory transfer Reads to this register indicate the current count of a direct memory transfer In the 8 bit transfer mode the coun
99. dicates the status of RI Battery warning change When 16 bit memory is installed the socket bit 1 indicates whether the source of a PCI1211 interrupt was due to a battery low warning condition This bit is encoded as 1 BATWARN 0 No battery warning condition default 1 Detected battery warning condition When a 16 bit I O card is installed bit 1 is always 0 35 TEXAS INSTRUMENTS 88 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA card status change interrupt configuration register index 05h 7 e s s 2 1 Name ExCA status change interrupt configuration Register ExCA card status change interrupt configuration 0 Read Write see individual bit descriptions Offset CardBus socket address 805h ExCA offset 05h Default 00h Description This register controls interrupt routing for card status change interrupts as well as masking CSC interrupt sources See Table 46 for a complete description of the register contents Table 46 ExCA Card Status Change Interrupt Configuration Register Index 05h SIGNAL TYPE FUNCTION Interrupt select for card status change Bits 7 4 select the interrupt routing for card status change interrupts 0000 CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register PCI Offset 93h is set to 1b In this case bit 4 of 803 is
100. e cleared by PCI reset They can be immediately set again if when coming out of PC Card reset the bridge finds the status unchanged i e CSTSCHG reasserted or card detect is still true Software must clear this register before enabling interrupts If itis not cleared when interrupts are enabled an interrupt is generated but not masked based on any bit set See Table 55for a complete description of the register contents Table 55 Socket Event Register SIGNAL TYPE FUNCTION RSVD O R Reserved Bits 31 4 return Os when read 3 PWREVENT R wC Power cycle Bit 3 is set when the PCI1211 detects that the PWRCYCLE bit in the socket present state register has changed This bit is cleared by writing a 1 CCD2 Bit 2 is set when the PCI1211 detects that the CDETECT2 field in the socket present state CD2EVENT register has changed This bit is cleared by writing a 1 CCD1 Bit is set when the PCI1211 detects that the CDETECT1 field in the socket present state CDIEVENT RING register has changed This bit is cleared by writing a 1 CSTSCHG Bit 0 is set when the CARDSTS field in the socket present state register has changed state CSTSEVENT R WC For CardBus cards bit 0 is set on the rising edge of CSTSCHG For 16 bit PC Cards bit 0 is set on both transitions of CSTSCHG This bit is reset by writing a 1 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 105 1211 GGU PGE PC CARD CONTROLLERS SCPS
101. e no effect 2 GPI2 DATA GPI2 Data Bit The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal Writes have no effect 1 GPM DATA GPI1 Data Bit The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal Writes have no effect GPIO DATA GPIO Data Bit The value read from bit 0 represents the logical value of the data input from the MFUNCO terminal Writes have no effect 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 75 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 general purpose output register 15 14 t3 12 f t0 9 8 v e js ja 2 1 0 General purpose output mwe n n nw mw petan o o 1 090 090 9 0 Register General purpose output Type Read only Read Write see individual bit descriptions Offset AEh Default 0000h Description This register is used for control of the general purpose outputs See Table 35 for a complete description of the register contents Table 35 General Purpose Output Register SIGNAL TYPE FUNCTION RSVD Reserved Bits 15 5 return Os when read Writes have effect GPOA Data Bit The value written to bit 4 represents the logical value of the data driven to the GPOA DATA MFUNCS5 terminal if configured as GPO4 Re
102. e serial bus data register See Table 39 for a complete description of the register contents Table 39 Serial Bus Control and Status Register SIGNAL TYPE FUNCTION Protocol select When bit 7 is set the send byte protocol is used on write requests and the receive byte R W protocol is used on read commands The word address byte in the serial bus index register is not output by the PCI1211 when bit 7 is set Reserved Bit 6 returns 0 when read Requested serial bus access busy Bit 5 indicates that a requested serial bus access byte read or write is in progress A request is made and bit 5 is set by writing to the serial bus slave address register Bit 5 must be polled on reads from the serial interface After the byte read access has been requested the read data is valid in the serial bus data register m Serial EEPROM Busy status Bit 4 indicates the status of the PCI1211 serial EEPROM circuitry Bit 4 is BIT PROT SEL RSVD REQBUSY set during the loading of the subsystem ID and other default values from the serial bus EEPROM 0 Serial EEPROM circuitry is not busy 1 Serial EEPROM circuitry is busy Serial bus detect When bit 3 is set it indicates that the serial bus interface is detected Pullup resistors must be implemented on the MFUNC1 and MFUNCA SDA and SCL terminals for bit 3 to be set If bit 3 is reset then the MFUNC4 and MFUNC1 terminals can be used for alternate functions such as general purpose inputs an
103. e serial bus slave address must be programmed with both the 7 bit slave address and the read write indicator bit must be reset On byte reads the byte address is programmed into the serial bus index register the serial bus slave address must be programmed with both the 7 bit slave address and the read write indicator bit must be set and the REQBUSY bit in the serial bus control and status register must be polled until clear Then the contents of this register are valid read data from the serial bus interface See Table 36 for a complete description of the register contents Table 36 Serial Bus Data Register SIGNAL TYPE FUNCTION 7 0 SBDATA R W Serial bus data This bit field represents the data byte in a read or write transaction on the serial interface On reads the REQBUSY bit must be polled to verify that the contents of this register are valid serial bus index register 7 e 5 4 s 2 0 Serial bus index Register Serial bus index Type Read Write Offset Bih Default 00h Description This register is for programmable serial bus byte reads and writes This register represents the byte address when generating cycles on the serial bus interface To write a byte the serial bus data register must be programmed with the data this register must be programmed with the byte address and the serial bus slave address must be programmed with both the 7 bit slave address and the read write indicator On
104. e to CardBus CSERR enable Bit 1 controls the response of the PCI1211 to CSERR signals on the CardBus bus This R bit is common between the two sockets R W R W R W R W R W R W R W ISAEN R W AN CSERREN 0 CSERR is not forwarded to PCI SERR 1 CSERR is forwarded to PCI SERR CPERREN 0 CardBus parity errors are ignored 1 CardBus parity errors are reported using CPERR CardBus parity error response enable Bit 0 controls the response of the 11211 to CardBus parity errors This bit is common between the two sockets ki TEXAS INSTRUMENTS 56 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 subsystem vendor ID register pt 14 t3 12 f 9 8 7 6 5 4 2 1 0 Subsystem vendor ID Name 2 SubssemvedorID S in Jn Rn n pea o o 0 Register Subsystem vendor ID Type Read only read write when bit 5 in the system control register is 0 Offset 40h Default 0000h Description This register is used for system and option card identification purposes and may be required for certain operating systems This register is read only or read write depending on the setting of bit 5 SUBSYSRW in the system control register When bit 5 is 0 this register is read write when bit 5 is 1 this re
105. ed similarly to an 8237 controller and the 1211 awaits a DREQ assertion from the PC Card requesting a DMA transfer DMA writes transfer data from the PC Card to PCI memory addresses The PCI1211 accepts data 8 or 16 bits at a time depending on the programmed data width and then requests access to the PCI bus by asserting its REQ signal Once granted the PCI bus and the bus returns to an idle state The 1211 initiates a PCI memory write command to the current memory address and transfers the data in a single data phase After terminating the PCI cycle the 1211 accepts the next byte s from the PC Card until the transfer count expires DMA reads transfer data from PCI memory addresses to the PC Card application Upon the assertion of DREQ the PCI1211 asserts REQ to acquire the PCI bus Once granted the bus and the bus is idle the PCI1211 initiates a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data depending on the programmed data width After terminating the PCI cycle the data is passed on to the PC Card After terminating the PC Card cycle the PCI1211 requests access to the PCI bus again until the transfer count has expired The 1211 target interface acts normally during this procedure and accepts I O reads and writes to the registers While a DDMA transfer is in progress and the host resets the DMA channel the PCI1211 asserts TC and ends the PC Card cycle s TC is
106. efault 1 Centralized DMA enabled 6 INSTRUMENTS 60 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 multifunction routing register gt so 29 28 27 26 25 24 23 22 2t 20 19 18 17 16 Multifunction routing Rw Rw Raw mw Raw peat o o o Fo 0 0 gt 14 t3 12 Wf v0 9 8 v je Ps ja 2 1 0 Multifunction routing petan o o o fo Register Multifunction routing Type Read only Read Write see individual bit descriptions Offset 8Ch Default 0000 0000h Description This register is used to configure the MFUNCO MFUNCE6 terminals These terminals may be configured for various functions All multifunction terminals default to the general purpose input configuration Pullup resistors are required for terminals configured as outputs This register is intended to be programmed once at power on initialization The default value for this register may also be loaded through a serial bus EEPROM See Table 22 for a complete description of the register contents Table 22 Multifunction Routing Register SIGNAL TYPE FUNCTION 31 28 RSVD Reserved These bits return 05 when read Multifunct
107. either parallel IRQs or serialized IRQs as detailed in the sections that follow All interrupt signalling is provided through the seven multifunction terminals MFUNCO MFUNCS PC Card functional and card status change interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially defined signals on the PC Card interface Functional interrupts are generated by 16 bit PC Cards and by CardBus PC Cards Card status change 5 interrupts are defined as events at the PC Card interface that are detected by the 1211 and may warrant notification of host card and socket services software for service CSC events include both card insertion and removal from PC Card sockets as well as transitions of certain PC Card signals Table 12 summarizes the sources of PC Card interrupts and the type of card associated with them CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket The three types of cards that can be inserted into any PC Card socket are 16 bit memory card 16 bit I O card CardBus cards 34 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PC Card functional and card status change interrupts continued Table 12 Interrupt Mask and Flag Registers Battery conditions ExCA of
108. en bit 22 is set the RSVD CardBus terminals are driven low when a CardBus card is inserted When this bit is low as default these signals 3 stated 0 3 state CardBus RSVD 1 Drive Cardbus RSVD low default SMIENB RSVD CBRSVD Vcc protection enable 0 Vcc protection enabled for 16 bit cards default 1 Vcc protection disabled for 16 bit cards Reduced Zoom Video Enable When this bit is enabled 25 22 of the card interface for PC Card 16 cards is placed in the high impedance state This bit should not be set for normal ZV operation This bit is encoded as 0 Reduced zoom video disabled default 1 Reduced zoom video enabled PC PCI DMA card enable When bit 19 is set the PCI1211 allows 16 bit PC Cards to request PC PCI R W A VCCPROT e REDUCEZV DMA using the DREQ signaling DREQ is selected through the socket DMA register 0 0 Ignore DREQ signaling from PC Cards default 1 Signal DMA request on DREQ PC PCI DMA channel assignment Bits 18 16 are encoded as 0 3 8 bit DMA channels 4 PCI master not used default 5 7 16 bit DMA channels Memory read burst enable downstream When bit 15 is set memory read transactions are allowed to burst downstream 0 Downstream memory read burst is disabled 1 Downstream memory read burst is enabled default CDREQEN CDMACHAN MRBURSTDN Memory read burst enable upstream When bit 14 is set the PCI1
109. ents Table 41 ExCA Identification and Revision Register Index 00h 7 6 Interface type These bits which hardwired as 10b identify the 16 bit PC Card support provided by the 11211 PCI1211 supports both I O and memory 16 bit PC cards RSVD Reserved Bits 5 4 can be used for Intel 82365SL DF emulation Intel 82365SL DF revision This field stores the Intel 82365SL DF revision supported by the PCI1211 Host 3 0 365REV R W software can read this field to determine compatibility to the Intel 82365SL DF register set This field defaults to 0100b upon PCI1211 reset 35 TEXAS INSTRUMENTS 84 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA interface status register index 01h Epp T 4 31 13 J 9 Jj Name ExCA interface status po EXOAmtaests R R R pem x x x j x x Register ExCA interface status Type Read only see individual bit descriptions Offset CardBus socket address 801h ExCA offset 01h Default 00XX XXXXb Description This register provides information on the current status of the PC Card interface An X in the default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface See Table 42 for a complete description of the register contents Table 42 ExCA Interface Status Registe
110. erted Until IRDY and TRDY are both sampled asserted wait states are inserted PCI parity error indicator PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register PCI bus request REQ is asserted by the PCI1211 to request access to the PCI bus as an initiator PCI system error SERR is an output that is pulsed from the PCI1211 when enabled through the command register indicating a system error has occurred The PCI1211 need not be the target of the PCI cycle to assert this signal When SERR is enabled in the control register this signal also pulses indicating that an address parity error has occurred on a CardBus interface PCI cycle stop signal STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers PCItarget ready TRDY indicates the primary bus target s ability to complete the current data phase ofthe transaction A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted Until both IRDY and TRDY are asserted wait states are inserted 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 13 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Terminal Functions Continued multifunction and miscellaneous pins TERMI
111. es not cause CSC interrupt default el CDMASK RAY 01 Reserved undefined 10 Reserved undefined 11 Insertion removal causes CSC interrupt CSTSCHG mask Bit 0 masks the CARDSTS field in the socket present state register from causing a CSC interrupt 0 CARDSTS event does not cause CSC interrupt default 1 CARDSTS event causes CSC interrupt 35 TEXAS INSTRUMENTS 106 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Socket present state register Socket present state Name R R R R R RJRJ R iR Jn R n R o o o fo x x Register Type Offset Default Description Socket present state Read only CardBus socket address 08h 3000 00XXh This register reports information about the socket interface Writes to the socket force event register are reflected here as well as general socket interface status Information about PC Card Vcc support and card type is updated only at each insertion Also note that the PCI121 1 uses CCD1 and CCD2 during card identification and changes on these signals during this operation are not reflected in this register See Table 57 for a complete description of the register contents 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 107 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER
112. escription The Texas Instruments 1211 is a high performance PCI to PC Card controller that supports a single PC Card socket compliant with the 1995 PC Card Standard The PCI1211 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers The 1997 PC Card Standard retains the 16 bit PC Card specification defined in PCMCIA Release 2 2 and defines the new 32 bit PC Card CardBus capable of full 32 bit data transfers at 33 MHz The PCI1211 supports both 16 bit and CardBus PC Cards powered at 5 V or 3 3 V as required The 1211 is compliant with the PCI Local Bus Specification Revision 2 2 and its PCI interface can act as either a PCI master device or a PCI slave device The PCI bus mastering is initiated during 16 bit PC Card direct memory access DMA transfers or CardBus PC Card bridging transactions The PCI1211 is also compliant with the latest PCI Bus Power Management Interface Specification Revision 1 0 All card signals are internally buffered to allow hot insertion and removal without external buffering The PCI1211 is register compatible with the Intel 82365SL DF ExCA controller The PCI1211 internal data path logic allows the host to access 8 16 and 32 bit cards using full 32 bit PCI cycles for maximum performance Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting The 1211 can also
113. ess has occurred This bit is cleared by a read access 25 SISTBOGES 0 A PC card access has not occurred default 1 PC card access has occurred Socket mode status This bit provides clock mode information 24 SKTMODE 0 Clock is operating normally 1 Clock frequency has changed 23 17 RSVD Reserved Bits 23 17 return 0s when read CardBus clock control enable When bit 16 is set clock control CLKCTRL bit 0 is enabled CLKCTRLEN R W 0 Clock control is disabled default 1 Clock control is enabled RSVD Reserved Bits 15 1 return 05 when read CardBus clock control The bit determines whether the CB CLKRUN protocol will attempt to stop or slow the CB clock during idle states Bit 16 enables this bit RW 0 Allows CB CLKRUN protocol to stop the CB clock default 1 Allows CB CLKRUN protocol to slow the CB clock by a factor of 16 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 111 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 distributed DMA DDMA registers The DMA base address programmable in PCI configuration space at offset 98h points to a 16 byte region in PCI I O space where the DDMA registers reside The names and locations of these registers are summarized in Table 61 These 1211 register definitions are identical in function but differ in location to the 8237 DMA controller The similarity between the register models retains some leve
114. et the PC Card when used and the PWRDOWN bit will not Furthermore the PWRDOWN bit is an automatic COE that is the PWRDOWN performs the COE function when there is no card activity NOTE The 16 bit PC Card must implement the proper pullup resistors for the COE and PWRDOWN modes TEXAS INSTRUMENTS 38 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 suspend mode The SUSPEND signal is provided for backward compatibility and gates the PCI reset RST signal from the 1211 However additional functionality has been defined for SUSPEND to provide additional power management options SUSPEND provides a mechanism to gate the PCLK from the 1211 as well as gate RST This can potentially save power while in an idle state however it requires substantial design effort to implement Some issues to consider are What if a card is present in the socket What if the card in the socket is powered How to pass CSC insertion removal events Even without the PCI clock to the PCI1211 core there are asynchronous type functions such as RI OUT that can pass CSC events wake up events etc back to the system Figure 16 is a functional implementation diagram for SUSPEND RST PCI1211 Core SUSPEND dis SUSPENDIN GNT PCLKIN PCLK EXTERNAL SIGNALS INTERNAL SIGNALS Figure 16 SUSPEND Functional Implementation
115. etting a bit is accomplished by one of two methods a read of this register or an explicit write back of 1 to the status bit The choice of these two methods is based on the interrupt flag clear mode select bit 2 in the global control register See Table 45 for a complete description of the register contents Table 45 ExCA Card Status Change Register Index 04h SIGNAL TYPE FUNCTION RSVD R Reserved Bits 7 4 return Os when read Writes have no effect Card detect change Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface This bit is encoded as 0 No change detected either CD1 or CD2 1 Change detected on either CD1 or CD2 READYCHANGE Ready change When a 16 bit memory is installed in the socket bit 2 includes whether the source of a PCI1211 interrupt was due to a change on READY at the PC Card interface indicating that the PC Card is now ready to accept new data This bit is encoded as 0 No low to high transition detected on READY default 1 Detected low to high transition on READY When a 16 bit I O card is installed bit 2 is always 0 Battery dead or status change When a 16 bit memory card is installed in the socket bit 0 indicates whether the source of a PCI1211 interrupt was due to a battery dead condition This bit is encoded as 0 STSCHG deasserted default 1 STSCHG asserted Ring indicate When the PCI1211 is configured for ring indicate operation bit 0 in
116. fers are initiated by the serial bus master The beginning of a data transfer is indicated by a start condition which is signalled when the SDA line transitions to a low state while SCL is in the high state as illustrated in Figure 9 The end of a requested data transfer is indicated by a stop condition which is signalled by alow to high transition of SDA while SCL is in the high state as shown in Figure 9 Data on SDA must remain stable during the high state of the SCL signal as changes on the SDA signal during the high state of SCL is interpreted as control signals that is a start or a stop condition 30 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 serial bus interface protocol continued E CF Start Stop Change of Condition Condition Data Allowed Data Line Stable Data Valid Figure 9 Serial Bus Start Stop Conditions and Bit Transfers Data is transferred serially in 8 bit bytes The number of bytes that may be transmitted during a data transfer is unlimited however each byte must be completed with an acknowledge bit An acknowledge is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal Figure 10 illustrates the acknowledge protocol SCL From Master 1 2 3 22 7 8 9 SDA Output co 555 By Transmitter SDA
117. fset 05h 805h ExCA offset 04h 804h 16 bit BVD1 BVD2 bits 1 and 0 bits 1 and 0 memory Wait states ExCA offset 05h 805h ExCA offset 04h 804h READY bit 2 bit 2 Change in card status ExCA offset 05h 805h ExCA offset 04h 804h STSCHG bit 0 bit 0 16 bit I O Interrupt request configuration offset 91h IREQ All 16 bit complet ExCA offset 05h 805h ExCA offset 04h 804h PC Cards er bit 3 bit 3 Change in card status Socket mask Socket event CSTSCHG bit 0 bit 0 Interrupt request PCI configuration offset 91h CINT Always enabled bit 0 CardBus Powers molet Socket mask Socket event ower cycle complete bit 3 bit 3 Card insertion or Socket mask Socket event removal bits 2 and 1 bits 2 and 1 Functional interrupt events are valid only for 16 bit and CardBus cards that is the functional interrupts are not valid for 16 bit memory cards Furthermore card insertion and removal type CSC interrupts are independent of the card type Table 13 describes the PC Card interrupt events Table 13 PC Card Interrupt Events and Description CARD TYPE EVENT TYPE SIGNAL DESCRIPTION BVD1 STSCHG CSTSCHG 4 2 Battery conditions csc ar attery conditions BVD1 BVD2 A transition on BVD2 indicates a change in the pe RnR PC Card battery conditions A transition on READY indicates a change in CSC READY IREQ CINT the ability of the memory PC Card to accept or provide data 16 bit memor
118. functioning using parallel IRQ interrupts The seven multifunction terminals MFUNC6 MFUNCO implemented in the PCI1211 may be routed to obtain a subset of the ISA IRQs The IRQ choices provide ultimate flexibility in PC Card host interruptions To use the parallel ISA type IRQ interrupt signaling software must program the device control register located at PCI offset 92h to select the parallel IRQ signaling scheme Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals A system using parallel IRQs requires at a minimum one PCI terminal INTA to signal CSC events This requirement is dictated by certain card and socket services software The INTA requirement calls for routing the MFUNCO terminal for INTA signaling This leaves ata maximum six different IRQs to support legacy 16 bit PC Card functions 36 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 using parallel IRQ interrupts continued As an example suppose the six IRQs used by legacy PC Card applications are IRQ3 IRQ4 IRQ5 IRQ10 IRQ11 and IRQ15 The multifunction control register must be programmed to a value of OxOFBA5432 This value routes the MFUNCO terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 15 Not shown is that INTA must also be routed to the programmable interrupt
119. gation See Table 58 for a complete description of the register contents Table 58 Socket Force Event Register SIGNAL TYPE FUNCTION 31 15 RSVD O R Reserved Bits 31 15 return 05 when read 14 CVSTEST W Card VS test When bit 14 is set the PCI1211 reinterrogates the PC Card updates the socket present state register and reenables the socket power control 13 FYVCARD W Force YV card Writes to bit 13 cause the YVCARD bit in the socket present state register to be written When set this bit disables the socket power control FXVCARD Force XV card Writes to bit 12 cause the XVCARD bit in the socket present state register to be written When set this bit disables the socket power control F3VCARD Force 3 V card Writes to bit 11 cause the 3VCARD bit in the socket present state register to be written When set this bit disables the socket power control F5VCARD Force 5 V card Writes to bit 10 cause the 5VCARD bit in the socket present state register to be written When set this bit disables the socket power control FBADVCCREQ Force bad Vcc request Changes to the BADVCCREQ bit in the socket present state register can be made by writing to bit 9 EDATALOST W Force data lost Writes to bit 8 cause the DATALOST bit in the socket present state register to be written FNOTACARD 2 card Writes to bit 7 cause the NOTACARD bit in the socket present state register to 16 RSVD OR Reserved Bit 6 returns 0 when read 5 FCBCARD W Force
120. gister is read only The default mode is read only subsystem ID register pt 14 t3 12 Wt fo 9 8 7 je Ps tats 2 1 0 Subsystem ID R R R R R RJRJ R iR Jn R n RR o o o jo o jo poo jogpjogpjogpo 69 9 Register Subsystem ID Type Read only read write when bit 5 in the system control register is 0 Offset 42h Default 0000h Description This register is used for system and option card identification purposes and may be required for certain operating systems This register is read only or read write depending on the setting of bit 5 SUBSYSRW in the system control register When bit 5 is 0 this register is read write when bit 5 is 1 this register is read only The default mode is read only 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 57 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PC Card 16 bit I F legacy mode base address register m Ts Tz T2 TO RTF legacy mode base address O O O 0 raw RW aw aw Aw Aw AW fo o 5 3 2 1 Name Card 16 bit I F legacy mode base address Tye Rw RW RW RW RW RW RW RW RW RW RW RW petu o o fo fo fo fo fo fo Register PC Card 16 bit I F legacy mode base address Type Read
121. he microprocessor know that they require servicing The dynamic nature of PC Cards and the abundance of PC Card I O applications require substantial interrupt support from the PCI1211 The 1211 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards The ExCA register set provides interrupt control for some 16 bit PC Card functions and the CardBus socket register set provides interrupt control for the CardBus PC Card functions The 1211 is therefore backward compatible with existing interrupt control register definitions and new registers have been defined where required 1211 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols To simplify the discussion of interrupts in the 1211 PC Card interrupts are classified as either card status change 5 or as functional interrupts The method by which any type of PCI1211 interrupt is communicated to the host interrupt controller varies from system to system The PCI1211 offers system designers the choice of using parallel PCI interrupt signaling parallel ISA type IRQ interrupt signaling or the IRQSER serialized ISA and or PCI interrupt protocol It is possible to use the parallel PCI interrupts in combination with
122. idual bit descriptions Offset DDMA base address 08h Default 00h Size One byte Description This register indicates the terminal count and DMA request DREQ status See Table 63 fora complete description of the register contents Table 63 DDMA Status Register SIGNAL TYPE FUNCTION Channel request In the 8237 bits 7 4 indicate the status of DREQ of each DMA channel In the PCI1211 7 4 DREQSTAT these bits indicate the DREQ status of the single socket being serviced by this register All four bits are set when the PC Card asserts DREQ and are reset when DREQ is deasserted The status of the mask bit in the multichannel mask register has no effect on these bits Channel terminal count The 8327 uses bits 3 0 to indicate the TC status of each of its four DMA channels 3 0 In the PCI1211 these bits report information about a single DMA channel therefore all four of these register bits indicate the TC status of the single socket being serviced by this register All four bits are set when the TC is reached by the DMA channel These bits are reset when read or the DMA channel is reset DDMA request register pr Low 5 s dq jJ 5 Name DDMA request Type Ww WwW W w w w w w w w w pea o o j o o o o Register DDMA request Type Write only Offset base address 09h Default 00h Size One byte Descri
123. inal numbers are also listed for convenient reference Terminal numbers are shown for both the PGE LQF package and the GGU ball grid array package TERMINAL FUNCTION PGE NUMBER GGU NUMBER 6 22 42 58 78 94 114 130 B6 10 D3 Device ground terminals 14 30 50 66 86 102 122 B4 C8 D12 F3 H11 K2 L6 Power supply terminal for core logic 3 3 V 138 M10 Clamping voltage for PC Card interface Indicates card signaling environment of 5 V or 3 3 V Clamping voltage for multifunction terminals 5 V or 3 3 V Clamping voltage for PCI signaling 5 V or 3 3 V power supply TERMINAL PIN NUMBER FUNCTION PGE GGU ur Logic controls to the TPS2211 PC Card power interface switch to control AVCC 71 N12 72 12 Logic controls to the 52211 Card power interface switch to control AVPP TERMINAL PIN NUMBER FUNCTION PGE GGU NAME PCI bus clock PCLK provides timing for all transactions on the PCI bus All PCI signals are sampled at the rising edge of PCLK PCI reset When the PCI bus reset is asserted RST causes the PCI1211 to place all output buffers in a high impedance state and reset all internal registers When RST is asserted the device is completely nonfunctional After RST is deasserted the PCI1211 is in its default state When SUSPEND and RST are asserted the device is protected from RST clearing the internal registers All outputs are placed in a high impedance state but the contents of
124. indicated in the DDMA status register At the PC Card interface the PCI1211 supports demand mode transfers The PCI1211 asserts DACK during the transfer unless DREQ is deasserted before TC TC is mapped to the OE PC Card terminal for DMA write operations and is mapped to WE PC Card terminal for DMA read operations The DACK signal is mapped to the PC Card REG signal in all transfers and the DREQ terminal is routed to one of three options which is programmed through socket DMA register 0 PC Card 16 PC PCI DMA Some chipsets provide a way for legacy devices to do DMA transfers on the PCI bus In the PC PCI DMA protocol the PCI1211 acts as a PCI target device to certain DMA related I O addresses The 1211 PCREQ and PCGNT signals are provided as a point to point connection to a chipset supporting PC PCI DMA The PCREQ and PCGNT signals may be routed to the MFUNC2 and MFUNCS terminals respectively Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals Under the PC PCI protocol a PCI DMA slave device such as the 1211 requests a DMA transfer on a particular channel using a serialized protocol on PCREQ The I O DMA bus master arbitrates for the PCI bus and grants the channel through a serialized protocol on PCGNT when it is ready for the transfer The I O cycle and memory cycles are then presented on the PCI bus which perform the DMA transfers similarly to legacy
125. ing ov Waveform 1 50 Vcc see Notes VoL 0 3 V B and C VoL VoH Waveform 2 Von 0 3 V see Notes 50 Vcc B and C 0v VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES 3 STATE OUTPUTS NOTES A Phase relationships between waveforms were chosen arbitrarily All input pulses are supplied by pulse generators having the following characteristics PRR 1 MHz Zo 50 tr 6 ns B Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control C Fortp 7 and VoL and are measured values Figure 23 Load Circuit and Voltage Waveforms 35 TEXAS INSTRUMENTS 122 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PCI BUS PARAMETER MEASUREMENT INFORMATION thigh 2V e tlow HM 0 8 V 2 V MIN Peak to Peak je gt trst gt RSTIN N k tsrst clk D Figure 25 RSTIN Timing Waveforms PCLK 15V tval lt tinv PCI Output Valid ton 9 tsu K th Figure 26 Shared Signals Timing Waveforms 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 123 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOB
126. ion on the PCI bus with a target abort 10 9 PCI SPEED DEVSEL timing These bits encode the timing of DEVSEL and are hardwired 01b indicating that the 1211 asserts PCI SPEED at a medium speed on nonconfiguration cycle accesses Data parity error detected 0 The conditions for setting bit 8 have not been met 1 A data parity error occurred and the following conditions were met BMG a PERR was asserted by PCI device including the 1211 b The 11211 was the bus master during the data parity error c The parity error response bit is set in the command Fast back to back capable 11211 cannot accept fast back to back transactions thus bit 7 is 7 hardwired to 0 UDF User definable feature support The PCI1211 does not support the user definable features thus bit 6 is hardwired to 0 66 MHz capable The PCI1211 operates at a maximum PCLK frequency of 33 MHz therefore bit 5 is 5 66MHZ hardwired to 0 Capabilities list Bit 4 returns 1 when read This bit indicates that capabilities in addition to standard 4 CAPLIST capabilities are implemented The linked list of PCI power management capabilities is implemented in this function RSVD Reserved Bits 3 0 return Os when read TEXAS INSTRUMENTS 46 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 revision ID register
127. ion terminal 6 configuration These bits control the internal signal mapped to the MFUNC6 terminal as follows 0000 RSVD Reserved high impedance input default 0001 CLKRUN PCI clock control signal 0010 IRQ2 Parallel ISA type 0011 IRQ3 Parallel ISA type 0100 IRQ4 Parallel ISA type 0101 IRQS Parallel ISA type 0110 IRQ6 Parallel ISA type 0111 IRQ7 Parallel ISA type 1000 IRQ8 Parallel ISA type 1001 IRQS Parallel ISA type 1010 IRQ10 Parallel ISA type 1011 IRQ11 Parallel ISA type 1100 IRQ12 Parallel ISA type 1101 1RQ13 Parallel ISA type 1110 IRQ14 Parallel ISA type 1111 IRQ15 Parallel ISA type 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 61 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 22 Multifunction Routing Register Continued SIGNAL TYPE FUNCTION Multifunction terminal 5 configuration These bits control the internal signal mapped to the MFUNC5 terminal as follows 0000 GPIA General purpose input default 0001 GPO4 General purpose output 0010 PCGNT PC PCI centralized DMA grant 0011 IRQ3 Parallel ISA type 0100 IRQ4 Parallel ISA type 0101 IRQ5 Parallel ISA type 0110 ZVSTAT Zoom video status output 23720 MEUNGS EWY 0111 ZVSELO Zoom video select output 1000 CAUDPWM PWM output of CAUDIO CardBus terminal 1001 IRQS Parallel ISA type 1010 IRQ10 Parallel ISA type 1011
128. iption These registers contain the low byte of the 16 bit memory window end address for memory windows 0 1 2 3 and 4 The eight bits of these registers correspond to bits A19 A12 of the end address 35 TEXAS INSTRUMENTS 96 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA memory window 0 4 end address high byte register index 13h 1Bh 23h 2Bh 33h gu v 6 5 4 3 2 1 o ExCA memory window 0 4 end address high byte R W aw A Aw Aw AW AW Register ExCA memory window 0 end address high byte Offset CardBus socket address 813h ExCA offset 13h Register ExCA memory window 1 end address high byte Offset CardBus socket address 81Bh ExCA offset 1Bh Register ExCA memory window 2 end address high byte Offset CardBus socket address 823h ExCA offset 23h Register ExCA memory window 3 end address high byte Offset CardBus socket address 82Bh ExCA offset 2Bh Register ExCA memory window 4 end address high byte Offset CardBus socket address 833h ExCA offset 33h Type Read only Read Write see individual bit descriptions Default 00h Size One byte Description Theseregisters contain the high nibble of the 16 bit memory window end address for memory windows 0 1 2 3 and 4 The lower four bits of these registers correspond to bits A23 A20 of the end address In addition the memory wind
129. iption This register controls how the ExCA registers for the socket respond to card removal as well as reports the status of VS1 and VS2 at the PC Card interface See Table 52 for a complete description of the register contents Table 52 ExCA Card Detect and General Conirol Register Index 16h SIGNAL TYPE FUNCTION VS2 state Bit 7 reports the current state of VS2 at the PC Card interface and therefore does not have a default value 7 VS2STAT 0 VSZ low 1 VS2 high VS1 state Bit 6 reports the current state of VS1 at the PC Card interface and therefore does not have a default value VS1STAT 0 VST low 1 VST high Software card detect interrupt If the card detect enable bit in the card status change interrupt configuration register is set writing a 1 to bit 5 causes a card detect card status change interrupt for the 5 SWCSC associated card socket If the card detect enable bit is cleared to 0 the card status change interrupt configuration register writing a 1 to the software card detect interrupt bit has no effect Bit 5 is write only A read always returns 0 Card detect resume enable If bit 4 is set to 1 then once a card detect change has been detected CD1 and CD2 inputs RI OUT goes from high to low RI OUT remains low until the card status change bit CDRESUME R W in the card status change register is cleared If this bit is a 0 then the card detect resume functionality is disabled 0 Card detect resu
130. it I O window end address for I O windows 0 and 1 The eight bits of these registers correspond to the upper eight bits of the end address 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 93 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA memory window 0 4 start address low byte register index 10h 18h 20h 28h 30h 7 Name ExCA memory window 0 4 start address low byte Register ExCA memory window 0 start address low byte Offset CardBus socket address 810h ExCA offset 10h Register ExCA memory window 1 start address low byte Offset CardBus socket address 818h ExCA offset 18h Register ExCA memory window 2 start address low byte Offset CardBus socket address 820h ExCA offset 20h Register ExCA memory window 3 start address low byte Offset CardBus socket address 828h ExCA offset 28h Register ExCA memory window 4 start address low byte Offset CardBus socket address 830h ExCA offset 30h Type Read Write Default 00h Size One byte Description These registers contain the low byte of the 16 bit memory window start address for memory windows 0 1 2 3 and 4 The eight bits of these registers correspond to bits A19 A12 of the start address 35 TEXAS INSTRUMENTS 94 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA memory window 0 4 start address high byte register index
131. it is set SUAM 0 SPKR to SPKROUT not enabled default 1 SPKR to SPKROUT enabled Interrupt flag Bit 0 is the interrupt flag for 16 bit I O PC Cards and for CardBus cards Bit 0 is set when IFG R WC a functional interrupt is signaled from a PC Card interface Write back a 1 to clear this bit 0 No PC Card functional interrupt detected default 1 PC Card functional interrupt detected 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 65 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 device control register 7 e s 4 s 2 1 9 Name Device control 3 w w A Aw AW w AW o 1 1 7 o o 7 0 Register Device control Type Read only Read Write see individual bit descriptions Offset 92h Default 66h Description This register is provided for PCI1130 compatibility The mode select and socket capable force bits are programmed through this register See Table 25 for a complete description of the register contents Table 25 Device Control Register SIGNAL TYPE FUNCTION RSVD Reserved Bit 7 returns 0 when read 3 V socket capable force 3VCAPABLE R W 0 Not 3 V capable 1 3 V capable default IO16R2 Diagnostic bit RSVD R Reserved Bit 4 returns 0 when read Writes have no effect TEST TI test Only a 0 should be written to bit 3 This bit can be set to shorten the interrogation counter
132. it outputs on the PCI1211 This bitis encoded as 7 COE R W 0 16 bit PC Card outputs disabled default 1 16 bit PC Card outputs enabled RSVD O R Reserved Bits 6 5 return 05 when read Writes no effect Vcc Bits 4 3 are used to request changes to card Vcc This field is encoded as 00 0 V default 4 3 EXCAVCC R W 01 0 V reserved 10 5V 11 3 RSVD O R Reserved Bit 2 returns 0 when read Writes have no effect Vpp Bits 1 0 are used to request changes to card Vpp The 1211 ignores this field unless Vcc to the socket is enabled i e 5 V or 3 3 V This field is encoded as 1 0 RW 90 0 default 01 Voc 10 12V 11 0 V reserved ki TEXAS INSTRUMENTS 86 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA interrupt and general control register index 03h 7 e s 4 s 2 1 Name ExCA interrupt and general control Register ExCA interrupt and general control Type Read Write see individual bit descriptions Offset CardBus socket address 803h ExCA offset 03h Default 00h Description This register controls interrupt routing for I O interrupts as well as other critical 16 bit PC Card functions See Table 44 for a complete description of the register contents Table 44 ExCA Interrupt and General Control Register Index 03h SIGNAL TYPE
133. l of compatibility with legacy DMA and simplifies the translation required by the master DMA device when it forwards legacy DMA writes to DMA channels While the DMA register definitions are identical to those in the 8237 ofthe same name some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment In such cases the PCI1211 implements these obsolete register bits as read only nonfunctional bits The reserved registers shown in Table 61 are implemented as read only and return Os when read Writes to reserved registers have no effect Table 61 Distributed DMA Registers DMA TYPE REGISTER NAME BASE ADDRESS OFFSET HEX OR Current address Reserved Page Reserved Reserved w R NA sms 9 Reserved Reserved TEXAS INSTRUMENTS 112 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 DDMA current address base address register 11 current address base address Name DDMA current address base address Register DDMA current address base address Type Read Write Offset DDMA base address 00h Default 0000h Size Two bytes Description This register is used to set the starting base memory address of a DDMA transfer Reads from this register indicate the current memory address of a direct memory transfer For the 8 bit DDMA transfer mode the current a
134. le to the CardBus Socket Exchangeable Card Architecture ExCA Compatible Registers Are Mapped in Memory and Space Intel 82365SL DF Register Compatible Supports Distributed DMA DDMA and PC PCI DMA Supports 16 Bit DMA on the PC Card Socket Supports Ring Indicate SUSPEND PCI CLKRUN and CardBus CCLKRUN Supports PCI Bus Lock LOCK LED Activity Pin Advanced Submicron Low Power CMOS Technology Choice of Surface Mount Packaging PGE Low Profile Plastic Quad Flat Package LQFP GGU High Density Ball Grid Array BGA Table of Contents Br t fornjorre eec 2 Card Controller Programming 43 System Block ee Ree 3 PCI Configuration Registers 43 Terminal 4 ExCA Compatibility Registers 80 Signal Name Terminal Assignments 6 CardBus Socket Registers 104 Terminal FUNCIONS 242 rare prr En fron ERPE 11 Distributed DMA Registers 112 Power Supply Sequencing 21 Absolute Maximum Ratings 118 Characteristics c 4492 4 ecrire eer 21 Recommended Operating Conditions 119 Clamping 66 eere xem Rene ee 21 Electrical Characteristics io
135. me disabled default 1 Card detect resume enabled RSVD OR Reserved Bits 3 2 return 05 when read Writes have no effect Register configuration on card removal Bit 1 controls how the registers for the socket react to card removal event This bit is encoded as 1 BESCONEIS 0 No change to ExCA registers on card removal default 1 Reset ExCA registers on card removal 0 RSVD Reserved Bit 0 returns 0 when read Writes no effect 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 101 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA global conirol register index 1Eh 7 e s 4 s 2 1 9 Name ExCA global control 3 A A aw Aw AW w AW Register ExCA global control Type Read only Read Write see individual bit descriptions Offset CardBus socket address 81Eh ExCA offset 1Eh Default 00h Description This register controls the PC Card socket The host interrupt mode bits in this register are retained for Intel 82365SL DF compatibility See Table 53 for a complete description of the register contents Table 53 ExCA Global Control Register Index 1Eh SIGNAL TYPE FUNCTION RSVD Reserved Bits 7 5 return Os when read Writes have no effect This bit has no assigned function Level edge interrupt mode select Bit selects the signaling mode for the PCI1211 host interrupt PC This 3 INTM
136. mpleted memory base registers 0 1 so 29 28 27 25 2a 2s 22 2t 20 t9 18 17 16 Memory base registers 0 1 Memory base registers 0 1 Name Hye ea rR n R JR JR pea o o o 1 Register Memory base registers 0 1 Type Read only Read Write Offset 1Ch 24h Default 0000 0000h Description These registers indicate the lower address of a PCI memory address range and are used by the 1211 to determine when to forward a memory transaction to the CardBus bus and likewise when to forward a CardBus cycle to PCI Bits 31 12 of these registers are read write and allow the memory base to be located anywhere in the 32 bit PCI memory space on 4K byte boundaries Bits 11 0 always return Os when read Writes to these bits have no effect Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable The memory base register or the memory limit register must be nonzero for the PCI1211 to claim any memory transactions through CardBus memory windows i e these windows are not enabled by default to pass the first 4K bytes of memory to CardBus 35 TEXAS INSTRUMENTS 52 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 memory limit registers O 1 29 29 27 26
137. ms actions dependent upon the address Table 8 I O Addresses Used for PC PCI DMA PUER IE 98 21 99 Lom The PC PCI DMA as a PC Card 16 DMA mechanism may not provide the performance levels of DDMA however the design of a PCI target implementing PC PCI DMA is considerably less complex No bus master state machine is required to support PC PCI DMA since the DMA control is centralized in the chipset This DMA scheme is often referred to as centralized DMA for this reason CardBus socket registers The 1211 contains all registers for compatibility with the latest PCl to PCMCIA CardBus bridge specification These registers exist as the CardBus socket registers and are listed in Table 9 Table 9 CardBus Socket Registers 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 29 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 serial bus interface 1211 provides a serial bus interface to accommodate loading subsystem identification and select register defaults through a serial EEPROM The PCI1211 serial bus interface is compatible with various 2 and SMBus components serial bus interface implementation The 1211 defaults to serial bus interface disabled To enable the serial interface appropriate pullup resistors must be implemented on the SDA and SCL signals i e the MFUNC1 and MFUNC4 terminals In addition
138. n The value read from the interrupt pin register is function dependent and reflects the interrupt signalling mode selected through the device control register 92h The PCI1211 defaults to serialized PCI and ISA interrupt mode 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 55 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 bridge control register gt 15 14 t3 12 f ft 9 8 v e Ps ja 3 2 1 0 Bridge control n Rw Rw Rw mw n aw Rw Rw R pea o o o jo ojoyj trj syjopsjoyjojopjopo 0 Register Bridge control Type Read only Read Write see individual bit descriptions Offset 3Eh Default 0340h Description This register provides control over various PCI1211 bridging functions See Table 20 for a complete description of the register contents Table 20 Bridge Control Register SIGNAL TYPE FUNCTION RSVD Reserved Bits 15 11 return Os when read Write posting enable Enables write posting to and from the CardBus sockets Write posting enables posting of write data on burst cycles Operating with write posting disabled inhibits performance on burst cycles Note that bursted write data can be posted but various write transactions may not mi POSTEN Memory window 1 type Bit 9 specifies whether or not memory window 1 is prefetchable This bit is socket dependent Bit 9 is encoded as 0 Memor
139. nals are redefined to support the ZV protocol The interrupt interface includes terminals for parallel PCI parallel ISA and serialized PCI and ISA signaling Other miscellaneous system interface terminals are available on the PCI1211 that include Programmable multifunction terminals SUSPEND OUT PME power management control signal e SPKROUT 4 PCI Bus 0 Activity LED Interrupt Controller TPS2211 PCI950 Power PCH211 IRQSER IRQSER Switch Deserializer Zoom Video VGA PC Card Socket 19 Controller PCI930 ZV Switch Zoom Video Audio External ZV Port Sub System NOTE The PC Card interface is 68 pins for CardBus and 16 bit PC Cards In ZV mode 23 pins are used for routing the ZV signals to the VGA controller 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 3 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 terminal assignments CTRDY CIRDY CFRAME CC BE2 CAD17 GND CAD18 CAD19 CVS2 CAD20 CRST CAD21 CAD22 Vcc 23 VCCCB CAD24 CAD25 CAD26 GND CVS1 CINT CSERR CAUDIO CSTSCHG CCLKRUN CCD2 CAD27 CAD28 CAD29 CAD30 RSVD CAD31 kwon o PGE LOW PROFILE QUAD FLAT PACKAGE BOTTOM VIEW x 72 0 a jo gt 21 2 lt
140. nd th hold time 5 ___ 7 PCI shared signals AD31 ADO 0 FRAME TRDY IRDY STOP IDSEL DEVSEL and PAR 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 121 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION LOAD CIRCUIT PARAMETERS TIMING CLoapt lot loH VLOAD PARAMETER pF mA mA V 0 t 50 8 8 tPZL 3 tPHZ idis 50 8 8 1 5 dis tPLZ tpd 50 8 8 t t includes the typical load circuit distributed capacitance V V t LOAD OL _ 50 Q where VoL 0 6 V IOL 8 mA loL Timing Mee Input 50 Vcc see Note A tsu et th Data 90 Vcc Vee Input 10 50 50 Vcc ov tr gt e ie tf VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES lt Vcc 50 Vcc ov 50 Vcc tpd In Phase m Output 50 50 Vcc VOL ipd P ee 50 50 utput MOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Input see Note A C From Output V Under Test FORD LOAD CIRCUIT High Level 50 Voc 50 Vcc Input ox poo Low Level 50 Voc 50 Vcc Input 0V VOLTAGE WAVEFORMS PULSE DURATION Output Vcc Control low level enabl
141. nnect to CVS2 Connect to CCD2 Ground Connect to CVS1 Connect to CCD2 Open Open Open 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 23 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 P2C power switch interface TPS2211 1211 provides a 2 PCMCIA peripheral control interface for control of the PC Card power switch The VCCD and VPPD terminals are used with the TPS2211 single slot PC Card power interface switch to provide power switch support Figure 2 shows the terminal assignments for the TPS2211 Figure 3 illustrates a typical application where the PCI1211 represents the Card controller SHDN VPPDO VPPD1 AVCC AVCC AVCC AVPP 12V 1 2 3 4 5 6 7 8 Figure 2 TPS2211 Terminal Assignments The PCI1211 also includes support for the Maxim 1602 single channel CardBus and PCMCIA power switching network Application of this power switch would be similar to the TPS2211 Power Supply 1211 PCMCIA Controller Figure 3 TPS2211 Typical Application zoom video support 1211 allows for the implementation of zoom video for PC Cards Zoom video is supported by setting the ZVENABLE bit in the card control register Setting this bit puts PC Card 16 address lines A25 A4 of the PC Card interface in the high impedance state These lines can then be used to transfer video and audio data directly to
142. no effect Memory window 4 enable Bit 4 enables disables memory window 4 for the card This bit is encoded as MEMWIN4EN 0 Memory window 4 disabled default 1 Memory window 4 enabled window 0 enable Bit 6 enables disables 1 window 0 for the card This bit is encoded as 0 I O window 0 disabled default Memory window 3 enable Bit 3 enables disables memory window 3 for the card This bit is encoded as 0 Memory window 3 disabled default 1 Memory window 3 enabled Memory window 2 enable Bit 2 enables disables memory window 2 for the card This bit is encoded as 0 Memory window 2 disabled default 1 Memory window 2 enabled Memory window 1 enable Bit 1 enables disables memory window 1 for the card This bit is encoded as MEMWIN2EN MEMWIN1EN 0 Memory window 1 disabled default 1 Memory window 1 enabled Memory window 0 enable Bit 0 enables disables memory window 0 for the card This bit is encoded as MEMWINOEN R 0 Memory window 0 disabled default 1 Memory window 0 enabled R W R W R W R W R W R W AN MEMWINSEN 35 TEXAS INSTRUMENTS 90 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA I O window conirol register index 07h 7 e s a s 2 1 Name ExCA window control Register ExCA l O window control Type Read Write see individual bit descriptions Offset CardBus so
143. ns table on page 119 provides the electrical characteristics of the inputs and outputs NOTE 1211 meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus Specification Revision 2 2 Tied for Open Drain o gt Paa Figure 1 3 State Bidirectional Buffer NOTE Unused pins input or I O must be held high or low to prevent them from floating clamping voltages The clamping voltages are set to match whatever external environment the PCI1211 will be working with 3 3 V or 5 V The I O sites can be pulled through a clamping diode to a voltage that protects the core from external signals The core power supply is always 3 3 V and is independent of the clamping voltages For example PCI signaling can be either 3 3 V or 5 V and the PCI1211 must reliably accommodate both voltage levels This is accomplished by using a 3 3 V I O buffer that is 5 V tolerant with the applicable clamping voltage applied If a system designer desires a 5 V PCI bus can be connected to a 5 V power supply The 1211 requires three separate clamping voltages because it supports a wide range of features The three voltages are listed and defined in the recommended operating conditions on page 119 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 21 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 peripheral component interconnect interf
144. o renes 120 Peripheral Component Interconnect PCI Interface 22 PCI Clock Reset Timing Requirements 121 PC Card Applications 23 PCI Timing Requirements 121 Serial Bus Interface 30 Parameter Measurement Information 122 Programmable Interrupt Subsystem 34 PCI Bus Parameter Measurement Information 123 Power Management Overview 38 Mechanical Data 22 25 anew ea 128 Please be aware that important notice concerning availability standard warranty use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Intel is a trademark of Intel Corporation PC Card is a trademark of Personal Computer Memory Card International Association PCMCIA 35 TEXAS Tl is a trademark of Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 1998 Texas Instruments Incorporated INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 d
145. oc 76 CADO CC BE2 D8 CAD22 CAD8 35 CIRDY D9 CVS2 CC BEO 36 CTRDY CAD17 AD17 39 AD14 GNT D11 CBLOCK AD16 43 CAD31 Voc C BE2 47 CAD29 CPAR FRAME 51 AD6 53 AD4 CAUDIO AD24 CAD6 58 GND AD25 5 62 SPKROUT AD26 RSVD 66 Vcc CREQ RSVD IRDY 69 MFUNC6 CRST 72 VPPD1 CAD18 CAD16 TRDY 74 VCCD1 CFRAME CAD14 AD12 37 CCLK AD22 AD10 38 015 CDEVSEL AD23 AD7 40 AD13 AD30 Voc AD1 44 AD31 IDSEL MFUNCO 48 CAD30 CAD15 MFUNC2 52 05 CAD27 CAD12 CAD2 54 AD3 CSTSCHG GND GND 57 ADO CVS1 CAD13 CAD1 61 MFUNC1 CAD24 CAD4 65 AD21 DEVSEL 68 MFUNC5 CAD20 AD20 STOP 71 VPPDO GND RST PERR 73 VCCDO t The PGE LQFP pin numbers are shown also 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 7 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 2 CardBus Card Signal Names Sorted Alphabetically SIGNAL NAME Mei SIGNAL NAME a SIGNAL NAME SIGNAL def PGE GGU PGE GGU PGE GGU PGE GGU CADO CC BE2 MFUNC2 CAD1 CC BE3 MFUNC3 CAD2 CCLK MFUNC4 CAD3 CCD1 MFUNC5 CAD4 CCD2 MFUNC6 CAD5 CCLKRUN PAR CAD6 CDEVSEL PCLK CAD7 CFRAME PERR CGNT REQ CAD9 CINT RI OUT PME CAD10 CIRDY RST CAD11 CPAR SERR CAD12 CPERR RSVD CAD13 CREQ RSVD CAD14 CRST RSVD CAD15 CSERR SPKROUT CAD16 CSTOP STOP CAD17 CSTSCHG SUSPEND CAD18 CTRDY TRDY CAD19
146. only Read Write see individual bit descriptions Offset 44h Default 0000 0001h Description 1211 supports the index data scheme of accessing the ExCA registers which is mapped by this register An address written to this register is the address for the index register and the address 1 is the data address Using this access method applications requiring index data ExCA access can be supported The base address can be mapped anywhere in 32 bit I O space on a word boundary hence bit 0 is read only returning 1 when read Refer to ExCA compatibility registers on page 80 for register offsets RW Rw RW R system control register Bit s 30 2 2 27 26 25 24 29 22 2t 20 19 18 17 16 System control Name Hye aw R R Rw ew mw mw Rw Rw RAW Fw Deta 1 0 115 a 9 12 vt 00 J 8 8 jy 6 s 4 3 2 1 0 System control Rw Rw RnR in nn n n n mw P mw RW RW RW RW petan 1 o o ts jo jo oo jo jt jt opo po jo 0 Register System control Type Read only Read Write see individual bit descriptions Offset 80h Default 0044 9060h Description System level initializations are performed through programming this doubleword register See Table 21 for a complete description of the register contents 35 TEXAS INSTRUMENTS 58 POST OFF
147. ons to a 16 bit PC Card that supports DMA The PCI1211 asserts REG to indicate a DMA operation REG is used in conjunction with the DMA read IOWR or DMA write IORD strobes to transfer data PC Card reset RESET forces a hard reset to a 16 bit PC Card Bus cycle wait WAIT is driven by a 16 bit PC Card to delay the completion of i e extend the memory or I O cycle in progress Write enable WE is used to strobe memory write data into 16 bit memory PC Cards WE is also used for memory PC Cards that employ programmable memory technologies DMA terminal count WE is used as TC during DMA operations to a 16 bit PC Card that supports DMA The PC1211 asserts WE to indicate TC for a DMA read operation Write protect WP applies to 16 bit memory PC Cards WP reflects the status of the write protect switch 16 bit memory PC Cards For 16 bit I O cards WP is used for the 16 bit port IOIS16 function I O is 16 bits IOIS16 applies to 16 bit I O PC Cards IOIS16 is asserted by the 16 bit PC Card when the address on the bus corresponds to an address to which the 16 bit PC Card responds and the I O port that is addressed is capable of 16 bit accesses DMA request WP can be used as the DMA request signal during DMA operations to a 16 bit PC Card that supports DMA If used the PC Card asserts WP to indicate a request for a DMA operation 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 17 1211 GGU PGE
148. oubleword registers are loaded from the EEPROM and all bit fields must be considered when programming the EEPROM The serial EEPROM is addressed at slave address 1010000b by the 1211 All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address The serial EEPROM chip in the sample application circuit Figure 8 assumes the 1010b high address nibble The lower three address bits are terminal inputs to the chip and the sample application shows these terminal inputs tied to GND When a valid offset reference is read four bytes are read from the EEPROM MSB first as illustrated in Figure 14 The address auto increments after every byte transfer according to the doubleword read protocol The word addresses align with the data format illustrated in Figure 13 The PCI1211 continues to load data from the serial EEPROM until an end of list indicator is read Three reserved bytes are stuffed to maintain eight byte data structures The eight byte data structure is important to provide correct addressing per the doubleword read format shown in Figure 14 In addition the reference offsets must be loaded in the EEPROM in sequential order that is 01h 02h 04h If the offsets are not sequential then the registers may be loaded incorrectly Slave Address Word Address Slave Address EXE a 1 i Tm pil M PIE ii EE Data Byte 3 Data Byte 2 Data Byte 1 m
149. ount OE is used as terminal count TC during DMA operations to a 16 bit PC Card that supports DMA The PCI1211 asserts OE to indicate TC for a DMA write operation 35 TEXAS INSTRUMENTS 16 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Terminal Functions Continued 16 bit PC Card interface control continued TERMINAL PIN NUMBER FUNCTION NAME Reagy The ready function is provided by READY when the 16 bit PC Card and the host socket are configured for the memory only interface READY is driven low by the 16 bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command READY is driven high when the 16 bit memory PC Card is ready to accept a new data transfer command Interrupt request IREQ is asserted by a 16 bit I O PC Card to indicate to the host that a device on the 16 bit O PC Card requires service by the host software IREQ is high deasserted when interrupt is requested Attribute memory select REG remains high for all common memory accesses When REG is asserted access is limited to attribute memory OE or WE active and to the space IORD or IOWR active Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information DMA acknowledge REG is used as a DMA acknowledge DACK during DMA operati
150. ow data width is 16 bits SIGNAL Bcz ac 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 91 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA I O window 0 and 1 start address low byte register index 08h OCh 7 6 5 4 3 2 j 1 90 Name EXAlOwWndbwOaniTsatadiessiowbfe 0 R W R W R W R W R W R W R W R W Register ExCA window 0 start address low byte Offset CardBus socket address 808h ExCA offset 08h Register ExCA I O window 1 start address low byte Offset CardBus socket address 80Ch ExCA offset OCh Type Read Write Default 00h Size One byte Description These registers contain the low byte of the 16 bit I O window start address for I O windows 0 and 1 The eight bits of these registers correspond to the lower eight bits of the start address ExCA window 0 and 1 start address high byte register index 09h ODh 7 e s 4 3 2 1 0 Name ExCA window 0 and 1 start address high byte R W R W R W R W R W R W R W R W Register ExCA I O window 0 start address high byte Offset CardBus socket address 809h ExCA offset 09h Register ExCA I O window 1 start address high byte Offset CardBus socket address 80Dh ExCA offset ODh Type Read Write Default 00h Size One byte Description These registers contain the high byte of the 16 bit I O window start
151. ow wait states are set in this register See Table 50 for a complete description of the register contents Table 50 Memory Window 0 4 End Address High Byte Register Index 13h 1Bh 23h 2Bh 33h Wait state Bits 7 6 specify the number of equivalent ISA wait states to be addedto 16 bit memory accesses The number of wait states added is equal to the binary value of these two bits RSVD R Reserved Bits 5 4 return Os when read Writes no effect ENDHN a high nibble Bits 3 0 represent the upper address bits 23 20 of the memory window end 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 97 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA memory window 0 4 offset address low byte register index 14h 1Ch 24h 2Ch 34h 7 Name ExCA memory window 0 4 offset address low byte Register ExCA memory window 0 offset address low byte Offset CardBus socket address 814h ExCA offset 14h Register ExCA memory window 1 offset address low byte Offset CardBus socket address 81Ch ExCA offset 1Ch Register ExCA memory window 2 offset address low byte Offset CardBus socket address 824h ExCA offset 24h Register ExCA memory window 3 offset address low byte Offset CardBus socket address 82Ch ExCA offset 2Ch Register ExCA memory window 4 offset address low byte Offset CardBus socket address 834h ExCA offset 34h Type Read Write Default 00h Si
152. port the source of an interrupt By reading these status bits the interrupt service routine can determine the action to be taken Table 12 details the registers and bits associated with masking and reporting potential interrupts All interrupts can be masked except the functional PC Card interrupts and an interrupt status flag is available for all types of interrupts Notice that there is not a mask bit to stop the 1211 from passing PC Card functional interrupts through to the appropriate interrupt scheme These interrupts are not valid until the card is properly powered and there should never be a card interrupt that does not require service after proper initialization There are various methods of clearing the interrupt flag bits listed in Table 12 The flag bits in the ExCA registers 16 bit PC Card related interrupt flags can be cleared using two different methods One method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register The selection of flag bit clearing is made by bit 2 in the global control register ExCA offset 1Eh 81Eh and defaults to the flag cleared on read method The CardBus related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register Although some of the functionality is shared between the CardBus registers and the ExCA registers software should not program the chip through both register sets when a CardBus card is
153. power off default 001 Request Vpp 12 V 010 Request Vpp 5 011 Request Vpp 3 3 V 100 Request Vpp V 101 Request Vpp Y Y V 110 Reserved 111 Reserved ki TEXAS INSTRUMENTS 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 socket power management register gt 3o 20 28 27 26 25 24 23 22 2t 20 19 18 17 16 Socket power management po Socket power management 0 iR Jn R Jn re pea o o o fe 14 t3 12 v0 9 8 7 je 5 2 1 0 Socket power management po Socket powermanagement in ew o 0 59 9 Register Socket power management Type Read only Read Write see individual bit descriptions Offset CardBus socket address 20h Default 0000 0000h Description This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle See Table 60 for a complete description of the register contents Table 60 Socket Power Management Register SIGNAL TYPE FUNCTION 31 26 RSVD R Reserved Bits 31 26 return Os when read Socket access status This bit provides information on when a socket acc
154. progress When set bit 8 indicates an interrogation is in progress and clears when interrogation completes INTERROGATE 0 Interrogation not in progress default 1 Interrogation in progress RSVD R Reserved Bit 7 returns 0 when read PWRSAVINGS Power savings mode enable When this bit is set if a CB card is inserted idle and without a CB clock the applicable CB state machine will not be clocked SUBSYSRW CB_DPAR Subsystem ID SSID subsystem vendor ID SSVID ExCA ID and revision register read write enable 0 SSID SSVID ExCA ID and revision register are read write 1 SSID SSVID ExCA ID and revision register are read only default CardBus data parity SERR signaling enable 0 CardBus data parity not signaled on PCI SERR 1 CardBus data parity signaled on PCI SERR RSVD KEEPCLK RIMUX Reserved Bit 2 returns 0 when read Keep clock This bit works with PCI and CB CLKRUN protocols 0 Allows normal functioning of both CLKRUN protocols default 1 Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols RI OUT PME multiplex enable __ 0 RI OUT and PME are both routed to the RI OUT PME terminal If both are enabled at the same time RI OUT has precedence over PME 1 Only PME is routed to the RI OUT PME terminal PC PCI DMA enable Bit 3 enables DMA when set if MFUNC routing is configured for centralized DMA BEMEOEN iod 0 Centralized DMA disabled d
155. ption These registers contain the low byte of the 16 bit I O window offset address for I O windows 0 and 1 The eight bits of these registers correspond to the lower eight bits of the offset address and bit 0 is always 0 ExCA I O window 0 and 1 offset address high byte register index 37h 39h 7 e 5 4 3 2 1 0 ExCA I O window 0 1 offset address high byte Register ExCA I O window 0 offset address high byte Offset CardBus socket address 837h ExCA offset 37h Register ExCA I O window 1 offset address high byte Offset CardBus socket address 839h ExCA offset 39h Type Read Write Default 00h Size One byte Description These registers contain the high byte of the 16 bit I O window offset address for I O windows 0 and 1 The eight bits of these registers correspond to the upper eight bits of the offset address 35 TEXAS INSTRUMENTS 100 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA card detect and general control register index 16h 7 e s 4 s 2 1 Name ExCA I O card detect and general control wm A A w aw a a A mmm x x o o o o o 0 Register ExCA card detect and general control Type Read only Write only Read Write see individual bit descriptions Offset CardBus socket address 816h ExCA offset 16h Default XX00 0000b Descr
156. ption This register is used to request a DDMA transfer through software Any write to this register enables software requests and this register is to be used in block mode only 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 115 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 DDMA mode register 7 e s 46 s 2 1 09 Name mode w aw w aw Aw AW Ja Register DDMA mode Type Read only Read Write see individual bit descriptions Offset DDMA base address OBh Default 00h Size One byte Description This register is used to set the DDMA transfer mode See Table 64 for a complete description of the register contents Table 64 DDMA Mode Register SIGNAL TYPE FUNCTION Mode select The PCI1211 uses bits 7 6 to determine the transfer mode 00 Demand mode select default 7 6 DMAMODE R W 01 Single mode select 10 Block mode select 11 Reserved Address increment decrement The PCI1211 uses bit 5 to select the memory address in the current address base address register to increment or decrement after each data transfer This is in accordance 5 INCDEC R W with the 8237 use of this register bit and is encoded as follows 0 Addresses increment default 1 Addresses decrement Auto initialization 4 AUTOINIT R W 0 Auto initialization disabled default 1 Auto initialization enabled Transfer type Bits 3 2 selec
157. r Index 01h SIGNAL TYPE FUNCTION RSVD Reserved Bit 7 returns 0 when read Writes have no effect Card Power Bit 6 indicates the current power status of the PC Card socket This bit reflects how the power control register is programmed Bit 6 is encoded as 0 Vcc and Vpp to the socket turned off default 1 Vcc and Vpp to the socket turned on BIT CARDPWR Bit 5 indicates the current status of the READY signal at the PC Card interface 0 PC Card not ready for data transfer 1 PC Card ready for data transfer Card write protect Bit 4 indicates the current status of WP at the PC Card interface This signal reports to the PCI1211 whether or not the memory card is write protected Furthermore write protection for an entire PCI1211 16 bit memory window is available by setting the appropriate bit in the memory window offset high byte register 0 2 WP is 0 PC Card is R W 1 WP is 1 PC Card is read only n Card detect 2 Bit 3 indicates the status of CD2 at the PC Card interface Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket CDETEGT2 0 CD2 is 1 No PC Card is inserted 1 CD2 is 0 PC Card is at least partially inserted Card detect 1 Bit 2 indicates the status of CD1 at the PC Card interface Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket 0 CD1 is 1 No PC Card is inserted 1 CD1 is 0 PC Card is at least p
158. r and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses subordinate bus number register pe qo 7 s Jp q 1 Subordinate bus number Register Subordinate bus number Type Read Write Offset 1Ah Default 00h Description This register is programmed by the host system to indicate the highest numbered bus below the CardBus bus The 1211 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 51 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 CardBus latency timer register 7 s 4 j 3 2 1 90 Name CardBus latency timer R W R W R W R W R W R W R W R W Register CardBus latency timer Type Read Write Offset 1Bh Default 00h Description This register is programmed by the host system to specify the latency timer for the PCI1211 CardBus interface in units of CCLK cycles When the PCI1211 is a CardBus initiator and asserts CFRAME the CardBus latency timer begins counting If the latency timer expires before the PCI1211 transaction has terminated then the PCI1211 terminates the transaction at the end of the next data phase A recommended minimum value for this register is 20h which allows most transactions to be co
159. rotocol implemented in the PCI1211 uses a single terminal to communicate all interrupt status information to the host controller The protocol defines a serial packet consisting of a start cycle multiple interrupt indication cycles and a stop cycle All data in the packet is synchronous with the PCI clock The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA INTB INTC and INTD For details on the IRQSER protocol refer to the document Serialized IRQ Support for PCI Systems SMI support in the 1211 The PCI1211 provides a mechanism of interrupting the system when power changes have been made to the PC Card socket interface The interrupt mechanism is designed to fit into a system maintenance interrupt SMI scheme SMI interrupts are generated by the PCI1211 when enabled after a write cycle to either the socket control register of the CardBus register set or the power control register of the ExCA register set causes a power cycle change sequence sent on the power switch interface The SMI control is programmed through three bits in the system control register These bits are SMIROUTE SMISTATUS and SMIENB The SMI control bits function as described in Table 14 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 37 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 SMI support in the PCI1211 continued Table 14 SMI Control BIT NAME FUNCTION SM
160. s power management control for the Socket Host PCI1211 Configuration Registers Memory Space 3 g Offset Offset 00h CardBus Socket 10h CardBus Socket ExCA Base Address Registers 16 Bit Legacy Mode Base Address 44h Figure 22 Accessing CardBus Socket Registers Through PCI Memory Table 54 CardBus Socket Registers Socket mask Socket present state Socket force event 104 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 socket event register git 3o 29 28 zz 26 25 24 29 22 zt 20 19 te 17 16 Socket event Socket event Name JR JR jRWoj nwc awe Register Socket event Type Read only Read Write to Clear see individual bit descriptions Offset CardBus socket address 00h Default 0000 0000h Description This register indicates that a change in socket status has occurred These bits do not indicate what the change is only that one has occurred Software must read the socket present state register for current status Each bit in this register can be cleared by writing a 1 to that bit The bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register All bits in this register ar
161. s set This bit is encoded as R W R W IOSIS16W1 R W R W 0 Window data width is 8 bits default R W N R W R W DATASIZE1 1 Window data width is 16 bits I O window 0 wait state Bit controls the I O window 0 wait state for 16 bit I O accesses Bit has no effect on 8 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 16 bit cycles have standard length default 1 16 bit cycles are extended by one equivalent ISA wait state WAITSTATEO I O window 0 zero wait state Bit 2 controls the I O window 0 wait state for 8 bit I O accesses Bit 2 has no effect on 16 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 8 bit cycles have standard length default 1 8 bit cycles are reduced to equivalent of three ISA cycles ZEROWSO R window 0 IOIS16 source Bit 1 controls the I O window 0 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I O data transfer This bit is encoded as 0 Window data width is determined by DATASIZEO bit 0 default 1 Window data width is determined by IOIS16 window 0 data size Bit 0 controls the I O window 0 data size Bit 0 is ignored if the I O window 0 DATASIZEO IOIS16 source bit bit 1 is set This bit is encoded as 051516 0 0 Window data width is 8 bits default 1 Wind
162. st 1211 Configuration Registers Memory Space 9 9 Offset dala Offset CardBus Socket CardBus Socket ExCA Base Address 10h Registers lon 16 Bit Legacy Mode Base Address 44h Registers Figure 21 ExCA Register Access Through Memory 844h 80 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA compatibility registers continued The interrupt registers as defined by the 82365SL DL Specification in the EXCA register set control such card functions as reset type interrupt routing and interrupt enables Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1211 to ensure that all possible 1211 interrupts can potentially be routed to the programmable interrupt controller The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h Access to I O mapped 16 bit PC Cards is available to the host system via two ExCA I O windows These are regions of host I O address space into which the card I O space is mapped These windows are defined by start end and offset addresses programmed in the ExCA registers described in this section I O windows have byte granularity Access to memory mapped 16 bit PC Cards is available to the host system via five EXCA memory windows These are regions of host memory space into whi
163. sters The exchangeable card architecture ExCA registers implemented in the PCI1211 are register compatible with the Intel 8B2365SL DF PCMCIA controller EXCA registers are identified by an offset value that is compatible with the legacy I O index data scheme used on the Intel 82365 ISA controller The ExCA registers are accessed through this scheme by writing the register offset value into the index register I O base and reading or writing the data register I O base 1 The I O base address used the index data scheme is programmed in the PC Card 16 Bit I F legacy mode base address register The offsets from this base address run contiguous from 00h to 3Fh for the socket Refer to Figure 20 for an ExCA I O mapping illustration 1211 Configuration Registers Host I O Space Offset Enn Offset 00h PC Card ExCA _ gt n CardBus Socket ExCA Base Address 10h Index Registers ach 16 Bit Legacy Mode Base Address 44h ae C Figure 20 EXCA Register Access Through The 1211 also provides a memory mapped alias of the registers by directly mapping them into PCI memory space They are located through the CardBus socket registers ExCA registers base address register PCI register 10h at memory offset 800h Refer to Figure 21 for an EXCA memory mapping illustration This illustration also identifies the CardBus socket register mapping which is mapped into the same 4K window at memory offset Oh Ho
164. t is decremented by 1 after each transfer Likewise the count is decremented by 2 in the 16 bit transfer mode command register pit 7 e s 46 s 2 1 9 Name PMA command 0 J a p m m T m Rw m pea o o o o 9 o Register DDMA command Type Read only Read Write see individual bit descriptions Offset DDMA base address 08h Default 00h Size One byte Description This register is used to enable and disable the DMA controller Bit 2 the only read write bit defaults to 0 enabling the DMA controller All other bits are reserved See Table 62 for a complete description of the register contents Table 62 DDMA Command Register TYPE TYPE FUNCTION RSVD R Reserved Bits 7 3 return 05 when read DMA controller enable Bit 2 enables and disables the distributed DMA slave controller in the PCI1211 and defaults to the enabled state 2 DMAEN 0 DMA controller enabled default 1 DMA controller disabled RSVD Reserved Bits 1 0 return 05 when read ki TEXAS INSTRUMENTS 114 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 DDMA status register 7 e j s 4 s 2 1 Name status PMA Stats R R pem o o o o 9 Register DDMA status Type Read only see indiv
165. t is serviced The GPE can be signaled only if one of the multifunction terminals MFUNC6 MFUNCO are configured for GPE signaling See Table 33 for a complete description of the register contents Table 33 General Purpose Event Enable Register SIGNAL TYPE FUNCTION ZV EN PC card socket ZV enable When bit 15 is set a GPE is signaled on a change in status of ZVENABLE in the PC Card controller function of the PCI1211 O R Reserved These bits return 05 when read Power change event enable When bit 11 is set a GPE is signaled on when software has changed the power state of the socket O R Reserved These bits return 05 when read 12 Volt Vpp request event enable When bit 8 is set a GPE is signaled when software has changed the requested Vpp level to or from 12 Volts for the card socket RSVD OR Reserved These bits return 05 when read R W R W R W E R W 4 event enable When bit 4 is set a GPE is signaled when there has been a change in status R W R W R W AN RSVD PWR_EN RSVD VPP12_EN 7 5 of the MFUNCS terminal input level if configured as GPI4 GPI3 event enable When bit 3 is set a GPE is signaled when there has been a change in status GPS E of the MFUNCA terminal input level if configured as GPI3 2 GPI2 event enable When bit 2 is set a GPE is signaled when there has been a change in status Ce of the MFUNC2 terminal input if configured as 2 GPI1 event enable
166. t the type of direct memory transfer to be performed A memory write transfer moves data from the PCI1211 PC Card interface to memory and a memory read transfer moves data from memory to the PCI1211 PC Card interface The field is encoded as 3 2 XFERTYPE R W 00 No transfer selected default 01 Write transfer 10 Read transfer 11 Reserved RSVD R Reserved Bits 1 0 return 05 when read 35 TEXAS INSTRUMENTS 116 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 DDMA master clear register 7 e j s s 2 1 Name 7 DDMAmesercea pm o o o o o o o 0 Register DDMA master clear Type Write only Offset DDMA base address ODh Default 00h Size One byte Description This register is used to reset the DMA controller and resets all DDMA registers DDMA multichannel mask register B ql DDMA multichannel mask Name j R R pem o e o 0 Register DDMA multichannel mask Type Read only see individual bit descriptions Offset base address OFh Default 00h Size One byte Description The PCI1211 uses only the least significant bit of this register to mask the PC Card DMA channel The 1211 sets the mask bit when the PC Card is removed Host software is responsible for
167. tails Multifunction Terminal 4 MFUNCA can be configured as PCI LOCK GPI3 socket activity LED RI OUT output ZV output select CardBus audio PWM GPE or a parallel IRQ Refer to the multifunction routing register description on page 61 for configuration details Serial Clock SCL When the serial bus mode is implemented by pulling the SDA and SCL terminals the MFUNCA terminal provides the SCL signaling The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset Refer to the serial bus interface protocol description on page 30 for details on other serial bus applications MFUNC4 RI OUT PME Multifunction Terminal 5 MFUNCS can be configured as PC PCI DMA Grant GPI4 GPO4 socket activity LED output ZV output select CardBus audio PWM GPE ora parallel IRQ Refer to the multifunction routing register description on page 61 for configuration details Multifunction Terminal 6 MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ Refer to the multifunction routing register description on page 61 for configuration details Ring Indicate Out and Power Management Event Output Provides output for either RI RI OUT or PME signals Suspend SUSPEND is used to protect the internal registers from clearing when the RST signal is asserted See suspend mode on page 39 for details Speaker output SPKROUT is the output to the host system that can carry S
168. te Bit 6 controls the memory window wait state for 8 and 16 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as ZEROWAIT 0 8 and 16 bit cycles have standard length default 1 8 bit cycles are reduced to equivalent of three ISA cycles 16 bit cycles are reduced to equivalent of two ISA cycles SCRATCH Scratch pad bits Bits 5 4 have no effect on memory window operation 3 0 STAHN R W Start address high nibble Bits 3 0 represent the upper address bits 23 20 of the memory window start address 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 95 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA memory window 0 4 end address low byte register index 12h 1Ah 22h 2Ah 32h 7 Name ExCA memory window 0 4 end address low byte Register ExCA memory window 0 end address low byte Offset CardBus socket address 812h ExCA offset 12h Register ExCA memory window 1 end address low byte Offset CardBus socket address 81Ah ExCA offset 1Ah Register ExCA memory window 2 end address low byte Offset CardBus socket address 822h ExCA offset 22h Register ExCA memory window 3 end address low byte Offset CardBus socket address 82Ah ExCA offset 2Ah Register ExCA memory window 4 end address low byte Offset CardBus socket address 832h ExCA offset 32h Type Read Write Default 00h Size One byte Descr
169. ter and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h This doubleword register is used for system and option card mobile dock identification purposes and is required by some operating systems Implementation of this unique identifier register is a PC 97 requirement The PCI1211 offers two mechanisms to load a read only value into the subsystem registers The first mechanism relies upon the system BIOS providing the subsystem ID value The default access mode to the subsystem registers is read only but can be made read write by setting the SUBSYSRW bit in the system control register bit 5 at PCI offset 80h Once this bit is set the BIOS can write a subsystem identification value into the registers at offset 40h The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read only access This approach saves the added cost of implementing the serial electrically erasable programmable ROM EEPROM 22 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 loading subsystem identification continued In some conditions such as in a docking environment the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via serial EEPROM The PCI1211 loads the data from the serial EEPROM after a reset of the primary bus
170. ter on page 89 for enable bits See ExCA card status change register on page 88 and the EXCA interface status register on page 85 for the status bits for this signal Status change STSCHG is used to alert the system to a change in the READY write protect or battery voltage dead condition of a 16 bit PC Card Ring indicate RI is used by 16 bit modem cards to indicate a ring detection Battery voltage detect 2 BVD2 is generated by 16 bit memory PC Cards that include batteries BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory Card Both BVD1 and BVD2 are high when the battery is good When BVD2 is low and BVD1 is high the battery is weak and should be replaced When BVD1 is low the battery is no longer serviceable and the data in the memory PC Card is lost See ExCA card status change interrupt configuration register on page 89 for enable bits See ExCA card status change register on page 88 and the interface status register on page 85 for the status bits for this signal Speaker SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16 bit I O interface The audio signals from cards A and B are combined by the PCI1211 and are output on SPKROUT DMA request BVD2 can be used as the DMA request signal during DMA operations to a 16 bit PC Card that supports DMA The PC Card asserts BVD2 to indicate a request for a DMA operation PC Card detect 1
171. the appropriate controller Card address lines A3 AO0 can still be used to access PC Card CIS registers for PC Card configuration Figure 4 illustrates PCI1211 ZV implementation TEXAS INSTRUMENTS 24 POST OFFICE BOX 655303 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 zoom video support continued lt Motherboard PCI Bus Speakers VGA Controller Zoom Video Port PC Card PCI1211 Figure 4 Zoom Video Implementation Using 1211 Not shown in Figure 4 is the multiplexing scheme used to route either a socket ZV source or an external ZV source to the graphics controller A typical external source might be provided from a high speed serial bus like IEEE1394 The 1211 provides ZVSTAT ZVSELO signals on the multifunction terminals to switch external bus drivers Figure 5 shows an implementation for switching between two ZV streams using external logic PCI1211 ZVSTAT ZVSELO Figure 5 Zoom Video Switching Application The example shown in Figure 5 illustrates an implementation using standard 3 state bus drivers with active low output enables ZVSELO is an active low output indicating that the Socket ZV mode is enabled ZVSTAT is an active high outputindicating the PCI1211 socket is enabled for ZV mode The implementation shown in Figure 5 can be used if PC Card ZV is prioritized over other sources
172. the host CardBus initiator ready CIRDY indicates the CardBus initiator s ability to complete the current data CIRDY phase of the transaction A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted Until CIRDY and CTRDY are both sampled asserted wait states are inserted CardBus parity error CPERR is used to report parity errors during CardBus transactions except CPERR 104 C13 y o during special cycles It is driven low by a target two clocks following that data when a parity error is detected CREG 123 B8 CardBus request CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator CardBus system error CSERR reports address parity errors and other system errors that could lead CSERR 133 A5 to catastrophic results CSERRis driven by the card synchronous to CCLK but deasserted by a weak pullup and may take several CCLK periods The PCI1211 can report CSERR to the system by assertion of SERR on the PCI interface CardBus stop CSTOP is driven by a target to request the initiator to stop the current CSTOP 105 C12 CardBus transaction CSTOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers CardBus status change CSTSCHG is used to alert the system to a change in the card s status and CSTSCHG 199 5 a is used as a wake up mechanism CardBus target ready CTRDY indicates the Car
173. the registers are preserved 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 11 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Terminal Functions Continued PCI address and data TERMINAL 1 0 NANE PIN NUMBER TYPE FUNCTION PGE GGU PCI address data bus These signals make up the multiplexed PCI address and data bus on the primary interface During the address phase of a primary bus PCI cycle AD31 ADO contain a 32 bit address or other destination information During the data phase AD31 ADO contain data PCI bus commands and byte enables These signals are multiplexed on the same PCI terminals During the address phase of a primary bus PCI cycle define the bus command During the data phase this 4 bit bus is used as byte enables The byte enables determine which byte paths of the full 32 bit data bus carry meaningful data C BEO applies to byte 0 AD7 ADO C BE1 applies to byte 1 AD15 AD8 C BE2 applies to byte 2 AD23 AD16 and applies to byte 3 AD31 AD 24 PCI bus parity In all PCI bus read and write cycles the PCI1211 calculates even parity across the AD31 ADO and C BE3 C BEO buses As an initiator during PCI cycles the PCI1211 outputs this parity indicator with a one PCLK delay As a target during PCI cycles the calculated parity is compared to the initiator s parity indicator A compare error results in the assertion of a parity error
174. ts Table 17 Command Register SIGNAL TYPE FUNCTION 15 10 RSVD R Reserved Bits 15 10 return 05 when read Writes have no effect 7 Fast back to back enable The PCI1211 does not generate fast back to back transactions therefore bit FBB EN 9 returns 0 when read System Error SERR enable Bit 8 controls the enable for the SERR driver on the PCI interface SERR can be asserted after detecting an address parity error on the PCI bus Both bit 8 and bit 6 must be set for the PCI1211 to report address parity errors 0 Disable SERR output driver default 1 Enable SERR output driver STEP EN Address data stepping control The PCI1211 does not support address data stepping and bit 7 is hardwired to 0 Writes to this bit have no effect PERR_EN SERR 0 PCI1211 ignores detected parity error default 1 11211 responds to detected parity errors m VGA palette snoop Bit 5 controls how PCI devices handle accesses to video graphics array VGA palette Parity error response enable Bit 6 controls the PCI1211 s response to parity errors through PERR Data parity errors are indicated by asserting PERR whereas address parity errors are indicated by asserting R W 5 registers The 1211 does not support VGA palette snooping therefore this bit is hardwired to 0 Bit 5 returns 0 when read Writes to this bit have no effect we commands it uses memory write commands instead therefore this bit is hardwired to 0 Bit
175. ult 1 Enables host interrupt generation Battery Warning Enable Bit 1 enables disables a battery warning condition to generate a CSC interrupt This bit is encoded as R W R W R W R W AN 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 89 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA address window enable register index 06h 7 e s 4 s 2 1 09 Name ExCA address window enable we w aw A aw Aw AW AW AW Register ExCA address window enable Type Read only Read Write see individual bit descriptions Offset CardBus socket address 806h ExCA offset 06h Default 00h Description This register enables disables the memory and I O windows to the 16 bit PC Card By default all windows to the card are disabled The 1211 does not acknowledge PCI memory or I O cycles to the card if the corresponding enable bit in this register is 0 regardless of the programming of the memory or I O window start end offset address registers See Table 47 for a complete description of the register contents Table 47 ExCA Address Window Enable Register Index 06h SIGNAL TYPE FUNCTION window 1 enable Bit 7 enables disables 1 window 1 for the card This bit is encoded as IOWIN1EN 0 window 1 disabled default 1 I O window 1 enabled IOWINOEN 1 window 0 enabled RSVD Reserved Bit 5 returns 0 when read Writes have
176. ure NOTE 3 Unused pins input or I O must be held high or low to prevent them from floating Low level input voltage 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 119 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 electrical characteristics over recommended operating conditions unless otherwise noted PARAMETER OPERATION TEST CONDITIONS 0 5 mA 5V 2 mA VOH High level output voltage see Note 4 3 3 V 0 15 mA 5V 0 15 mA 12 mA 4 mA 1 5 mA IOL 6 mA VOL Low level output voltage loL 12 mA lo 4 mA iah i lozL 3 state output high impedance state Output pins 1 VCC output current see Note 4 5 25 V VI Voc igh i 3 6 V V Vect IOZH 3 state output high impedance state Output pins VCC output current 5 25 V Vi Low level input current see Note 5 IL n Vi GND 3 6V VI Vi Vcc High level input current Vi Vect pins iaee 5 25 V VI Fail safe pins VI 67 Misc1 includes MFUNC6 69 MFUNC5 68 MFUNC4 67 MFUNC3 65 and MFUNC2 84 T Misc2 includes MFUNC1 61 MFUNCO 60 SERR 35 Misc3 includes SPKROUT 62 and RI_OUT 59 T For PCI pins Vj For PC Card pins Vj For miscellaneous pins V VCCI For I O pins input leakage 1 and
177. w 1 start address high byte 819 Memory window 1 end address low byte 81A Memory window 1 end address high byte 81B Memory window 1 offset address low byte 81C Memory window 1 offset address high byte 81D Global control 81E Reserved 35 TEXAS INSTRUMENTS 82 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 Table 40 ExCA Registers and Offsets Continued PCI MEMORY ADDRESS OFFSET window 2 ooo iy Memon windowpage0 DWemoywndwpae J wo o FMemon window page w Memoywindowpaes pase w 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 83 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA identification and revision register index 00h Bg 7 e s j 4 s 2 1 09 Name identification and revision 8 AW w w w w AW 1 0 o o o 1 o 09 Register ExCA identification and revision Type Read only Read Write see individual bit descriptions Offset CardBus socket address 800h ExCA offset 00h Default 84h Description This register provides host software with information on 16 bit PC Card support and Intel 82365SL DF compatibility See Table 41 for a complete description of the register cont
178. y Wait states READY Change in LLLA card status BVD1 STSCHG CSTSCHG 16 bit I O STSCHG Interrupt request 3 The assertion of IREQ indicates interrupt IREQ READYIIREQWCINT request from the PC Card Change in card status BVD1 STSCHG CSTSCHG CardBus CSTSCHG Interrupt request UATAN Ug The assertion of CINT indicates an interrupt CINT request from the Card A transition either CD1 CCD1 or or removal CD2 CCD2 The assertion of STSCHG indicates a status change on the PC Card The assertion of CSTSCHG indicates a status change on the PC Card CD2 CCD2 indicates an insertion or removal All PC Cards of a 16 bit CardBus PC Card Power cycle An interrupt is generated when a PC Card CSC N A complete power up cycle has completed 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 35 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 PC Card functional and card status change interrupts continued The naming convention for PC Card signals describes the function for 16 bit memory and I O cards as well as CardBus For example READY IREQ CINT includes READY for 16 bit memory cards IREQ for 16 bit I O cards and CINT for CardBus cards The 16 bit memory card signal name is first with the I O card signal name second enclosed in parentheses The CardBus signal name follows after a forward double slash
179. y window 1 is nonprefetchable 1 Memory window 1 is prefetchable default PREFETCH1 Memory window 0 type Bit 8 specifies whether or not memory window 0 is prefetchable This bit is PREFETCHO encoded as 0 Memory window 0 is nonprefetchable 1 Memory window 0 is prefetchable default PCI interrupt IREQ routing enable Bit 7 is used to select whether PC Card functional interrupts are routed to PCI interrupts or the IRQ specified in the ExCA registers 0 Functional interrupts routed to PCI interrupts default 1 Functional interrupts routed by ExCAs CardBus reset When bit 6 is set CRST is asserted on the CardBus interface CRST can also be asserted by passing a RST assertion to CardBus 0 CRST deasserted 1 CRST asserted default Master abort mode Bit 5 controls how the PCI1211 responds to a master abort when the PCI1211 is an initiator on the CardBus interface This bit is common between each socket 0 Master aborts not reported default 1 Signal target abort on PCI and SERR if enabled MABTMODE A RSVD Reserved Bit 4 returns 0 when read VGA enable Bit 3 affects how the PCI1211 responds to VGA addresses When this bit is set accesses VGAEN to VGA addresses are forwarded ISA mode enable Bit 2 affects how the PCI1211 passes I O cycles within the 64K byte ISA range This bitis not common between sockets When this bit is set the PCI1211 does not forward the last 768 bytes of each 1K I O rang
180. ze One byte Description These registers contain the low byte of the 16 bit memory window offset address for memory windows 0 1 2 and 4 The eight bits of these registers correspond to bits A19 A12 of the offset address 35 TEXAS INSTRUMENTS 98 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1211 GGU PGE PC CARD CONTROLLERS SCPS033A OCTOBER 1998 ExCA memory window 0 4 offset address high byte register index 15h 1Dh 25h 2Dh 35h gu v 6 5 4 3 2 1 o memory window 0 4 offset address high byte R W R W R W R W R W R W R W Register ExCA memory window 0 offset address high byte Offset CardBus socket address 815h ExCA offset 15h Register ExCA memory window 1 offset address high byte Offset CardBus socket address 81Dh ExCA offset 1Dh Register ExCA memory window 2 offset address high byte Offset CardBus socket address 825h ExCA offset 25h Register ExCA memory window 3 offset address high byte Offset CardBus socket address 82Dh ExCA offset 2Dh Register ExCA memory window 4 offset address high byte Offset CardBus socket address 835h ExCA offset 35h Type Read Write see individual bit descriptions Default 00h Size One byte Description These registers contain the high six bits of the 16 bit memory window offset address for memory windows 0 1 2 3 and 4 The lower six bits of these registers correspond to bits 25 20 of the offset address

TEXAS INSTRUMENTS PCI1211 GGU/PGE PC CARD CONTROLLERS handbook

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