ALTERA DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Manual
Contents
1. 25 22 2 y By 7 0 08740 Invert 918 10 gt 2 n LL 5 0 0 cas Increment 6 Seven Segment et US d re Display 1 LED4 Case Statement BusBuikl Cyclone Il EP2C70 DSP Board The Cyclone II EP2C70 DSP board is an enhanced version of the EP2C35 board which has two 14 bit analog to digital converters and two 14 bit digital to analog converters DSP Builder Handbook June 2012 Altera Corporation Volume 2 DSP Builder Standard Blockset Chapter 24 Boards Library Board Configuration 24 5 Table 24 3 lists the blocks available to support the Cyclone II EP2C70 DSP board Table 24 3 Cyclone Il EP2C70 DSP Board Blocks Block Description z Controls the 14 bit signed analog to digital converters You can optionally specify ie the clock signal D2A_1 and D2A_2 Controls the 14 bit unsigned digital to analog converters Dip Switch Controls the user definable dual in line package switch S1 You can optionally p specify the clock signal LEDO LED7 Controls eight user definable LEDs D2 D9 PROTO and Santa Cruz connectors which control the prototyping area 1 0 You can optionally PROTO1 specify Input or Outp2. 4 2 Design Flow Using MegaCore Functions 4 2 Adding the MegaCore Function in the Simulink Model 4 2 Parameterizing the MegaCore Function Variation 4 3 Generating the MegaCore Function Variation 4 3 Connecting the MegaCore Function Variation Block to the Design 4 3 Simulating the MegaCore Function Variation in the Model 4 3 MegaCore Function Design Example 22 4 3 Creating a New Simulink Model 4 3 Adding the FIR Compiler Function 2222 4 4 Parameterizing the FIR Compiler Function 2 4 5 Generating the FIR Compiler Function Variation 4 5 Adding Stimulus and Scope Blocks 4 6 Simulating the Design in Simulink 222 4 8 Compiling the Design made A Mote ee eee tine al SN ee 4 9 Performing RTL Simulation 220 4 10 MegaCore Functions Design Issues 4
3. DEBUG ES DEBUG 4 Ls en DEBUG 4 DEBUG DEBUG DEBUG Y 4 1 Unsigned DEBUG Y Increment Y Decrement Eis 501 2 Tr wv ww 7 Y v N N Wo WU febr abr ula obo ul obo ub uh A A DEBUG A A DEBUG A Y 2 Generator BUTTON Swo BRASS Signed ToUnsigned Delay 14 Bit Unsigned 2 j 28 0 Me 30 0 28 25 o pla BusConversion Binary To Seven Segments Seven Segment display 0 BUTTON SW1 Stratix DSP Board EP1S25 a LEDI glen 7 0 018 10 9 8 10 25 0 25 23 BusConversiont p gt Case Statement BusBuikl Stratix EP1S80 DSP Board The Stratix EP1S80 DSP board is a powerful development platform for digital signal processing DSP designs and features the Stratix 1580 device in the speed grade 6 956 pin package Tabl
4. Table 17 38 shows the Pattern block parameters Table 17 38 Pattern Block Parameters Name Value Description Binary Sequence User Defined Specify the sequence that you want to use Specify Clock On or Off Turn on to explicitly specify the clock name DSP Builder Handbook June 2012 Altera Corporation Volume 2 DSP Builder Standard Blockset Chapter 17 Gate amp Control Library Table 17 38 Pattern Block Parameters 17 23 Value Description User defined Clock Parameterizable Specify the name of the required clock signal Use Enable Port On or Off Turn on to use the clock enable input ena Use Synchronous Clear Port On or Off Turn on to use the synchronous clear input sclr Table 17 39 shows the Pattern block I O formats Table 17 39 Pattern Block 1 0 Formats 1 1 0 Simulink 2 VHDL Type 4 1 1 11 in STD_LOGIC Explicit optional 1201 12 in STD_LOGIC Explicit optional 011 01 out STD_LOGIC Explicit Notes to Table 17 39 1 For signed integers and signed binary fractional numbers the MSB is the sign bit 2 L is the number of bits on the left side of the binary point R is the number of bits on the right side of the binary point For signed or unsigned integers R 0 that is L 0 For single bits R 0 that is 1 is a single bit 3 lij nj is an input port 1 gj is an output port 4 Explici
5. 222 9 6 Chapter 10 Adding a Board Library Creating New Board Description 2 10 1 Predefined Components crees eer een she een Rad pires ane dieser 10 1 Component Types ne a dece Vae de Se e Va ae 10 1 Component Description File 0 0 6 nes 10 2 Example Component Description File 10 3 Board Descriptor deep erre ek etin ex te eec MR walla Wa trees 10 4 Header Section eder eee e Dun OA erede tec d ecl doe oe et o tete 10 4 Board Description Section 10 4 Building the Board Library eere Ree ee dan done C Un Eva e idee diee d de ente 10 6 Chapter 11 Using the State Machine Library Using the State Machine Table Block 11 2 Using the State Machine Editor Block 11 7 Chapter 12 Managing Projects and Files Integration with Source Control Systems 12 1 uses Aus nement Dei whens 12 2 MegaCore Functions he e eel 12 2 Memory Initialization Files A Rs ses 12 2 Exporting HDL 2 rever tea tne eee ones eme ses trees 12 3 Using Exported HDL 244 06 teste stad Coie iis see eens sms sun ER y Ee DE eds 12 4 Migration of DSP Buil
6. June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 16 8 Chapter 16 Complex Type Library Table 16 11 shows the Complex Constant block I O formats Table 16 11 Complex Constant Block 1 0 Formats 1 1 0 0 Simulink 2 3 1 neat tLt R1 Imag L1 01Real in STD LOGIC VECTOR LP1 RP1 1 DOWNTO 0 R1 O1lmag in STD LOGIC VECTOR ILP1 RP1 1 DOWNTO 0 VHDL Explicit Type 4 Notes to Table 16 11 For signed integers and signed binary fractional numbers the MSB is the sign bit L is the number of bits on the left side of the binary point R is the number of bits on the right side of the binary point For signed or unsigned integers R 0 that is L 0 For single bits R 0 that is 1 is a single bit Hj cR IS an input port O1 gj is an output port Explicit means that the port bit width information is a block parameter Implicit means that the port bit width information is set by the datapath bit width propagation mechanism To specify the bus format of an implicit input port use a Bus Conversion block to set the width 1 Figure 16 4 shows an example with Complex Constant blocks as inputs to a Complex AddSub block Figure 16 4 Complex Constant Block Example Complex AddSub Output1 Complexto Real Imag Complex Delay The Complex Delay block delays the incoming data by an amount sp
7. og swt z BusConversiond Binary To LEDGS IncrementS Seven Segment Simple 7 Segment Display 4 EURE z ES DW T LED12 1 1 1 swi2 ana 1 2 p2 L M bz EE p 25 0 P 25 0 25 23 p cased D 35 0 d 7 0 Invertq 7 0 gt z gt LED13 esI aa j ES BusConversion 5I M5 LA sus E g Increment4 ae lt i Simple 7 Segment Display 5 wiz 5114 LED14 Case Statement pusBuild y N LI LEDG7 ETS z LEDGE 1 016 1 A SWAB lici gt 3 T psi 28 0 P 08 0 28 25 9 102 0 6 0 z _S bz 11 sel Y Y BusCenversion Binary To C poi Increments Seven Segmenb3 Simple 7 Segment Display 5 gi 5 le LEDI7 ena a R2 517 25 0 25 0 25 23 p 38 0 d 7 10 Invert qi71 10 gt 3 soy aL R3 BusConversion7 5 5 kkl Increment lefautt p 6 Simple 7 Segment Display 7 Case Statement pusBuilda Cyclon
8. Use Add Subtract Port On or Off Turn on to use the direction input addsub Use Enable Port On or Off Turn on to use the clock enable input ena Dee SUTTON OUS GBA On or Off Turn on to use the asynchronous clear input 1 DSP Builder Handbook Volume 2 DSP Builder Standard Blockset June 2012 Altera Corporation Chapter 15 Arithmetic Library 15 25 Table 15 37 shows the Multiply Accumulate block I O formats Table 15 37 Multiply Accumulate Block 1 0 Formats 1 V0 Simulink 2 9 VHDL mE 11 in STD_LOGIC_VECTOR L1 R1 1 DOWNTO 0 I2 123 I2 in STD LOGIC VECTOR L2 R2 1 DOWNTO 0 13 13 STD_LOGIC Explicit Mj 14 in STD LOGIC Explicit 5r I5 in STD LOGIC li 16 in STD LOGIC O Ot roj o 01 out STD_LOGIC_VECTOR LO RO 1 DOWNTO 0 Explicit Notes to Table 15 37 1 For signed integers and signed binary fractional numbers the MSB is the sign bit 2 L is the number of bits on the left side of the binary point R is the number of bits on the right side of the binary point For signed or unsigned integers R 0 that is L 0 For single bits R 0 that is 1 is a single bit 3 Hj is an input port O1 is an output port L R L R 4 Explicit means that the port bit width information is a block parameter Implicit means that the port bit width information is set by the datapath bit width propagatio
9. V0 Simulink 9 VHDL m I1 in STD LOGIC 1211 12 STD_LOGIC O Opp re 01 out STD_LOGIC_VECTOR LP RP 1 DOWNTO 0 Explicit Notes to Table 15 27 1 For signed integers and signed binary fractional numbers the MSB is the sign bit 2 L isthe number of bits on the left side of the binary point R is the number of bits on the right side of the binary point For signed or unsigned integers R 0 that is L 0 For single bits R 0 that is 1 is a single bit 2 4A 2 5 1 IS an input port 01 is an output port Explicit means that the port bit width information is block parameter Implicit means that the port bit width information is set by the datapath bit width propagation mechanism To specify the bus format of an implicit input port use a Bus Conversion block to set the width DSP Builder Handbook Volume 2 DSP Builder Standard Blockset June 2012 Altera Corporation Chapter 15 Arithmetic Library 15 19 Figure 15 10 shows an example with the Increment Decrement block Figure 15 10 Increment Decrement Block Example Increment Output Increment Output1 Unsigned Scope Integrator The Integrator block is a signed integer integrator with the equation q n D q n d n where D is the delay parameter Use this block for DSP functions such as CIC filters The equation z ig describes the transfer fun
10. Function Block Parameters Delay Delay AlteraBlockset mask link Delay Implements a parameterized delay The Number of Pipeline Levels specifies the delay length of the block The delay must be greater than or equal to 1 The Clock Phase Selection is a binary string which sets the phases in which the block is enabled For example 0100 The delay block is enabled only on the 2nd phase of 4 Use the Optional Ports tab to select use of the additional clock enable and reset control inputs Use the Initialization tab to select use of an optional non zero reset value use of which will increase the hardware resources used Main Optional Ports Initialization Number of Pipeline Stages 1 5 Click the Optional Ports tab and set the parameters Table 2 3 Table 2 3 Parameters for the Delay Block Parameter Value Clock Phase Selection 01 Use Enable Port Off Use Synchronous Clear port Off 6 Click OK 7 Draw a connection line from the right side of the SinIn block to the left side of the Delay block Add the SinDelay and Sinin2 Blocks To add the SinDelay and SinIn2 blocks follow these steps 1 Select the IO amp Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser 2 Dragand drop two Output blocks into your model positioning them to the right of the Delay block 3 Click the text under the block s
11. Scope RESERVE DATA1 AFTER CONFIGURATION E USE AS REGULAR IO RESERVE NCEO AFTER CONFIGURATION USE AS REGULAR IO RESERVE DCLK AFTER CONFIGURATION E USE AS REGULAR IO La Figure 24 18 shows the test design for the daughtercard connected to HSMC port A The test design for the daughtercard connected to HSMC port B is very similar Setting Up the Mezzanine Card Test Designs The required pin and clock assignments are already set up in the design examples If necessary you can set up your own test design with similar procedures to the procedures that Cyclone III EP3C120 DSP Board on page 24 9 describes June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 24 20 Chapter 24 Boards Library Board Configuration DSP Builder Handbook June 2012 Altera Corporation Volume 2 DSP Builder Standard Blockset N D E 5XAN 25 MegaCore Functions Library The MegaCore Functions library contains blocks that represent parameterizable IP that installs with the Quartus software DSP Builder supports the following Altera DSP IP CIC implements a cascaded integrator comb filter Te For more information refer to the MegaCore Function User Guide FFT implements a high performance fast Fourier transform or inverse FFT processor Te For more information refer to the FFT MegaCore Function User Guide FIR implements a finite impulse r
12. Stratix EP3SL150 DSP Board The Stratix III EP3SL150 DSP board provides a hardware platform for developing and prototyping low power high volume feature rich designs that demonstrate the Stratix III device s on chip memory embedded multipliers and the Nios II embedded soft processor Table 24 11 lists the blocks available to support the Stratix III EP3SL150 DSP board Table 24 11 Stratix Ill EP3SL150 DSP Board Blocks Block Description DisplayO User defined 4 digit seven segment LED display U27 o A2D 1 HSMC A me A2D 1 HSMC B Controls 14 bit signed analog to digital converters on the optional high speed A2D 2 HSMC A mezzanine cards HSMC You can optionally specify the clock signal A2D 2 HSMC B o D2A 1 HSMC A 0 D2A_1_HSMC_B Controls the 14 bit unsigned digital to analog converters on the optional high speed D2A 2 HSMC A mezzanine cards HSMC D2A 2 HSMC B Dip Switch Controls the user definable dual in line package switch SW5 You can optionally specify the clock signal June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 24 18 Chapter 24 Boards Library Board Configuration Table 24 11 Stratix Ill EP3SL150 DSP Board Blocks Block Description LEDO LED7 Controls eight user definable LEDs 020 027 PBO PB3 Controls four user definable push button switches 52 55 and the CPU reset CPU_RESETN push button
13. Name Value Description Double Constant Value Parameterizable Specifies the constant value that is formatted with the specified bus type Signed Integer Bus Type Signed The number format of the bus Unsigned Integer Single Bit number of bits gt 0 Parameterizable Specifies the number of bits to the left of the binary point including the sign bit This parameter does not apply to single bit buses number of bits gt 0 Parameterizable Specifies the number of bits to the right of the binary point This parameter applies only to signed fractional buses Rounding Mode Truncate Round Towards Zero Round Away From Zero Round To Plus Infinity Convergent Rounding The rounding mode Refer to the description of the Round block for more information about the rounding modes Saturation Mode Wrap Saturate The saturation mode Specify Clock On or Off Turn on to explicitly specify the clock name Clock User defined Parameterizable Specifies the name of the required clock signal Table 19 15 Constant Block 1 0 Formats 1 Table 19 15 shows the Constant block I O formats 1 0 Simulink 2 3 01 out STD_LOGIC_VECTOR LP 1 DOWNTO 0 VHDL Type Explicit Notes to Table 19 15 1 For signed integers and signed binary fractional numbers the MSB is the sign bit
14. Table 22 6 shows the Down Sampling block I O formats Table 22 6 Down Sampling Block 1 0 Formats 1 0 Simulink 2 3 VHDL Mat 11 in STD_LOGIC_VECTOR L1 R1 1 DOWNTO 0 Type 4 Implicit June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 22 4 Chapter 22 Storage Library Table 22 6 Down Sampling Block 1 0 Formats 1 0 Simulink 2 9 VHDL 4 011181 01 in STD_LOGIC_VECTOR L1 R1 1 DOWNTO 0 Implicit Notes to Table 22 6 1 For signed integers and signed binary fractional numbers the MSB is the sign bit 2 L is the number of bits on the left side of the binary point R is the number of bits on the right side of the binary point For signed or unsigned integers R 0 that is L 0 For single bits R 0 that is 1 is a single bit 3 Mur is an input port 1 gj is an output port 4 Explicit means that the port bit width information is a block parameter Implicit means that the port bit width information is set by the datapath bit width propagation mechanism To specify the bus format of an implicit input port use a Bus Conversion block to set the width Figure 22 2 shows an example with the Down Sampling block Figure 22 2 Down Sampling Block Example AltBus1 Down Sampling Scope Dual Clock FIFO The Dual Clock FIFO block implements a parameterized d
15. data valid DalaValid Ready Avalon MM Read FIFO To Workspace 1 n to 1 Multiplexer prewitt Compiling the Design In this example you use the Signal Compiler block to verify that your design generates valid HDL Alternatively use the TestBench block Avalon MM Interface Blocks Design Example in Verifying the Design on page 7 11 To verify your design follow these steps 1 Double click the Signal Compiler block 2 Select the family and device for the DSP Development board you are using The design example is configured for a Stratix 1525 board Figure 7 11 June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 7 18 Chapter 7 Using the Interfaces Library Avalon MM FIFO Design Example 3 Click Compile Figure 7 11 Signal Compiler Dialog Box DSPBuilder Signal Compiler Description This block controls the compilation of the design Parameters Quartus II Project sopc detector dspbuilder sopc _detector qpf Family C Use Board Block to Specify Device Device AUTO Simple Advanced SignalTap II Export Step 1 Compile Design Step 2 Select Device to Program Es Step 3 Program Device Messages Into Subscription Agreement Altera MegaCore Function License Info Agreement or other applicable license agreement including Info without limitation that your us
16. resumtt 0 Jena see 0 dataa 47 0 ot mm resist a 0 ati Hataa 7 01 i pr JF a mt dataa 7 144 Jena 0 scir resum5 0 mn This design requires three multipliers and one parallel adder The arithmetic operations increase the bus width in the following ways m Multiplying a x b in SBF format where lis left and r is right is equal to Ia ra x Ib rb The bus width of the resulting signal is Hal rb DSP Builder Handbook June 2012 Altera Corporation Volume 2 DSP Builder Standard Blockset Chapter 3 Design Rules and Procedures 3 7 Bit Width Design Rule m Adding a b SBF format where lis left and r is right is equal to la ra Ib rb Ic rc The bus width of the resulting signal is max la Ib 1 2 max ra rb rc The parallel adder has three input buses of 14 16 and 14 bits To perform this addition in binary DSP Builder automatically sign extends the 14 bit busses to 16 bits The output bit width of the parallel adder is 18 bits which covers the full resolution The following options can change the internal bit width resolution and therefore change the size of the hardware required to perform the function that Simulink describes m Change the bit width of the input data m Change the bit width of the output dat
17. DSP Builder Handbook Volume 2 DSP Builder Standard Blockset June 2012 Altera Corporation Chapter 16 Complex Type Library 16 5 Table 16 6 shows the Complex AddSub block I O formats Table 16 6 Complex AddSub Block 1 0 Formats 1 0 Simulink 2 3 l Real L1 R1 Imag L1 R1 INReal Ln Rn Imag Ln Rn 1 1 n 2 r4 VHDL 11Real in STD_LOGIC_VECTOR LP1 RP1 1 DOWNTO 0 in STD_LOGIC_VECTOR LP1 RP1 1 DOWNTO 0 InReal in STD LOGIC VECTOR ILPn RPn 1 DOWNTO 0 Inlmag in STD_LOGIC_VECTOR LPn RPn 1 DOWNTO 0 1 1 in STD_LOGIC 1 2 in STD_LOGIC Type 4 Implicit Implicit Implicit Implicit Ol Real max L1 Ln 1 max RI Rn 1 lmag max L1 Ln 1 max RI Rn 1 01Real out STD_LOGIC_VECTOR max LI Ln max RI Rn DOWNTO 0 Implicit O1Imag out STD_LOGIC_VECTOR max LI Ln max RI Rn DOWNTO 0 Implicit Notes to Table 16 6 For signed integers and signed binary fractional numbers the MSB is the sign bit L is the number of bits on the left side of the binary point R is the number of bits on the right side of the binary point For signed or unsigned integers R 0 that is L 0 For single bits R 0 that is 1 is a single bit Muj pry S an input port 01 gj is an output port Explicit means that the port bit width information is a block parameter Implicit means that the port b
18. Table 15 55 shows the Square Root block I O formats Table 15 55 Square Root Block 1 0 Formats 1 0 Simulink VHDL m 11 in STD_LOGIC_VECTOR L R DOWNTO 0 lr 12 in STD LOGIC Explicit Ir 13 in STD LOGIC 1 01 out STD_LOGIC_VECTOR L DOWNTO 0 Explicit 021 02 out STD_LOGIC_VECTOR L R DOWNTO 0 Notes to Table 15 55 1 For signed integers and signed binary fractional numbers the MSB is the sign bit 2 L isthe number of bits on the left side of the binary point R is the number of bits on the right side of the binary point For signed or unsigned integers R 0 that is L 0 For single bits R 0 that is 1 is a single bit 3 lij nj is an input port 1 gj is an output port 4 Explicit means that the port bit width information is a block parameter Implicit means that the port bit width information is set by the datapath bit width propagation mechanism To specify the bus format of an implicit input port use a Bus Conversion block to set the width Figure 15 21 shows an example of the Square Root block Figure 15 21 Square Root Block Design Example Increment Decrement Square Root DSP Builder Handbook June 2012 Altera Corporation Volume 2 DSP Builder Standard Blockset Chapter 15 Arithmetic Library Sum of Products The Sum of Products block implements the following expression q a 0 CO a
19. Outputs are idle valid 0 1 and 2 cycles of every packet respectively because the worst case input packet takes 4 cycles Symbols Per Beat 2 Packet Description A ZE Y Avalon ST Interface Symbols Per Beat 5 Packet Description Z Y X W U G EE D C B A Packet Mapping Packet mapping is the process of determining where the data for each field in each output interface is coming from as an input interface position pair To achieve packet mapping compare the field name strings For example the source of data for the Red field in a given output interface is the field on an input interface with the name Red It is not valid for any field name to exist on multiple input interfaces no two input interfaces may have a Red field It is valid however for multiple output interfaces to have the same field you may copy the Red data to two or more output interfaces DSP Builder Handbook Volume 2 DSP Builder Standard Blockset June 2012 Altera Corporation Chapter 18 Interfaces Library 18 17 single input or output interface can have multiple instances of the same field For example Red Green Red Blue represents a packet with two red symbols per packet The PFC matches the nth instance of a field on an input interface to the nth instance of the same field on an output interface If an output interface has Blue Green Red Red the data for the first Red field is taken from the
20. Signal Direction Description a0 a3 Input Operand a b0 b3 Input Operand b ena Input Optional clock enable 1 Input Optional asynchronous clear Output Result Table 15 39 shows the Multiply Add block parameters Table 15 39 Multiply Add Block Parameters Name Number of Multipliers Value 2 3 4 Description The number multipliers you want to feed the adder Signed Integer Bus Type Signed Fractional The number format you want to use for the bus Unsigned Integer gt 0 Specify the number of data input bits to the left of the binary point Input number of bits RN Parameterizable including the sign bit gt 0 Specify the number of data input bits to the right of the binary put Parameterizable point This option applies only to signed fractional formats Adder Mode Add Add Add Sub Sub Add Sub Sub The operation mode of the adder m Add Add Adds the products of each multiplier m Add Sub Adds the second product and subtracts the fourth m Sub Add Subtracts the second product and adds the fourth m Sub Sub Subtracts the second and fourth products Pipeline Register No Register Inputs Only Multiplier Only Adder Only Inputs and Multiplier Inputs and Adder Multiplier and Adder Inputs Multiplier and Adder The elements to pipeline The clock enable and asynchronous clear ports are available only if the block is registered I
21. number of bits Parameterizable option applies only to signed fractional formats Table 16 26 shows the Real Imag to Complex block I O formats Table 16 26 Real Imag to Complex Block 1 0 Formats 1 1 0 Simulink 2 9 VHDL 1 Real L1 R1 11Real in STD_LOGIC_VECTOR LP1 RP1 1 DOWNTO 0 implicit I2imag Lt R1 I11Imag in STD_LOGIC_VECTOR LP1 RP1 1 DOWNTO 0 OtReal in STD_LOGIC_VECTOR LP1 RP1 1 DOWNTO 0 Explicit R1 O1lmag in STD LOGIC VECTOR ILP1 RP1 1 DOWNTO 0 Notes to Table 16 26 1 For signed integers and signed binary fractional numbers the MSB is the sign bit 2 L is the number of bits on the left side of the binary point is the number of bits on the right side of the binary point For signed or unsigned integers R 0 that is L 0 For single bits R 0 that is 1 is a single bit 3 lin is an input port 1 gj is an output port 4 Explicit means that the port bit width information is a block parameter Implicit means that the port bit width information is set by the datapath bit width propagation mechanism To specify the bus format of an implicit input port use a Bus Conversion block to set the width Figure 16 9 shows an example with the Real Imag to Complex block Figure 16 9 Real Imag to Complex Block Example Complex Delay Output1 Increment Decrement1 Complex to Real
22. Saturate block 19 20 Serial To Parallel block 22 19 Shift Taps block 22 20 Signal Compiler 3 19 Adding to a model 2 17 16 14 Enabling SignalTap II options 6 6 License 13 1 Synthesis and compilation flows 3 19 Signal Compiler block 14 13 Signal data type display format 3 25 SignalTap II Design flow 6 1 Walkthrough 6 3 SignalTap logic analyzer 6 1 Features 1 2 Performing logic analysis 6 1 Signal Compiler options Trigger conditions 6 7 6 6 SignalTap II Logic Analyzer block 14 13 SignalTap II Node block 14 15 Simulation Setting the Simulink solver 2 3 Using ModelSim 2 18 Using Simulink 2 15 Simulation flow 3 20 Simulation library 21 1 Simulation model HDL 3 16 Simulink Comparison with Model Integration with 1 3 Solver 3 16 Single Pulse block 17 23 Sim 3 23 Single Port RAM block 22 22 Solver Setting simulation parameters 2 3 SOP Tap block 15 33 SOPC Builder June 2012 Altera Corporation Interfaces library 7 1 Support 1 2 SOPC builder Instantiating your design 7 12 Square Root block 15 35 State machine Implementing 11 1 State Machine Editor Walkthrough 11 7 State Machine Editor block 23 1 State Machine Functions library 23 1 State Machine table Walkthrough 11 2 State Machine Table block 23 3 Storage library 22 1 Stratix EP1S25 DSP board 24 11 Stratix EP1S80 DSP board 24 12 Stratix II EP2S180 DSP board 24 15 Stratix II EP2S60 DSP board 24 13 Stratix II EP2S90GX
23. 8 bit Signed Found Up B bit Signed 01000111 010010 0 7 2 7050 Constant Round Output Display 01000111 010001 7 lt a Constant1 Round1 Output Display1 Saturate Table 19 32 Saturate The Saturate block limits output to a maximum value If the output is greater than the maximum positive or negative value to be represented the output is forced or saturated to the maximum positive or negative value respectively Alternatively you can truncate the MSB Table 19 32 shows the Saturate block parameters Block Parameters Input Bus Type Value Description Signed Integer Signed Fractional Unsigned Integer The number format of the bus number of bits Specifies the number of bits to the left of the binary point including the gt 2 Paramaterizable sign bit This parameter does not apply to single bit buses number of bits Specifies the number of bits to the right of the binary point This gt 0 Parameterizabie parameter applies only to signed fractional buses Number of MSB Bits to Remove Saturation Type gt 0 Parameterizable Specifies how many bits to remove Saturate Truncate MSB Saturate truncate or specify the saturation limits for the output Enter Saturation Limits DSP Builder Handbook June 2012 Altera Corporation Volume 2 DSP Builder Standard Blockset Chapter 19 10 amp Bus Library Table 19 32 Saturate Block P
24. Name Value Description FPGA device device name The FPGA device Compile with Quartus Click to compile the IL block with the Quartus II software JTAG Cable cable name The JTAG cable Device in chain device location The required entry for the location of the device Scan JTAG Click to scan the JTAG interface for all JTAG cables attached to the system including any remote computers and the devices on each JTAG cable The available cable names and device names are loaded into the JTAG Cable and Device in chain list boxes Configure FPGA Click to configure the FPGA Transcript window Displays the progress of the compilation Figure 14 2 Example With the HIL Block Figure 14 2 shows an example with the HIL block Product Input Inputi20 0 OutputCordic 20 0 2 0 Input Inputt 0 0 OutputFilten29 0 OutputFilter HIL_ Scope L Refer to the Using Hardware in the Loop chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook Quartus II Global Project Assignment This block passes Quartus II global project assignments to the Quartus II project Each block sets a single assignment If you need to make multiple assignments use multiple blocks Figure 14 3 These assignments could set Quartus II compilation directives such as target device or timing requirements
25. Multiplier June 2012 Altera Corporation The Multiplier block supports two scalar inputs no multidimensional Simulink signals Operand a is multiplied by operand and the result r output as the following equation shows r axb The differences between the Multiplier block and the Product block are The Product block supports clock phase selection while the Multiplier block does not The Product block uses implicit input port data widths that it inherits from the signals sources whereas the Multiplier block uses explicit input port data widths that you must specify as parameters The Product block allows you to use the LPM multiplier megafunction whereas the Multiplier block always uses the LPM DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 15 22 Chapter 15 Arithmetic Library Table 15 32 shows the Multiplier block inputs and outputs Table 15 32 Multiplier Block Inputs and Outputs Signal Direction Description a Input Operand a b Input Operand b ena Input Optional clock enable 1 Input Optional asynchronous clear r Output Result r Table 15 33 lists the parameters for the Multiplier block Table 15 33 Multiplier Block Parameters Name Value Description Signed Integer Bus Type Signed Fractional The bus number format to use for the Multiplier block Unsigned Integer gt 0 Specify the number of bi
26. Notes to Table 15 34 1 For signed integers and signed binary fractional numbers the MSB is the sign bit 2 L is the number of bits on the left side of the binary point is the number of bits on the right side of the binary point For signed or unsigned integers 0 that is L 0 For single bits 0 that is 1 is a single bit 3 lp ig is an input port 01 rg is an output port 4 Explicit means that the port bit width information is a block parameter Implicit means that the port bit width information is set by the datapath bit width propagation mechanism To specify the bus format of an implicit input port use a Bus Conversion block to set the width Figure 15 14 shows an example with the Multiplier block Figure 15 14 Multiplier Block Example Increment Decrement Increment Decrement Output Pattern Multiplier St For more information about multiplier operations refer to the Multiplier Megafunction User Guide Multiply Accumulate The Multiply Accumulate block consists of a single multiplier feeding an accumulator which performs the calculation y a x b The input is signed integer unsigned integer or signed binary fractional formats June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 15 24 Chapter 15 Arithmetic Library Table 15 35 shows the Multiply Accumulate block inputs and outputs Table 15 35 Multiply Accum
27. Table 18 5 Signals Supported by the Avalon MM Read FIFO Block Signal Direction Description This port must be connected to Simulink blocks It simulates stall conditions of the Avalon MM bus and hence back pressure to the SOPC component For any simulation Stall Input cycle where the Stall signal is asserted no Avalon MM reads take place and the internal FIFO buffer fills When full the Ready output is de asserted so that no data is lost ics input This port should be connected to DSP Builder blocks and should be connected to outgoing data from the user design Input This port should be connected to DSP Builder blocks and should be asserted whenever z p the signal on the Data port corresponds to real data This port should be connected to Simulink blocks and corresponds to the data received TestDataOut Output over the Avalon MM bus This port should be connected to Simulink blocks and is asserted whenever TestDataOut corresponds to real data Ready Output When asserted indicates that the block is ready to receive data TestDataValid Output Table 18 6 shows the Avalon MM Read FIFO block parameters Table 18 6 Avalon MM Read FIFO Block Parameters Name Value Description Signed Integer Data Type Signed Fractional The number format of the bus Unsigned Integer number of bits gt 0 Specifies the number of bits to the left of the binary point including the
28. When on the multiplier output bit width is full resolution When off you Full Resolution for a Output Result On or Off can specify the number of bits in the output signal and the number of least significant bits LSBs truncated from the output signal gt 0 Output Number of Bits Specify the number of bits in the output signal Parameterizable gt 0 Output Truncated LSB Specify the number of LSBs to be truncated from the output signal Parameterizable June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 15 38 Chapter 15 Arithmetic Library Table 15 57 Sum of Products Block Parameters FPGA Implementation Value Distributed Arithmetic Dedicated Multiplier Circuitry Auto Description Use a distributed arithmetic dedicated multiplier or automatically determined implementation Use Enable Port On or Off Turn on to use the clock enable input ena Use Asynchronous Clear Port On or Off Turn on to use the asynchronous clear input aclr Table 15 58 shows the Sum of Product block I O formats Table 15 58 Sum of Products Block 1 0 Formats 1 1 0 Simulink 2 9 VHDL 4 11040 11 in STD LOGIC VECTOR IL 1 DOWNTO 0 id Explicit Ing joy In in STD LOGIC VECTOR IL 1 DOWNTO 0 1 I n 1 STD_LOGIC Explicit I n 2 l n 2 STD_LOGIC 0102 2 94 out STD_LOGIC
29. gt 1 T Width of Input a Parameterizable Specifies the width of the first bus to concatenate gt 1 Width of Input b Parameterizable Specifies the width of the second bus to concatenate Table 19 9 shows the Bus Concatenation block I O formats Table 19 9 Bus Concatenation Block 1 0 Formats 1 1 0 Simulink 2 9 VHDL 4 11 in STD_LOGIC_VECTOR N1 1 DOWNTO 0 12 12 in STD_LOGIC_VECTOR N2 1 DOWNTO 0 i June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 19 8 Chapter 19 10 amp Bus Library Table 19 9 Bus Concatenation Block 1 0 Formats 1 1 0 Simulink 2 3 01 out STD_LOGIC_VECTOR N1 N2 1 DOWNTO 0 Explicit VHDL Type 4 Notes to Table 19 9 1 For signed integers the MSB is the sign bit 2 N is the number of bits 3 M N is an input port O1 N is an output port 4 Explicit means that the port bit width information is a block parameter Figure 19 6 shows an example with the Bus Concatenation block Figure 19 6 Bus Concatenation Block Example Constant 1 Constant3 Constant a 7 0 NH bt oT amp CT ee Constant a 0 22 090 b 1 0 oA Display Display Bus Conversion The Bus Conversion block extracts a subsection of a bus including bus type and width con
30. q 3 0 Delayed Count Delayed Count Flipflop If Statement The If Statement block outputs a 0 or 1 result based on the IF condition expression Table 17 19 shows the If Statement block inputs and outputs Table 17 19 If Statement Block Inputs and Outputs Signal Direction Description a j Input Input ports n Input Optional ELSE IF input port true Output Output port high when true false Output Optional ELSE output port high when false You can build an IF condition expression with the signal values 0 or 1 and any of the permitted operators given in Table 17 20 Table 17 20 Supported If Statement Block Operators Operator Operation amp AND OR XOR Equal To E Not Equal To June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 17 12 Chapter 17 Gate amp Control Library Table 17 20 Supported If Statement Block Operators Operator Operation gt Greater Than lt Less Than Parentheses When writing expressions in an If Statement block ensure that the operators are always operating on the same types That is bus signals compare with and operate with bus signals and booleans the true or false result of such operations only compare with and operate with booleans In other words the types must be the same on either side of an operator Treat
31. 12 Double click on the Avalon MM Read Slave block to bring up the Block Parameters dialog box 13 Select Read for the address type Signed Integer for the data type and specify 8 bits for the data width 14 Click OK and notice that the Avalon MM Read Slave block redraws with three ports Address i1 0 Read ibit and Read Data 07 0 15 Complete your design by connecting the Avalon MM Read Slave ports Figure 7 7 To The default design example uses the Stratix II EP2S60 DSP Development Board If you have a different board such as the Cyclone II EP2C35 Development Board you must replace the board block and analog to digital converter blocks by corresponding blocks for the appropriate board For more information refer to the Boards Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook 16 Add oscilloscope probes to monitor the signals on the DSP development board 17 Click Save on the File menu in your model window to save your model DSP Builder Handbook June 2012 Altera Corporation Volume 2 DSP Builder Standard Blockset Chapter 7 Using the Interfaces Library 7 11 Avalon MM Interface Blocks Design Example 18 Run a simulation and observe the results on the oscilloscope probes Coefficient values 1 0 0 0 load into the filter Verifying the Design Before using your design in SOPC Builder use the TestBench block to verify your design To verify your design f
32. A Specified Path Cannot be Found or a File Name is Too Long The maximum length for a path is limited to 256 characters in the Windows operating system When the file path to a model or the name of the model is very long DSP Builder may attempt to create a file path exceeding this limit If this problem occurs reduce the length of the file path to the model or the length of its name Incorrect Interpretation of Number Format in Output from MegaCore Functions For some MegaCore functions DSP Builder may be unable to infer whether it should interpret output signals as signed unsigned signed fractional This issue can cause problems when visualizing the output For example by directly attaching scopes when the signal waveform may obscur because of the incorrectly inferred number formats Correct this issue by connecting to the output with an AltBus block or a Non synthesizable Output block as appropriate with the correct bus type assignment Simulation Mismatch For FIR Compiler MegaCore Function FIR Compiler MegaCore function generated functional simulation models generally do not output valid data until the data storage of these models is clear T For more information including a formula that estimates the number of cycles before relevant samples are available refer to the Simulate the Design section in the FIR Compiler User Guide Simulation Mismatch After Changing Signals or Parameters The simulation results may not mat
33. Block Description RS232 ROUT and Controls the RS232 serial receive output and transmit input J8 You can optionally RS232 TIN specify the clock signal for RS232 TIN Tur DisplayO and NET 8 Display Controls a dual user definable seven segment LED display D4 Controls three user definable push button switches SW0 SWO2 You can optionally SW0 SW2 ifv the clock sianal m specify the clock signal For information about setting up the board refer to the DSP Development Kit Stratix amp Stratix Professional Edition Getting Started User Guide For information about the supported hardware features refer to the Stratix EP1S80 DSP Development Board Data Sheet Figure 24 12 shows the design example for the Stratix EP1580 DSP board Figure 24 12 Design Example for the Stratix EP1S80 DSP Board gt a p DEBUG A 5 DEBUG ES zi as url 2 29 PEBUS A 3 rs SignalCompiler Chek SignalTap Il Analysis DEBUG A 5 DSP Board 1580 E gt 3 gt i ES Configuration DEBUG A u eo 1 a 3l Output Scope 5 E E p DEBUG A j Sine Wave st ADI _ A2D 1 DEBUG A 12 Btsgned PY t 6 a 1 ER pp DEBUG A Ma 5 0 ALAR socal E DEBUG A st DAC gt __ gt LUT 5 DAI 5088 Signed ToUnsigned 1
34. If you use Clock Derived blocks and there is only one system clock you must generate an appropriate clock signal for connection to the hardware device input pins for the derived clocks The Clock block defines the base clock domain and Clock Derived blocks define other clock domains DSP Builder specifies sample times in terms of the base clock sample time If there is no Clock block DSP Builder uses a default base clock with a Simulink sample time of 1 and a hardware clock period of 20 us This feature is available across all device families that DSP Builder supports If no Clock block is present the design uses a default clock pin named clock and a default active low reset pin named 1 The Signal Compiler block assigns a clock buffer and a dedicated clock tree to clock signal input pin automatically to maintain minimum clock skew If your design contains more Clock and Clock Derived blocks than there are clock buffers available non dedicated routing resources route the clock signals Clock Assignment DSP Builder identifies registered DSP Builder blocks such as the Delay block and implicitly connects the clock clock enable and reset signals in the VHDL design for synthesis When your design does not contain a Clock block Clock Derived block or PLL block all the registered DSP Builder block clock pins connect to a single clock domain signal clock in VHDL Define clock domains by the clock source blocks the Clock block
35. ScalingFactor 2 CoefBitWidth 1 1 FpCoef fix ScalingFactor FlCoef plot FpCoef o title Fixed point scaled coefficient value ImpulseData zeros 1 1000 ImpulseData 1 100 h conv ImpulseData FpCoef fftplot h title FIR Frequency response FirSamplingPeriod 1 The example model is AltrFir32 mdl DSP Builder Handbook June 2012 Altera Corporation Volume 2 DSP Builder Standard Blockset Chapter 26 Design Examples 26 1 MAC based 32 FIR Filter This design example illustrates how to implement a MAC based fixed coefficient 32 tap low pass FIR finite impulse response filter with a single Multiply Accumulate block and a single memory element for the tap delay line This design requires the MathWorks Signal Processing ToolBox to calculate the coefficient with the firl function coef fix fir1 32 3 8 2 16 1 Impulse zeros 1 1000 Impulse 1 1 h conv coef Impulse plot coef o title Fixed point scaled coefficient value fftplot h title Impulse Frequency response The example model is FIR MAC32 mdl Color Space Converter This design example illustrates how to implement a color space converter which converts R G B to Y C bCr The example model is TopCsc mdl Farrow Based Resampler This design example illustrates how to implement a Farrow based decimating sample rate converter Many integrated systems such as software defined radios S
36. You can use these blocks for large fan out signals and to enhance the diagram clarity June 2012 Altera Corporation DSP Builder Handbook Volume 2 DSP Builder Standard Blockset 3 22 Chapter 3 Design Rules and Procedures Create Black Box and HDL Import Figure 3 20 shows an example of the Goto and From blocks Figure 3 20