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ALTERA MAX II Device Handbook handbook

1. TC K al eee 5 TDI eee TDO S VL B eee SHIFT_IR X X X X n SHIFT DR X STATE i EXIT1 IR SELECT DR SCAN Data stored in After boundry scan EXIT1 DR register data has been Instruction Code UPDATE CAPTURE DR oundary scan dud out data UPDATE DR register is shifted entered into TDI will out of TDO shift out of EXTEST Instruction Mode The EXTEST instruction mode is used primarily to check external pin connections between devices Unlike the SAMPLE PRELOAD mode EXTEST allows test data to be forced onto the pin signals By forcing known logic high and low levels on output pins opens and shorts can be detected at pins of any device in the scan chain Figure 13 10 shows the capture shift and update phases of the EXTEST mode October 2008 Altera Corporation MAX II Device Handbook 13 12 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Devices IEEE Std 1149 1 BST Operation Control Figure 13 10 IEEE Std 1149 1 BST EXTEST Mode SDO INJ OEJ OUTJ PIN OUT N Capture Update Registers Registers SHIFT CLOCK X UPDATE HIGHZ MODE ms Capture Phase SDO
2. SDO PIN IN IN iB aar 2 4 Input A gt 0 Hb o From Device OE 1 1 0 Cell Circuitry And Or Logic Core OUT gt 0 00 D 1 1 0 D Q Pin pne Output Output Output A A A SHIFT CLOCK UP DATE HIGHZ MODE Global Signals EON Capture Update Registers Registers Table 13 2 describes the capture and update register capabilities of all boundary scan cells within MAX II devices Table 13 2 II Device s Boundary Scan Cell Descriptions Note 1 Captures Drives Output Output Capture OE Capture Input Capture Update 0 Update InputUpdate Pin Type Register Register Register Register Register Register Notes User 1 0 OUTJ OEJ PIN IN PIN OUT PIN OE Includes User Clocks Note to Table 13 2 1 TDI TDO TMS and pins and all VCC and GND pin types do not have boundary scan cells JTAG Pins and Power Pins MAX II devices do not have boundary scan cells for the dedicated JTAG pins TDI TDO TMS and TCK and power pins VCCINT VCCIO GNDINT and GNDIO October 2008 Altera Corporation MAX II Device Handbook 13 6 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices IEEE Std 1149 1 BST Operation Control IEEE Std 1149 1 BST Operation Control MAX II devices
3. E Pin A1 ID 7 e amp 0000000000000000 gt lt lt TE X 1 a iq LL PEP LS LLCS LS LOLOL PLS Le Lele Lele Lele Le Le II Device Handbook October 2008 Altera Corporation Chapter 7 Package Information Package Outlines 256 Pin FineLine Ball Grid Array FBGA dimensions and tolerances conform to ANSI Y14 5M 1994 Controlling dimension is in millimeters 1 15 Pin A1 may be indicated an ID dot or special feature in its proximity on package surface Moisture Sensitivity Level bag Package Information Package Outline Dimension Table Description Specification Millimeters Ordering Code Reference F Min Nom Max Package Acronym FBGA A 2 20 Substrate Material BT A1 0 30 A2 1 80 Regular 63Sn 37P b Typ Solder Ball Composition eL Pb free n 3Ag 0 5Cu Typ 0 70 REF JEDEC Outline Reference MS 034 Variation AAF 1 D 17 00 BSC Maximum Lead 17 00 BSC Coplanarity 0 008 inches 0 20 mm Weight 15g b 0 50 0 60 0 70 Printed on moisture barrier e 1 00 BSC October 2008 Altera Corporation
4. 2 UB Uses 8 bit x 16 bit Instruction Address s XX em XXX XX KK X MSB MSB High Impendance 50 16 bit Data Out 1 16 bit Data Out2 MSB MSB October 2008 Altera Corporation MAX II Device Handbook 9 28 Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Figure 9 27 shows the READ operation sequence for Base mode Figure 9 27 READ Operation for Base Mode nCS A SCK 1234 5 6 7 8 9 10111213 1415 16 171819 20 21 2223 23 li 51 8 bit e 8 bit e Instruction Instruction 50 5 High Impendance 8 bit Data Out 1 8 bit Data Out 2 MSB MSB II Device Handbook WRITE WRITE is the instruction for data transmission where the data is written to the UFM block The targeted location in the UFM block that will be written must be in the erased state FFFF before initiating a WRITE operation When data transfer is taking place the MSB is always the first bit to be transmitted or received nCS must be driven high before the instruction is executed internally You may poll the nRDY bit in the software status register for the completion of the internal self timed WRITE
5. Chapter 7 Package Information 1 9 Package Outlines Package Information Package Outline Dimension Table A2 1 05 REF 2 Regular 63Sn 37Pb Typ Solder Ball Composition Pb free Sn 3Ag 0 5Cu Typ m H H Um J EDEC Outline Reference MO 192 Variation DAC 1 D 11 00 BSC 1 0 008 inches 0 20 11 00 5 Weight 0 6 g b 0 45 0 50 0 55 Moisture Sensitivity Level on moisture barrier e 1 00 BSC Figure 7 4 100 Pin FineLine BGA Package Outline TOP VIEW BOTTOM VIEW a D 1 10 9 7 6 5 4 3 2 1 s icd DOO DD 000000 D n m JE G J 0000060660 EE b October 2008 Altera Corporation MAX II Device Handbook 1 10 144 Pin Plastic Thin Quad Flat Pack TQFP Chapter 7 Package Information Package Outlines dimensions and tolerances conform to ANSI Y14 5M 1994 Controlling dimension is in millimeters Pin 1 may be indicated by an ID dot or a special feature in its proximity on package surface II Device Handbook Package Information Package Outline Figure Reference Description Specificatio
6. M IN LA m EM 24 v 256 Pin Micro FineLine Ball Grid Array MBGA m All dimensions and tolerances conform to ASME Y14 5 1994 m Controlling dimension is in millimeters m Pin A1 may beindicated by an ID dot or a special feature in its proximity on package surface Package Information Part 1 of 2 Package Outline Dimension Table Part 1 of 2 Description Specification Millimeters Symbol Ordering Code Reference M Min Nom Max Package Acronym MBGA A 1 20 Substrate Material BT 1 0 15 Solder Ball Composition Pb free 5 3 9 0 5 2 1 00 J EDEC Outline Reference MO 192 Variation BH A3 0 60 REF ERU 0 003 inches 0 08 mm Weight 0 3 g E 11 00 BSC October 2008 Altera Corporation MAX II Device Handbook 1 14 Chapter 7 Package Information Package Outlines Package Information Part 2 of 2 Package Outline Dimension Table Part 2 of 2 0 30 Printed on moisture barrier bag Moisture Sensitivity Level 0 50 BSC Figure 7 7 256 Pin Micro FineLine BGA Package Outline TOP VIEW BOTTOM VIEW 20 18 16 14 12 10 8 6 4 2 Pin 1 19 17 15 13 11 9 7 5 3 1 Corner
7. About xiii How to Contact eh ee ge eee AN Ree 1 xiii Typographic Conventions 1 1 1 1 xiii Section MAX Il Device Family Data Sheet REVISION Elistory dent e ebd LL Op e nier Ph ue I 1 Chapter 1 Introduction troduction Ed eee entend ied deg aub Rer iR rice de honda dg Bede Vek tiens 1 1 Features NOTES 1 1 Referenced Documents 1 1 1 21 1 4 Document Revision History 1 1 2 2 1 4 Chapter 2 MAX II Architecture Introd uM UL PO MM UU EL 2 1 Functional Description eere RU RE HERES RENT RO ees ee Meee eat 2 1 Logic BLOCKS LEE 2 4 LAB Interconnects 2 2 2 2 2 2 4 LAB Control Signals si sais etudes ptores amore der ton died 2 5 Logic Elements eoque Rer EE HERE eae RE POE 2 6 LUT Chain and Register 2 8 addnsub Signal jeres te prt eee et eae Mane ex quos 2 8 LE Modes sss dome tpe tege e
8. Data Delay Y tra gt ra Data In LUT Chain Y E fe User Logic Element Output Routing Output t lh lash X LUT Delay ca Delay Delay emory 4 ur gt Taso po lt 5 XZ 1 0 Input Delay 28 Register Control ty Ux 1 0 P in t Delay ty NN Y te P bre aN gt tee NN N N N NON ES N Lo N N NN From Adjacent LE GLOB lt lt VO Pin Lg N Combinational Path Delay Global Input Delay To Adjacent LE me das The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device External timing parameters which represent pin to pin timing delays can be calculated as the sum of internal parameters Ss Refer to the Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook for more information This section describes and specifies the performance internal external and UFM timing specifications specifications are representative of the worst case supply voltage and junction temperature conditions Preliminary and Final Timing Timing models can have either preliminary or final status The Quartus II software issues an informational message during the design compilation if the timing models are preliminary Table 5 13 shows the status of
9. 4 4 6 2 Document Revision History 1 6 2 Section Il PCB Layout Guidelines Revision HIStory URL hber TU Ple cds ud 1 Chapter 7 Package Information Introduction 5552 9945 kde eR e ry ue rs PRSE ERE REPRE UE RARE gro 7 1 Board Decoupling Guidelines 7 1 Device and Package Cross Reference 7 1 Thermal Resistance ott gaat dia Sd D Ee ie ewe d 7 2 Package Outlines eta decd us Vp SR Ra HR ee IC ee rae er pe e dete 7 3 68 Pin Micro FineLine Ball Grid Array MBGA Wire Bond 7 3 100 Pin Plastic Thin Quad Flat Pack TOFP 7 5 100 Pin Micro FineLine Ball Grid Array 7 7 100 Pin FineLine Ball Grid Array FBGA 7 8 144 Pin Plastic Thin Quad Flat Pack TOFP 7 10 144 Pin Micro FineLine Ball Grid Array MBGA Wire Bond 7 12 256 Pin Micro FineLine Ball Grid Array 7 13 256 Pin FineLine Ball Grid Array FBGA
10. Exit Code Description 0 Success 1 Checking chain failure 2 Reading IDCODE failure 3 Reading USERCODE failure 4 Reading UESCODE failure 5 Entering ISP failure 6 Unrecognized device ID 7 Device version is not supported 8 Erase failure 9 Blank check failure 10 Programming failure 11 Verify failure 12 Read failure 13 Calculating checksum failure 14 Setting security bit failure 15 Querying security bit failure 16 Exiting ISP failure 17 Performing system test failure Running the Jam STAPL Byte Code Player Calling the Jam STAPL Byte Code Player is like calling any other sub routine In this case the sub routine is given actions and a file name and then it performs its function In some cases in field upgrades can be performed depending on whether the current device design is up to date The JTAG USERCODE is often used as an electronic stamp that indicates the PLD design revision If the USERCODE is set to an older value the embedded firmware updates the device The following pseudocode illustrates how the Jam Byte Code Player could be called multiple times to update the target PLD result jbi execute jbc file pointer jbc file size 0 0 READ USERCODE 0 error line exit code The Jam STAPL Byte Code Player will now read the JTAG USERCODE and export it using the jbi export routine The code can then branch based upon the result October 2008 Altera Corporation MAX I
11. Date and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 1 7 December 2007 m Removed Figure 13 14 version 1 6 m Updated Figure 13 6 m Added Referenced Documents section December 2006 m Added document revision history version 1 5 August 2006 m Updated IEEE Std 1149 1 BST Operation version 1 4 m Control section July 2006 m Updated BST for Programmed Devices section version 1 3 June 2005 m Added a paragraph under the USERCODE Instruction Mode section version 1 2 m Added a new section BST for Programmed Devices January 2005 Previously published as Chapter 14 No changes to content version 1 1 March 2004 m Initial Release version 1 0 II Device Handbook October 2008 Altera Corporation 14 Using Jam STAPL for ISP via an ANU S p AN Embedded Processor Introduction Advances in programmable logic devices PLDs have enabled the innovative in system programmability ISP feature The Jam Standard Test and Programming Language STAPL JEDEC standard JESD 71 is compatible with all current PLDs that offer ISP via Joint Test Action Group JTAG providing a software level vendor independent standard for in system programming and configuration Designers who use Jam STAPL to implement ISP enhance the quality flexibility and life cycle of their end products Regardless of the number of PLDs
12. 11 5 Disabling IEEE Std 1149 Circuitry nere euren Rope dte ed ERROR AR 11 5 Working with Different Voltage Levels 11 6 Sequential versus Concurrent Programming 2 1 4 2 1 11 6 Sequential Programming 2 1 24 1 1 2 11 6 Concurrent Programming ions use tenor dedos Pippo s deg eg ope ated eh 11 6 ISP Troubleshooting Guidelines 11 7 Invalid ID and Unrecognized Device Messages 11 7 Download Cable Connected Incorrectly 11 7 TDO Is Not Connected essens rras eee ed led ee ga dn 11 8 Incomplete JTAG Chain 11 8 Noisy TCK ep tie BE mata woe res terree qe se restos Rol 11 8 Jam Player Ported Incorrectly 11 8 Troubleshooting Dips oen I Rer m ehe a entend eee ce en 11 8 Verify the JTAG Chain Continuity 11 8 Check the Vcc Level of the Board During In System Programming 11 9 Power p Problems 22 nrc te ee
13. Symbol Parameter Min Max Unit JTAG port setup time 2 8 ns lon JTAG port hold time 10 ns JTAG port clock to output 2 15 ns Lex JTAG port high impedance to valid output 2 15 ns lox JTAG port valid output to high impedance 2 15 ns tissu Capture register setup time 8 ns sn Capture register hold time 10 ns tsco Update register clock to output 25 5 tszx Update register high impedance to valid output 25 ns Low Update register valid output to high impedance 25 ns Notes to Table 5 34 1 2 Minimum clock period specified for 10 pF load on the pin Larger loads on will degrade the maximum frequency This specification is shown for 3 3 V LVITL LVCMOS and 2 5 V LVTTL LVCMOS operation of the JTAG pins For 1 8 V LVTTL LVCMOS and 1 5 V LVCMOS the minimum is 6 ns and typco tyezx and tpxz are maximum values at 35 ns Referenced Documents II Device Handbook This chapter references the following documents m Structure section in the MAX II Architecture chapter in the MAX II Device Handbook m Hot Socketing and Power On Reset in MAX II Devices chapter in the MAX II Device Handbook m Operating Requirements for Altera Devices Data Sheet m PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook m Understanding and Evaluating Power in MAX II Devices chapter in the MAX II Device Handbook
14. 15 5 Create the Library for the Target Device Scan Chain 15 5 Run the Test Consultant ots e ger E a RE ex a e Ra ERR ER 15 6 Create Digital Tests 15 6 Create the Wirelist Information for the Tests 15 6 Modify the Test Plans ES a E eL b Picea di uet 15 6 Step 5 Compile the Executable Tests 15 7 Debug the Test occ oec erectis de 15 7 Development Flow for Agilent 3070 with PLD ISP Software 15 8 Programming TIMES 12 xe sem aidan EE Re br dob e pue 15 10 Guidelines st vaa E cdot ita 15 10 Conclusion hatin eh endet 15 11 Referenced Documents ku eee ERR ERE EAE ek br rds 15 11 Document Revision History 1 2 2 1 15 11 Section V Design Considerations Revision History esset Re Re ERE epe er e n eu peri ega s bee V 1 Chapter 16 Understanding Timing in MAX II Devices Rm 16 1 External Timing Parameters 16 1 Internal Timing Parameters eeu ye
15. 9 13 Inter Inteerated Circuit 42 cese cirit we C EE P erp ete het d 9 14 IX Protocolo eoo cease ces ed rU IUDICIUM Le 9 14 Device Addressing vetere eR erode ean COE Cpu p dex das 9 16 Byte Write Op ration Edu tiger estesa sese itn aedis id 9 16 Page Write Operation evadere t RI uer eR ER RR HERR GU ERR re dq 9 17 Waite Protection ics ces coe mins a thea er NECI Sees pe 9 17 Erase Op ration de neat date OE 9 18 Read Operation ccs 9 20 ALTUFM Interface Timing Specification 9 22 Instantiating the I2C Interface Using the Quartus II altufm Megafunction 9 22 Serial Peripheral Interface bx eme RHENUM henri 9 24 Opcodes vele e b LII E 9 25 ALTUFM SPI Timing Specification 9 34 Instantiating SPI Using Quartus altufm Megafunction 9 35 Parallel Int tface sic icoe E ER b Der Reb ES pede bebe PROPERE 9 36 ALTUFM Parallel Interface Timing Specification 9 37 Instantiating Parallel Interface Using Quartus altufm Megafunction 9 38 None Altera Serial Interface
16. DRCIK 4 DRDin X X T gt 1 DDH i DRDout MZ XX 5 5 USCH x OSC_ENA EN Program M Erase u ie Erase The ERASE signal initiates an erase sequence to erase one sector of the UFM The data register is not needed to perform an erase sequence To indicate the sector of the to be erased the MSB of the address register should be loaded with 0 to erase the UFM sector 0 or 1 to erase the UFM sector 1 Figure 9 2 on page 9 5 On a rising edge of the ERASE signal the memory sector indicated by the MSB of the address register will be erased The BUSY signal is asserted until the erase sequence is completed The address register should not be modified until the BUSY signal is de asserted to prevent the content of the flash from being corrupted This ERASE signal will be ignored when the BUSY signal is asserted Figure 9 10 illustrates the UFM waveforms during erase mode 5 When the UFM sector is erased it has 16 bit locations all filled with FFFF Each UFM storage bit can be programmed no more than once between erase sequences You can write to any word up to two times as long as the second programming attempt at that location only adds Os 1s are mask bits for your input word that cannot overwrite Os in the flash array New 1s in the location can only be achieved by an erase Therefore it is pos
17. 2 MHz 1 8 to 5 5 EEPROM BR93L66FJ W 4096 7 2 MHz 1 8 to 5 5 EEPROM BR93L56RFJ W 2 048 2 MHz 1 8 to 5 5 EEPROM BR93L66RFJ W 4096 m 2 MHz 1 8 to 5 5 EEPROM BR93L56FV W 2 048 2 MHz 1 8 to 5 5 EEPROM BR93L66FV W 4096 2 MHz 1 8 to 5 5 EEPROM BR93L56RFV W 2 048 2 MHz 1 8 to 5 5 EEPROM BR93L66RFV W 4096 2 MHz 1 8 to 5 5 EEPROM BR93L56RFVM W 2 048 2 MHz 1 8 to 5 5 EEPROM BR93L66RFVM W 4096 2 MHz 1 8 to 5 5 EEPROM BR9020 W 2 048 m 2 MHz 2 7 t0 5 5 EEPROM BR9040 W 4096 2 MHz 2 7 t0 5 5 EEPROM BR9080AF W 8 19 2 MHz 2 7 t0 5 5 EEPROM BR9020F W 2 048 2 MHz 2 7 t0 5 5 EEPROM BR9040F W 409 2 MHz 2 7 to 5 5 EEPROM BR9080ARFV W 8 19 2 MHz 2 7 t0 5 5 October 2008 Altera Corporation MAX II Device Handbook 10 8 Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory List of Vendors and Devices Table 10 10 Rohm Co Ltd Device Characteristics Part 2 of 2 Interface Operating Size 2 3 Voltage V Type Device Bits SCI SPI Wire Wire
18. 2 2 7 15 324 Pin FineLine Ball Grid Array FBGA 2 7 16 Document Revision History 7 18 Chapter 8 Using MAX II Devices in Multi Voltage Systems TRE OG HCHOD no ean nthe D No teen DU ILLE M D EE 8 1 TO Standards Ped ee DE ep est das 8 2 MultiVolt CoreandI OOperation 2 24 4 8 3 5 0 V Device Compatibility ad RES ERES REG OR RESP Een 8 3 August 2009 Altera Corporation MAX II Device Handbook Recommended Operating Condition for 5 0 V Compatibility 8 7 HotSocketing kr tb TE ORE nes dis aes Deda a pe ps 8 8 Power U pSeq encdng er ved dede Y Eee pP PE PA ed 8 8 Power On 4 8 8 Conclusion bodes ERREUR REEL evertere E REP he des 8 8 Referenced Documents 1 4 8 9 Document Revision History 8 9 Section Ill User Flash Memory Revision HISTOrY em Ee III 1 Chapter 9 Using U
19. F tay J t gt Een Data In LUT Chain NNI 10E User Logic Element Output Routing Output Fan LUT Delay gt tea Delay Delay emory d i tur e sno Routin to 1 0 Input Delay gt urs a 9 Register Control tu ZX C 1 0 Pin t Delay ty n Y E p NN N LR N N gt X NN N k N N N N N N NN NS X NN From Adjacent LE GLOB 1 0 Pin INEU lt Combinational Path Delay N lt Global Input Delay To Adjacent LE N Register Delays Data Out II Device Handbook October 2008 Altera Corporation Chapter 16 Understanding Timing in MAX II Devices 16 5 Calculating Timing Delays Calculating Timing Delays You can calculate approximate pin to pin timing delays for MAX II devices with the timing model shown in Figure 16 1 and by referring to the DC and Switching Characteristics chapter in the MAX II Device Handbook Each external timing parameter is calculated from a combination of internal timing parameters Figure 16 2 through Figure 16 6 show the external timing parameters for the MAX II device family To calculate the delay for a signal that follows a different path through the MAX IT device refer to the timing model to determine which internal timing parameters to add together For the most precise timing results use the Quartus II Timing Analyzer which accounts for the effects of secondary factors such as placeme
20. Symbol Parameter Conditions Minimum Typical Maximum Unit Input pin leakage V to 0 V 2 10 10 current loz Tri stated 1 0 pin Vo Veciomax to 0 V 2 10 10 leakage current lecstaNDBY Vc Supply current II devices 12 mA standby 3 MAX IIG devices 2 mA EPM240Z Commercial 25 90 grade 4 EPM240Z Industrial 25 139 grade 5 EPM570Z Commercial 27 96 grade 4 EPM570Z Industrial 27 152 grade 5 6 Hysteresis for Schmitt Vecio 3 3 V 400 mV trigger input 7 Vus 2 5 V 190 mV lccPoweRuP Vecwr SUpply current MAX II devices 55 mA during power up 8 MAX IIG and MAX IIZ 40 mA devices Reutue Value of 1 0 pin pull up Vecio 3 3 V 9 5 25 resistor during user Veco 2 5 V 9 10 40 mode and in system programming Veco 1 8 V 9 25 60 Vecio 1 5 V 9 45 95 KQ August 2009 Altera Corporation MAX II Device Handbook Table 5 4 MAX II Device DC Electrical Characteristics Note 1 Part 2 of 2 Chapter 5 DC and Switching Characteristics Operating Conditions Symbol leui tup 0 pull up resistor current when 1 0 is unprogrammed Conditions Typical Maximum 300 Unit Cio Input capacitance for user 1 0 pin pF Notes to Table 5 4 1 Typical values are for Ta 25 C 3 3 or 2 5 V
21. 1 5 V VCCI ER 0 0 0 0 5 1 0 15 20 Voltage V 2 5 30 35 MAX II Output Drive lo Characteristics Maximum Drive Strength 3 3 V VCCIO 1 8 V VCCIO Typical Output Current mA 1 5 V VCCIO 10 15 20 25 Voltage V MAX II Output Drive Characteristics Minimum Drive Strength 3 3 V VCCIO 10 118 V VCCIO Typical l Output Current mA XX 0 o 0 0 0 5 10 15 20 Voltage V 2 5 3 0 3 5 MAX II Output Drive lo Characteristics Minimum Drive Strength 3 3 V VCCIO 84V VCCIO Typically Output Current mA 10 15 20 25 Voltage V Note to Figure 5 1 1 The DC output current per pin is subject to the absolute maximum rating of Table 5 1 1 0 Standard Specifications Table 5 5 through Table 5 10 show the MAX II device family I O standard specifications Table 5 5 3 3 V LVTTL Specifications Symbol Parameter Conditions Minimum Maximum Unit Vecio 1 0 supply voltage 3 0 3 6 V High level input voltage 1 7 4 0 V Vi Low level input voltage 0 5 0 8 V Von High level output voltage IOH 4 7 2 4 V Low level output voltage IOL 4 mA 7 0 45 Table 5 6 3 3 LV
22. 4 1 I O Pins Remain Tri Stated during Power Up 4 2 Signal Pins Do Not Drive the or Vecint Power Supplies 4 2 AC and DC Specihca tions ic a a aea a a E 4 2 Hot Socketing Feature Implementation in MAX Devices 4 2 Rower Oni Reset CIECUIE cea REESE ee diet dhe Ele 4 5 Power Up Characteristics Lawes pede 4 6 Referenced Documents metes eet v scu Ve data eae bos ets 4 8 Document Revision History 4 8 Chapter 5 DC and Switching Characteristics INtrOdUCtION 5 1 II Device Handbook August 2009 Altera Corporation Operating Conditions inner ner be 5 1 Absolute Maximum Ratings 5 1 Recommended Operating Conditions 5 2 Programming Erasure Specifications 5 3 DC Electrical Characteristics 222 25 225 e e be e b ee aer sue ded 5 3 Output Drive Characteristics oec om ote teo Atte 5 5 Standard Specifications i c cile cesa ek us exu EUR RR eR C
23. EPM1270G EPM2210 V4 EPM2210G 2407 v EPM570Z v v II Device Handbook August 2009 Altera Corporation Chapter 1 Introduction Features MAX II devices are available in space saving FineLine BGA Micro FineLine BGA and thin quad flat pack TOFP packages refer to Table 1 3 and Table 1 4 MAX II devices support vertical migration within the same package for example you can migrate between the EPM570 1270 and EPM2210 devices in the 256 pin FineLine BGA package Vertical migration means that you can migrate to devices whose dedicated pins and JTAG pins are the same and power pins are subsets or supersets for a given package across device densities The largest density in any package has the highest number of power pins you must lay out for the largest planned density in a package to provide the necessary power pins for migration For I O pin migration across densities cross reference the available I O pins using the device pin outs for all planned densities of a given package type to identify which I O pins can be migrated The Quartus II software can automatically cross reference and place all pins for you when given a device migration list Table 1 3 MAX Packages and User 1 0 Pins 68 Pin 100 Pin 144 Pin 256 Pin Micro Micro 100 Pin Micro Micro 256 Pin 324 Pin FineLine Fin
24. ritti ERR RE RR estab dead ECERERUERE E E 9 39 Instantiating None Using Quartus II altufm Megafunction 9 39 Creating Memory Content 9 40 Memory Initialization for the altufm parallel Megafunction 9 43 Memory Initialization for the altufm spi Megafunction 9 43 Memory Initialization for the altufm_i2c Megafunction 9 44 II Device Handbook August 2009 Altera Corporation vii Simulation Parameters RE EUER COE amp ie a ade 9 46 Conclusi n kn P NUR EUR DG Cid xc br ide not RN Ga Ease did 9 46 Referenced Documents 4 9 47 Document Revision History 9 47 Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory introduction 4 2 o er Ebr de CE ERN EE RE RE ee deans keV HES e 10 1 DesigniConsiderations ee eu na a cc rs 10 1 List of Vendors and Devices 1 0 2 10 2 Conclusion ebur Ce Gc De e T RO RI EE CDU TAS 10 11 Referenced Documents 202 1 10 11 Document Revision Hi
25. CONFIG lt tconric 0v User Mode Operation User Mode nm Tri State _ Tri State Notes to Figure 4 5 1 Time scale is relative 2 Figure 4 5 assumes all Vecio banks power up simultaneously with the profile shown If not tcoyrig stretches out until all Vecio banks are powered gt After SRAM configuration all registers in the device are cleared and released into user function before I O tri states are released To release clears after tri states are released use the CLRn pin option To hold the tri states beyond the power up configuration time use the DEV OE pin option October 2008 Altera Corporation MAX II Device Handbook 4 8 Chapter 4 Hot Socketing and Power On Reset in MAX II Devices Referenced Documents Referenced Documents This chapter refereces the following documents m DC and Switching Characteristics chapter in the MAX II Device Handbook m Using MAX II Devices in Multi Voltage Systems chapter in the MAX II Device Handbook Document Revision History Table 4 1 shows the revision history for this chapter Table 4 1 Document Revision History Date and Revision Changes Made Summary of Changes October 2008 m Updated MAX II Hot Socketing Specifications and Power On version2 1 Reset Circuitry sections Updated New Document Format December 2007 m Updated Hot Socketing Feature Implementation in MAX
26. Votes to Table 13 1 1 The and TMs pins have internal weak pull up resistors 2 The pin has an internal weak pull down resistor The IEEE Std 1149 1 BST circuitry requires the following registers m Theinstruction register which is used to determine the action to be performed and the data register to be accessed m Thebypass register which is a 1 bit long data register used to provide a minimum length serial path between TDI and TDO m Theboundary scan register that is a shift register composed of all the boundary scan cells of the device II Device Handbook October 2008 Altera Corporation Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Il Devices 13 3 IEEE Std 1149 1 Boundary Scan Register Figure 13 2 shows a functional model of the IEEE Std 1149 1 circuitry Figure 13 2 IEEE Std 1149 1 Circuitry TDI gt em UPDATEIR 5 52 1 gt CLOCKIR ja SHIFTIR gt M TAP Instruction Decode TMS Controller VIEN ELT gt UPDATEDR gt Data Registers CLOCKDR Bypass Register SHIFTDR j 4 Boundary Scan Register 1 ISP Registers Note to Figure 13 2 1 Refer to the J7AG and In System Programmability chapter in the MAX Device Handbook for the boundary scan regi
27. 3 1 JT AG Block EE E E DECIES EE 3 3 Parallel Flash Loader RR e ere 3 3 In System Programmability rx RS tente UES fonde 3 4 1532 SuppOrt senem eR heed tie RR RR bee RE GERD bee das 3 5 Jam Standard Test and Programming Language STAPL 3 5 Programming Sequence 225454255 y Rer pu v RE PEE TY ee RP RR EORR E Rea 3 5 UFM d d die et 3 6 In System Programming 2 2 2 2 2 2 2 2 22 2 2 2 2 2 2 2 3 6 Real Time ISP 3544 DEC a aes ma Rub E E daw have ba ae 3 7 Security d ruota races Abest aces dent fures Gender 3 7 Programming with External Hardware 3 7 Referenced Documents 1 e e ah he 3 7 Document Revision History iiec e x aH EUR E e He eo 3 8 Chapter 4 Hot Socketing and Power On Reset in MAX Il Devices MUSS 4 1 MAX II Hot Socketing Specifications 4 1 Devices Can Be Driven before Power Up
28. 4 Logic Logic Logic Element Element Element MultiTrack gt Interconnect 4 Logic Logic Logic Element Element Element 3 4 Logic Logic Logic Element Element e e Logic Logic Logic Logic ca Element Element Element Block LAB e A MultiTrack Interconnect II Device Handbook Each MAX II device contains a flash memory block within its floorplan On the 240 device this block is located on the left side of the device On the EPM570 EPM1270 EPM2210 devices the flash memory block is located on the bottom left area of the device The majority of this flash memory storage is partitioned as the dedicated configuration flash memory CFM block The CFM block provides the non volatile storage for all of the SRAM configuration information The CFM automatically downloads and configures the logic and I O at power up providing instant on operation For more information about configuration upon power up refer to the Hot Socketing and Power On Reset in MAX II Devices chapter in the MAX II Device Handbook A portion of the flash memory within the MAX II device is partitioned into a small block for user data This user flash memory UFM block provides 8 192 bit
29. 460 530 966 1 410 ps generated output enable delay Inputrouting delay 224 291 358 318 410 509 ps too 2 Output delay buffer 1 064 1 383 1 702 1 319 1 526 1 543 ps and pad delay te 3 Output buffer 756 982 1 209 1 045 1 264 1 276 ps disable delay tx 4 Output buffer 1 003 1 303 1 604 1 160 1 325 1 353 ps enable delay Notes to Table 5 16 1 device target Refer to Table 5 32 5 24 for delay adders associated with different 1 0 standards drive strengths and slew rates Refer to Table 5 19 and 5 14 for ty delay adders associated with different 1 0 standards drive strengths and slew rates Refer to Table 5 17 and 5 13 for tx delay adders associated with different 1 0 standards drive strengths and slew rates Delay numbers for differ for each device density and speed grade The delay numbers for teros shown in Table 5 16 are based on an 240 Table 5 17 through Table 5 20 show the adder delays for t7 and tj microparameters when using an I O standard other than 3 3 V LVTTL with 16 mA drive strength Table 5 17 t7 IOE Microparameter Adders for Fast Slew Rate Part 1 of 2 MAX II MAX IIG MAX 112 3 Speed 4 Speed 5 Speed 6 Speed 7 Speed 8 Speed Grade Grade Grad
30. ns period toss Data register shift 60 60 60 60 60 60 ns signal setup to data register clock Data register shift 20 20 20 20 20 20 ns signal hold from data register clock MAX II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics Timing Model and Specifications Table 5 21 UFM Block Internal Timing Microparameters Part 2 of 3 5 15 Symbol tons Parameter Data register data in setup to data register clock MAX II MAX IIG 3 Speed Grade 4 Speed Grade 5 Speed Grade Min 20 Max Min 20 Max Min 20 Unit ns toon Data register data in hold from data register clock 20 20 20 20 20 20 ns Program signal to data clock hold time ns Maximum delay between program rising edge to UFM busy signal rising edge 960 960 960 960 960 960 ns Minimum delay allowed from UFM busy signal going low to program signal going low 20 20 20 20 20 20 ns Maximum length of busy pulse during a program 100 100 100 100 100 100 us Minimum erase signal to address clock hold time ns Maximum delay between the erase rising edge to the UFM busy signal rising edge 960 960 960 960 960 960 ns
31. rames rer 16 2 Internal Timing Parameters for MAX UFM 16 3 Timing Models m 16 4 August 2009 Altera Corporation MAX II Device Handbook Calculating Timing D lays 454 rb eR ER Y p beds 16 5 Setup and Hold Time from an I O Data and Clock Input 16 6 Programmable Input Delay 16 7 Timing Model versus Quartus II Timing Analyzer 16 7 Conclusion 21 2 EE 16 8 Referenced Documents 16 8 Document Revision History 1 4 16 8 Chapter 17 Understanding and Evaluating Power in MAX II Devices IntroducHoD ci eei iu de eto eH Ld 17 1 Power MAX IT Devices 1 2 2 2 2 2 2 2 2 2 2 17 1 MAX II Power Estimation Using the PowerPlay Early Power Estimator 17 3 PowerPlay Early Power Estimator Inputs 17 3 Input Parameters eto IG ek nn usa Pob Van eee 17 4 Clock Section fiends dd ea Ctr ne Meee fuss abet ded ds 17 5 Lo
32. 2 0 MHz Read 1 8 5 5 Write 2 5 5 5 EEPROM S 29453A 8 192 v 2 0 MHz Read 1 8 5 5 Write 2 5 5 5 EEPROM 5 29330 4 096 va 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM S 29230A 2 048 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM S 29220A 2 048 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM S 29331A 4 096 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM S 29231A 2 048 Y 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM S 29221A 2 048 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM 29390A 4 096 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 II Device Handbook October 2008 Altera Corporation Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory 10 9 List of Vendors and Devices Table 10 11 Seiko Instruments Inc Device Characteristics Part 2 of 3 Interface Size Operating Voltage Type Device Bits SCI 1 Wire 2 Wire 3 Wire FC Microwire fmax 1 EEPROM S 29290A 2 048 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM 5 29391 4 096 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM 5 29291
33. 500 kHz 0 9 to 3 6 EEPROM 5 297 30 8 192 v 500 kHz 0 9 to 3 6 EEPROM S 24CS08A 8 192 V4 400 kHz Read 1 8 to 5 5 Write 2 7 to 5 5 EEPROM S 24CS04A 4 096 V4 400 kHz Read 1 8 5 5 Write 2 7 5 5 EEPROM S 24CS02A 2 048 v 400 kHz Read 1 8 5 5 Write 2 7 5 5 EEPROM S 24C08A 8 192 v 400 kHz Read 1 8 5 5 Write 2 7 5 5 October 2008 Altera Corporation MAX II Device Handbook 10 10 Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory Table 10 11 Seiko Instruments Inc Device Characteristics Part 3 of 3 List of Vendors and Devices Interface Size Operating Voltage Type Device Bits SCI 1 Wire 2 Wire 3 Wire FC Microwire fmax V 1 EEPROM S 24C04A 4 096 100 kHz Read 1 8 5 5 Write 2 5 5 5 EEPROM 5 24602 2 048 v 100 kHz Read 1 8 5 5 Write 2 5 5 5 EEPROM S 24C04B 4 096 V4 400 KHz 2 0 to 5 5 EEPROM S 24C02B 2 048 v 400 KHz 2 0 to 5 5 Note to Table 10 11 1 The MAX II device supports two different Vecint of operating voltage ranges which supports the 1 71 to 1 89 V operating voltage range Table 10 12 STMicroelectronics Device Characteristics Part 1 o
34. For SPI Extended mode the WRITE operation is always done through the following sequence as shown in Figure 9 28 1 nCS is pulled low to indicate the start of transmission 2 An 8 bit WRITE opcode 00000010 is received from the master device If internal programming is in progress the WRITE operation is ignored and not accepted 3 A 16 bit address is received from the master device The LSB of the address will be received last As the UFM block can take only nine bits of address maximum the first seven address bits received are discarded 4 Acheck is carried out on the status register see Table 9 11 to determine if the WRITE operation has been enabled and the address is outside of the protected region otherwise Step 5 is bypassed 5 One word 16 bits of data is transmitted to the slave device through 51 6 is pulled back to high to indicate the end of transmission For SPI Base mode the WRITE operation is always performed through the following sequence in SPI 1 nCSis pulled low to indicate the start of transmission 2 An 8 bit WRITE opcode 00000010 is received If the internal programming is in progress the WRITE operation is ignored and not accepted 3 An 8 bit address is received A check is carried out on the status register see Table 9 11 to determine if the WRITE operation has been enabled and the address is outside of the protected region otherwise Step 4 is skipped Octo
35. II Device Handbook August 2009 Altera Corporation Section PCB Layout Guidelines RYA This section provides information for board layout designers to successfully layout their boards for MAX II devices It contains the required printed circuit board PCB layout guidelines device pin tables and package specifications This section includes the following chapters m Chapter 7 Package Information m Chapter 8 Using MAX II Devices in Multi Voltage Systems Revision History Refer to each chapter for its own specific revision history For information about when each chapter was updated refer to the Chapter Revision Dates section which appears in the complete handbook October 2008 Altera Corporation MAX II Device Handbook 2 Section Il Layout Guidelines Revision History MAX II Device Handbook October 2008 Altera Corporation 7 Package Information S RYAN MII51007 2 1 Introduction This chapter provides package information for Altera s MAXe II devices and includes these sections m Board Decoupling Guidelines on page 7 1 m Device and Package Cross Reference on page 7 1 m Thermal Resistance on page 7 2 m Package Outlines on page 7 3 In this chapter packages are listed in order of ascending pin count See Figure 7 1 through 7 17 Board Decoupling Guidelines Decoupling requirements are based on the amount of logic used in the device and the
36. Position Status Default at Power Up Description Bit 7 X 0 Bit 6 X 0 2 Bit 5 X 0 m Bit 4 X 0 Bit 3 BP1 0 Indicate the current level of block write protection 7 Bit2 BPO 0 Indicate the current level of block write protection 7 Bit 1 WEN 0 1 SPI WRITE enabled state 0 WRITE disabled state Bit 0 nRDY 0 1 Busy UFM WRITE Or ERASE cycle in progress 0 No UFM WRITE ERASE cycle in progress Note to Table 9 11 1 Refer to Table 9 12 and Table 9 13 for more information about status register bits BPI and BPO II Device Handbook The following paragraphs describe the instructions for SPI READ READ is the instruction for data transmission where the data is read from the UFM block When data transfer is taking place the MSB is always the first bit to be transmitted or received The data output stream is continuous through all addresses until it is terminated by a low to high transition at the nCS port The READ operation is always performed through the following sequence in SPI as shown in Figure 9 26 October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX II Devices 9 27 Software Support for UFM Block 1 nCS is pulled low to indicate the start of transmission 2 An 8 bit READ opcode 00000011 is received from the master device If internal programming is in progress READ is ignored and not accepted 3 16 bit address is received from the master device The LSB of t
37. version 1 4 January 2005 m Previously published as Chapter 12 No changes to content version 1 3 December 2004 m Added section User Flash Memory Operations During In System version 1 2 Programming June 2004 m Pull up resistor values Textual updates version 1 1 October 2008 Altera Corporation MAX II Device Handbook 11 12 Chapter 11 In System Programmability Guidelines for MAX II Devices Document Revision History II Device Handbook October 2008 Altera Corporation 12 Real Time ISP and ISP Clamp for S RYAN e Il Devices Introduction During in system programming most CPLDs automatically tri state their input output I O pins to prevent contention issues on a board After successful programming the device enters user mode and the new design begins to function Apart from this normal programming mode MAX devices also support real time in system programmability ISP and ISP Clamp programming modes which allow control of I O and device behavior during ISP This chapter describes the following two features and how to use them in the Quartus II software as well as the Jam Standard Test and Programming Language STAPL and Jam STAPL Byte Code Players m Real Time ISP on page 12 1 m ISP Clamp on page 12 4 Real Time ISP Real time ISP allows you to program a MAX II device while the device is still in operation The new design only replaces the existing de
38. 3856 915 923 923 ps 3 3 V PCI 20mA 19 25 31 72 7 74 ps Table 5 18 Microparameter Adders for Slow Slew Rate II IIG MAX 112 Standard Unit 3 3 V LVTTL 16 mA ps 8 mA ps 3 3 V LVCMOS 8mA ps 4 mA ps 2 5 VIVTTL 14 mA ps LVCMOS 7 m ps 3 3 V PCI 20 mA ps Table 5 19 t Microparameter Adders for Fast Slew Rate II MAX IIG 112 Standard Unit 3 3 V LVTTL 16 mA ps 8 mA ps 3 3 V LVCMOS 8 mA ps 4 mA ps 2 5 V IVTTL 14mA ps LVCMOS 7 mA ps 1 8 V IVITL 6mA ps LVCMOS 3 mA ps 1 5 V IVCMOS 4 mA ps 2 mA ps 3 3 V PCI 20 mA ps August 2009 Altera Corporation MAX II Device Handbook 5 14 Chapter 5 DC and Switching Characteristics Timing Model and Specifications Table 5 20 ty 0 Microparameter Adders for Slow Slew Rate MAX II MAX IIG 112 3 Speed 4 Speed 5 Speed 6 Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade Standard Min Min Max Min Max Min Max Min Max Min Max Unit 3 3 V LVTTL 16mA 206 20 247 1 433 1 446 1 454 ps 8mA 891 665 438 1 332 1 345 1 348 ps 3 3 05 8mA 206 20 247 1 433 1 446 1 454 ps 4mA 891
39. 687 1 1 1 ps m 326 423 521 1 1 1 ps Tocat 330 429 529 1 1 1 ps Note to Table 5 22 1 The numbers will only be available in a later revision August 2009 Altera Corporation MAX II Device Handbook 5 18 External Timing Parameters Chapter 5 DC and Switching Characteristics Timing Model and Specifications External timing parameters are specified by device density and speed grade external I O timing parameters shown are for the 3 3 V LVTTL I O standard with the maximum drive strength and fast slew rate For external I O timing using standards other than LVTIL or for different drive strengths use the I O standard input and output delay adders in Table 5 27 through Table 5 31 For more information about each external timing parameters symbol refer to the Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook Table 5 23 shows the external I O timing parameters for EPM240 devices Table 5 23 EPM240 Global Clock External 1 0 Timing Parameters Part 1 of 2 MAX II MAX IIG Symbol Parameter Condition Worst case pin to pin delay through 1 look up table LUT Unit Best case 10 pF 37 48 pin to pin delay through 1 LUT 5 8 5 Global clock 17 2 2 setup time 24 ns t Global clock
40. Airflow Select an available ambient airflow in linear feet per minute Ifm or meters per second m s The options are still air 100 Ifm 0 5 m s 200 Ifm 1 0 m s or 400 Ifm 2 0 m s Increased airflow results in a lower junction to air thermal resistance and thus lower junction temperature Clock Section MAX II devices have four global clocks each Each row in the Clock Domain subsection of the spreadsheet represents a clock network or a separate clock domain You must enter the clock frequency fmax in MHz the total fan out for each clock network used and the local clock enable percentage Figure 17 4 shows the Clock section in the PowerPlay Early Power Estimator spreadsheet Figure 17 4 Clock Section Total Power User Comments 50 0 00 50 0 00 Table 17 2 Clock Sect Table 17 2 describes the parameters in the Clock section of the PowerPlay Early Power Estimator spreadsheet ion Information Column Heading Clock Domain Clock Frequency MHz Description Enter a name for the clock network in this column optional entry Enter the frequency of the clock domain The operating frequency for MAX II and MAX IIG is between 0 and 304 MHz For MAX IIZ the operating frequency is between 0 and 152 MHz Total Fanout Enter the total number of logic element LE flipflops fed by this clock The number of resources driven by every global clock is reported in the Fanout column of th
41. II Device Handbook October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor 14 3 Embedded Systems Figure 14 2 Interface Logic Design Example data 1 0 2 0 result 2 0 mux Byteblaster nProcessor Select PR D TDI Reg gt ByteBlaster nProcessor Select CLR data 0 0 ByteBlaster TDI ByteBlaster TD DATAS TD data 110 ByteBlaster TMS d ByteBlaster TMS data 0 1 ByteBlaster PR TMS_Reg e 2 TDO TMS Reg data 1 1 ByteBlaster lt lt EU ByteBlaster TCK data 0 2 TCK_Reg data 1 2 DATA2 J d TCK Reg address decode EN u adr 19 0 C adr 19 0 AD VALID EM CLR gt TDI result gt gt 5 result2 gt TDO CLK nRESET In Figure 14 2 the embedded processor asserts the JTAG chain s address and the nW and R AS signals can be set to tell the interface PLD when the processor wants to access the chain A write involves connecting the data path data 3 0 tothe JTAG outputs of the PLD via the three D registers that are clocked by the system clock CLK This clock can be the same clo
42. Set preprocessor statements to exclude extraneous code Map JTAG signals to hardware pins Handle text messages from jbi_ export Customize delay calibration October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Software Development Step 1 Set Preprocessor Statements to Exclude Extraneous Code At the top of jbistub c change the default PORT parameter to EMBI all DOS Windows and UNIX source code and included libraries define PORT EMBEDDED Step 2 Map JTAG Signals to Hardware Pins 14 9 EDDED to eliminate The jbi jtag io function contains the code that sends and receives the binary programming data Each of the four JTAG signals should be re mapped to the embedded processor s pins By default the source code writes to the PC s parallel port The jbi jtag io signal maps the JTAG pins to the PC parallel port registers shown in Figure 14 6 Figure 14 6 Default PC Parallel Port Signal Mapping Note 1 Note to Figure 14 6 1 The PC parallel port hardware inverts the most significant bit 0 TDI 0 0 0 0 5 TCK OUTPUT DATA Base Address TDO X X X X INPUT DATA Base Address 1 The mapping is highlighted in the following jbi jtag io source code int jbi jtag io int tms int tdi int read tdo int data 0 int tdo 0 if jtag hardware _initialized initiali
43. m The device can be driven before and during power up or power down without any damage to the device itself m I O pins remain tri stated during power up The device does not drive out before or during power up thereby affecting other buses in operation m Signal pins do not drive the Veco or Vecinr power supplies External input signals to device I O pins do not power the device Veco or Ver power supplies via internal paths This is true if the Vccmr and the Veco supplies are held at GND gt Altera uses GND as reference for the hot socketing and I O buffers circuitry designs You must connect the GND between boards before connecting the V eccmr and the Vecio power supplies to ensure device reliability and compliance to the hot socketing specifications Devices Can Be Driven before Power Up Signals be driven into the MAX II device I O pins and GCLK 3 0 pins before or during power up or power down without damaging the device MAX II devices support any power up or power down sequence V Vccio Vecos Vcciov simplifying the system level design October 2008 Altera Corporation MAX II Device Handbook 4 2 Chapter 4 Hot Socketing and Power On Reset MAX II Devices Hot Socketing Feature Implementation in MAX II Devices 1 0 Pins Remain Tri Stated during Power Up A device that does not support hot socketing may interrupt system operation or cause contention by driving out before or during power up
44. August 2009 Altera Corporation 6 Reference and Ordering Information ANU S n AN MII51006 1 6 Software II devices are supported by the Altera Quartus II design software with new optional MAX PLUS look and feel which provides HDL and schematic design entry compilation and logic synthesis full simulation and advanced timing analysis and device programming Refer to the Design Software Selector Guide for more details about the Quartus II software features The Quartus software supports the Windows XP 2000 NT Sun Solaris Linux Red Hat v8 0 and HP UX operating systems It also supports seamless integration with industry leading EDA tools through the NativeLink interface Device Pin Outs Printed device pin outs for MAX II devices are available on the Altera website www altera com Ordering Information Figure 6 1 describes the ordering codes for MAX II devices For more information about a specific package refer to the Package Information chapter in the MAX II Device Handbook Figure 6 1 MAX II Device Packaging Ordering Information 240 G T 100 3 ES Family Signature Optional Suffix EPM MAX II Indicates specific device options or shipment method 3 ES Engineering sample Device Type A N Lead free packaging 240 240 Logic Elements 570 570 Logic Elements Speed Grade 1270 1 270 Logic Elements 2210 2 210 Logic Elements 3 4 5 6 7 or 8 with 3 being the
45. October 2008 Altera Corporation 7 3 MAX II Device Handbook 1 4 Chapter 7 Package Information Package Outlines Package Information Part 2 of 2 Package Outline Dimension Table Part 2 of 2 2 1 0 003 inches 0 08 mm 2 00 BSC Weight 0 19 5 00 BSC Moisture Sensitivity Level 2 on moisture barrier b 0 25 0 30 0 35 e 0 50 BSC Figure 7 1 68 Pin Micro FineLine BGA Package Outline TOP VIEW BOTTOM VIEW D Pin A1 Corner 9 8 7 6 4 3 2 1 1 OOOOO00000 A B Pin A11D 0 OO IN D 7 7 7 7 m eue OO G OOOOO00000 H O a _ b api e OO0OOO0 O0 O0 pure II Device Handbook October 2008 Altera Corporation Chapter 7 Package Information Package Outlines 100 Pin Plastic Thin Quad Flat Pack TQFP dimensions and tolerances conform to ANSI Y14 5M 1994 Controlling dimension is in millimeters 1 5 Pin 1 may be indicated by an ID dot or a special feature in its proximity on package surface October 2008 Altera Corporation Package Information Package Outline Dimension Table Description Specification Millimeters Symbol Ordering Code Reference T Min Nom Max Package Acronym TQFP A 120 Leadframe Materia
46. function sends text messages to stdio using the printf function The Jam STAPL Byte Code Player uses the jbi export signal to pass information for example the device UES or USERCODE to the operating system or software that calls the Player The function passes text in the form of a string and numbers in the form of a decimal integer For definitions of these terms refer to AN 39 IEEE 1149 1 JTAG Boundary Scan Testing in Altera Devices If there is no device available to stdout the information can be redirected to a file or storage device or passed as a variable back to the program that calls the Player Step 4 Customize Delay Calibration The calibrate delay function determines how many loops the host processor runs in a millisecond This calibration is important because accurate delays are used in programming and configuration By default this number is hard coded as 1 000 loops per millisecond and represented as the following assignment one ms delay 1000 If this parameter is known it should be adjusted accordingly If it is not known you can use code similar to that for Windows and DOS platforms Code is included for these platforms that count the number of clock cycles that run in the time it takes to execute a single while loop This code is sampled over multiple tests and averaged to produce an accurate result upon which the delay can be based The advantage to this approach is that calibration can vary ba
47. 0 0 hold time ns too Global clock 10 pF 2 0 4 3 2 0 56 to output delay 20 6 9 ns tou Global clock 166 216 high time ps ter Global clock 166 216 low time 253 ps global clock period for 16 bit counter 5 4 5 MAX II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics 5 19 Timing Model and Specifications Table 5 23 240 Global Clock External 1 0 Timing Parameters Part 2 of 2 MAX Il MAX IIG MAX 112 3 Speed 4 Speed 5Speed 6 Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Min Max Unit font Maximum 304 0 247 5 201 1 184 1 1235 118 3 MHz global clock 1 frequency for 16 bit counter Note to Table 5 23 1 The maximum frequency is limited by the 1 0 standard on the clock input The 16 bit counter critical delay performs faster than this global clock input pin maximum frequency Table 5 24 shows the external I O timing parameters for EPM570 devices Table 5 24 EPM570 Global Clock External 1 0 Timing Parameters Part 1 of 2 II MAX IIG 112 3 Speed 4 Speed 5 Speed 6 Speed 7Spe
48. 3 4 5 67 SCK Instruction 8 bit si y 20 5 50 High Impendance October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 31 Software Support for UFM Block UFM ERASE The UFM ERASE CE instruction erases both UFM sector 0 and sector 1 for SPI Extended Mode While for SPI Base mode the CE instruction has the same functionality as the SECTOR ERASE SE instruction which erases UFM sector 0 only WEN bit and the UFM sectors must not be protected for CE operation to be successful nCS must be driven high before the instruction is executed internally You may poll the nRDY bit in the software status register for the completion of the internal self timed CE cycle For both SPI Extended mode and Base mode the UFM ERASE operation is performed in the following sequence as shown in Figure 9 32 1 ncs is pulled low 2 Opcode 01100000 is transmitted into the interface 3 5 is pulled back to high Figure 9 32 shows the UFM ERASE operation sequence Figure 9 32 UFM ERASE Operation Sequence nCS 01234567 SCK Il 8 bit Instruction y s Y yx High Impendance WREN Write Enable The interface is powered up in the write disable state Therefore WEN in the status register see Table 9 11 is 0 at power up Before any writ
49. 34 34 34 ME 3 3 V LVCMOS 304 304 304 304 304 304 MHz 2 5 V LVTTL 220 220 220 220 220 220 MHz 2 5 V LVCMOS 220 220 220 220 220 220 MHz 1 8 V LVTTL 200 200 200 200 200 200 MHz 1 8 V LVCMOS 200 200 200 200 200 200 MHz 1 5 V LVCMOS 150 150 150 150 150 150 MHz 3 3 V PCI 304 304 304 304 304 304 MHz JTAG Timing Specifications Figure 5 6 shows the timing waveforms for the JTAG signals Figure 5 6 MAX II JTAG Timing Waveforms TMS X TDI C Y gt t psu jiet pH l C 0 1 9 i tpcok Rn 0550 Signal a N i i i to be X X X Captured 452 gt si sxzi Signal to be Driven Table 5 34 shows the JTAG Timing parameters and values for MAX II devices Table 5 34 MAX II JTAG Timing Parameters Part 1 of 2 Symbol Parameter Min Max Unit tee 1 Clock period for Veco 3 3 V 55 5 ns clock period for Veco 2 5 V 62 5 ns Clock period for Voc 1 8 V 100 ns Clock period for Vecio 1 5 V 143 ns tes TCK Clock high time 20 ns to TCK clock low time 20 ns August 2009 Altera Corporation MAX II Device Handbook 5 26 Chapter 5 DC and Switching Characteristics Referenced Documents Table 5 34 MAX II JTAG Timing Parameters Part 2 of 2
50. 665 438 1 332 1 345 1 348 ps 2 5 V LVTTL 14mA 222 4 2831 213 208 213 ps LVCMOS 7mA 943 717 490 166 161 166 ps 3 3 V PCI 20mA 161 210 258 1 332 1 345 1 348 ps 57 The default slew rate setting for MAX II devices in the Quartus II design software is fast Table 5 21 UFM Block Internal Timing Microparameters Part 1 of 3 MAX II MAX IIG MAX 112 3 Speed 4Speed 5Speed 6Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade Symbol Parameter Min Max Min Max Min Min Max Min Max Min Max Unit Addressregisterclock 100 100 100 100 100 100 ns period tasu Address register shift 20 20 20 20 20 20 ns signal setup to address register clock tan Address register shift 20 20 20 20 20 20 ns signal hold to address register clock Tos Address register data 20 20 20 20 20 20 ns in setup to address register clock bos Address register data 20 20 20 20 20 20 ns in hold from address register clock Data register clock 100 100 100 100 100 100
51. Chapter 5 DC and Switching Characteristics Timing Model and Specifications II MAX IIG 112 3 Speed 4Speed 5Speed 6 Speed 7Speed 8 Speed Grade Grade Grade Grade Grade Grade 1 0 Standard Min Max Min Max Min Max Min Min Max Min Max Unit 3 3 VLVCMOS Without Schmitt 0 0 0 0 0 0 ps Trigger With Schmitt 334 434 535 387 434 442 ps Trigger 2 5 V LVTTL WithoutSchmitt 23 30 37 42 4 43 ps LVCMOS Trigger With Schmitt 339 441 543 429 476 483 ps Trigger 1 8 VLVTTL WithoutSchmitt 291 378 46 378 373 373 ps LVCMOS Trigger 1 5 V LVCMOS Without Schmitt 681 885 1 090 681 622 658 ps Trigger 3 3 V PCI Without Schmitt 0 0 0 0 0 0 ps Trigger Table 5 28 External Timing Input Delay t Adders for GCLK Pins MAX II MAX IIG MAX 3 Speed 4 Speed bSpeed 6Speed 7Speed 8 Speed Grade Grade Grade Grade Grade Grade 1 0 Standard Min Max Min Max Min Max Min Min Max Min Unit 3 3 V LVTTL Without Schmitt 0 0 0 0 0
52. Create a Step 1 Printed Circuit Board PCB and Test Fixture Create SVF Jam or J BC File Create Executable Tests from F iles Compile Executable Step 4 Tests Step 2 Step 3 gt Debug Step 5 Programming Successful Some advantages of using the Agilent PLD ISP software over the SVF2PCF flow for device programming are The tester can support the programming of devices using 5 Jam STAPL or JBC file formats directly that is no conversion to PCF or VCL The Agilent 3070 digital test to program a device is only one file Pull up and pull down resistors are not required on the TCK and TMS lines in the fixture of the tester since the device programming executes entirely as one test The size of the digital test source file as well as the compiled object file is much smaller than with the SVF2PCF solution October 2008 Altera Corporation MAX II Device Handbook 15 10 Chapter 15 Using the Agilent 3070 Tester for In System Programming Programming Times m Execution time for larger CPLDs and configuration devices is faster as only single digital test file is executed With Agilent s PLD ISP software a Jam Byte Code Player is implemented in the Control XTP card of the tester This allows users to program devices using JBC files created directly from
53. MAX II Device Handbook JA DTE n AN 101 Innovation Drive San Jose CA 95134 www altera com MII5V1 3 3 Copyright 2009 Altera Corporation rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other productor service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending ap plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty butreserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services LS EN ISO 9001 NBD RYN Contents Chapter Revision Dates xi About this Handbook
54. Thermal Analysis Junction Temp Ty 9 4 Junction Ambient Maximum Allowed T October 2008 Altera Corporation Chapter 17 Understanding and Evaluating Power in MAX II Devices 17 15 Power Saving Techniques Table 17 8 Thermal Analysis Information Column Heading Description Junction Temp T Represents the estimated device junction temperature 0 Junction Ambient Represents the junction to ambient thermal resistance through the top of the device C W Maximum Allowed C Represents a guideline for the maximum ambient temperature C that the device can be subjected to without violating maximum junction temperature Power Supply Current The power supply current provides the estimated current consumption for power supplies The Iccpowerur is only applicable during power up when the configuration flash memory CFM block downloads to the SRAM The current is the supply current required from V c The total Icco current is the supply current required from Veco for all I O banks For estimates of based on I O banks refer to the I O Section on page 17 8 of the PowerPlay Early Power Estimator spreadsheet Figure 17 16 shows the Power Supply Current section Figure 17 16 Power Supply Current Power Supply Current mA lccPoweRUP Iccio Click lo for per Bank Table 17 9 describes the Power Supply Current parameters of
55. 1 The MAX II device supports two different Vccinr of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device supports the 1 71 to 1 89 V operating vo tage range Table 10 4 Catalyst Semiconductor Inc Device Characteristics Part 1 of 2 Interface Operating Size Voltage V Type Device Bits SCI SPI 2 Wire 3 Wire FC Microwire fmax 1 EEPROM CAT93C56 2 048 v 1 MHz 1 8 to 6 0 EEPROM CAT93C57 2 048 1 MHz 1 8 to 6 0 EEPROM CAT93C66 4 096 v 1 MHz 1 8 to 6 0 EEPROM CAT34WCO2 2 048 v 400 kHz 1 8 to 6 0 EEPROM CAT24WC03 2 048 v 400 kHz 1 810 6 0 October 2008 Altera Corporation MAX II Device Handbook 10 4 Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory List of Vendors and Devices Table 10 4 Catalyst Semiconductor Inc Device Characteristics Part 2 of 2 Interface Operating Size Voltage V Type Device Bits SCI SPI 2 Wire 3 Wire FC Microwire fmax 1 EEPROM CAT24WC05 400 kHz 1 8 to 6 0 EEPROM CAT24WC02 400 kHz 1 8 to 6 0 EEPROM CAT24WC04 400 kHz 1 8 to 6 0 EEPROM CAT24WCO08 400 kHz 1 8 to 6 0 EEPROM 641020 1 MHz 2 5 to 6 0 EEPROM CAT64LC40 1MHz 2 5 to 6 0 EEPROM CAT25C02 V4 10 MHz 1 8 to 6 0 E
56. 3 0 3 0 n 4 4 4 VOBlock Local Interconnect Fast 1 0 Interconnect LAB Column Path Clock 3 0 R4 Interconnects ENT Lr LAB LAB LAB LAB Local N LAB Local us LAB Local Interconnect VA Interconnect Interconnect 64 Interconnects 64 Interconnects Note to Figure 2 21 1 Each of the four IOEs in the column 1 0 block can have one data out Or fast out output one output and data in input 1 0 Standards and Banks MAX II device IOEs support the following I O standards m 3 3 V LVTTL LVCMOS m 2 5 VIVTIL LVCMOS m 1 8 V IVTIL LVCMOS m 1 5 V IVCMOS 3 3 V PCI II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 21 1 0 Structure Table 2 4 describes the 1 0 standards supported by MAX II devices Table 2 4 MAX II 1 0 Standards Output Supply Voltage 1 0 Standard Type VCCIO V 3 3 V LVTTL LVCMOS Single ended 3 3 2 5 V LVITL LVCMOS Single ended 2 5 1 8 V LVITL LVCMOS Single ended 1 8 1 5 V LVCMOS Single ended 1 5 3 3 V PCI 1 Single ended 3 3 Note to Table 2 4 1 3 3 V PCI compliant 1 0 is supported in Bank of the EPM1270 and EPM2210 devices The EPM240 and 570 devices support two I O banks as shown in Figure 2 22 Each of these banks support all the LVTTL and LVCMOS standards shown in Table 2 4 PCI compliant I O is
57. As Ai Ao Slave Address Input These inputs set the UFM slave address The Ag As As Slave address bits are programmable set internally to 1010 by default October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 15 Software Support for UFM Block START and STOP Condition The master always generates start S and stop P conditions After the start condition the bus is considered busy Only a stop P condition frees the bus The bus stays busy if the repeated start Sr condition is executed instead of a stop condition In this occurrence the start 5 and repeated start Sr conditions are functionally identical A high to low transition on the SDA line while the SCL is high indicates a start condition A low to high transition on the SDA line while the SCL is high indicates a stop condition Figure 9 12 shows the start and stop conditions Figure 9 12 Start and Stop Conditions Start Condition Stop Condition Acknowledge Acknowledged data transfer is a requirement of PC The master must generate a clock pulse to signify the acknowledge bit The transmitter releases the SDA line high during the acknowledge clock pulse The receiver slave must pull the SDA line low during the acknowledge clock pulse so that SDA remains a stable low during the clock high period indicating positive acknowledgement from the receiver If the receiver pulls the SDA line high du
58. E Memory E ditor Fonts El Messages Filtering E Resource Property E ditor Colors RTL Technology Map Viewer E SignalT ap Il Logic Analyzer View Colors Fonts Printing Er Text Editor Colors Fonts B B Editor zl Cars Real Time ISP with Jam and JBC Players ISP Clamp II Device Handbook You can use the Jam or JBC file created from the POF to program a MAX II device in real time ISP mode with the Jam or JBC Player For real time ISP with the Jam File and Jam Player type the following at the command line prompt jp_23 aprogram ddo real time isp 1 file name jam For Real Time ISP with the JBC File and JBC Player type the following at the command line prompt jbi 22 aprogram ddo real time isp 1 file name jbc The names of the executable files for the players are different depending on the version of the players Download the latest version of the Jam and JBC Player from the Altera web site at www altera com When a MAX II device enters normal ISP operation all the I O pins tri state and are weakly pulled up to Veco with internal pull up resistors However there are situations when the I O pins of the device should not be tri stated when the device is in ISP operation For instance in a running system some signals e g output enable or chip enable signals might use some of the I O pins and require those I O pins to assume a high or low logic level or even maintain their
59. EEPROM 24AA04 4096 v 400 kHz 2 1 8105 5 EEPROM 24AA08 8 192 v 400 kHz 2 1 8105 5 October 2008 Altera Corporation MAX II Device Handbook 10 6 Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory Table 10 8 Microchip Technology Inc Device Characteristics Part 2 of 2 List of Vendors and Devices Interface Operating Size Voltage V Type Device Bits SCI SPI 2 Wire 3 Wire Microwire fmax 1 EEPROM 24LC04B 4 096 400 1 8105 5 EEPROM 24LC08B 8192 400 kHz 1 8 to 5 5 EEPROM 24LC09 3 8 192 Advanced 400 kHz 2 5 to 5 5 Communic ation Riser 4 EEPROM 93LC66A 4096 2 5 to 6 0 EEPROM 93AA66 4096 1 8 to 5 5 EEPROM 93LC66B 4096 2 5 to 6 0 EEPROM 93LC56A 2048 2 5 to 6 0 EEPROM 93AA56 2048 2 MHz 1 8 to 5 5 EEPROM 93LC56B 2 048 2 MHz 2 5 to 6 0 EEPROM 25LC080 8192 v 2 MHz 2 510 5 5 EEPROM 25LC040 40 2 MHz 2 510 5 5 EEPROM 25AA080 8192 1MHz 1 8 to 5 5 EEPROM 25AA040 40 1 MHz 1 8 to 5 5 Notes to Table 10 8 1 supports the 1 71 to 1 89 V operating voltage range 100 kHz for Vec lt 2 5 This device i
60. For more information about resolving in system programming problems contact Altera Applications Referenced Documents II Device Handbook This chapter references the following documents m AN 75 High Speed Board Designs m ByteBlasterMV Download Cable User Guide m ByteBlaster Download Cable User Guide m DC and Switching Characteristics chapter in the MAX II Device Handbook m IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices chapter in the MAX II Device Handbook m JTAG and In System Programmability chapter in the MAX II Device Handbook m MasterBlaster Serial USB Communications Cable User Guide October 2008 Altera Corporation Chapter 11 In System Programmability Guidelines for MAX II Devices 11 11 Document Revision History m USB Blaster Download Cable User Guide m Using Jam STAPL for ISP via an Embedded Processor chapter in the MAX II Device Handbook Document Revision History Table 11 1 shows the revision history for this chapter Table 11 1 Document Revision History Date and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 1 7 December 2007 m Updated Pull Up and Pull Down of JTAG Pins During In System External pull up for is version 1 6 Programming section optional m Added Referenced Documents section December 2006 m Added document revision history version 1 5 August 2006 m Corrected Figure 11 1
61. In a hot socketing situation the MAX II device s output buffers are turned off during system power up MAX II devices do not drive out until the device attains proper operating conditions and is fully configured Refer to Power On Reset Circuitry on page 4 5 for information about turn on voltages Signal Pins Do Not Drive the V or Power Supplies MAX II devices do not have a current path from I O pins or GCLK 3 0 pins to the Veco Or pins before or during power up MAX II device may be inserted into or removed from a system board that was powered up without damaging or interfering with system board operation When hot socketing MAX II devices may have a minimal effect on the signal integrity of the backplane AC and DC Specifications Le You can power up or power down the Vecio and pins in any sequence During hot socketing the I O pin capacitance is less than 8 pF MAX II devices meet the following hot socketing specifications m Thehotsocketing DC specification is Lopn lt 300 uA m Thehotsocketing AC specification is lox 8 mA for 10 ns or less MAX II devices are immune to latch up when hot socketing If the TCK JTAG input pin is driven high during hot socketing the current on that pin might exceed the specifications above is the current at any user I O pin on the device The AC specification applies when the device is being powered up or powered down This specification take
62. Minimum delay allowed from the UFM busy signal going low to erase signal going low 20 20 20 20 20 20 ns Maximum length of busy pulse during an erase 500 500 500 500 500 500 ms Delay from data register clock to data register output ns August 2009 Altera Corporation MAX II Device Handbook 5 16 Chapter 5 DC and Switching Characteristics Timing Model and Specifications Table 5 21 UFM Block Internal Timing Microparameters Part 3 of 3 MAX II MAX IIG liZ 3 Speed 4Speed 5Speed 6Speed 7 Speed Grade Grade Grade Grade Grade Symbol Parameter Min Min Max Min toe Delay from data 180 180 180 register clock to data register output Unit ns tra Maximum read 6 65 access time ns loscs Maximum delay 250 250 250 250 between the OSC_ENA rising edge to the erase program signal rising edge toscu Minimum delay 250 250 250 allowed from the erase program signal going low to OSC_ENA signal going low 250 250 250 ns ns Figure 5 3 through Figure 5 5 show the read program and erase waveforms for UFM block timing parameters shown in Table 5 21 Figure 5 3 UFM Read Waveforms ARSht 1 tak 9 Address Bis tuh ARCIK
63. October 2008 Altera Corporation MAX II Device Handbook 4 4 Chapter 4 Hot Socketing and Power On Reset MAX II Devices Hot Socketing Feature Implementation in MAX II Devices Figure 4 2 Transistor Level Diagram of MAX II Device 1 0 Buffers VPAD Ensures 3 3 V Tolerance and IOE Signal or the The Larger of Hot Socket IOE Signal Larger of VCCIO or VPAD VCCIO or VPAD Protection p substrate The CMOS output drivers in the I O pins intrinsically provide electrostatic discharge ESD protection There are two cases to consider for ESD voltage strikes positive voltage zap and negative voltage zap A positive ESD voltage zap occurs when a positive voltage is present on an I O pin due to an ESD charge event This can cause the N Drain P Substrate junction of the N channel drain to break down and the N Drain P Substrate N Source intrinsic bipolar transistor turn on to discharge ESD current from I O pin to GND The dashed line see Figure 4 3 shows the ESD current discharge path during positive ESD zap Figure 4 3 ESD Protection During Positive Voltage Zap 1 0 Source FA D PMOS JF N V Drain ILE i i I i P Substrate G Drain i i 4 S NMOS Gate 5 N Source Y GND GND MAX II Device Handbook October 2008 Altera Corporation Chapter 4 Hot Socketing and Power On Reset MAX II Devices 4 5 Power On
64. algorithm Use the following equation to estimate the JBC file size Equation 14 2 N JBC file size Alg gt Data 1 Notes to Equation 14 2 1 Alg Space used by algorithm 2 Data Space used by compressed programming data 3 k Index representing device being targeted 4 N Number of target devices in the chain This equation provides a JBC file size estimate that may vary by 10 depending on device utilization When device utilization is low JBC file sizes tend to be smaller because the compression algorithm used to minimize file size is more likely to find repetitive data The equation also indicates that the algorithm size stays constant for a device family but the programming data size grows slightly as more devices are targeted For a given device family the increase in JBC file size due to the data component is linear Table 14 2 shows algorithm file size constants when targeting a single MAX II device Table 14 2 Algorithm File Size Constants Targeting a Single Altera Device Family Device Typical JBC File Algorithm Size Khytes MAX II 24 3 October 2008 Altera Corporation MAX II Device Handbook 14 12 II Device Handbook Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Software Development Table 14 3 shows data size constants for MAX II devices that support the Jam language for ISP Table 14 3 Data Constants Typical Jam STAPL
65. altufm spi altufm 12 contain control logic to automatically monitor the BUSY signal and will cease operations to the when a real time ISP operation is in progress 57 You can program and CFM blocks independently without overwriting the other block which is not programmed The Quartus II programmer provides the options to program the UFM and CFM blocks individually or together the entire MAX II Device Refer to the In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook for guidelines about using ISP and real time ISP while utilizing the UFM block within your design UL Refer to the MAX II Architecture chapter in the MAX II Device Handbook for a complete description of the device architecture and for the specific values of the timing parameters listed in this chapter Read Stream Read The three control signals PROGRAM ERASE and BUSY are not required during read or stream read operation To perform a read operation the address register has to be loaded with the reference address where the data is or is going to be located in the The address register can be stopped from incrementing or shifting addresses from ARDin by stopping the ARCLK clock pulse DRSHFT must be asserted low at the next rising edge of DRCLK to load the data from the UFM to the data register To shift the bits from the register 16 clock pulses have to be provid
66. and Veco 1 5 V 1 8 V 2 5 V or 3 3 V Cock Input capacitance for dual purpose GCLK user 1 0 pin pF 2 This value is specified for normal device operation The value may vary during power up This applies for all Vecio settings 3 3 2 5 1 8 and 1 5 V V ground no load no toggling inputs Commercial temperature ranges from 0 C to 85 C with maximum current at 85 C Industrial temperature ranges from 40 C to 100 C with maximum current at 100 C This value applies to commercial and industrial range devices For extended temperature range devices the Vscumi typical value is 300 mV for Vecio 3 3 V and 120 mV for Vecio 2 5 7 The input is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all 1 0 standards 8 This is a peak current value with a maximum duration of tconrig time 9 Pin pull up resistance values will lower if an external source drives the pin higher than II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics Operating Conditions Output Drive Characteristics 5 5 Figure 5 1 shows the typical drive strength characteristics of MAX II devices Figure 5 1 Output Drive Characteristics of MAX II Devices MAX II Output Drive loy Characteristics Maximum Drive Strength 37V VCCI 1 8V VCCIO Typical l Output Current mA
67. clamp so that the Jam or JBC files will contain the pin state information The following are the steps to save the pin state information from the IPS file to the programming files 1 Add in the programming file in the programmer window 2 Addin the IPS file to the programmer 3 Click Save File in the programmer window or on the Edit menu and the Save Data To File As dialog box will appear See Figure 12 10 4 Enter the file name check the Include IPS file information box and click Save The POF with saved IPS information only supports ISP clamp operation in the Quartus II software and not with third party programming tools For third party tools Jam or JBC files should be used if ISP clamp is required Figure 12 10 Save Data To File as Menu Save in O test gt er db test pof File name Save as type Files Include IPS file information 2 When programming a device with the ISP Clamp box checked the Quartus II Programmer will first look for the IPS file If the IPS file is not found only then it will look into the POF for the pin state information II Device Handbook October 2008 Altera Corporation Chapter 12 Real Time ISP and ISP Clamp for MAX Il Devices 12 9 ISP Clamp Defining the Pin States in Assignment Editor Another way to define the pin states is through the Assignment Editor After you have defined the pin s
68. default these programming files and methods will program the entire flash memory contents which includes the CFM block and UFM contents The stand alone embedded Jam STAPL player and Jam Byte Code Player provides action commands for programming or reading the entire flash memory UFM and together or each independently Ss For more information refer to the Using Jam STAPL for ISP via an Embedded Processor chapter in the MAX II Device Handbook In System Programming Clamp II Device Handbook By default the IEEE 1532 instruction used for entering ISP automatically tri states all I O pins with weak pull up resistors for the duration of the ISP sequence However some systems may require certain pins on MAX II devices to maintain a specific DC logic level during an in field update For these systems an optional in system programming clamp instruction exists in MAX IIcircuitry to control I O behavior during the ISP sequence The in system programming clamp instruction enables the device to sample and sustain the value on an output pin an input pin would remain tri stated if sampled or to explicitly set a logic high logic low or tri state value on any pin Setting these options is controlled on an individual pin basis using the Quartus II software For more information refer to the Real Time ISP and ISP Clamp for MAX II Devices chapter in the MAX II Device Handbook October 2008 Altera Corporation Chapter 3 JTAG an
69. device logic array or the user flash memory UFM block As you can program the UFM section independently from the logic array separate Jam STAPL and JBC options can be used in the command line to separately program UFM and configuration flash memory blocks For more information see MAX II Jam JBC Actions and Procedure Commands on page 14 15 Jam Players Jam Players read the descriptive information in Jam files and translate them into data that programs the target PLDs Jam Players do not program a particular device architecture or vendor they only read and understand the syntax defined by the Jam file specification In field changes are confined to the Jam file not the Jam Player As result you do not need to modify the Jam Player source code for each in field upgrade There are two types of Jam Players to accommodate the two types of Jam files an ASCII Jam STAPL Player and a Jam STAPL Byte Code Player The general concepts within this chapter apply to both player types however the following information focuses on the Jam STAPL Byte Code Player Jam Players can be used to program or write the MAX II configuration flash memory block and the UFM block separately since Jam STAPL and JBC files can be generated targeting only to either one or both sectors of the MAX II UFM block Jam Player Compatibility The embedded Jam Player is able to read Jam files that conform to the standard JEDEC file format The embed
70. m Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook m Using MAX II Devices in Multi Voltage Systems chapter in the MAX II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics 5 27 Document Revision History Document Revision History Table 5 35 shows the revision history for this chapter Table 5 35 Document Revision History Part 1 of 2 Date and Revision Changes Made Summary of Changes August 2009 m Added Table 5 28 Table 5 29 and Table 5 30 Added information for version 2 5 m Updated Table 5 2 Table 5 4 Table 5 14 Table 5 15 Table 5 16 Speed grade 8 Table 5 17 Table 5 18 Table 5 19 Table 5 20 Table 5 21 Table 5 22 Table 5 23 Table 5 24 Table 5 27 Table 5 31 Table 5 32 and Table 5 33 November 2008 m Updated Table 5 2 version 2 4 m Updated Internal Timing Parameters section October 2008 m Updated New Document Format version 2 3 m Updatea Figure 5 1 July 2008 m Updated Table 5 14 Table 5 23 and Table 5 24 version 2 2 March 2008 m Added Note 5 to Table 5 4 version 2 1 December 2007 m Updated Note 3 and 4 to Table 5 1 Updated document with version 2 0 Updated Table 5 2 and added Note 5 IIZ information m Updated ICCSTANDBY and ICCPOWERUP information and added IPULLUP information in Table 5 4 m Added Note 1 to Table 5 10 m Updated Figure 5 2 m Added Note 1 to Table
71. m Useanl O Pin State file ips or m Usethe Assignment Editor to set the clamp states of the pins October 2008 Altera Corporation MAX II Device Handbook 12 6 II Device Handbook Chapter 12 Real Time ISP and ISP Clamp for MAX II Devices ISP Clamp Using the IPS File Creating an IPS File You can specify the clamp states of the pins when the device is in ISP clamp operation without configuring the settings in the Assignment Editor and recompiling the design You must first create a new I O pin state file ips file and define the states of the pins in the file or use an existing IPS file The IPS file defines the states for all the pins of the device when the device is in ISP clamp operation The file created is usable for programming the device with any designs as long as it targets the same device and package An IPS file must be used together with a POF file which contains the programming data to program the device To create an IPS file perform the following 1 Click Programmer on the toolbar or on the Tools menu click Programmer to open the Quartus II Programmer window 2 Click Add File in the programmer to add the programming file POF Jam or JBC into the programmer window 3 Click on the programming file in the programmer the entire row will be highlighted and on the Edit menu click ISP CLAMP State Editor See Figure 12 6 Figure 12 6 Fdit Menu Delete Del Select All Ctr A 2b
72. output pin and compared against the expected data Programming a pattern into the device requires the following six ISP steps A stand alone verification of a programmed pattern involves only stages 1 2 5 and 6 These steps are automatically executed by third party programmers the Quartus II software or the Jam STAPL and Jam Byte Code Players 1 Enter ISP The enter ISP stage ensures that the I O pins transition smoothly from user mode to ISP mode 2 Check ID Before any program or verify process the silicon ID is checked The time required to read this silicon ID is relatively small compared to the overall programming time 3 Sector Erase Erasing the device in system involves shifting in the instruction to erase the device and applying an erase pulse s The erase pulse is automatically generated internally by waiting in the run test idle state for the specified erase pulse time of 500 ms for the CFM block and 500 ms for each sector of the UFM block 4 Program Programming the device in system involves shifting in the address data and program instruction and generating the program pulse to program the flash cells The program pulse is automatically generated internally by waiting in the run test idle state for the specified program pulse time of 75 This process is repeated for each address in the CFM and UFM blocks 5 Verify Verifying MAX II device in system involves shifting in addresses applying the verify ins
73. pointer to a long integer Returns a code if there is an error that applies to the syntax or structure of the JBC file If this kind of error is encountered the supporting vendor should be contacted with a detailed description of the circumstances in which the exit code was encountered Votes to Table 14 5 1 Mandatory parameters must be passed for the Player to run 2 For more information refer to AN 122 Using Jam STAPL for ISP amp ICR via an Embedded Processor MAX II Jam JBC Actions and Procedure Commands Jam JBC supported action commands for MAX II devices are listed in Table 14 6 including their definitions The optional procedures that you can execute with each action are listed along with their definitions in Table 14 7 Table 14 6 II Jam JBC Actions Part 1 of 2 Optional Procedures Off by Jam JBC Action Description Default PROGRAM Programs the device You can optionally program CFM and DO BYPASS CFM UFM separately DO BYPASS UFM DO SECURE DO REAL TIME ISP DO READ USERCODE BLANKCHECK Blank checks the entire device You can optionally blank check DO BYPASS CFM and UFM separately DO BYPASS UFM DO REAL TIME ISP VERIFY Verifies the entire device against the programming data in the DO BYPASS Jam file You can optionally verify CFM and UFM separately DO BYPASS UFM DO REAL TIME ISP DO READ USERCODE October 2008 A
74. state the proper TAP controller state has not been reached To solve this problem try one of the following procedures m Verify that the controller has reached the SHIFT state correctly To advance the TAP controller to the SHIFT state return to the RESET state and clock the code 01100 on the TMS pin m Check the connections to the vcc GND and JTAG pins on the device m Performa SAMPLE PRELOAD test cycle prior to the first EXTEST test cycle to ensure that known data is present at the device pins when the EXTEST mode is entered If the OEJ update register contains a 0 the data in the OUTJ update register will be driven out The state must be known and correct to avoid contention with other devices in the system m Do notperform EXTEST and SAMPLE PRELOAD tests during ISP These instructions are supported before and after ISP but not during ISP If problems persist contact Altera Applications II Device Handbook October 2008 Altera Corporation Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Il Devices 13 17 Boundary Scan Description Language BSDL Support Boundary Scan Description Language BSDL Support Conclusion Le The BSDL a subset of VHDL provides a syntax that allows you to describe the features of an IEEE Std 1149 1 BST capable device that can be tested Test software development systems then use the BSDL files for test generation analysis failure diagnosti
75. 0 Functions gt jbistub c file gt Ne TMS gt TDI gt Main P rogram y y Compare Parse m Interpret nd Export Porting the Jam STAPL Byte Code Player The default configuration of the jbistub c file includes code for DOS 32 bit Windows and UNIX so that the source code can be easily compiled and evaluated for the correct functionality and debugging of these pre defined operating systems For the embedded environment this code is easily removed using a single preprocessor define statement In addition porting the code involves making minor changes to specific parts of the code in the jbistub c file To port the Jam Player you need to customize several functions in the jbistub c file which are shown in Table 14 1 Table 14 1 Functions Requiring Customization Function jbi_jtag_io Description Interface to the four IEEE 1149 1 JTAG signals TDI TMS TCK and TDO jbi_export Passes information such as the User Electronic Signature UES back to the calling program jbi_delay jbi_vector_map Implements the programming pulses or delays needed during execution Processes signal to pin map for 1149 1 JTAG signals jbi vector io Asserts non IEEE 1149 1 JTAG signals as defined in the VECTOR MAP To ensure that you have customized all of the necessary code follow these four steps Be
76. 01100 to advance the TAP controller to SHIFT_IR Figure 13 7 Selecting the Instruction Mode TCK EE TMS TDI TDO eee rT STATE X SHIFT ji 1 RUN TEST DLE SELECT SCAN EE m SELECT DR SCAN CAPTURE IR TEST LOGIC RESET The pin is tri stated in all states except the SHIFT IR and SHIFT DR states The TDO pin is activated at the first falling edge of TCK after entering either of the shift states and is tri stated at the first falling edge of TCK after leaving either of the shift states When the SHIFT IR state is activated TDO is no longer tri stated and the initial state of the instruction register is shifted out on the falling edge of TCK TDO continues to shift out the contents of the instruction register as long as the SHIFT IR state is active The TAP controller remains in the 5 IR state as long as TMS remains low II Device Handbook October 2008 Altera Corporation Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Il Devices 13 9 IEEE Std 1149 1 BST Operation Control During the 5 IR state an instruction code is entered by shifting data on the TDI pin on the rising edge of TCK The last bit of the opcode must be clocked at the same time that the next state EXIT1 IR isactivated EXIT1_IR is entered by cl
77. 10 115 9 796 9 141 9 154 9 297 ps LVCMOS 7mA 11548 11229 10910 9861 9 874 10 037 ps 1 8 V LVTTL 6mA 22 927 22 608 22 299 21 811 21 854 21 857 ps LVCMOS 3mA 24731 24412 24093 23 081 23034 23 107 ps 1 5 VLVCMOS 4mA 38 723 38 404 38 085 39 121 39 124 39 124 ps 2mA 41 330 41 011 40 692 40 631 40 634 40 634 ps 3 3 V PCI 20mA 261 339 418 6 644 6 627 6914 ps August 2009 Altera Corporation MAX II Device Handbook 5 24 Table 5 31 II IOE Programmable Delays Chapter 5 DC and Switching Characteristics Timing Model and Specifications Parameter Il MAX IIG 112 3 Speed 4 Speed 5 Speed 6 Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade Min Max Min Max Min Max Min Max Min Max Min Max Unit Input Delay from Pinto 1 225 1 592 1 960 1 858 2171 2 214 ps Internal Cells 1 Input Delay from Pin to 89 115 142 569 609 616 ps Internal Cells 0 Maximum Input and Output Clo
78. 1149 1 Boundary Scan Testing chapter in the MAX II Device Handbook Working with Different Voltage Levels When devices in a JTAG chain operate at different voltage levels a device s output voltage specification must meet the subsequent device s input voltage specification If the devices do not meet this criteria you must add additional circuitry such as a level shifter to adjust the voltage levels For example when a 5 0 V device drives a 2 5 V device you must adjust the 5 0 V device s output voltage to meet the 2 5 V device s input voltage specification Because all devices in a JTAG chain are tied together you must also ensure that the first device s TDO output meets the subsequent device s TDI input voltage specification to program a chain of devices successfully MAX II devices include a MultiVolt I O feature which allows these devices to interface with systems that have different supply voltages MAX II devices can be set for 3 3 V 2 5 V 1 8 V or 1 5 V I O operation TheJTAG pins of MAX II devices support these voltage levels Refer to the MAX II Architecture chapter in the MAX II Device Handbook for I O standard compatibility for each Veco voltage For example Veco at 3 3 V does not allow JTAG input pins to accept 1 8 or 1 5 V signals Sequential versus Concurrent Programming This section describes how to program multiple devices using sequential and concurrent programming The JTAG chain setup for seque
79. 3 to determine Data size where Equation 14 5 N JBC File Size Alg Data k 1 Notes to Equation 14 5 1 Alg 21 Kbytes 2 Data EPM7064AE Data EPM7128AE Data 8 4 12 Kbytes Thus the JBC file size equals 33 Kbytes 2 Estimate the JBC Player size This example uses a JBC Player size of 62 Kbytes because this 68000 is a 16 bit processor Use the following equation to determine the amount of ROM needed Equation 14 6 ROM Size JBC File Size Jam Player Size ROM Size 95 Kbytes 3 Estimate the RAM usage with the following equation Equation 14 7 N RAM Size 33 Kbytes Data Uncompressed Data Size k k 1 Because the JBC file uses compressed data the uncompressed data size for each device must be summed to find the total amount of RAM used The Uncompressed Data Size constants are as follows m EPM7064AE 8 Kbytes m EPM7128AE 12 Kbytes October 2008 Altera Corporation MAX II Device Handbook 14 14 Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Updating Devices Using Jam Calculate the total DRAM usage as follows Equation 14 8 RAM Size 33 Kbytes 8 Kbytes 12 Kbytes 53 Kbytes In general Jam Files use more RAM than ROM which is desirable because RAM is cheaper and the overhead associated with easy upgrades becomes less of a factor larger number of devices are programmed In most applications easy upgrades outweigh the mem
80. 3 6 V the MAX IIG device supports the 1 71 to 1 89 V operating voltage range II Device Handbook October 2008 Altera Corporation Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory 10 3 List of Vendors and Devices Table 10 3 Atmel Corporation Device Characteristics Interface Size Operating Type Device Bits SCI SPI 2 Wire 3 Wire FC Microwire fmax Voltage V 1 EEPROM AT25020 2 048 3 MHz 2 7 2 7 5 5 EEPROM AT25040 4 096 3 MHz 2 7 2 7 5 5 EEPROM AT25020A 2 048 20 MHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT25040A 4 096 20 MHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT25080 8 192 3 MHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT25080A 8 192 20 MHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT24C02 2 048 400 kHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT24C04 4 096 400 kHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT24C08 8 192 400 kHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT24C02A 2 048 400 kHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT24C04A 4 096 400 kHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT24C08A 8 192 400 kHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT34C02 2 048 400 kHz 2 7 2 7 5 5 1 8 1 8 5 5 EEPROM AT93C56 2 048 2 MHz 2 7 2 7 5 5 2 5 2 5 5 5 1 8 1 8 5 5 EEPROM AT93C66 4 096 2 MHz 2 7 2 7 5 5 2 5 2 5 5 5 1 8 1 8 5 5 Note to Table 10 3
81. 4 Jam Player Ported Incorrectly You will receive an error if the Jam Player was not ported correctly for your platform To check if the Jam Player is causing the error apply the IDCODE instruction to the target device using a Jam file You can use a Jam file to load an IDCODE instruction and then shift out the IDCODE value This test determines if the JTAG chain is set up correctly and if you can read and write to the JTAG chain properly You can download the idcode zip file from the Altera website to obtain the idcode jam file Troubleshooting Tips II Device Handbook This section discusses some additional suggestions for troubleshooting ISP issues Verify the JTAG Chain Continuity For in system programming to occur successfully the number of devices physically in theJTAG chain must match the number reported in the Quartus II software The following steps show one simple way to verify that the JTAG chain is connected properly 1 Open the Programmer in the Quartus II software 2 Click Auto Detect in the Programmer The Quartus II software reports the number of devices found on the JTAG chain If this fails check the JTAG chain to make sure itis not broken October 2008 Altera Corporation Chapter 11 In System Programmability Guidelines for MAX II Devices 11 9 ISP via Embedded Processors Check the V Level of the Board During In System Programming Using an oscilloscope monitor the V ccmr signal on your JTAG
82. 500 us 2 Formore information about POR trigger voltage refer to the Hot Socketing Power On Reset in MAX II Devices chapter in the MAX II Device Handbook Power Consumption Designers can use the Altera PowerPlay Early Power Estimator and PowerPlay Power Analyzer to estimate the device power For more information about these power analysis tools refer to the Understanding and Evaluating Power in MA X II Devices chapter in the MAX II Device Handbook and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook Timing Model and Specifications II Device Handbook MAX II devices timing can be analyzed with the Altera Quartus II software a variety of popular industry standard EDA simulators and timing analyzers or with the timing model shown in Figure 5 2 MAX II devices have predictable internal delays that enable the designer to determine the worst case timing of any design The software provides timing simulation point to point delay prediction and detailed timing analysis for device wide performance evaluation August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics Timing Model and Specifications Figure 5 2 MAX II Device Timing Model 5 9 Output and Output Enable
83. AK e e sen 5 5 Bbus HoldSpecificationsocc ss RE deditus 5 7 Power Up Timing 24484 sucres samba ersesereaemeneen Fade a dedi 5 8 Power CONnSUM PUON siie nitin Die dca die di di ion 5 8 Timing Model and Specifications 5 8 Preliminary and Final Timing 5 9 Performance M ms 5 10 Internal Timing Parameters i deed em ERO eie eka Rb dE oes 5 11 External Timing Parameters 5 18 External Timing I O Delay Adders 5 21 Maximum Input and Output Clock Rates 5 24 Timing Specifications 5 25 Referenced Documents 5 26 Document Revision History 5 27 Chapter 6 Reference and Ordering Information 2 5 bande Lin aie bb 6 1 Device Pin O ts cese bre ha eae EE DEOR ERA DRI E Pc 6 1 Ordering Information xus ER IRE SG CPG Mp ud ep Ee A abides RED EGER 6 1 Referenced Documents
84. An option set before compilation in the Quartus II software controls this pin This chip wide output enable uses its own routing resources and does not use any of the four global resources If this option is turned on all outputs on the chip operate normally when DEV OE is asserted When the pin is deasserted all outputs are tri stated If this option is turned off the OE pin is disabled when the device operates in user mode and is available as a user I O pin Programmable Drive Strength The output buffer for each MAX IT device I O pin has two levels of programmable drive strength control for each of the LVTTL and LVCMOS I O standards Programmable drive strength provides system noise reduction control for high performance I O designs Although a separate slew rate control feature exists using the lower drive strength setting provides signal slew rate control to reduce system noise and signal overshoot without the large delay adder associated with the slew rate control feature Table 2 6 shows the possible settings for the I O standards with drive strength control The Quartus II software uses the maximum current strength as the default setting The PCI I O standard is always set at 20 mA with no alternate setting October 2008 Altera Corporation MAX II Device Handbook 2 30 Chapter 2 MAX II Architecture 1 0 Structure Table 2 6 Programmable Drive Strength Note 1 1 0 Standard IOH IOL Current Stre
85. Byte Code Player Memory Usage 14 11 Updating Devices Using Jam eben EXER EE E EE eee eR RE 14 14 MAX II Jam JBC Actions and Procedure Commands 14 15 Running the Jam STAPL Byte Code 14 17 CONCLUSION eA s and a ut a eda iren de deed tok ees 14 18 Referenced Documents dee et o C xn b Ree aes pd e da edet 14 18 Document Revision History 14 19 Chapter 15 Using the Agilent 3070 Tester for In System Programming Introd e Oe 15 1 New PLD Product for Agilent 3070 15 1 Device SUpport st ty a lee ii os 15 1 Agilent 3070 Development Flow without the PLD ISP Software 15 2 Step 1 Create a and Test Fixture 15 3 Creating the PCBs sss besei ve per Leere be eb hohe had 15 3 Creatine the Fixtures este suem cocos P Autor o aped ue ee LI 15 3 Step 2 Create a Serial Vector Format 15 4 Step 3 Convert SVE Files to PCF Files ise midi entendent 15 5 Step 4 Create Executable Tests from Files
86. Compile times can be long depending on the number of PCF vectors contained in the source files the type of controller and controller loading Altera recommends using a batch file to automate the compilation of the ISP tests If a boundary scan chain containing Altera devices is defined only the Altera devices will be programmed when the PCF vectors have been applied to the JTAG interface Step 6 Debug the Test Once the executable tests have been created the test system can be debugged The applied vector set ensures that the device is programmed correctly by verifying the contents of the device The programming algorithm uses the TDO pin to check the bitstream coming from the device If any vector does not match the expected value the test fails indicating one of two things The device ID does not match what is expected This scenario is evident if the failure occurs at the beginning of the first test m Device programming failed Because many vectors are verified it may not be practical to sift through each vector to determine the cause of the failure Use the following troubleshooting guidelines if the device fails to program m Checkthe pull down resistor in the test fixture The design engineer may have placed pull up resistors on the board for the TCK pin If the pull down resistor is too large the TCK pin may be above the device s threshold for a logic low Adjust the value of the resistor accordingly See the appropriate
87. E Note The frequency setting is for simulation only and has no impact on the on chip oscillator frequency Resource Usage Cancel Back Mext gt Finish MAX II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory Il Devices 9 9 UFM Operating Modes UFM Operating Modes There are three different modes for the UFM block m Read Stream Read m Program Write m Erase During program address and data can be loaded concurrently You can manipulate the UFM interface controls as necessary to implement the specific protocol provided the UFM timing specifications are met Figure 9 7 through Figure 9 10 show the control waveforms for accessing UFM in three different modes For PROGRAM mode Figure 9 9 and ERASE mode Figure 9 10 the PROGRAM and ERASE signals are not obligated to assert immediately after loading the address and data They can be asserted anytime after the address register and data register have been loaded Do not assert the READ PROGRAM and ERASE signals or shift data and address into the UFM after entering the real time ISP mode You can use the RTP BUSY signal to detect the beginning and end of real time ISP operation and generate control logic to stop all UFM port operations This user generated control logic is only necessary for the altufm none megafunction which provides no auto generated logic The other interfaces for the altufm megafunction altufm parallel
88. I O standard is only supported in Bank of the EPM1270 and EPM2210 devices Bus Hold Specifications Table 5 11 shows the MAX II device family bus hold specifications Table 5 11 Bus Hold Specifications current Vecio Level 1 5V 1 8V 2 5V 3 3V Parameter Conditions Min Max Min Max Min Max Min Max Unit Low sustaining V gt V maximum 20 30 50 70 pA current High sustaining Vw lt VA minimum 20 30 50 70 pA current Low overdrive 0 V lt Vy lt Vecio 160 200 300 500 pA current August 2009 Altera Corporation MAX II Device Handbook 5 8 Chapter 5 DC and Switching Characteristics Power Consumption Power Up Timing Table 5 12 shows the power up timing characteristics for MAX II devices Table 5 12 MAX II Power Up Timing Symbol Parameter Device Min Typ Max Unit teonris 1 The amount of time from when EPM240 200 us minimum is reached until EpM570 E 300 us the device enters user mode 2 EPM1270 300 us EPM2210 450 us Notes to Table 5 12 1 Table 5 12 values apply to commercial and industrial range devices For extended temperature range devices the tours maximum values are as follows Device EPM240 570 1270 2210 Maximum 300 ys 400 us 400 us
89. II Devices Power On RENTE Reset Vccio Monitor Weak d Pull Up i i Resistor Output Enable PAD gt Voltage Hot Socket Tolerance 1 Control Input Buffer to Logic Array The POR circuit monitors and voltage levels and keeps I O pins tri stated until the device has completed its flash memory configuration of the SRAM logic The weak pull up resistor from the I O pin to Veco is enabled during download to keep the I O pins from floating The 3 3 V tolerance control circuit permits the I O pins to be driven by 3 3 V before Vcc and or are powered and it prevents the I O pins from driving out when the device is not fully powered or operational The hot socket circuit prevents I O pins from internally powering Vago and Veco when driven by external signals before the device is powered SS For information about 5 0 V tolerance refer to the Using MAX II Devices in Multi Voltage Systems chapter in the MAX II Device Handbook Figure 4 2 shows a transistor level cross section of the MAX II device I O buffers This design ensures that the output buffers do not drive when Veco is powered before Veanr or if the I O pad voltage is higher than Veco This also applies for sudden voltage spikes during hot insertion The leakage current charges the 3 3 V tolerant circuit capacitance
90. II Updated document with version 2 0 Devices section MAX IIZ information m Updated Power On Reset Circuitry section m Updated Figure 4 5 m Added Referenced Documents section December 2006 m Added document revision history version 1 5 February 2006 m Updated MAX II Hot Socketing Specifications section version 1 4 m Updated and DC Specifications section m Updated Power On Reset Circuitry section June 2005 m Updated AC and DC specifications on page 4 2 version 1 3 December 2004 m Added content to Power Up Characteristics section version 1 2 Updated Figure 4 5 June 2004 m Corrected Figure 4 2 version 1 1 II Device Handbook October 2008 Altera Corporation 5 DC and Switching Characteristics RYA MII51005 2 5 Introduction System designers must consider the recommended DC and switching conditions discussed in this chapter to maintain the highest possible performance and reliability of the MAX II devices This chapter contains the following sections m Operating Conditions on page 5 1 m Power Consumption on page 5 8 m Timing Model and Specifications on page 5 8 Operating Conditions Table 5 1 through Table 5 12 provide information about absolute maximum ratings recommended operating conditions DC electrical characteristics and other specifications for MAX II devices Absolute Maximum Ratings Table 5 1 shows the absolute
91. II device The total thermal power is shown in mWatts and is a sum of the thermal power of all the resources being used in the device The total thermal power includes the typical power from standby and dynamic power Figure 17 13 shows the Power section Figure 17 13 Power Section Power mW Voltage Regulator Protal Table 17 7 describes the thermal power parameters in the PowerPlay Early Power Estimator spreadsheet Table 17 7 Power Information Column Heading Description Clock Represents the dynamic power consumed by clock networks Click Clocks for details Logic Represents the dynamic power consumed by LEs and associated routing Click Logic for details UFM Represents the dynamic power consumed by the UFM block Click UFM for details 1 0 Represents the dynamic power consumed by 1 0 pins and associated routing Click 1 0 for details Voltage Regulator Represents the dynamic power consumed by the on chip voltage regulator for a device that supports 2 5 V 3 3 V Panos Represents the standby static power consumed irrespective of clock frequency The value includes static power consumed by the 1 0 banks and the voltage regulator 15 dependent on the selected device and the Vox supply voltage Prora Represents the total power consumed by the CPLD Refer to Power Supply Current on page 17 15 for the current draw from the CPLD supp
92. In System Programmability Guidelines for MAX II Devices ISP Troubleshooting Guidelines 11 7 3 On the File menu point to Create Update and click Create JAM SVE or ISC File 4 Specify a filein the File format list 5 Click OK Figure 11 2 Create JAM SVF or ISC File Create JAM SVF or ISC File File name D Data Example svf El File format Serial Vector Format svf x Operation r Programming options Program Blank check Verify Verity r Clock frequency TCK frequency fi 0 0 MHz Supply voltage volts x ISP Troubleshooting Guidelines This section provides tips for troubleshooting ISP related problems Invalid ID and Unrecognized Device Messages The first step during in system programming is to check the device s silicon ID If the silicon ID does not match an Invalid ID or Unrecognized Device error is generated Typical causes for this error are shown below m Download cable connected incorrectly BH TDOisnotconnected m Incomplete JTAG chain m Noisy TCK signal m Jam Player ported incorrectly Download Cable Connected Incorrectly You will receive an error if the download cable is connected incorrectly to the parallel or USB port or if it is not receiving power from your board For more information about installing the MasterBlaster ByteBlasterMV ByteBlaster or USB Blaster download cable refer to the
93. J EDEC Outline Reference MS 034 Variation AAG 1 D 19 00 BSC Maximum Lead 19 00 5 Coplanarity 0 008 inches 0 20 mm Weight 1 69 b 0 50 0 60 0 70 II Device Handbook October 2008 Altera Corporation Chapter 7 Package Information 7 17 Package Outlines Package Information Part 2 of 2 Package Outline Dimension Table Part 2 of 2 Moisture Sensitivity Level da on moisture barrier e 1 00 BSC Figure 7 9 324 Pin FineLine BGA Package Outline TOP VIEW BOTTOM VIEW 1 18 16 14 12 10 8 6 4 2 Corner 17 15 13 11 9 7 5 3 1 a F OoOOOOOOOOOOOO0O0000 B Pin A1 ID i H E K 000000000000000000 L 000000000000000000 M U 909 9 0 9 0 0 0 90 9 0 0 0 59650 V Sel mire A3 A2 A VIXTIVIAXATIVIAIIAIGIAIGIGAIGIAIAIAIAIAT 1 October 2008 Altera Cor
94. MAX II Device Handbook 1 16 Chapter 7 Package Information Package Outlines Figure 7 8 256 Pin FineLine BGA Package Outline TOP VIEW BOTTOM VIEW D 16 14 12 10 8 6 4 2 1 15 13 n 9 7 5 3 1 Corner rB000000000000000 B OOOOOOOOOOOOOOOO D F G H OOOOOOOOOO00000084J K OOOOOOOOOOOOOOOO L R 0000000000000 9 T ms se Pin ALID 324 FineLine Ball Grid Array FBGA m All dimensions and tolerances conform to ANSI Y14 5M 1994 m Controlling dimension is in millimeters m Pin A1 may be indicated by an ID dot or a special feature in its proximity on package surface Package Information Part 1 of 2 Package Outline Dimension Table Part 1 of 2 Description Specification Millimeters Symbol Ordering Code Reference F Min Nom Max Package Acronym FBGA A 2 20 Substrate Material BT A1 0 30 A2 1 80 Regular 63Sn 37Pb Solder Ball Composition Pb free 5 3 9 0 5 Typ 0 70 REF
95. MAX II Device Handbook 13 16 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices Disabling IEEE Std 1149 1 BST Circuitry Disabling IEEE Std 1149 1 BST Circuitry The IEEE Std 1149 1 BST circuitry for MAX II devices is enabled upon device power up Because this circuitry may be used for BST or ISP this circuitry must be enabled only if these features are used This section describes how to disable the IEEE Std 1149 1 circuitry to ensure that the circuitry is not inadvertently enabled when it is not needed Table 13 3 shows the pin connections necessary for disabling JTAG in MAX II devices that have dedicated IEEE Std 1149 1 pins Table 13 3 Disabling IEEE Std 1149 1 Circuitry JTAG Pins 1 TMS TCK TDI TDO vcc 2 GND 3 vcc 2 Leave Open Votes to Table 13 3 1 There is no software option to disable JTAG in MAX II devices The JTAG pins are dedicated 2 vec refers to Veco of Bank 1 3 The signal may also be tied high If TCK is tied high power up conditions must ensure that TMS is pulled high before Pulling low avoids this power up condition Guidelines for IEEE Std 1149 1 Boundary Scan Testing Use the following guidelines when performing boundary scan testing with IEEE Std 1149 1 devices m Ifa pattern for example a 10 bit 1010101010 pattern does not shift out of the instruction register via the TDO pin during the first clock cycle of the SHIFT IR
96. MAX II Devices chapter in the MAX II Device Handbook Using User Flash Memory in MAX II Devices chapter in the MAX II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture Document Revision History Document Revision History Table 2 8 shows the revision history for this chapter Table 2 8 Document Revision History 2 33 Date and Revision Changes Made Summary of Changes October 2008 m Updated Table 2 4 and Table 2 6 version 2 2 m Updated I O Standards and Banks section m Updated New Document Format March 2008 m Updated Schmitt Trigger section version 2 1 December 2007 m Updated Clear and Preset Logic Control section Updated document with version 2 0 m Updated MultiVolt Core section MAX 112 information m Updated MultiVolt 1 0 Interface section Updated Table 2 7 m Added Referenced Documents section December 2006 m Minor update in Internal Oscillator section Added document version 1 7 revision history August 2006 m Updated functional description and 1 0 structure sections version 1 6 July 2006 m Minor content and table updates vervion 1 5 February 2006 m Updated LAB Control Signals section version 1 4 Updated Clear and Preset Logic Control section m Updated Internal Oscillator section m Updated Table 2 5 August 2005 m Removed Note 2 from Table 2 7 version 1 3 D
97. MasterBlaster Serial USB Communications Cable User Guide ByteBlasterMV Download Cable User Guide ByteBlaster I1 Download Cable User Guide or USB Blaster Download Cable User Guide October 2008 Altera Corporation MAX II Device Handbook 11 8 Chapter 11 In System Programmability Guidelines for MAX II Devices ISP Troubleshooting Guidelines TDO Is Not Connected You will receive an error if the TDO port of one device in the chain is not connected During in system programming data must be shifted in and out of each device in the chain through the JTAG pins Therefore each device s TDO port must be connected to the subsequent device s TDI port and the last device s TDO port must be connected to the download cable s TDO port Incomplete JTAG Chain You will receive an error if the JTAG chain is not complete To check if an incomplete chain is causing the error use an oscilloscope to monitor vectors coming out of each device in the chain If each device s TDO port does not toggle during in system programming your JTAG chain is not complete Noisy TCK Signal Noise on the TCK signal is the most common reason for in system programming errors Noisy transitions on rising or falling edges can cause incorrect clocking of the IEEE Std 1149 1 TAP controller causing the state machine to be lost and in system programming to fail For more information about dealing with noisy TCK signals refer to TCK Signal on page 11
98. O output Table 8 1 shows the programmable drive strength settings that are available for the 3 3 V LVTTL LVCMOS I O standard for MAX II devices The Quartus II software uses the maximum current strength as the default setting The PCI I O standard is always set at 20 mA with no alternate setting Table 8 1 3 3 V LVTTL LVCMOS Programmable Drive Strength 1 0 Standard Current Strength Setting mA 3 3 V LVTTL 16 8 3 3 V LVCMOS II Device Handbook October 2008 Altera Corporation Chapter 8 Using MAX II Devices in Multi Voltage Systems 8 5 5 0 V Device Compatibility To compute the required value of R first calculate the model of the open drain transistors on the MAX II device This output resistor R r can be modeled by dividing Vo by lo Ra Table 8 2 shows the maximum Vo for the 3 3 V LVTTL LVCMOS I O standard for MAX II devices lt information about I O standard specifications refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook Table 8 2 3 3 V LVTTL LVCMOS Maximum Vo 1 0 Standard Voltage V 3 3 V LVTTL 0 45 3 3 V LVCMOS 0 20 Select R4 so that the MAX II device s Io specification is not violated You can compute the required pull up resistor value of R by using the equation Ry Rinr For example if an I O pin is configured as a 3 3 V LVTTL with a 16 mA drive strength given tha
99. PIN IN 4 OEJ PIN OE OUTJ PIN OUT Pin Output Buffer SHIFT CLOCK X UPDATE HIGHZ MODE sis ne d Capture Update SDI Registers Registers Shift and Update Phase II Device Handbook October 2008 Altera Corporation Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Il Devices 13 13 IEEE Std 1149 1 BST Operation Control EXTEST selects data differently than SAMPLE PRELOAD EXTEST chooses data from the update registers as the source of the output and output enable signals Once the EXTEST instruction code is entered the multiplexers select the update register data thus data stored in these registers from a previous EXTEST or SAMPLE PRELOAD test cycle can be forced onto the pin signals In the capture phase the results of this test data are stored in the capture registers and then shifted out of TDO during the shift phase New test data can then be stored in the update registers during the update phase The waveform diagram in Figure 13 11 resembles the SAMPLE PRELOAD waveform diagram except that the instruction code for EXTEST is different The data shifted out of TDO consists of the data that was present in the capture registers after the capture phase New test data shifted into the TDI pin appears at the TDO pin after being clocked through the entire boundary scan register Figure 13 11 EXTEST Shift Data Re
100. PowerPlay Early Power Estimator spreadsheet with device resource information from the specified power estimation file After importing a file manually specify some of the input parameters in the main section These input parameters include supply voltage m Ambient temperature m Airflow The ambient temperature and airflow are used for thermal analysis only Refer to the input parameters section for more information on these parameters The clock frequency values imported into PowerPlay Early Power Estimator Clock Domain Logic and I O modules are the same as the fmax values of the design You can manually edit the clock frequency and the toggle percentage in the PowerPlay Early Power Estimator spreadsheet to suit your system requirements October 2008 Altera Corporation Chapter 17 Understanding and Evaluating Power MAX II Devices 17 13 Power Estimation Summary Power Estimation Summary Power The main worksheet of the PowerPlay Early Power Estimator spreadsheet summarizes the power and current estimates for the design It displays the total power thermal analysis and power supply current information The accuracy of the information depends on the information entered The power consumed can also vary greatly depending on the toggle rates entered The following sections provide a description of the results of the PowerPlay Early Power Estimator spreadsheet This section shows the power dissipated in the MAX
101. Revision History Document Revision History Date and Revision December 2004 v1 2 Changes Made Updated text to RTP_BUSY in Table 9 4 Updated text in the Oscillator section Updated text in the UFM Operating Modes section Updated text in the Serial Peripheral Interface section Added a row to Table 9 6 Updated Table 9 7 Updated text to the READ section Updated text to the WRITE section Updated text to the SECTOR ERASE section Added a new UFM ERASE section Updated text to the WRSR section Updated Table 9 8 Added Table 9 9 Added section ALTUFM SPI Timing Specification Added Figures 9 13 9 15 9 16 9 21 and 9 24 Added Table 9 10 Added section ALTUFM Parallel Interface Timing Specification Added section Simulation Parameters Added Table 9 12 Summary of Changes June 2004 v1 1 Updated Figures 9 4 through 9 7 II Device Handbook October 2008 Altera Corporation 10 Replacing Serial EEPROMs with MAX S p AN Il User Flash Memory Introduction Each MAXe II device has a user flash memory UFM block to store up to 8 Kbits of user data You can use the UFM block to replace on board flash and EEPROM memory devices which are used to store ASSP or processor configuration bits or electronic ID information for a board during manufacturing MAX II device logic capacity allows integration of system power on reset POR interface bridging and I O expans
102. Symbol File Chain Description File Hexadecimal Intel Format File In System Sources and Probes E ditor File Logic Analyzer Interface File Memory Initialization File SignalT ap Il Logic Analyzer File Synopsys Design Constraints File Tcl Script File Text File Vector Waveform File Immediately after clicking OK a dialog box appears In this dialog box the Number of words represents the numbers of address lines while the Word size represents the data width To create a memory content file for the altufm megafunction enter 512 for the number of words and 16 for the word size as shown in Figure 9 46 Figure 9 46 Number of Words and Word Size Dialog Box Number of Words amp Word Size Number of words 512 Word size October 2008 Altera Corporation MAX II Device Handbook 9 42 Chapter 9 Using User Flash Memory in MAX II Devices Creating Memory Content File Figure 947 shows the memory content being written into a HEX file Figure 9 47 Hexadecimal Intel Format File This memory content file is then included using the altufm megafunction On the Tools menu click MegaWizard Plug In Manager The memory content file data hex is included on page5 of the altufm megafunction Figure 9 48 Click Yes and use this file for the memory content file Click Browse to include the m
103. System Programming Clamp on page 3 6 and Real Time ISP on page 3 7 These devices also offer an ISP DONE bit that provides safe operation when in system programming is interrupted This 5 DONE bit which is the last bit programmed prevents all I O pins from driving until the bit is programmed October 2008 Altera Corporation Chapter 3 JTAG and In System Programmability 3 5 In System Programmability IEEE 1532 Support The JTAG circuitry and ISP instruction set in MAX II devices is compliant to the IEEE 1532 2002 programming specification This provides industry standard hardware and software for in system programming among multiple vendor programmable logic devices PLDs in a JTAG chain The MAX II 1532 BSDL files will be released on the Altera website when available Jam Standard Test and Programming Language STAPL The Jam STAPL JEDEC standard JESD71 can be used to program MAX II devices with in circuit testers PCs or embedded processors The Jam byte code is also supported for MAX II devices These software programming protocols provide a compact embedded solution for programming MAX II devices Ss For more information refer to the Using Jam STAPL for ISP via an Embedded Processor chapter in the MAX II Device Handbook Programming Sequence During in system programming 1532 instructions addresses and data are shifted into the MAX II device through the TDI input pin Data is shifted out through the
104. The MAX II UFM block is organized as a 512 x 16 memory Since the UFM block is organized into two separate sectors the MSB of the address indicates the sector that will be in action 0 is for sector 0 UFMO while 1 is for sector 1 UFM1 An ERASE instruction erases the content of the specific sector that is indicated by the MSB of the address register Figure 9 2 shows the selection of the UFM sector in action using the MSB of the address register Refer to Erase on page 9 11 for more information about ERASE mode Figure 9 2 Selection of the UFM Sector Using the MSB of the Address Register ARDin b ua A Sector 0 pei Address Register B Block A2 A3 4 5 A6 1 viser UFM Block ET l ARCIK Sector1 WM 7 Three control signals exist for the address register ARSHFT ARCLK and ARDin ARSHFT is used as both a shift enable control signal and an auto increment signal If the ARSHFT signal is high a rising edge on ARCLK will load address data serially from the ARDin port and move data serially through the register A clock edge with the ARSHFT signal low increments the address register by 1 This implements an auto increment of the address to allow data streaming When a program read or an erase sequence is executing the address that is in the address register becomes the active UFM location UFM Data Register T
105. The column interconnect operates similarly to the row interconnect Each column of LABs is served by a dedicated column interconnect which vertically routes signals to and from LABs and row and column IOEs These column resources include m LUT chain interconnects within an LAB m Register chain interconnects within an LAB m C4 interconnects traversing a distance of four LABs in an up and down direction MAX II devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections The LUT chain connection allows the combinational output of an LE to directly drive the fast input of the LE right below it bypassing the local interconnect These resources can be used as a high speed connection for wide fan in October 2008 Altera Corporation MAX II Device Handbook 2 14 II Device Handbook Chapter 2 MAX II Architecture MultiTrack Interconnect functions from LE 1 to LE 10 in the same LAB The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance Figure 2 11 shows the LUT chain and register chain interconnects Figure 2 11 LUT Chain and Register Chain Interconnects Local Interconnect Routin
106. can also view the settings in the Quartus II Settings File qsf Running ISP Clamp in the Quartus Il Programmer In the Quartus II Programmer window make sure that the ISP Clamp check box is checked before programming the device Do not add any IPS file in the programmer as the programmer will use the values specified in the IPS file instead of the values you set in the Assignment Editor which is stored in the POF Figure 12 12 shows the Quartus II Programmer window with ISP Clamp checkbox Jam and JBC files created using the POF will have the pin state information in them October 2008 Altera Corporation MAX II Device Handbook 12 10 Chapter 12 Real Time ISP and ISP Clamp for MAX II Devices Conclusion Figure 12 12 Quartus II Programmer Window with ISP Clamp Checkbox ax Hardware ByteBlaster LPT1 Mode JTAG x Progress 0 IV Enable realtime ISP to allow background programming for MAX II devices Wb Start File Device checksum ail Stop a LES ISP 12707144 S2EE2C FFFFFFFF BP Auto Detect Dn Fi X Delete Add File li Change Fi GP Gave Fie Add Device T tp Program Blank ISP Congre Verity Check Examine Erase LAMP lies File Li m m Li Li ISP Clamp with Jam JBC Files The Jam or JBC files used for ISP clamp should contain all the pin state info
107. chain and set the trigger to the minimum V level listed in the recommended operating conditions table of the appropriate device family data sheet If a trigger occurs during in system programming the devices may need more current than is being supplied by the existing power supply Try replacing the existing power supply with one that provides more current Power Up Problems Excessive voltage or current on I O pins during power up can cause one of the devices in the chain to experience latch up Check if any of the devices are hot to the touch hot devices have probably experienced latch up and may have been damaged In this situation check all voltage sources to make sure that excessive voltage or current is not being fed into the device Then replace the affected device and try programming again Random Signals on JTAG Pins During normal operation each device s TAP controller must be in the test logic reset state To force the device back into this state try pulling the TMS signal high and pulsing the TCK clock signal six times If the device then powers up successfully you must add a higher pull down resistor on the TCK signal Software Issues Failures during in system programming may occasionally be related to the Quartus II software Software related issues are documented in the Find Answers section under the Support Center on the Altera website at ww w altera com Search the database for information relating to software
108. current state when the device is in ISP mode October 2008 Altera Corporation Chapter 12 Real Time ISP and ISP Clamp for MAX Il Devices 12 5 ISP Clamp With the ISP clamp feature in MAX II devices you can hold each I O pin of a device to a specified static state when programming the device You can set the state in the Quartus II software After successfully programming the device in ISP clamp mode those I O pins will be released and function according to the new design This feature can be used to indicate when the device is being programmed and when the programming is done by setting a particular pin to a specific state different from the state when the device is in user mode when the device enters ISP clamp mode How ISP Clamp Works When the ISP clamp feature is used you can set the I O pins to tri state default high low or even sample the existing state of a pin and hold the pin to that state when the device is in ISP clamp operation The software determines the values to be scanned into the boundary scan registers of each I O pin based on your settings This will determine the state of the pins to be clamped to when the device programming is in progress The weak I O pull up resistors are disabled during programming when the ISP clamp feature is used even if the I O is clamped to a tri state value Before clamping the I O pins the SAMPLE PRELOAD JTAG instruction is first executed to load the appropriate values to the
109. device operation Make sure all pins that transition during in system programming do not have a ground or Vec overshoot Overshoot problems typically occur on free running clocks or data buses that can toggle during in system programming All pins that have an overshoot greater than 1 0 V must have series termination For more information about the recommended operating conditions and the absolute maximum ratings for MAX II devices and termination refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook and AN 75 High Speed Board Designs respectively UFM Operations During In System Programming II Device Handbook If your design allows you to access the MAX II UFM write or erase you must ensure that all the erase or write operations of the UFM are completed before starting any ISP session including stand alone verify examine setting security bit and reading the contents of the UFM You should never start an ISP session when any erase or write operation of the UFM is on going as this may put the device in an unrecoverable state However this restriction does not apply to the read operation of the If you cannot ensure that any erase or write operation of the UFM is complete before attempting an ISP operation to the MAX II device then you should enable the real time ISP feature When used properly this feature can help guard against any UFM ISP operation contention When real time ISP is enab
110. file should contain eight addresses of data 25 addresses each word containing 16 bits If the initial content at the location 000 is intended to be 10101010 you should specify 1010101011111111 for address 000 in the HEX file gt This specification applies only to HEX files used with the parallel interface MIFs do not require you to fully specify 16 bits for each data word However both MIF and HEX files require you to specify all addresses of data according to the address width selected in the megafunction Memory Initialization for the altufm spi Megafunction The same 16 bit data padding mentioned for altufm parallel is required for HEX files used with the SPI Base 8 bits and Extended 16 bits mode interface In addition for SPI Base and Extended mode you must fully specify memory content for all 512 addresses both sector 0 and sector 1 in the HEX file and MIF even if sector 1 is not used You can put valid data for SPI Base mode addresses 0 to 255 sector 0 and initialize sector 1 to all ones October 2008 Altera Corporation MAX II Device Handbook Chapter 9 Using User Flash Memory in MAX II Devices Creating Memory Content File Memory Initialization for the altufm i2c Megafunction The MAX II UFM physical memory block contains a 16 bit wide and 512 deep 9 bit address array The altufm_i2c megafunction uses the following smaller array sizes m An 8 bit wide and 128 deep 7 bit address mapping for 1 Kbit memory
111. following dates Where chapters or groups of chapters are available separately part numbers are listed Introduction Revised August 2009 Part Number MII51001 1 9 MAX II Architecture Revised October 2008 Part Number MII51002 2 2 JTAG and In System Programmability Revised October 2008 Part Number MII51003 1 6 Hot Socketing and Power On Reset in MAX II Devices Revised October 2008 Part Number MII51004 2 1 DC and Switching Characteristics Revised August 2009 Part Number MII51005 2 5 Reference and Ordering Information Revised August 2009 Part Number MII51006 1 6 Package Information Revised October 2008 Part Number MII51007 2 1 Using MAX II Devices in Multi Voltage Systems Revised October 2008 Part Number MII51009 1 7 Using User Flash Memory in MAX II Devices Revised October 2008 Part Number MII51010 1 8 Replacing Serial EEPROMs with MAX II User Flash Memory Revised October 2008 Part Number MII51012 1 5 In System Programmability Guidelines for MAX II Devices Revised October 2008 Part Number MII51013 1 7 Real Time ISP and ISP Clamp for MAX II Devices August 2009 Altera Corporation MAX II Device Handbook xii Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 II Device Handbook Revised October 2008 Part Number 51019 1 6 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices Revised October 2008 Part Number MII51014 1 7 Using Jam STAPL for I
112. for UFM Block on page 9 13 Creating Memory Content File on page 9 40 Simulation Parameters on page 9 46 UFM Array Description Each UFM array is organized as two separate sectors with 4 096 bits per sector Each sector can be erased independently Table 9 1 shows the dimension of the UFM array Table 9 1 UFM Array Size Device 240 570 1270 2210 Sectors Address Bits Data Width 2 4 096 hits per sector 9 16 Total Bits 8 192 Memory Organization Map October 2008 Altera Corporation Table 9 2 shows the memory organization for the MAX II UFM block There 512 locations with 9 bits addressing a range of 000h to 1FFh Each location stores 16 bit wide data The most significant bit MSB of the address register indicates the sector in operation MAX II Device Handbook 9 2 Chapter 9 Using User Flash Memory in MAX II Devices UFM Array Description Table 9 2 Memory Organization Sector Address Range 1 100h 1FFh 0 000h OFFh Using and Accessing UFM Storage You can use the UFM to store data of different memory sizes and data widths Even though the UFM storage width is 16 bits you can implement different data widths or a serial interface with the altufm megafunction Table 9 3 shows the different data widths available for the three types of interfaces supported in the Quartus software Table 9 3 Data Widths for Logic Array Interfa
113. implement the following IEEE Std 1149 1 BST instructions SAMPLE PRELOAD EXTEST BYPASS IDCODE USERCODE CLAMP and HIGHZ The length of the BST instructions is 10 bits These instructions are described in detail later in this chapter Sse Refer to the JTAG and In System Programmability chapter in the MAX II Device Handbook for a summary of the BST instructions and their instruction codes The IEEE Std 1149 1 TAP controller a 16 state state machine clocked on the rising edge of TCK uses the TMS pin to control IEEE Std 1149 1 operation in the device Figure 13 5 shows the TAP controller state machine II Device Handbook October 2008 Altera Corporation Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Il Devices 13 7 IEEE Std 1149 1 BST Operation Control Figure 13 5 IEEE Std 1149 1 TAP Controller State Machine TMS 0 SELECT_DR_SCAN TMS 1 SELECT_IR_SCAN TMS 1 TMS 1 TMS 0 TMS 0 TMS 1 TMS 1 CAPTURE_DR CAPTURE IR TMS 0 9 TMS 0 TMS 1 TMS 1 EXITI DR a TMS 0 PAUSE DR o 2 TMS 1 TMS 1 TMS 1 UPDATE DR TMS 0 UPDATE IR When the TAP controller is in the TEST LOGIC RESET state the BST circuitry is disabled the device is in normal operation and the instruction register is initialized with IDCODE as the initial instruction At device power up the TAP controller starts inthis TEST LOGIC RESET
114. is not guaranteed for voltages that are between the maximum recommended 2 5 V operating voltage and the minimum recommended 3 3 V operating voltage The MAX and MAX IIZ devices use external 1 8 V supply The 1 8 V Vcc external supply powers the device core directly Figure 2 18 MultiVolt Core Feature in MAX II Devices 3 3 V or 2 5 V on VCCINT Pins gt PNE 1 8 V on gt ou VCCINT Pins 1 8 V Core Voltage MAX II Device 1 8 V Core Voltage MAX 116 or MAX 112 Device II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 23 1 0 Structure 1 0 Structure IOEs support many features including m LVTTL and LVCMOS I O standards 3 3 V 32 bit 66 MHz PCI compliance Joint Test Action Group boundary scan test BST support Programmable drive strength control Weak pull up resistors during power up and in system programming Slew rate control Tri state buffers with individual output enable control Bus hold circuitry Programmable pull up resistors in user mode Unique output enable per pin Open drain outputs Schmitt trigger inputs m FastI O connection m Programmable input delay MAX II device IOEs contain a bidirectional I O buffer Figure 2 19 shows the MAX II IOE structure Registers from adjacent LABs can drive to or be driven from the IOE s bidirectional I O buffers The Quartus II software automatically attempts to
115. is not protected by the security bit and is accessible through JTAG or logic array connections Programming with External Hardware MAX II devices can be programmed by downloading the information via in circuit testers embedded processors the Altera ByteblasterMV MasterBlaster ByteBlaster II and USB Blaster cables BP Microsystems System General and other programming hardware manufacturers provide programming support for Altera devices Check their websites for device support information Referenced Documents This chapter references the following documents m DC and Switching Characteristics chapter in the MAX II Device Handbook m IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices chapter in the MAX II Device Handbook m Real Time ISP and ISP Clamp for MAX II Devices chapter in the MAX II Device Handbook m Using Jam STAPL for ISP via an Embedded Processor chapter in the MAX II Device Handbook October 2008 Altera Corporation MAX II Device Handbook 3 8 Chapter 3 JTAG and In System Programmability Document Revision History Document Revision History Table 3 5 shows the revision history for this chapter Table 3 5 Document Revision History Date and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 1 6 December 2007 m Added warning note after Table 3 1 version 1 5 Updated Table 3 3 and Table 3 4 m Added Referen
116. issued to the MAX II device as this may put the device into an unknown state requiring a power cycle to recover device operation WARNING The MAX II device instruction register length is 10 bits and the USERCODE register length is 32 bits Table 3 2 and Table 3 3 show the boundary scan register length and device IDCODE information for MAX II devices Table 3 2 MAX II Boundary Scan Register Length Device Boundary Scan Register Length 240 240 570 480 1270 636 2210 816 Table 3 3 32 Bit MAX II Device IDCODE Part 1 of 2 Binary IDCODE 32 Bits 1 Version Manufacturer LSB Device 4 Bits Part Number Identity 11 Bits 1 Bit 2 HEX IDCODE EPM240 0000 0010 0000 1010 0001 000 0110 1110 1 OxO20A10DD EPM240G EPM570 0000 0010 0000 1010 0010 000 0110 1110 1 0x020A20DD EPM570G EPM1270 0000 0010 0000 1010 0011 000 0110 1110 1 0x020A30DD EPM1270G EPM2210 0000 0010 0000 1010 0100 000 0110 1110 1 0x020A40DD EPM2210G II Device Handbook October 2008 Altera Corporation Chapter 3 JTAG and In System Programmability 3 3 IEEE Std 1149 1 JTAG Boundary Scan Support Table 3 3 32 Bit MAX II Device IDCODE Part 2 of 2 Binary IDCODE 32 Bits 7 Version Manufacturer LSB Device 4 Bits Part Number Identity 11 Bits 1 Bit 2 HEX IDCODE 2407 0000 0010 0000 1010 0101 00
117. issues that interfere with in system programming ISP via Enbedded Processors This section provides guidelines for programming ISP capable devices using the Jam Standard Test and Programming Language STAPL and an embedded processor Processor and Memory Requirements The Jam Byte Code Player supports 8 bit and higher processors the ASCII Jam Player supports 16 bit and higher processors The Jam Player uses memory in a predictable manner which simplifies in field upgrades by confining updates to the Jam File The Jam Player memory uses both ROM and dynamic memory RAM ROM is used to store the Jam Player binary and the Jam File dynamic memory is used when the Jam Player is called For information about how to estimate the maximum amount of RAM and ROM required by the Jam Player refer to the Using Jam STAPL for ISP via an Embedded Processor chapter in the MAX II Device Handbook October 2008 Altera Corporation MAX II Device Handbook 11 10 Chapter 11 In System Programmability Guidelines for MAX II Devices ISP via In Circuit Testers Porting the Jam Player The Altera Jam Player both Byte Code and ASCII versions works with a PC parallel port To port the Jam Player to your processor you only need to modify the jamstub c or jbistub c file for the ASCIIJam Player or Jam Byte Code Player respectively other files should remain the same If the Jam Player is ported incorrectly an Unrecognized Device error is generated T
118. of the LUT output October 2008 Altera Corporation MAX II Device Handbook 2 8 Chapter 2 MAX II Architecture Logic Elements LUT Chain and Register Chain addnsub Signal In addition to the three general routing outputs the LEs within an LAB have LUT chain and register chain outputs LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions Register chain outputs allow registers within the same LAB to cascade together The register chain output allows an LAB to use LUTS for a single combinational function and the registers to be used for an unrelated shift register implementation These resources speed up connections between LABs while saving local interconnect resources Refer to MultiTrack Interconnect on page 2 12 for more information about LUT chain and register chain connections The LE s dynamic adder subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor This feature is controlled by the LAB wide control signal addnsub The addnsub signal sets the LAB to perform either A Bor A B The LUT computes addition subtraction is computed by adding the two s complement of the intended subtractor The LAB wide signal converts to two s complement by inverting the B bits within the LAB and setting carry in to 1 which adds one to the least significant bit LSB The LSB of an adder subtractor must be placed in the first LE of the LAB where
119. output switching requirements As the number of I O pins and the capacitive load on the pins increase more decoupling capacitance is required As many as possible 0 1 mF power supply decoupling capacitors should be connected to the VCC and GND pins or the and GND planes These capacitors should be located as close as possible to the MAX II device Each VCCINT GNDINT and VCCIO GNDIO pair should be decoupled with a 0 1 mF capacitor When using high density packages such as ball grid array BGA packages it may not be possible to use one decoupling capacitor per VCC GND pair In this case you should use as many decoupling capacitors as possible For less dense designs a reduction in the number of capacitors may be acceptable Decoupling capacitors should have a good frequency response such as monolithic ceramic capacitors Device and Package Cross Reference Table 7 1 shows which Altera MAX II devices are available in thin quad flat pack TOFP FineLine BGA FBGA and Micro Fineline BGA MBGA packages Table 7 1 MAX II Devices in TQFP FineLine BGA and Micro FineLine BGA Packages Part 1 of 2 Device Package Pin EPM24Z MBGA 68 240 FBGA 1 100 2406 240 MBGA 7 100 2406 EPM240Z EPM240 TQFP 100 EPM240G October 2008 Altera Corporation MAX II Device Handbook 1 2 Chapter 7 Package Information Thermal Resistance Table 7 1 MAX II Devices in TQFP FineLine B
120. p EU 12 4 How ISP Clamp WOEKS omes se teme eie 12 5 Using ISP Clamp in the Quartus Software 12 5 the PS le UAE CE 12 6 Defining the Pin States in Assignment Editor 12 9 ISP Clamp with Jam JBC Files a 949 eei ee eee ERR ERR 12 10 Conclusion x ss pRR REESE RERO REPE CREE REUS CEU MEE EDEN UM PH 12 10 Referenced Documents 1 1 1 2 12 10 Document Revision History 1 1 1 2 12 11 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices Introd ction 22i ert PR A E AU E ER IU 13 1 IEEE Std 1149 1 BST Architecture syri uso we tea e pare ee xar ERIT Eq IERI REPE RES 13 2 IEEE Std 1149 1 Boundary Scan Register 13 3 Boundary Scan Cells of a MAX Device I O Pin 13 4 JTAG Pins and Power Pins 13 5 IEEE Std 1149 1 BST Operation Control 13 6 SAMPLE PRELOAD Instruction 13 9 EXTEST Instruction Mode sss erp CREE S REESE ehh baw Rake RENE EN einen 13 11 BYPASS
121. place registers in the adjacent LAB with fast I O connection to achieve the fastest possible clock to output and registered output enable timing For input registers the Quartus II software automatically routes the register to guarantee zero hold time You can set timing assignments in the Quartus II software to achieve desired I O timing Fast 1 0 Connection A dedicated fast I O connection from the adjacent LAB to the IOEs within an I O block provides faster output delays for clock to output and tpp propagation delays This connection exists for data output signals not output enable signals or input signals Figure 2 20 Figure 2 21 and Figure 2 22 illustrate the fast I O connection October 2008 Altera Corporation MAX II Device Handbook 2 24 Chapter 2 MAX II Architecture 1 0 Structure Figure 2 19 MAX II IOE Structure Data in Fast out Data out OE Optional PCI Clamp 1 Programmable Wee 1 P4 2 PR Pin Drive Strength i Optional Bus Hold Open Drain Output Circuit Slew Control r Optional Schmitt Programmable Trigger Input Input Delay Note to Figure 2 19 1 Available in EPM1270 and EPM2210 devices only 1 0 Blocks The IOEs are located in I O blocks around the periphery of the MAX II device There are up to seven IOEs per row I O block 5 maximum in the EPM240 device and up to four IOEs per column I O block Each col
122. register 3 After the transmission of the eighth bit of WRDI the interface is in wait state waiting for nCS to be pulled back to high Any transmission after this is ignored 4 nCS is pulled back to high Figure 9 34 WRDI Operation Sequence ncs E NN 01234567 SCK I 8 bit Instruction 9 XXX MSB so High Impendance RDSR Read Status Register The content of the status register be read by issuing RDSR Once RDSR is received the interface outputs the content of the status register through the SO port Although the most significant four bits Bit 7 to Bit 4 do not hold valuable information all eight bits in the status register will output through the SO port This allows future compatibility when Bit 7 to Bit 4 have new meaning in the status register During the October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 33 Software Support for UFM Block internal program cycle in the UFM RDSR is the only valid opcode recognized by the interface therefore the status register can be read at any time and nRDY is the only valid status bit Other status bits are frozen and remain unchanged until the internal program cycle is ended RDSR is issued through the following sequence as shown in Figure 9 35 1 ncs is pulled low 2 Opcode 00000101 is transmitted into the interface 3 SIignores i
123. required for a signal to be routed to the clock preset or clear input of an LE register trastio Combinational output delay thasrois the time required for a combinational signal from the LE adjacent to the 1 0 block using the fast 1 0 connection 1 0 input pad and buffer delay The t applies to 1 0 pins used as inputs teros applies to GCLK pins when used for global signals 4 is the delay required for a global signal to be routed from the GCLK pins to the LAB column clocks through the global clock network II Device Handbook October 2008 Altera Corporation Chapter 16 Understanding Timing in MAX II Devices 16 3 Internal Timing Parameters for MAX 11 Table 16 2 Internal Timing Microparameters Part 2 of 2 Parameter Description lioc Internal generated output enable delay The delay from an internally generated signal on the interconnect to the output enable of the tri state buffer Input routing delay The delay incurred from the row 1 0 pin used as input to the LE adjacent to it Output data delay for the row interconnect The delay incurred by signals routed from an interconnect 0 cell top Output delay buffer and pad delay Refer to Timing Model and Specifications section in the DC and Switching Characteristics chapter the MAX II Device Handbook for delay adders associated with different 0 standards drive strengths and slew rates ty
124. signal voltages within the device Additionally with the Quartus II software efficient implementation of most interconnects with local routing in MAX II devices significantly lowers the dynamic power Figure 17 1 shows the typical power consumption versus frequency for MAX II devices The power consumption mWatts provided is based on typical conditions using a pattern that fills a device with a 16 bit loadable enabled up down counter with no output load October 2008 Altera Corporation MAX II Device Handbook 11 2 Chapter 17 Understanding and Evaluating Power MAX II Devices Power in MAX II Devices Figure 17 1 Power Consumption versus Frequency for MAX II Devices Note 1 2 240 570 3 120 00 m 250 00 100 00 4 200 00 S 80 00 5 150 00 2 6000 2 S S 5 jtd fe 2 100 00 6 8 20004 p sue 0200 0 00 0 50 100 150 0 50 100 150 Frequency MHz Frequency MHz 1000 00 4 EPM2210 EPM1270 3 600 00 3 900 00 800 00 4 500 00 4 700 00 4 E 4 z 400 00 4 E 600 00 a S 500 00 4 e amp 300 00 5 5 5 2 400 00 4 E e amp 200 00 8 300 00 F 200 00 4 100 00 100 00 4 0 00 0 00 0 50 100 150 0 50 100 150 Frequency MHz Frequency MHz Notes to Figure 17 1 1 Every device is fully utilized with 16 bit counters for power estimation The MAX II and MAX IIG
125. size m 8 wide and 256 deep 8 bit address mapping for 2 Kbits memory size m 8 bit wide and 512 deep 9 bit address mapping for 4 Kbits memory size m 8 bit wide and 1 024 deep 10 bit address mapping for 8 Kbits memory size Altera recommends that you pad the MIF or HEX file for both address and data width to fill the physical memory map for the UFM block and ensure the MIF HEX file represents a full 16 bit word size and a 9 bit address space Memory Map for 1 Kbit Memory Initialization Figure 9 49 shows the memory map initialization for the altufm 12 megafunction of 1 Kbit memory size The altufm i2c megafunction byte address location of 00h to 3Fh is mapped to the block address location of 000h to 03Fh The altufm 12 megafunction byte address location of 40h to 7Fh is mapped to the UFM block address location of 1C0h to 1FFh Altera recommends that you pad the unused address locations of the UFM block with all ones Figure 9 49 Memory Map for 1 Kbit Memory Initialization MIF or HEX File Contents to represent the actual data and address size for the UFM block lFFh 1 Kbit altufm i2c Megafunction Address 40h in logical memory maps to Logical Memory Contents 1COh in the MIF HEX file Address 7Fh in logical memory maps to 1FFh in the MIF HEX file and all data in between follows the order in the 1COh logical memory Upper Half Addresses 40h to 7Fh This section of the UFM is unused the MIF H
126. standard 4 pin IEEE Std 1149 1 JTAG interface In system programmability ISP offers quick efficient iterations during design development and debugging cycles The logic circuitry and interconnects in the MAX II architecture are configured with flash based SRAM configuration elements These SRAM elements require configuration data to be loaded each time the device is powered The process of loading the SRAM data is called configuration The on chip configuration flash memory CFM block stores the SRAM element s configuration data The CFM block stores the design s configuration pattern in a reprogrammable flash array During ISP the MAX II JTAG and ISP circuitry programs the design pattern into the CFM block s non volatile flash array The MAX II JTAG and ISP controller internally generate the high programming voltages required to program the CFM cells allowing in system programming with any of the recommended operating external voltage supplies that is 3 3 V 2 5 V or 1 8 V for the MAX IIG and MAX IIZ devices ISP can be performed anytime after and all Veciobanks have been fully powered and the device has completed the configuration power up time By default during in system programming the I O pins are tri stated and weakly pulled up to to eliminate board conflicts The in system programming clamp and real time ISP feature allow user control of I O state or behavior during ISP For more information refer to In
127. the LAB The Quartus II software automatically places any registers that are not used by the counter into other LABs The addnsub LAB wide signal controls whether the LE acts as an adder or subtractor Figure 2 8 LE in Dynamic Arithmetic Mode LAB Carry In 0 lt sload Sclear aload Carry Inl e LAB Wide LAB Wide LAB Wide addnsub LAB Wide 1 Register chain 9 datal connection data2 data3 Note to Figure 2 8 ALD PRE ADATA Q Row column and D direct link routing 25 gt gt Row column and ENA gt direct link routing CLRN 9 clock LAB Wide eu ena LAB Wide M I Local routing acir LAB Wide eo LUT chain connection Register chain output J Register Feedback v Carry Out0 Carry Outl 1 The addnsub signal is tied to the carry input for the first LE of a carry chain only II Device Handbook Carry Select Chain The carry select chain provides a very fast carry select function between LEs in dynamic arithmetic mode The carry select chain uses the redundant carry calculation to increase the speed of carry functions The LE is configured to calculate outputs for a possible carry in of 0 and ca
128. the MAX II device has an ISP DONE bit that will only be set at the very end of a successful program sequence The I O pins will only drive out if this bit is set This prevents a partially programmed device from driving out and operating unpredictably MultiVolt Devices and Power Up Sequences For the JTAG circuitry to operate correctly during in system programming or boundary scan testing all devices in a chain must be in the same state Therefore in systems with multiple power supply voltages the JTAG pins must be held in the test logic reset state until all devices in the chain are completely powered up This procedure is particularly important because systems with multiple power supplies cannot power all voltage levels simultaneously MAX II devices have the MultiVolt feature and can use more than one power supply voltage Vccy and Veco for each 1 0 bank Vc provides power to the JTAG circuitry V cco provides power to input pins and output drivers for output pins including TDO Therefore when using two power supply voltages the JTAG circuitry must be held in the test logic reset state until both power supplies are turned on If the pins are not held in the test logic reset state in system programming errors can occur Vecio Powered before Vo If Vcao is powered up before V cany the JTAG circuitry is not active but TDO is tri stated Even though the JTAG circuitry is not active if the next device in the JTAG chain
129. the LAB local interconnect are inputs to a four input LUT see Figure 2 7 The Quartus II Compiler automatically selects the carry in or the data3 signal as one of the inputs to the LUT Each LE can use LUT chain connections to drive its combinational output directly to the next LE in the LAB Asynchronous load data for the register comes from the data3 input of the LE LEs in normal mode support packed registers Figure 2 7 LE in Normal Mode addnsub LAB Wide datal data2 cin from cout of previous LE data4 sload sclear aload LAB Wide LAB Wide LAB Wide Register chain connection ALD PRE T Q Row column and 1 L DirectLink routing J e Row column and ENA L a data3 ___ 4 Input CLRN eq DirectLink routing LUT clock LAB Wide Local routing ena LAB Wide Pi aclr LAB Wide LUT chain e gt connection Register Feedback Note to Figure 2 7 chain output 1 This signal is only allowed in normal mode if the LE is at the end of an adder subtractor chain October 2008 Altera Corporation Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders counters accumulators wide parity functions and comparators An LE in dynamic arithmetic mode uses four 2
130. the LAB wide addnsub signal automatically sets the carry in to 1 The Quartus II Compiler automatically places and uses the adder subtractor feature when using adder subtractor parameterized functions LE Operating Modes II Device Handbook The MAX II LE can operate in one of the following modes m Normal Mode m Dynamic Arithmetic Mode Each mode uses LE resources differently In each mode eight available inputs to the LE the four data inputs from the LAB local interconnect carry in0 and carry inl from the previous LE the LAB carry in from the previous carry chain LAB and the register chain connection are directed to different destinations to implement the desired logic function LAB wide signals provide clock asynchronous clear asynchronous preset load synchronous clear synchronous load and clock enable control for the register These LAB wide signals are available in all LE modes The addnsub control signal is allowed in arithmetic mode The Quartus II software in conjunction with parameterized functions such as library of parameterized modules LPM functions automatically chooses the appropriate mode for common functions such as counters adders subtractors and arithmetic functions October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 9 Logic Elements Normal Mode The normal mode is suitable for general logic applications and combinational functions In normal mode four data inputs from
131. the R W bit must be set to 1 Three different read operations are supported m Current Address Read Single Byte m Random Address Read Single byte m Sequential Read Multi Byte After each UFM data has been read and transferred to the master the UFM address register is incremented for all single and multi byte read operations Current Address Read This read operation targets the current byte location pointed to by the UFM address register Figure 9 18 shows the current address read sequence Figure 9 18 Current Address Read Sequence S Slave Address RW A Data P 4 read S Start Condition From Master to Slave P Stop Condition A Acknowledge From Slave to Master Random Address Read Random address read operation allows the master to select any byte location for a read operation The master first performs a dummy write operation by sending the start condition slave address and byte address of the location it wishes to read After the altufm_i2c megafunction acknowledges the slave and byte address the master generates a repeated start condition the slave address and the R W bitis set to 1 The altufm_i2c megafunction then responds with acknowledge and sends the 8 bit data requested The master then generates a stop condition Figure 9 19 shows the random address read sequence October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX II
132. the test fixture During operation there should be enough access points to allow quiet PCB operation Having too few access points results in a noisy system that can disrupt JTAG scans m Turn off on board oscillators During programming oscillators should have the ability to be electrically turned off to reduce system noise m Add external resistors to pull outputs to a defined logic level during programming 57 Output pins are tri stated during programming and are pulled up by a weak internal resistor However Altera recommends that signals requiring a pre defined level be externally forced to the appropriate level using an external resistor For more information about board design for ISP refer to the In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook Creating the Fixture Providing a clean interface between the test fixture and the target board is essential for successful in system programming To provide a clean interface use short wires in the test fixture to improve the TCK connection Longer wires can introduce inductive noise into the system which can disrupt programming The wire connecting TCK should be no longer than 1 inch Use the Agilent Fixture Consultant to manage the layout and creation of the test fixture see the Agilent Board Test Family Manual October 2008 Altera Corporation MAX II Device Handbook 15 4 Chapter 15 Using the Agilent 3070 Teste
133. to enter a data word when writing to the UFM The data register is 16 bits wide and data is shifted serially from the least significant bit LSB to the MSB with each DRCLK This port is required for writing but unused if the UFM is in read only mode DRCLK Input Clock input that controls the data register It is required and takes control when data is shifted from DRDin to DRDout or loaded in parallel from the flash memory The maximum frequency for DRCLK is 10 MHz DRSHFT Input Signal that determines whether to shift the data register or load it on a DRCLK edge high value shifts the data from DRDin into the LSB of the data register and from the MSB of the data register out to DRDout A low value loads the value of the current address in the flash memory to the data register ARDin Input Serial input to the address register It is used to enter the address of a memory location to read program or erase The address register is 9 bits wide for the UFM size 8 192 bits October 2008 Altera Corporation MAX II Device Handbook 9 4 Chapter 9 Using User Flash Memory in MAX II Devices UFM Functional Description Table 9 4 UFM Interface Signals Part 2 of 2 Port Name Port Type Description ARCLK Input Clock input that controls the address register It is required when shifting the address data from ARDin into the address register or during the increment stage The maximum freque
134. to help address the issues of programming PLDs There are several advantages of using the new product that are discussed later in this chapter Device Support When programming MAX II devices together with devices from other families using the Agilent 3070 tester ensure that all devices in the chain can be programmed using the tester October 2008 Altera Corporation MAX II Device Handbook 15 2 Chapter 15 Using the Agilent 3070 Tester for In System Programming Agilent 3070 Development Flow without the PLD ISP Software Agilent 3070 Development Flow without the PLD ISP Software Programming devices with the Agilent 3070 tester using a Serial Vector Format svf File without Agilent s PLD ISP software requires the following steps Refer to Figure 15 1 Figure 15 1 Agilent 3070 Development Flow for In System Programming Using SVF File without PLD ISP Designer Test Engineer Step 1 Create a Printed Circuit Board PCB and Test Fixture Step 2 gt Create a Serial Vector Format svf File Step 3 gt Convert the SVF File to Pattern Capture Format pcf File Step 4 Create Executable Tests from F iles Step 5 gt Compile Executable Tests Programming Debug Step 6 No Successful II Device Handb
135. top view of the silicon die Figure 8 1 is a graphical representation only Refer to the pin list and the Quartus II software for exact pin locations 240 and EPM570 devices only have two 1 0 banks The 3 3 V PCI 1 0 standard is only supported in EPM1270 and EPM2210 devices The Schmitt trigger input option for 3 3 V and 2 5 V 1 0 standards is supported for all 1 0 pins II Device Handbook October 2008 Altera Corporation Chapter 8 Using MAX II Devices in Multi Voltage Systems 8 3 MultiVolt Core and 1 0 Operation MultiVolt Core and 1 0 Operation MAX II devices include MultiVolt core I O operation capability allowing the core and I O blocks of the device to be powered up with separate supply voltages The VCCINT pins supply power to the device core and the VCCIO pins supply power to the device I O buffers The VCCINT pins can be powered up with 1 8 V for MAX and MAX IIZ devices or 2 5 3 3 V for MAX II devices the VCCIO pins for a given I O bank that have MultiVolt capability should be supplied from the same voltage level for example 5 0 3 3 2 5 1 8 or 1 5 V See Figure 8 2 Figure 8 2 Implementing a Multiple Voltage System with a MAX II Device Note 1 2 3 4 1 8 V 2 5 V 3 3 V Power Supply Vccio V 5 0 V MAX II CCIO 3 3 V Device Device Device Vccio 2 5 V Device Notes to Figure 8 2 1 For MAX IIG and MAX
136. write and erase operation is not allowed In this case the altufm 12 megafunction acknowledges the slave address and memory address After the master transfers the first data byte the altufm i2c megafunction sends a not acknowledge condition to the master to indicate that the instruction will not execute When WP is set to 0 the write and erase operations are allowed October 2008 Altera Corporation MAX II Device Handbook 9 18 II Device Handbook Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Erase Operation Commercial serial EEPROMs automatically erase each byte of memory before writing into that particular memory location during a write operation However the MAX II block is flash based and only supports sector erase operations and not byte erase operations When using read write mode a sector or full memory erase operation is required before writing new data into any location that previously contained data The block cannot be erased when the altufm_i2c megafunction is in read only mode Data can be initialized into memory for read write and read only modes by including a memory initialization file mif or hexidecimal file hex in the altufm MegaWizard Plug In Manager This data is automatically written into the UFM during device programming by the Quartus II software or third party programming tool The altufm i2c megafunction supports four different erase operation meth
137. 0 12 5 0 00 12 5 0 00 125 000 Each row the Logic section represents a separate design module Table 17 3 describes the parameters in the Logic section of the PowerPlay Early Power Estimator spreadsheet Table 17 3 Logic Section Information Part 1 of 2 Column Heading Logic Module Description Enter a name for each module of the design optional entry Clock Frequency MHz Enter a clock frequency MHz The operating frequency for Il and MAX IIG is between 0 and 304 MHz For MAX IIZ the operating frequency is between 0 and 152 MHz A 100 MHz input clock with a 12 5 toggle means that each look up table LUT or flipflop output toggles 12 5 million times per second 100 x 12 5 LES Toggle Enter the number of LES in this module Enter the average percentage of logic toggling on each clock cycle The toggle percentage ranges from 0 to 100 Typically the toggle percentage is 12 5 which is the toggle percentage of a 16 bit counter To ensure you do not underestimate the toggle percentage you can use a higher toggle percentage Most logic toggles infrequently and therefore toggle rates of lt 50 are more realistic For example a TFF with its input tied to V has a toggle rate of 100 because its output is changing logic states on every clock cycle see Figure 17 6 Figure 17 7 shows an example of a 4 bit counter The first TEF with least sign
138. 0 0 0 0 ps 4mA 65 84 19 6 2 3 ps 2 5 V LVTTL 14mA 122 158 195 63 71 88 ps LVCMOS 7 193 251 309 to 1 ps 1 8 V LVTTL 6mA 568 738 909 128 118 118 ps LVCMOS 654 850 1 046 352 327 332 ps 1 5 VLVCMOS 4mA 1 059 1 376 1 694 421 400 400 ps 2mA 1 167 1 517 1 867 757 743 743 ps 3 3 V PCI 20mA 3 4 5 6 2 3 ps Table 5 30 External Timing Output Delay and to Adders for Slow Slew Rate MAX II MAX IIG 112 3 Speed 4 Speed 5 Speed 6 Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade 1 0 Standard Min Max Max Min Max Min Max Min Max Min Max Unit 3 3 V LVTTL 16 7 064 6 745 6 426 5 966 5 992 6 118 ps 8mA 7 946 7 627 7 308 6 541 6 570 6720 ps 3 3 V LVCMOS 8 7 064 6 745 6 426 5 966 5 992 6 118 ps 4mA 7 946 7 627 7 308 6 541 6 570 6720 ps 25 VIVITL 14mA 10 434
139. 0 0110 1110 1 0x020A50DD EPM570Z 0000 0010 0000 1010 0110 000 0110 1110 1 0x020A60DD Notes to Table 3 2 1 most significant bit MSB is on the left 2 The IDCODE s least significant bit LSB is always 1 JTAG Block October 2008 Altera Corporation For JTAG AC characteristics refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook For more information about BST refer to the IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices chapter in the MAX II Device Handbook The MAX ITJTAG block feature allows you to access the JTAG TAP and state signals when either the USERO or USER1 instruction is issued to the JTAG TAP The USERO and USERI instructions bring the JTAG boundary scan chain TDI through the user logic instead of the MAX II device s boundary scan cells Each USER instruction allows for one unique user defined JTAG chain into the logic array Parallel Flash Loader The JTAG block ability to interface JTAG to non JTAG devices is ideal for general purpose flash memory devices such as Intel or Fujitsu based devices that require programming during in circuit test The flash memory devices can be used for configuration or be part of system memory In many cases the MAX II device is already connected to these devices as the configuration control logic between the FPGA and the flash device Unlike ISP capable CPLD devices bulk flash devices do not have T
140. 0 ps Trigger With Schmitt 308 400 493 387 434 442 ps Trigger 3 3 V LVCMOS Without Schmitt 0 0 0 0 0 0 ps Trigger With Schmitt 308 40 493 387 434 442 ps Trigger 2 5 V LVTTL WithoutSchmitt 21 27 33 42 43 43 ps LVCMOS Trigger With Schmitt 423 550 677 429 476 483 ps Trigger 1 8 VLVTTL WithoutSchmitt 353 459 565 378 373 373 ps LVCMOS Trigger 1 5 V LVCMOS Without Schmitt 855 1 111 1 368 681 622 658 ps Trigger 3 3 Without Schmitt 6 7 9 0 0 0 ps Trigger MAX II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics 5 23 Timing Model and Specifications Table 5 29 External Timing Output Delay and to Adders for Fast Slew Rate MAX II MAX IIG 112 3 Speed 4 Speed 5 Speed 6 Speed 1 Speed 8 Speed Grade Grade Grade Grade Grade Grade 1 0 Standard Min Max Min Max Min Max Min Max Min Max Min Max Unit 3 3 V LVTTL 16mA 0 0 0 0 0 0 ps 8mA 65 84 14 amp 2 ps 3 3 V LVCMOS 8mA 0 0
141. 096 2 MHz 1 8 to 5 5 EEPROM M93C56 R 2 048 2 MHz 1 8 to 5 5 EEPROM M93S66 W 4 096 2 MHz 2 5 to 5 5 EEPROM M93S56 W 2 048 v 2 MHz 2 5 to 5 5 EEPROM M93S66 R 4 096 2 MHz 1 8 to 5 5 EEPROM M93S56 R 2 048 2 MHz 1 8 to 5 5 EEPROM M95080 W 8 192 10 MHz 2 5 to 5 5 EEPROM M95040 W 4 096 5 MHz 2 5 to 5 5 EEPROM M95020 W 2 048 5 MHz 2 5 to 5 5 II Device Handbook October 2008 Altera Corporation Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory 10 11 Conclusion Table 10 12 STMicroelectronics Device Characteristics Part 2 of 2 Interface Operating Size Voltage V Type Device Bits SCI SPI 2 Wire 3 Wire Microwire fmax 1 EEPROM M95080 R 8 192 10 MHz 1 8 to 5 5 EEPROM 95040 5 4 096 5 MHz 1 8 to 3 6 EEPROM M95020 S 2 048 X 5 1 8 to 3 6 Note to Table 10 12 1 The MAX II device supports two different Vcr of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device supports the 1 71 to 1 89 V operating voltage range Table 10 13 Toshiba
142. 1 erase is selected memory size 2 You can specify another byte location as the trigger erase addresses for each sector This sector erase operation supports up to eight UFM blocks or serial EEPROMs on the PC bus This sector erase operation requires acknowledge polling Sector Erase Triggered This sector erase operation uses the received slave address bit to distinguish between erase or read write operation This slave operation decoding occurs when the master transmits the slave address after generating the start condition If the A bit received by the UFM slave is 1 the sector erase operation is selected If the A bit received is 0 the read write operation is selected While this reserves the A bit as an erase or read write operation bit the A and A bits still act as slave address bits to address the UFM With this erase option there can be up to four UFM slaves cascaded on the bus for 1 Kbit and 2 Kbit memory sizes Only two UFM slaves can be cascaded on the bus for 4 Kbit memory size since A of the slave address becomes the ninth bit MSB of the byte address After the slave acknowledges the slave address and its erase or read write operation bit the master can transfer any byte address within the sector that must be erased The internal UFM sector erase operation only begins after the master generates a stop condition Figure 9 17 shows the sector erase sequence using the A bit of the slave address Figure 9 1
143. 1 through Table 1 5 Updated document with MAX IIZ information versiont 7 m Added Referenced Documents section December 2006 m Added document revision history version 1 6 August 2006 m Minor update to features list version 1 5 July 2006 m Minor updates to tables version 1 4 II Device Handbook August 2009 Altera Corporation Chapter 1 Introduction Document Revision History Table 1 6 Document Revision History Date and Revision Changes Made Summary of Changes June 2005 m Updated timing numbers in Table 1 1 version 1 3 December 2004 m Updated timing numbers in Table 1 1 version 1 2 June 2004 m Updated timing numbers in Table 1 1 version 1 1 August 2009 Altera Corporation MAX II Device Handbook 1 6 Chapter 1 Introduction Document Revision History MAX II Device Handbook August 2009 Altera Corporation 2 MAX Il Architecture RYA Introduction This chapter describes the architecture of the MAX II device and contains the following sections Functional Description on page 2 1 Logic Array Blocks on page 2 4 Logic Elements on page 2 6 MultiTrack Interconnect on page 2 12 Global Signals on page 2 16 User Flash Memory Block on page 2 18 m MultiVolt Core on page 2 22 T O Structure on page 2 23 Functional Description MAX II devices contain a two
144. 192 Maximum User 1 0 pins 80 160 212 272 80 160 teo ns 1 4 7 5 4 6 2 7 0 7 5 9 0 four MHz 2 304 304 304 304 152 152 tsu ns 1 7 1 2 12 1 2 2 3 2 2 tco ns 4 3 4 5 4 6 4 6 6 5 6 7 Notes to Table 1 1 1 teo represents a pin to pin delay for the worst case 1 0 placement with a full diagonal path across the device and combinational logic implemented in a single LUT and LAB that is adjacent to the output pin 2 The maximum frequency is limited by the 1 0 standard onthe clock input pin The 16 bit counter critical delay will run faster than this number La For more information about equivalent macrocells refer to the MAX II Logic Element to Macrocell Conversion Methodology white paper MAX MAX IIG devices are available in three speed grades 3 4 and 5 with 3 being the fastest Similarly MAX IIZ devices are available in three speed grades 6 7 and 8 with 6 being the fastest These speed grades represent the overall relative performance not any specific timing parameter For propagation delay timing numbers within each speed grade and density refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook Table 1 2 shows MAX II device speed grade offerings Table 1 2 MAX II Speed Grades Speed Grade Device 3 4 5 6 7 8 240 v v EPM240G EPM570 v v EPM570G EPM1270 v
145. 2 048 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM S 29394A 4 096 va 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM 5 29294 2 048 v 2 0 MHz Read 1 8 6 5 Write 2 5 6 5 EEPROM 29355A 4 096 v 2 0 MHz Read 1 8V 6 5V Write 2 7 V 6 5 V EEPROM 5 29255 2 048 V4 2 0 MHz Read 1 8 6 5 Write 2 7 6 5 EEPROM S 29L330A 4 096 V4 2 0 MHz 1 8 to 5 5 EEPROM 29L220A 2 048 V4 2 0 MHz 1 8 to 5 5 EEPROM 29L331A 4 096 v 2 0 MHz 1 8 to 5 5 EEPROM 29L221A 2 048 v 2 0 MHz 1 8 to 5 5 EEPROM S 29L394A 4 096 v 2 0 MHz 1 8 to 5 5 EEPROM 5 291294 2 048 v 2 0 MHz 1 8 to 5 5 EEPROM 29U330A 4 096 v 500 kHz Read 0 9 3 6 Write 1 8 3 6 EEPROM S 29U220A 2 048 v 500 kHz Read 0 9 3 6 Write 1 8 3 6 EEPROM S 29U331A 4 096 v 500 kHz Read 0 9 3 6 Write 1 8 3 6 EEPROM S 29U221A 2 048 V4 500 kHz Read 0 9 3 6 Write 1 8 3 6 EEPROM 29U394A 4 096 V4 500 kHz Read 0 9 3 6 Write 1 8 3 6 EEPROM 29U294A 2 048 v 500 kHz Read 0 9 3 6 Write 1 8 3 6 EEPROM 5 297330 4 096 v
146. 3 MAX II Device Compatibility with 5 0 V CMOS Devices 5 0V 0 5V 33V UC Vccio Vccio Y Vccio 1 ZN Rexr Open Drain Model as R INT 4 4 5 0 CMOS Device VSS Note to Figure 8 3 1 This diode is only active after power up MAX II devices require an external diode if driven by 5 0 V before power up The open drain pin never drives high only low or tri state When the open drain pin is active it drives low When the open drain pin is inactive the pin is tri stated and the trace pulls up to 5 0 V by the external resistor The purpose of enabling the I O clamp diode is to protect the MAX II device s I O pins The 3 3 V V cco supplied to the I O clamp diodes causes the voltage at point A to clamp at 4 0 V which meets the MAX II device s reliability limits when the trace voltage exceeds 4 0 V The device operates successfully because a 5 0 V input is within its input specification 57 TheI O clamp diode is only supported in the 1270 and 2210 devices I O Bank 3 An external protection diode is needed for other I O banks EPM1270 and 2210 devices and all I O pins in EPM240 and 570 devices The pull up resistor value should be small enough for sufficient signal rise time but large enough so that it does not violate the Io output low specification of MAX devices The maximum MAX II device Io depends on the programmable drive strength of the I
147. 5 MAX II Devices and Speed Grades that Support 3 3 V PCI Electrical Specifications and Meet PCI Timing Device 33 MHz PCI 66 MHz PCI EPM1270 All Speed Grades 3 Speed Grade EPM2210 All Speed Grades 3 Speed Grade The input buffer for each MAX II device I O pin has an optional Schmitt trigger setting for the 3 3 V and 2 5 V standards The Schmitt trigger allows input buffers to respond to slow input edge rates with a fast output edge rate Most importantly Schmitt triggers provide hysteresis on the input buffer preventing slow rising noisy input signals from ringing or oscillating on the input signal driven into the logic array This provides system noise tolerance on MAX II inputs but adds a small nominal input delay The JTAG input pins TMS and TDI have Schmitt trigger buffers that are always enabled The TCK input is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all I O standards Output Enable Signals Each MAX II IOE output buffer supports output enable signals for tri state control The output enable signal can originate from the GCLK 3 0 global signals or from the MultiTrack interconnect The MultiTrack interconnect routes output enable signals and allows for a unique output enable for each output or bidirectional pin MAX II devices also provide a chip wide output enable DEV OE to control the output enable for every output pin in the design
148. 5 13 m Updated Table 5 13 through Table 5 24 and Table 5 27 through Table 5 30 m Added tCOMB information to Table 5 15 m Updated Figure 5 6 m Added Referenced Documents section December 2006 m Added note to Table 5 1 version 1 8 m Added document revision history July 2006 m Minor content and table updates version 1 7 February 2006 m Updated External Timing 1 0 Delay Adders section version 1 6 Updated Table 5 29 m Updated Table 5 30 November 2005 m Updated Tables 5 2 5 4 and 5 12 version 1 5 August 2005 m Updated Figure 5 1 version 1 4 Updated Tables 5 13 5 16 and 5 26 Removed Note 1 from Table 5 12 August 2009 Altera Corporation MAX II Device Handbook 5 28 Chapter 5 DC and Switching Characteristics Table 5 35 Document Revision History Part 2 of 2 Document Revision History Date and Revision Changes Made Summary of Changes June 2005 m Updated the Ru parameter in Table 5 4 version 1 3 Added Note 2 to Tables 5 8 and 5 9 m Updated Table 5 13 m Added Output Drive Characteristics section m Added 126 mode and Notes 5 and 6 to Table 5 14 m Updated timing values to Tables 5 14 through 5 33 December 2004 m Updated timing Tables 5 2 5 4 5 12 and Tables 15 14 through 5 34 version 1 2 m Table 5 31 is new June 2004 m Updated timing Tables 5 15 through 5 32 version 1 1 II Device Handbook
149. 5 describes the I O bank parameters in the I O section of the PowerPlay Early Power Estimator spreadsheet Table 17 5 1 0 Bank Information Column Heading Description Vecio Select the Veco voltage for each bank Used to cross check selected 1 0 standards in 1 0 section for warning purposes Shows the total supply current due to the 1 0 pins in each 1 0 bank Unassigned Represents the leco of all 1 0 modules not assigned to an 1 0 bank Each row in the I O section represents a design module where the I O pins have the same frequency toggle percentage average capacitive load I O standard and I O bank Figure 17 11 shows the I O section of the PowerPlay Early Power Estimator spreadsheet and Table 17 6 describes the I O module parameters October 2008 Altera Corporation MAX II Device Handbook 17 10 Figure 17 11 1 0 Section Chapter 17 Understanding and Evaluating Power in MAX II Devices PowerPlay Early Power Estimator Inputs Module VO Standard Power mW Supply Current mA Clock VO Toggle Bank Bank Freq Output Input Bidir Bank VO Std Voltage Routing Block Total lecint lecio User Comments MHz Pins Pins Pins Check Check Table 17 6 1 0 Section Information Part 1 of 2 Column Heading Description Module Enter a name for the module in this column optional entry 0 Standar
150. 541 545 ps delay LE register setup 208 271 333 260 319 321 ps time before clock t LE register hold 0 0 0 0 0 0 ps time after clock tco LE register clock 235 305 376 380 489 49 ps to output delay tcun Minimum clock 166 216 266 253 335 339 ps high or low time te Register control 857 11 114 1 372 1 356 1 722 1 741 ps delay August 2009 Altera Corporation MAX II Device Handbook 5 12 Table 5 16 IOE Internal Timing Microparameters Chapter 5 DC and Switching Characteristics Timing Model and Specifications MAX II MAX IIG 112 3 Speed 4 Speed 5 Speed 6 Speed 1 Speed 8 Speed Grade Grade Grade Grade Grade Grade Symbol Parameter Min Max Min Max Min Max Min Max Min Max Min Max Unit Data output delay 159 207 254 170 348 428 from adjacent LE to 1 0 block 0 input pad and 708 920 11132 907 970 986 ps buffer delay teros 7 1 0 input pad and 1 19 1 974 2 430 2 61 2 670 3 322 ps buffer delay used as global signal pin toe Internally 354 374
151. 7 Sector Erase Sequence Indicated Using the Bit of the Slave Address EIN uw A ByteAddress S Start Condition 0 write 1 From Master to Slave P Stop Condition A Acknowledge From Slave to Master Note to Figure 9 17 1 0 indicates a read write operation is executed in place of an erase In this case the RAW bit determines whether it is a read or write operation October 2008 Altera Corporation MAX II Device Handbook 9 20 II Device Handbook Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block If the altufm_i2c megafunction is write protected WP 1 the slave does not acknowledge the byte address which indicates the UFM sector to be erased sent in by the master The master should then send a stop condition to terminate the transfer and the sector erase operation will not be executed No Erase The no erase operation never erases the UFM contents This method is recommended when UFM does not require constant re writing after its initial write of data For example if the UFM data is to be initialized with data during manufacturing using EC you may not require writing to the UFM again In that case you should use the no erase option and save logic element LE resources from being used to create erase logic Read Operation The read operation is initiated in the same manner as the write operation except that
152. AMPLE PRELOAD mode October 2008 Altera Corporation MAX II Device Handbook 13 10 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Devices IEEE Std 1149 1 BST Operation Control Figure 13 8 IEEE Std 1149 1 BST SAMPLE PRELOAD Mode INJ OEJ 500 OUT N Capture Update Registers Registers SHIFT CLOCK X UPDATE HIGHZ MODE ms Capture Phase SDO PIN OUT Buffer SHIFT CLOCK X UPDATE HIGHZ MODE sms Capture Update SDI Registers Registers Shift and Update Phase II Device Handbook October 2008 Altera Corporation Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Il Devices 13 11 IEEE Std 1149 1 BST Operation Control During the capture phase multiplexers preceding the capture registers select the active device data signals this data is then clocked into the capture registers The multiplexers at the outputs of the update registers also select active device data to prevent functional interruptions to the device During the shift phase the boundary scan shift register is formed by clocking data through capture registers around the device periphery and then out of the TDO pin New test data can simultaneously be shifted int
153. AP pins or connections For small flash devices it is common to use the serial JTAG scan chain of a connected device to program the non JTAG flash device This is slow and inefficient in most cases and impractical for large parallel flash devices Using the MAX II device s JTAG block as a parallel flash loader with the Quartus II software to program and verify flash contents provides a fast and cost effective means of in circuit programming during test Figure 3 1 shows MAX II being used as a parallel flash loader MAX II Device Handbook 3 4 Chapter 3 JTAG and In System Programmability In System Programmability Figure 3 1 MAX II Parallel Flash Loader MAX II Device Flash Memory Device Altera FPGA DQ 7 0 DQ 7 0 CONF_DONE A 20 0 4 A 20 0 amp P nSTATUS OE 4 OE nCE WE 4 WE 4 RY BY gt RY BY gt DATAO TDO U p nCONFIG TDI TO U DEA 4 p DCLK Flash Loader TMS 5 Configuration TCK gt TCK U LF Logic SHIFT U 3 m CLKDR U gt 1 9 UPDATE U RUNIDLE U USER1U Notes to Figure 3 1 1 This block is implemented in LEs 2 This function is supported in the Quartus II software In System Programmability II Device Handbook MAX II devices can be programmed in system via the industry
154. AX II Device Handbook 1 12 144 Pin Micro FineLine Ball Grid Array MBGA Wire Bond dimensions and tolerances conform to ASME Y14 5M 1994 Controlling dimension is in millimeters Chapter 7 Package Information Package Outlines Pin A1 may be indicated by an ID dot or a special feature in its proximity on package surface Package Information Package Outline Dimension Table Description Specification Millimeters Symbol Ordering Code Reference M Min Nom Max Package Acronym MBGA A 120 Substrate Material BT A1 0 15 Solder Ball Composition Pb free n 3Ag 0 5Cu Typ A2 1 00 II Device Handbook J EDEC Outline Reference MO 195 Variation AD A3 0 60 REF Maximum Lead D 7 00 BSC Coplanarity 0 003 inches 0 08 mm Weight 010 7 00 5 Moisture Sensitivity Level us on moisture barrier b 0 25 0 30 0 35 e 0 50 BSC October 2008 Altera Corporation Chapter 7 Package Information 1 13 Package Outlines Figure 7 6 144 Pin Micro FineLine BGA Package Outline TOP VIEW BOTTOM VIEW D Pin A1 amp amp ASIE A 1 Q OO Gu qe A 000000000000 B i D O OQ QO m OQ OOO 6 1
155. AX II Device Performance Performance Resources Used MAX II MAX IIG MAX 112 8 4 5 6 7 8 Resource Design Size and UFM Speed Speed Speed Speed Speed Speed Used Function Mode LEs Blocks Grade Grade Grade Grade Grade Grade Unit LE 16 bit counter 1 16 0 304 0 247 5 201 1 184 1 123 5 MHz 64 bit counter 1 64 0 201 5 154 8 125 8 832 83 2 MHz 16 to 1 multiplexer 11 0 6 0 8 0 9 3 17 4 17 3 ns 32 to 1 multiplexer 24 0 9 0 11 4 12 5 228 ns 16 bit XOR function 5 0 5 1 6 6 8 2 9 0 15 0 ns 16 bit decoder with 5 0 5 2 6 6 8 2 9 2 15 0 ns single address line UFM 512 x 16 None 3 1 10 0 10 0 10 0 10 0 10 0 10 0 MHz 512 x 16 SPI 2 37 1 8 0 8 0 8 0 9 7 9 7 07 MHz 512 x8 Parallel 73 1 4 4 4 4 4 4 MHz 3 512 x 16 PC 3 142 1 100 100 100 100 100 100 kHz 5 5 5 5 5 5 Notes to Table 5 14 3 5 MAX II Device Handbook 1 This design is a binary loadable up counter 2 This design is configured for read only operation in Extended mode Read and write ability increases the number of LEs used This design is configured for read only operation Read and write ability increases the number of LEs used 4 This design is asynchronous The 126 megafunction is verified in hardware up to 100 kHz serial clock line SCL rate August 2009 Altera Corporati
156. BGA and 256 pin Micro FineLine BGA packages Except for external supply voltage requirements MAX II and MAX II G devices have identical pin outs and timing specifications Table 1 5 shows the external supply voltages supported by the MAX II family Table 1 5 MAX II External Supply Voltages Devices MultiVolt core external supply voltage 2 240 EPM570 EPM1270 2210 3 3 V 2 5 V 2406 5706 EPM12706 EPM22106 2402 5702 1 1 8V MultiVolt 1 0 interface voltage levels Vecio 1 5 V 1 8 V 2 5 V 3 3 V 1 5 V 1 8 V 2 5 V 3 3 V Notes to Table 1 5 1 IIG and MAX IIZ devices only accept 1 8 V on their vCCINT pins The 1 8 V Vecinr external supply powers the device core directly 2 MAX II devices operate internally at 1 8 V Referenced Documents This chapter references the following documents m DC and Switching Characteristics chapter in the MAX II Device Handbook m MAXII Logic Element to Macrocell Conversion Methodology white paper Document Revision History Table 1 6 shows the revision history for this chapter Table 1 6 Document Revision History Date and Revision Summary of Changes August 2009 m Updated Table 1 2 Added information for speed grade 8 version 1 9 October 2008 m Updated Introduction section version 1 8 m Updated new Document Format December 2007 m Updated Table 1
157. Byte Code Data Size Kbytes Device Compressed Uncompressed 7 EPM240 12 4 2 12 4 2 EPM570 114 19 6 EPM1270 16 9 31 9 EPM2210 24 7 49 3 Notes to Table 14 3 1 For more information about how to generate JBC files with uncompressed programming data contact Altera Applications 2 There is a minimum limit of 64K bits for compressed arrays with the JBC compiler Programming data arrays smaller than 64K bits 8K bytes are not compressed The EPM240 programming data array is below the limit which means the JBC files are always uncompressed The reason for this limit is that a memory buffer is needed for decompression and for small embedded systems it is more efficient to use small uncompressed arrays directly rather than to uncompress the arrays After estimating the JBC file size estimate the Jam Player size using the information in Table 14 4 Table 14 4 Jam STAPL Byte Code Player Binary Sizes Build Description Size Kbytes 16 bit Pentium 486 using the MasterBlaster or ByteBlaster MV download 80 cables 32 bit Pentium 486 using the MasterBlaster or ByteBlaster MV download 85 cables Estimating Dynamic Memory Usage Use the following equation to estimate the maximum amount of DRAM required by the Jam Player Equation 14 3 N RAM Size JBC File Size Data Uncompressed Data Size k k 1 The JBC file size is determined by a single or multi device equation see Estimating ROM U
158. CMOS Specifications Part 1 of 2 Symbol Parameter Conditions Minimum Maximum Unit Vecio 1 0 supply voltage 3 0 3 6 V High level input voltage 1 7 4 0 V Vi Low level input voltage 0 5 0 8 V August 2009 Altera Corporation MAX II Device Handbook 5 6 Table 5 6 3 3 V LVCMOS Specifications Part 2 of 2 Chapter 5 DC and Switching Characteristics Operating Conditions Symbol Parameter Conditions Minimum Maximum Unit Vou High level output voltage Vecio 3 0 Vecio 0 2 0 1 mA 1 Vo Low level output voltage Vecio 3 0 0 2 V IOL 0 1 mA 1 Table 5 7 2 5 V 1 0 Specifications Symbol Parameter Conditions Minimum Maximum Unit Vecio 1 0 supply voltage High level input voltage V Vu Low level input voltage 0 5 0 7 V Von High level output voltage 10H 0 1 mA 1 2 1 1 mA 7 2 0 V 2 2 mA 1 1 7 V Vor Low level output voltage IOL 0 1 mA 1 0 2 V IOL 1 mA 1 0 4 V IOL 2 mA 1 0 7 V Table 5 8 1 8 V 1 0 Specifications Symhol Parameter Conditions Minimum Maximum Unit Vecio 1 0 supply voltage 1 71 1 89 V High level input voltage 0 65 Vecio 2 25 2 V Vu Low level input voltage 0 3 0 35 x Vecio V Von High level output voltage 2 mA 1 Vecio 0 45 V Vo Low level outp
159. Corporation Device Characteristics Interface Size Operating Type Device Bits SCI 4 Wire 2 Wire 3 Wire PC Microwire fmax Voltage V 1 EEPROM TCOWMA2FK 2 048 V4 1 MHZ Read 1 8 5 5 Write 2 3 5 5 EEPROM TCOWMB2FK 2 048 400 kHz Read 1 8 5 5 Write 2 3 5 5 Note to Table 10 13 1 The MAX II device supports two different Vccwr of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device supports the 1 71 to 1 89 V operating voltage range Conclusion MAX II devices can be used to incorporate logic and memory devices on a design board eliminating chip to chip delays minimizing board space and reducing total system cost Since you can program the UFM block to suit your needs MAX II devices offer more interface flexibility than an off the shelf EEPROM device Referenced Documents This chapter references the following documents m DC and Switching Characteristics chapter in the MAX II Device Handbook m Using User Flash Memory in MAX II Devices chapter in the MAX II Device Handbook October 2008 Altera Corporation MAX II Device Handbook 10 12 Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory Document Revision History Table 10 14 shows the revision history for this chapter Table 10 14 Document Revision History Document Revision History Da
160. Devices 9 21 Software Support for UFM Block Figure 9 19 Random Address Read Sequence Slave Byte Slave MES 5 Address R W A Address Sr Address R W A Data P 0 write T read 5 Start Condition From Master to Slave Sr Repeated Start P Stop Condition From Slave to Master A Acknowledge Sequential Read Sequential read operation can be initiated by either the current address read operation or the random address read operation Instead of sending a stop condition after the Slave has transmitted one byte of data to the master the master acknowledges that byte and sends additional clock pulses on SCL line for the slave to transmit data bytes from consecutive byte addresses The operation is terminated when the master generates a stop condition instead of responding with an acknowledge Figure 9 20 shows the sequential read sequence Figure 9 20 Sequential Read Sequence Slave Byte Slave TEA 5 Address R W A Address Sr address RW A Data A Data P 0 write T read Data n bytes Acknowledgment n 1 bytes S Start Condition From Master to Slave Sr Repeated Start P Stop Condition From Slave to Master A Acknowledge October 2008 Altera Corporation MAX II Device Handbook 9 22 ALTUFM FC Interface Timing Specification Figure 9 21 shows the timing wa
161. EPROM CAT25C03 v 10 MHz 1 810 6 0 EEPROM CAT25C04 10 MHz 1 8 to 6 0 EEPROM 25005 10 MHz 1 8 to 6 0 EEPROM CAT25C08 8 192 10 MHz 1 810 6 0 EEPROM CAT25C09 8 192 v 10 MHz 1 8 to 6 0 EEPROM CAT25020 2048 10 MHz 1 8 to 6 0 EEPROM CAT25040 4 096 10 MHz 1 810 6 0 Note to Table 10 4 1 The MAX II device supports two different supports the 1 71 to 1 89 V operating vo Table 10 5 Dallas Semiconductor Maxim Integrated Products Inc Device Characteristics Vecinr Of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device tage range Type Device Size Bits Interface SCI 1 Wire 2 Wire 3 Wire 126 Microwire fmax MHz Operating Voltage V 1 EEPRO M 052433 4 096 2 8 to 6 0 Note to Table 10 5 1 The MAX II device supports two different Vcemr of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device supports the 1 71 to 1 89 V operating voltage range Table 10 6 Fairchild Semiconductor Device Characteristics Part 1 of 2 Interface Operating Size Voltage V Type Device Bits SCI SPI 2 Wire 3 Wire 126 Microwire fmax 1 EEPROM FM34W02UL 2 048 v 400 kHz 2 7 t0 5 5 E
162. EPROM FM93C56L 2 048 1 MHz 2 7 t0 5 5 EEPROM FM93666L 4 096 v 1MHz 2 7 t0 5 5 EEPROM FM93CS56L 2 048 v 1MHz 2 7 t0 5 5 EEPROM FM93CS66L 4 096 1MHz 2 7 to 5 5 EEPROM FM24CO8UL 8 192 400 kHz 2 7 to 5 5 EEPROM FM24CO9UL 8 192 v 400 kHz 2 7 to 5 5 II Device Handbook October 2008 Altera Corporation Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory 10 5 List of Vendors and Devices Table 10 6 Fairchild Semiconductor Device Characteristics Part 2 of 2 Interface Operating Size Voltage V Type Device Bits SCI SPI 2 Wire 3 Wire C Microwire fmax 1 EEPROM NM24C02L 2 048 v 400 kHz 2 7 to 5 5 EEPROM NM25C020L 2 048 V4 2 1 MHz 2 7 to 5 5 EEPROM NM25C040L 4 096 v 2 1 MHz 2 7 to 5 5 Note to Table 10 6 1 The MAX II device supports two different of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the IIG device supports the 1 71 to 1 89 V operating voltage range Tahle 10 7 Holtek Semiconductor Inc Device Characteristics Interface Clock Rate Operating Size MHz Voltage Type Device Bits SCI 1 Wire 2 Wire 3 Wire PC Microwire V 5 0
163. EX file contents should be set to all 1 for addresses 040h to 1BFh Lower Half Addresses 00h to 3Fh 03Fh Address 00h in logical memory maps to address 000h in the MIF HEX file Address 3Fh in logical memory maps to 03Fh in the MIF HEX file and all data in between follows the order in the logical memory II Device Handbook Memory Map for 2 Khit Memory Initialization Figure 9 50 shows the memory map initialization for the altufm i2c megafunction of 2 Kbits of memory The altufm i2c megafunction byte address location of 00h to 7Fh is mapped to the UFM block address location of 000h to 07Fh The altufm i2c megafunction byte address location of 80h to FFh is mapped to the UFM block address location of 180h to 1FFh Altera recommends that you pad the unused address location of the UFM block with all ones October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 45 Creating Memory Content File Figure 9 50 Memory Map for 2 Kbit Memory Initialization MIF or HEX File Contents to represent the actual data and address size for the UFM block 2 Kbit altufm i2c Megafunction Logical Memory Contents Address 80h in logical memory maps to address 180h in the MIF HEX file FFh in logical memory maps to 1FFh in the MIF HEX file and all data in between follows the order in the logical memory Upper Half Addresses 80h to FFh This section of the UFM is unused the MIF HEX file conten
164. F 2 none I960 00000000 lt gt 3 Quartusland 4land 4 pof EPM7128AEF100 001 1710 FFFFFFFF t oO L 4 CLAMPlDesigniltop pof EPM7512BB256 0089CC87 FFFFFFFF oO Figure 14 4 Generating a JBC File for a Multi Device JTAG Chain in the Quartus Software File name uartus Design configuration jbc File format peration Programming options Program Blank check Verity Verify Clock frequency 1x frequency ji 0 0 MHz Supply voltage fi 8 volts 71 Lok The following steps explain how to generate JBC files using the Quartus II software 1 On the Tools menu click Programmer 2 Click Add File and select programming files for the respective devices On the File menu point to Create Update and click Create JAM S VF or ISC File See Figure 14 4 4 Specify a Jam STAPL Byte Code File in the File format list 5 Click OK MAX II Device Handbook October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor 14 7 Software Development You can include both Altera and non Altera JTAG compliant devices in the JTAG chain If you do not specify a programming file in the Programming File Names field devices in the JTAG chain will be bypassed Using Jam Files with the MAX II User Flash Memory Block The Quartus II Programmer provides the option to individually target the entire
165. GA and Micro FineLine BGA Packages Part 2 of 2 Device Package Pin 570 FBGA 1 100 EPM570G 570 MBGA 1 100 EPM570G EPM570Z 570 TQFP 100 EPM570G EPM570Z MBGA 1 144 EPM570 TQFP 144 EPM570G 570 FBGA 256 EPM570G 570 MBGA 7 256 EPM570G EPM570Z EPM1270 TQFP 144 EPM1270G FBGA 256 MBGA 7 256 EPM2210 FBGA 256 EPM2210G FBGA 324 Note to Table 7 1 1 Packages available in lead free versions only Thermal Resistance Table 7 2 Thermal Resistance of MAX II Devices Part 1 of 2 Table 7 2 provides junction to ambient thermal resistance and 8 junction to case thermal resistance values for Altera MAX II devices Ou C W On On C W Ou 00M Device Pin Count Package C W Still Air 100 ft min 200 ft min 400 ft min EPM240Z 68 MBGA 35 5 68 7 63 0 60 9 59 2 EPM240 100 FBGA 20 8 51 2 45 2 43 2 41 5 EPM240G EPM240 100 MBGA 32 1 53 8 47 1 45 7 44 0 EPM240G EPM240Z EPM240 100 TQFP 12 0 39 5 37 5 35 5 31 6 EPM240G EPM570 100 FBGA 14 8 42 8 36 8 34 9 33 3 EPM570G II Device Handbook October 2008 Altera Corporation Chapter 7 Package Information Package Outlines Table 7 2 Thermal Resistance of MAX II Devices Part 2 of 2 Oy C W Oy C W On C W Device Pin Count P
166. I Device Handbook 14 18 Conclusion Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Conclusion The following shows example code for the Jam Player switch USERCODE case 0001 Rev 1 is old update to new Rev result jbi execute rev3 file file size 3 0 0 PROGRAM 0 error line exit code case 0002 Rev 2 is old update to new Rev result jbi excecute rev3 file file size 3 0 0 PROGRAM 0 error line exit code case 0003 Do nothing this is the current Rev default Issue warning and update to current Rev Warning unexpected design revision Program device with newest rev anyway result jbi execute rev3 file file size 3 0 0 PROGRAM 0 error line exit code A switch statement can be used to determine which device needs to be updated and which design revision should be used With Jam STAPL Byte Code software support PLD updates become as easy as adding a few lines of code Using Jam STAPL provides an simple way to benefit from ISP Jam meets all of the necessary embedded system requirements such as small file sizes ease of use and platform independence In field upgrades are simplified by confining updates to the Jam STAPL Byte Code file Executing the Jam Player is straightforward as is the calculation of resources that will be used For the most recent updates and information visit the Jam website at ww w altera com jamisp Reference
167. I devices in all packages to interface with systems of different supply voltages The devices have one set of VCC pins for internal operation and up to four sets for input buffers and I O output driver buffers V cco depending on the number of I O banks available in the devices where each set of VCC pins powers one I O bank The EPM240 and EPM570 devices have two I O banks respectively while the 1270 EPM2210 devices have four I O banks respectively October 2008 Altera Corporation MAX II Device Handbook 2 32 Table 2 7 MAX II MultiVolt 1 0 Support Note 1 Chapter 2 MAX II Architecture Referenced Documents Connect VCCIO pins to either a 1 5 V 1 8 V 2 5 V or 3 3 V power supply depending on the output requirements The output levels are compatible with systems of the same voltage as the power supply that is when VCCIO pins are connected to a 1 5 V power supply the output levels are compatible with 1 5 V systems When VCCIO pins are connected to a 3 3 V power supply the output high is 3 3 V and is compatible with 3 3 V or 5 0 V systems Table 2 7 summarizes MAX II MultiVolt I O support Input Signal Output Signal VCCIO V 1 5V 1 8V 2 5V 3 V 5 0 V 1 5V 1 8 V 2 5 V 3 3 V 5 0 V 1 5 v v v 1 8 v 2 25 v 3 3 s 4 v v 5 v 6 v 6 v 6 v 7 Notes to Ta
168. IIZ devices vCCINT pins will only accept a 1 8 V power supply 2 For MAXII devices VCCINT pins will only accept a 2 5 V or 3 3 V power supply 3 MAX Il devices can drive a 5 0 V TTL input when Vecio 3 3 V To drive a 5 0 V CMOS an open drain setting with internal 1 0 clamp diode and external resistor are required 4 MAX II devices can be 5 0 V tolerant with the use of an external resistor and the internal 1 0 clamp diode on EPM1270 and EPM2210 devices 5 0 V Device Compatibility A MAX II device can drive a 5 0 V TTL device by connecting the V pins of the MAX II device to 3 3 V This is possible because the output high voltage of a 3 3 V interface meets the minimum high level voltage of 2 4 V of a 5 0 V TTL device A MAX II device may not correctly interoperate with a 5 0 V CMOS device if the output of the MAX II device is connected directly to the input of the 5 0 V CMOS device If the MAX II device s Vov is greater than Vecto the PMOS pull up transistor still conducts if the pin is driving high preventing an external pull up resistor from pulling the signal to 5 0 V To make MAX II device outputs compatible with 5 0 V CMOS devices configure the output pins as open drain pins with the I O clamp diode enabled and use an external pull up resistor See Figure 8 3 October 2008 Altera Corporation MAX II Device Handbook 8 4 Chapter 8 Using MAX II Devices in Multi Voltage Systems 5 0 V Device Compatibility Figure 8
169. ISP Figure 12 2 Real Time ISP Operation Programming Data gt JTAG gt CFM J TAG CFM Power ra Cycle SRAM SRAM Logic Array Logic Array Programming of CFM CFM Contents Download Device Remains Operational Device 1 05 Tri Stated For the tconric value for a specific MAX II device refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook Real Time ISP with the Quartus Software II Device Handbook The programming file formats generated by the Quartus II software that support these two features are the Programmer Object File pof that is used with the Quartus programmer and the Jam File Jam Byte Code File jbc that are used with either the Quartus II programmer or other programming tools Ensure that you enable this feature before programming a MAX II device through the Quartus II programmer You can enable the real time ISP feature by selecting the Enable real time ISP to allow background programming for MAX II devices option from the Quartus II programmer window See Figure 12 3 October 2008 Altera Corporation Chapter 12 Real Time ISP and ISP Clamp for MAX Il Devices 12 3 Real Time ISP Figure 12 3 Real Time ISP Option in the Quartus Programmer Window E Chaint cdf Hardware Setup ByteBlaster ILPTI Mode JTAG v Progress 0 E
170. Instruction Mode 2 2 13 13 IDCODE Instruction Mode 21 24 2 13 14 USERCODE Instruction Mode 1 13 14 CLAMP Instruction 1 2 4 4 2 13 14 HIGHZ Instruction Mode 1 22 13 14 I O Voltage Support in Chain 13 15 BST for Programmed Devices 545555255 a ge ex RESET E ERE E V a 13 15 Disabling IEEE Std 1149 1 BST Circuitry 2 2 2 2 13 16 Guidelines for IEEE Std 1149 1 Boundary Scan Testing 13 16 Boundary Scan Description Language BSDL Support 13 17 Conclusion RENDERE ORS RR RE aes ds 13 17 Referenced Documents ss bes e a E ex eESeREUDUCRES ia had eee anes 13 17 Document Revision History 2 13 18 Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Introduction 4o edite A redet at baee iate eu idein 14 1 Embedded Systems Rate Eee eee epe 14 1 Connectin
171. K Inputs Inputs 1 0 Blocks I 1I A UFM Block CFM Block Note to Figure 2 2 1 The device shown is an EPM570 device EPM1270 and EPM2210 devices have a similar floorplan with more LABs For EPM240 devices the CFM and UFM blocks are located on the left side of the device October 2008 Altera Corporation MAX II Device Handbook 2 4 Chapter 2 MAX II Architecture Logic Array Blocks Logic Array Blocks Each LAB consists of 10 LEs LE carry chains LAB control signals a local interconnect alook up table LUT chain and register chain connection lines There are 26 possible unique inputs into an LAB with an additional 10 local feedback input lines fed by LE outputs in the same LAB The local interconnect transfers signals between LEs in the same LAB LUT chain connections transfer the output of one LE s LUT to the adjacent LE for fast sequential LUT connections within the same LAB Register chain connections transfer the output of one LE s register to the adjacent LE s register within an LAB The Quartus II software places associated logic within an LAB or adjacent LABs allowing the use of local LUT chain and register chain connections for performance and area efficiency Figure 2 3 shows the MAX II LAB Figure 2 3 MAX II LAB Structure Row Interconnect Column In
172. Output buffer disable delay The delay required for high impedance to appear at the output pin after the output buffer s enable control is disabled Refer to Timing Model and Specifications section in the DC and Switching Characteristics chapter the MAX II Device Handbook for delay adders associated with different 1 0 standards drive strengths and slew rates tx Output buffer enable delay required for the output signal to appear at the output pin after the tri state buffer s enable control is enabled Refer to Timing Model and Specifications section in the DC and Switching Characteristics chapter the MAX Device Handbook for delay adders associated with different 0 standards drive strengths and slew rates m Delay for a column interconnect with average loading The ts covers a distance of four LAB rows tra Delay for a row interconnect with average loading The tr covers a distance of four LAB columns ioca Local interconnect delay Internal Timing Parameters for Il UFM Timing parameters for MAX user flash memory are the timing delays contributed by the UFM architectural elements which cannot be measured explicitly timing parameters are shown in italic type Table 16 3 defines the timing microparameters for MAX II UFM Table 16 3 Internal Timing Microparameters for MAX II UFM Part 1 of 2 Parameter Description lusu Address register shift si
173. PC Microwire fmax 1 EEPROM BR9020FV W 2 048 Y 2 MHz 2 7 to 5 5 EEPROM BR9040FV W 4096 2 MHz 2 7 105 5 EEPROM BR9080ARFVM W 8 192 2 MHz 2 7 to 5 5 EEPROM BR9020RFV W 2 048 2 MHz 2 7 105 5 EEPROM BR9040RFV W 4096 2 MHz 2 7 to 5 5 EEPROM BR9020RFVM W 2 048 2 MHz 2 7 to 5 5 EEPROM BR9040RFVM W 4096 Y 2 MHz 2 7 to 5 5 Note to Table 10 10 1 The MAX II device supports two different Vecint of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device supports the 1 71 to 1 89 V operating voltage range Table 10 11 Seiko Instruments Inc Device Characteristics Part 1 of 3 Interface Size Operating Voltage Type Device Bits SCI 1 Wire 2 Wire 3 Wire FC Microwire fmax 1 EEPROM S 93C66B 4 096 v 2 0 MHz Read 1 8 5 5 Write 2 7 5 5 EEPROM S 93C56B 2 048 v 2 0 MHz Read 2 0 5 5 Write 2 4 5 5 EEPROM S 93C76A 8 192 v 2 0 MHz Read 1 8 5 5 Write 2 7 5 5 EEPROM S 93C66A 4 096 V4 2 0 MHz 1 8 to 5 5 EEPROM 93C56A 2 048 v 2 0 MHz 1 8 to 5 5 EEPROM S 29430A 8 192 v
174. Quartus The tester also supports Jam or SVF files as it has a JBC compiler to compile these files for programming The Jam Byte Code Player is executed via the microcontroller on the Control XTP card and allows users to apply vectors algorithmically rather than executing a sequence of vectors The Jam Byte Code Player reads the programming and erase pulse width registers of the devices and uses those values in the programming and erase algorithms Programming Times Guidelines II Device Handbook Programming times on the Agilent 3070 are very consistent The only variable is the TCK frequency which affects programming times The faster the clock the less time is spent shifting data into the device The programming time is a function of the TCK clock rate MAX II devices support clock rates up to 18 MHz While using the Agilent 3070 tester for programming use the following guidelines m Usecaution if a pin library is used to describe the target device in a stand alone boundary scan chain Altera does not recommend describing all of the ISP device s I O pins as bidirectional This practice uses a large number of hybrid card channels and potentially causes a fixture overflow error when developing the test m Do notinclude PCF vectors in the test library Use a setup only node library Creating a test library with vectors creates a large library object file and results in a much slower test development time This delay
175. R24L02 W 2 048 v 400 kHz 1 8 to 5 5 EEPROM BR24L04 W 4096 400 kHz 1 8 to 5 5 EEPROM BR24L08 W 8 19 v 400 kHz 1 8 to 5 5 EEPROM BR24L02F W 2 048 400 kHz 1 8 to 5 5 EEPROM BR24LO4F W 4096 400 kHz 1 8 to 5 5 EEPROM BR24L08F W 8 19 m 400 kHz 1 8 to 5 5 EEPROM BR24L02FJ W 2 048 v 400 kHz 1 8 to 5 5 EEPROM BR24L04FJ W 4096 400 1 8 to 5 5 EEPROM BR24L08FJ W 8 19 400 kHz 1 8 to 5 5 EEPROM BR24L02FV W 2 048 v x 400 kHz 1 8 to 5 5 EEPROM BR24L04FV W 4096 400 kHz 1 8 to 5 5 EEPROM BR24L08FV W 8 19 m 400 kHz 1 8 to 5 5 EEPROM BR24LO2FVM W 2 048 400 kHz 1 8 to 5 5 EEPROM BR24LO4FVM W 4096 400 1 8 to 5 5 EEPROM BR24L08FVM W 8 19 400 kHz 1 8 to 5 5 EEPROM BR93L56 W 2 048 2 MHz 1 8 to 5 5 EEPROM BR93L66 W 4096 2 MHz 1 8 to 5 5 EEPROM BR93L56F W 2 048 2 MHz 1 8 to 5 5 EEPROM BR93L66F W 4096 2 MHz 1 8 to 5 5 EEPROM BR93L56RF W 2 048 2 MHz 1 8 to 5 5 EEPROM BR93L66RF W 4096 2 MHz 1 8 to 5 5 EEPROM BR93L56FJ W 2 048
176. Red ne gs 11 9 Random Signals onJTAG Pins 11 9 Software Issues ce I eee d eed P Hae Fo e E e ee E Idee eee e ederet 11 9 ISP via Embedded Proc ssors eere peer he ceci e nt aen es 11 9 Processor and Memory Requirements 11 9 Porting the Jam Player eer oem Y IER nian te 11 10 ISP via In Circuit Testers de ie ane nm eme dent Fir eed deg 11 10 August 2009 Altera Corporation MAX II Device Handbook CONClUSION pet appe ob oe tei doe RR o Rte 11 10 Referenced Documents 11 10 Document Revision History 11 11 Chapter 12 Real Time ISP and ISP Clamp for MAX II Devices Introduction ses HERR RR EE ER RR E ER EX EUR AR 12 1 Real Ime ISP weg gid SE RR M ER nC EE EE e n e de Ree PET EE PE EEG 12 1 How Real Time ISP Works 2 0 2 12 1 Real Time ISP with the Quartus Software 12 2 Real Time ISP with Jam and JBC Players 1 12 4 CAMP
177. Reset Circuitry When the I O pin receives a negative ESD zap at the pin that is less than 0 7 V 0 7 V is the voltage drop across a diode the intrinsic P Substrate N drain diode is forward biased Therefore the discharge ESD current path is from GND to the I O pin as shown in Figure 4 4 Figure 4 4 ESD Protection During Negative Voltage Zap Gate ubstrate G Gate B N GND Power On Reset Circuitry MAX II devices have POR circuits to monitor V ccnt and Veco Voltage levels during power up The POR circuit monitors these voltages triggering download from the non volatile configuration flash memory CFM block to the SRAM logic maintaining tri state of the I O pins with weak pull up resistors enabled before and during this process When the MAX II device enters user mode the POR circuit releases the I O pins to user functionality The POR circuit of the MAX II except MAX IIZ device continues to monitor the Vc voltage level to detect a brown out condition The POR circuit of the MAX IIZ device does not monitor the Vc voltage level after the device enters into user mode More details are provided in the following sub sections October 2008 Altera Corporation MAX II Device Handbook 4 6 Chapter 4 Hot Socketing and Power On Reset in II Devices Power On Reset Circuitry Power Up Characteristics II Device Handbook When power is applied to a MAX II device the POR ci
178. SP via an Embedded Processor Revised October 2008 Part Number MII51015 1 8 Using the Agilent 3070 Tester for In System Programming Revised October 2008 Part Number MII51016 1 5 Understanding Timing in MAX II Devices Revised October 2008 Part Number MII51017 2 1 Understanding and Evaluating Power in MAX II Devices Revised October 2008 Part Number MII51018 2 1 August 2009 Altera Corporation About this Handbook ANU S RYAN This handbook provides comprehensive information about the Altera MAX II family of devices How to Contact Altera For the most up to date information about Altera products refer to the following table Contact Contact Note 1 Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Altera literature services Email literature altera com Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note 1 You can also contact your local Altera sales office or sales representative Typographic Conventions This document uses the typographic conventions shown in the following table Visual Cue Meaning Bold Type with Initial Capital Command names dialog box titles checkbox options and dialog box options are Letters shown in bold initial capital letters Example Save As dialog box bold type External timing paramete
179. V V 1 EEPROM HT24LCO2 2 048 0 4 2 2 to 5 5 EEPROM HT24LC04 4 096 0 4 2 4 to 5 5 EEPROM HT24LCO8 8 192 0 4 2 4 to 5 5 EEPROM HT93LC56 2 048 1 Read 2 0 5 5 Write 2 4 5 5 EEPROM HT93LC66 4 096 1 Read 2 0 5 5 Write 2 4 5 5 Note to Table 10 7 1 The MAX II device supports two different Vecmr of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device supports the 1 71 to 1 89 V operating voltage range Table 10 8 Microchip Technology Inc Device Characteristics Part 1 of 2 Interface Operating Size Voltage V Type Device Bits SCI SPI 2 Wire 3 Wire Microwire fmax 1 EEPROM 2416562 2048 v 400 kHz 2 5 to 5 5 EEPROM 2416552 2 048 v 400 kHz 2 5 to 5 5 24LC22A 2 048 v 400 kHz 2 5 to 5 5 EEPROM 24LC02B 2 048 v 400 kHz 2 5 to 5 5 2416025 2 048 400 kHz 2 5 to 5 5 EEPROM 2416024 2 048 v 400 kHz 2 5 to 5 5 EEPROM 24C02SC 2 048 400 kHz 2 5 to 5 5 EEPROM 24LCS22A 2 048 400 kHz 1 8 t0 5 5 EEPROM 24AA52 2 048 100 kHz 1 8 to 5 5 EEPROM 24AA02 2 048 v 100 kHz 1 8 to 5 5
180. V LVTTL The I O delay timing parameters for I O standard input and output adders and input delays are specified by speed grade independent of device density Table 5 27 through Table 5 31 show the adder delays associated with I O pins for all packages The delay numbers for 3 4 and 5 speed grades shown in Table 5 27 through Table 5 33 are based on an EPM1270 device target while 6 7 and 8 speed grade values are based on an EPM570Z device target If an I O standard other than 3 3 V LVTTL is selected add the input delay adder to the external tsy timing parameters shown in Table 5 23 through Table 5 26 If an I O standard other than 3 3 V LVTTL with 16 mA drive strength and fast slew rate is selected add the output delay adder to the external t and tpp shown in Table 5 23 through Table 5 26 Table 5 27 External Timing Input Delay Adders Part 1 of 2 MAX II MAX IIG 112 3 Speed 4Speed 5Speed 6Speed 7Speed 8 Speed Grade Grade Grade Grade Grade Grade 1 0 Standard Min Max Min Max Min Max Min Min Max Min Without Schmitt 0 0 0 0 0 0 Trigger With Schmitt 334 434 535 387 434 442 Trigger Unit ps ps August 2009 Altera Corporation MAX II Device Handbook 5 22 Table 5 27 External Timing Input Delay Adders Part 2 of 2
181. When this instruction is selected the bypass register is connected between the TDI and TDO ports HIGHZ will not override the I O weak pull up resistor or the I O bus hold if you have any of them selected October 2008 Altera Corporation Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Il Devices 13 15 1 0 Voltage Support in JTAG Chain 1 0 Voltage Support in JTAG Chain There can be several different Altera or non Altera devices in a JTAG chain However you should be cautious if the chain contains devices that have different V cco levels The pin of a device drives out at the voltage level according to the Vij of the device For MAX II devices the TDO pin will drive out at the voltage level according to the Voco of I O Bank 1 The devices can interface with each other although they might have different V cco levels For example a device with 3 3 V Veco can drive to a device with 5 0 V Veco because 3 3 V meets the minimum on TTL level input for the 5 0 V Veco device JTAG pins on MAX II devices can support 1 5 1 8 2 5 or 3 3 V input levels depending on the V qovoltage of I O Bank 1 Ss Refer to the MAX II Architecture chapter in the MAX II Device Handbook for more information on MultiVoltI M I O support You can interface the TDI and TDO lines of theJTAG pins of devices that have different Voco levels by inserting a level shifter between the devices If possible the JTAG chain should be built such tha
182. Ww ARDin X X X e DRShf a 16 Data Bis Gk _ DRCIk DRDin toco DRDout X X XX XXXXXXXXXXXXXX X Program Erase Busy MAX II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics 5 17 Timing Model and Specifications Figure 5 4 UFM Program Waveforms ARShft 9 Address Bits TE asuk lt ARGA tanh be ARDin X EO Xe X DRShf 1 os 16 Data Bits toss gt DSH amp DRCIk A Nt DRDin x X x 1 DRDout pos Xe gt scs USCH OSC_ENA NC Program N Erase E L ee eN Figure 5 5 UFM Erase Waveform AR S hft Loc 9 Address tan Se AR EN ARDin X X DRShft tApsi DRCIK DRDin DRDout 5 scs to H Program j c Erase A 4 A Koo o Busy tes y oes i Tak IR tepmx Table 5 22 Routing Delay Internal Timing Microparameters MAX Il MAX IIG MAX 112 3 Speed 4 Speed 5 Speed 6 Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade Routing Min Max Min Max Min Max Min Max Min Min Max Unit m 429 556
183. X Xe X X osc Ea XXX XX XX XX XX XX KX X KX XK Program Erase Busy Program To program or write to the UFM you must first perform a sequence to load the reference address into the address register DRSHFT must then be asserted high to load the data serially into the data register starting with the MSB Loading an address into the address register and loading data into the data register can be done concurrently After the 16 bits of data have been successfully shifted into the data register the PROGRAM signal must be asserted high to start writing to the UFM On the rising edge the data currently in the data register is written to the location currently in the address register The BUSY signal is asserted until the program sequence is completed The II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory in MAX II Devices 9 11 UFM Operating Modes data and address register should not be modified until the BUSY signal is de asserted or the flash content will be corrupted The PROGRAM signal is ignored if the BUSY signal is asserted When the PROGRAM signal is applied at exactly the same time as the ERASE signal the behavior is undefined and the contents of flash is corrupted Figure 9 9 shows the UFM waveforms during program mode Figure 9 9 UFM Program Waveforms ARShft 7 5 4 9 Address Bits LK tan ARCIk AR Din X X X is ios DRShft 77 aos v
184. You can also left click on the programming file this will highlight the entire row and on the Edit menu click Add IPS File to open the Select I O Pin State File dialog box as shown in Figure 12 8 Figure 12 8 Select 1 0 Pin State File Menu LT MER Look in test x E3 Ferme fe Files of type 1 0 Pin State File ips Cancel 2 1 TheIPS file you have selected will be listed in the Quartus II Programmer window as shown in Figure 12 9 L gt Make sure the ISP CLAMP check box is checked before you start programming your device October 2008 Altera Corporation MAX II Device Handbook 12 8 Chapter 12 Real Time ISP and ISP Clamp for MAX II Devices ISP Clamp Figure 12 9 The Quartus II Programmer Window with the Specific IPS File La Hodao El RPT om 1S Crate to bach ground progammng Por MAX B wu pee e e Botan T ve E T emre E T tome TTN 7 O z u B t El 1 J a Ate Detect J a o a i praem Saving the IPS File Information to the Programming File The pin state information in the IPS file can be saved into the POF to avoid requiring two files You will only need the programming file to program a device in ISP clamp mode This programming file is also used for creating the Jam and JBC files for the ISP
185. a Clock The clock signal produced from the master device to synchronize the data transfer 5 Chip Select Active low signal that enables the slave device to receive or transfer data from the master device Data transmitted to the SI port of the slave device is sampled by the slave device at the positive SCK clock Data transmits from the slave device through 50 at the negative SCK clock edge When 5 is asserted it means the current device is being selected by the master device from the other end of the SPI bus for service When 5 is not asserted the SI and SCK ports should be blocked from receiving signals from the master device and SO should be in High Impedance state to avoid causing contention on the shared SPI bus All instructions addresses and data are transferred with the MSB first and start with high to low nCs transition The circuit diagram is shown in Figure 9 25 Figure 9 25 Circuit Diagram for SPI Interface Read or Write Operations 51 SO SCK nCS ET Op Code Decoder im Read Write and Erase State Machine SPI Interface UFM Block Control Logic Address and Data Hub pe Eight Bit Status S hift Register Opcodes The 8 bit instruction opcode is shown in Table 9 10 After nCS is pulled low the indicated opcode must be provided Otherwise the interface assumes that the master device has internal logic errors and ignores the rest of the incoming sig
186. ackage C W Still Air 100 ft min 200 ft min 400 ft min EPM570 100 MBGA 25 0 46 5 40 4 38 4 36 8 EPM570G EPM570Z EPM570 100 TQFP 11 2 38 7 36 6 34 6 30 8 EPM570G EPM570Z 144 MBGA 20 2 51 8 45 1 43 2 41 5 EPM570 144 TQFP 10 5 32 1 30 3 28 7 26 1 EPM570G EPM570 256 FBGA 13 0 37 4 33 1 30 5 28 4 EPM570G EPM570 256 MBGA 12 9 39 5 33 6 31 6 30 1 EPM570G EPM570Z EPM1270 144 TQFP 10 5 31 4 297 28 2 25 8 EPM1270G 256 FBGA 10 4 33 5 29 3 26 8 24 7 256 MBGA 10 6 36 1 30 2 28 3 26 8 EPM2210 256 FBGA 8 7 30 2 26 1 23 6 21 7 22106 324 FBGA 8 2 29 8 25 7 23 3 21 3 Package Outlines The package outlines on the following pages are listed in order of ascending pin count Altera package outlines meet the requirements of JEDEC Publication No 95 68 Pin Micro FineLine Ball Grid Array MBGA Wire Bond All dimensions and tolerances conform to ASME Y14 5M 1994 Controlling dimension is in millimeters Pin A1 may be indicated by an ID dot or a special feature in its proximity on package surface Package Information Part 1 of 2 Package Outline Dimension Table Part 1 of 2 Description Specification Millimeters Symbol Ordering Code Reference M Min Nom Max Package Acronym MBGA A 1 20 Substrate Material BT A1 0 15 Solder Ball Composition Pb free n 3Ag 0 5Cu Typ A2 1 00 JEDEC Outline Reference MO 195 Variation AB A3 0 60 REF
187. add File amp Change File Save File Add IPS File che PS File 09 add Device 8 Change Device ft Up p Down Al Up Arrow AlE Down Arrow amp Hardware Setup ISP CLAMP State Editor Properties 4 Specify the states of the pins in your design in the ISP Clamp State Editor There are four clamp state choices tri state high low and sample and sustain By default all pins are set to tri state 5 Save the IPS file after making the modifications Figure 12 7 shows the ISP Clamp State Editor On the File menu you can also click Create Update gt Create Update IPS File to open the ISP Clamp State Editor and create a new IPS file October 2008 Altera Corporation Chapter 12 Real Time ISP and ISP Clamp for MAX Il Devices 12 7 ISP Clamp Figure 12 7 ISP Clamp State Editor Device 12707144 File name untitled ips Gpen IPS File Pin Name ISP CLAMP State Change Name 61 Tristate 62 Tristate Change State NC locked Esz 68 Tristate NC locked NC locked 69 Tristate NC locked NC locked 20 Tristate Using the IPS File In the Quartus II Programmer you must specify the IPS file you want to use by performing the following steps 1 Double click on the cell under the IPS File column The Select I O Pin State File menu appears 2 Choose the IPS file for your project and click Open
188. an LE where it is fed to local row or column interconnects Figure 2 9 Carry Select Chain LAB Carry In 0 1 e 7 LAB Carry In 1 E0 Sum1 Bl Carry In0 LAN a Carry In1 e _ i 8 LET peas LUT gt datal Sum T oae Suma e Suma y LUT E LUT LE4 Sum5 oo 0 1 AS LES Sum y a Carry O utd Carry eum 1 LEG Sum7 gt E LE7 Sum8 LES Sum9 510 go 8 t p To top of adjacent LAB LAB Carry Out October 2008 Altera Corporation MAX II Device Handbook 2 12 Chapter 2 MAX II Architecture MultiTrack Interconnect The Quartus II software automatically creates carry chain logic during design processing or you can create it manually during design entry Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions The Quartus II software creates carry chains longer than 10 LEs by linking adjacent LABs within the same row together automatically A carry chain can extend horizontally up to one full LAB row but does not extend between LAB rows Clear and Preset Logic Control LAB
189. aps to address 000h in physical memory and all addresses 000h follow the order in AD logical memory t o logical memory 000h Upper 8 bit byte Lower 8 bit byte 16 bit data in UFM Padding Data into Memory Map The altufm 12 megafunction uses the upper 8 bits of the UFM 16 bit word therefore the 8 least significant bit LSB should be padded with 1 as shown in Figure 9 53 Figure 9 53 Padding Data into Memory Map 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 8 bit valid data to be placed in the upper byte Pad the lower byte with eight 1 s Simulation Parameters Conclusion II Device Handbook Figure 9 48 on page 9 43 shows page 4 of the altufm megafunction where you can have an option to choose to simulate the OSC output port at the maximum or the minimum frequency during the design simulation The frequency chosen is only used as the timing parameter for the Quartus II simulator and does not affect the real MAX II device OSC output frequency The MAX II UFM block is a user accessible programmable non volatile flash memory block that provides significant flexibility in its interfacing MAX II devices fill the need for on board non volatile storage in any application minimizing board space and reducing total system cost October 2008 Altera Corporation Chapter 9 Using User Flash Mem
190. ariables In addition each LE contains a programmable register and carry chain with carry select capability A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB wide control signal Each LE drives all types of interconnects local row column LUT chain register chain and DirectLink interconnects See Figure 2 6 II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 1 Logic Elements Figure 2 6 MAX II LE Register chain routing from previous LE midi Register Bypass ynchronous LAB Carry In Load P a isi Programmable Carry In1 Sidi is addnsub y Synchronous ri Register Select id Carry In0 j y Clear J LUT chain Y Y routing to next LE datal 25 LL i 4 Row column data2 39 Look Up pus PRNIALD gt and DirectLink data3 e Table Chain Load and 9 gt routing LUT Clear Logic DAI data4 P lj CLRN gt Row column and DirectLink TT EL routing labcirl gt labclr2 gt Asynchronous gt labpre aload Clear P reset Local routing Chip Wide D Load Logic Reset DEV CLRn l Register chain sere Register output Clockand Clock Enable Select labclk1 labclk2 la
191. ary functions The purpose of this parameter is to restrict Player memory usage to a pre defined memory space This memory should be allocated before calling 1 execute If maximum dynamic memory usage is not a concern set this parameter to null which allows the Player to dynamically allocate the necessary memory to perform the specified action workspace size Optional A scalar representing the amount of memory in bytes to which workspace points II Device Handbook October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor 14 15 Updating Devices Using Jam Table 14 5 Parameters Note 1 Part 2 of 2 Parameter Status Description action Mandatory pointer to a string text that directs the Player Example actions are PROGRAM or VERIFY In most cases this parameter will be set to the string PROGRAM The Player is not case sensitive so the text can be either uppercase or lowercase The Player supports all actions defined in the Jam Standard Test and Programming Language Specification See Table 14 6 Note that the string must be null terminated init list Optional of pointers to strings This parameter is used when applying Jam version 1 1 files 2 error line xx pointer to a long integer If an error is encountered during execution the Player will record the line of the JBC file where the error occurred exit code
192. ax Min Max Min Max Unit font Maximum 3040 2475 201 1 1841 1235 118 3 MHz global clock 1 frequency for 16 bit counter Note to Table 5 24 1 The maximum frequency is limited by the 1 0 standard on the clock input pin The 16 bit counter critical delay performs faster than this global clock input pin maximum frequency Table 5 25 shows the external I O timing parameters for EPM1270 devices Table 5 25 1270 Global Clock External 1 0 Timing Parameters MAX II MAX IIG 8 Speed Grade 4 Speed Grade 5 Speed Grade Symbol Parameter Condition Min Max Min Max Min Max Unit loo Worst case pin to pin 10 pF 6 2 8 1 10 0 ns delay through 1 look up table LUT Best case pin to pin 10 pF 3 7 4 8 5 9 ns delay through 1 LUT Global clock setup time 1 2 1 5 1 9 ns ti Global clock hold time 0 0 0 5 tco Global clock to output 10 pF 2 0 4 6 2 0 5 9 2 0 7 3 ns delay Global clock high time 166 216 266 ps Global clock low time 166 216 266 ps tonr Minimum global clock 3 3 4 0 5 0 ns period for 16 bit counter four Maximum global clock 304 0 1 247 5 201 1 frequency for 16 bit counter Note to Table 5 25 1 The maximum frequency is limited by t
193. bclkenal gt labclkena2 gt L Carry Outd gt Carry Outl LAB Carry Out Each LE s programmable register can be configured for D T JK or SR operation Each register has data true asynchronous load data clock clock enable clear and asynchronous load preset inputs Global signals general purpose I O pins or any LE can drive the register s clock and clear control signals Either general purpose I O pins or LEs can drive the clock enable preset asynchronous load and asynchronous data The asynchronous load data input comes from the data3 input of the LE For combinational functions the LUT output bypasses the register and drives directly to the LE outputs Each LE has three outputs that drive the local row and column routing resources The LUT or register output can drive these three outputs independently Two LE outputs drive column or row and DirectLink routing connections and one drives local interconnect resources This allows the LUT to drive one output while the register drives another output This register packing feature improves device utilization because the device can use the register and the LUT for unrelated functions Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan out LUT This provides another mechanism for improved fitting The LE can also drive out registered and unregistered versions
194. begins after the master generates a stop condition Figure 9 16 shows the full erase sequence triggered by using the slave address If the memory is write protected WP 1 the slave does not acknowledge the erase trigger slave address A A A A 1 1 1 sent by the master The master should then send a stop condition to terminate the transfer The full erase operation will not be executed October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 19 Software Support for UFM Block Figure 9 16 Full Erase Sequence Triggered Using the Slave Address Slave Address am P aaan PM S Start Condition 0 write From Master to Slave P Stop Condition A Acknowledge From Slave to Master Sector Erase Byte Address Triggered This sector erase operation is triggered by defining a 7 to 10 bit byte address for each sector depending on the memory size The trigger address for each sector is entered on page 4 of the altufm MegaWizard Plug In Manager as shown in Figure 9 24 on page 9 24 When a write operation is executed targeting this special byte address location the UFM sector that contains that byte address location is erased This sector erase operation is automatically followed by a write of the intended write byte to that address The default byte address location for UFM Sector 0 erase is address 0x00 The default byte address location for UFM Sector
195. ben ee emma res 2 8 Normal Mod his beu e bale ede epa doe ordo a lcu obvio 2 9 Dynamic Arithmetic 2 9 Carry select Chain eo esee tp rend kt ew dated ele deles d esed tend addi V eaae 2 10 Clear and Preset Logic Control 22222552 e e Re RES ERR OE CREE Y 2 12 MultiTrack Interconnect 042 uses t RR Ore ei haan elon ACER RES ERE RARIOR 2 12 Global Signals wc 2 16 User Flash Memory Block 2 18 IJEMSIOFASE cde IM uU doi aie 2 19 Internal Oscillator uod dete bie RE eh bet RATER eb ERREUR RR pes s 2 20 Program Erase and Busy Signals 2 20 Auto Increment Addressing 2 2 20 sss E E eee e UM e Ue 2 20 Block to Logic Array Interface 2 20 stole ML e e i D 2 22 August 2009 Altera Corporation MAX II Device Handbook TO Structure usados m ep ek e Rh Vo ER OE RAI C RU o ER 2 23 Fast I O Connection ee beet ex RIDE a RE A Ne quo Pa d ed 2 23 BIOCKS ere bere PEDE tere eer E eee desee fo
196. ber 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 29 Software Support for UFM Block 4 An 8 bit data is transmitted through 51 5 nCSis pulled back to high to indicate the end of transmission Figure 9 28 WRITE Operation Sequence for Extended Mode ncs E SCK 50 1234 5 6 7 8 9 10111213 1415 16 171819 20 21 2223 23 8 bit mla 8 bit gt Instruction Instruction XX XANAX XA MSB MSB High Impendance 8 bit Data Out 1 8 bit Data Out 2 MSB MSB Figure 9 29 shows the WRITE operation sequence for Base mode Figure 9 29 WRITE Operation Sequence for Base Mode ncs A 0 1 2 3 4 5 6 7 8 9101112 13 14 15 16 17 18 19 20 21 22 23 see WEVA UU 8 bit Bebe 8 bit Instruction Address 51 024 8 bit Data In M 5 5 so High Impendance SECTOR ERASE SECTOR ERASE is the instruction of erasing one sector of the UFM block Each sector contains 256 words WEN bit and the sector must not be protected for SE operation to be successful nCS must be driven high before the instruction is executed internally You may poll the nRDY bit in the software status register for the completion of the interna
197. ble 2 7 1 To drive inputs higher than Vecio but less than 4 0 V including the overshoot disable the 1 0 clamp diode However to drive 5 0 V inputs to the device enable the 1 0 clamp diode to prevent V from rising above 4 0 V 2 When Vocio 1 8 V a MAX II device can drive a 1 5 V device with 1 8 V tolerant inputs 3 When Vecio 2 5 V a MAX II device can drive a 1 5 V or 1 8 V device with 2 5 V tolerant inputs 4 5 6 When Vecio 3 3 V a MAX II device drive a 1 5 V 1 8 V or 2 5 V device with 3 3 V tolerant inputs 7 When Vecio 3 3 V a MAX II device can drive a device with 5 0 V TTL inputs but not 5 0 V CMOS inputs In the case of 5 0 V CMOS open drain setting with internal 1 0 clamp diode available only on EPM1270 and EPM2210 devices and external resistor is required When Vecio 3 3 V and a 2 5 V input signal feeds an input pin the VCCIO supply current will be slightly larger than expected MAX II devices can be 5 0 V tolerant with the use of an external resistor and the internal 1 0 clamp diode on the EPM1270 and 2210 devices a For information about output pin source and sink current guidelines refer to the AN 428 MAX II CPLD Design Guidelines Referenced Documents II Device Handbook This chapter referenced the following documents AN 428 MAX II CPLD Design Guidelines DC and Switching Characteristics chapter in the MAX II Device Handbook Hot Socketing and Power On Reset in
198. block to your desired interface protocol For more information about programming and erasing the block and or the altufm megafunction refer to the Using User Flash Memory MAX II Devices chapter in the MAX II Device Handbook October 2008 Altera Corporation MAX II Device Handbook 10 2 List of Vendors and Devices Table 10 2 Asahi Kasei Microsystems Co Device Characteristics Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory List of Vendors and Devices The differences between the UFM block and serial EEPROMs that you should consider in your integration of serial EEPROM applications are the sector based erase and erase reprogram cycles Serial EEPROMs support byte wide erase which is automatically implemented during a byte write sequence The UFM block supports byte writes but does not support byte erase requiring a sector based erase sequence prior to any programming or writing If the data content of a specific byte location needs to be overwritten in the UFM the entire sector that byte resides in must be erased unless that byte location was already erased all 1s For programming endurance the erase reprogram cycles do not meet the 107 and greater cycles seen in serial EEPROMs the MAX II UFM block erase programming endurance specification Refer to the DC and Switching Characteristics chapter in the MA X II Device Handbook for Table 10 2 through Table 10 10 list the vendors and
199. board may potentially use many different supply voltages such as 5 0 3 3 2 5 1 8 and 1 5 V which can ultimately lead to voltage conflicts accommodate interfacing with a variety of devices on system boards MAX devices have MultiVolt I O interfaces that allow devices in a mixed voltage design environment to communicate directly with MAX II devices The MultiVolt interface separates the power supply voltage from the output voltage Veco enabling MAX II devices to interface with other devices using a different voltage level on the same printed circuit board Additionally the MAX II device family supports the MultiVolt core feature For 1 8 V operation use the MAX IIG or MAX IIZ devices The 1 8 V input directly powers the core of the devices For 2 5 V or 3 3 V operation use the MAX II devices MAX II devices that support 2 5 V and 3 3 V operation have an internal voltage regulator that regulates at 1 8 V This chapter discusses several features that allow you to implement Altera devices in multiple voltage systems without damaging the device or the system including m HotSocketing Insert or remove MAX II devices to and from a powered up system without affecting the device or system operation m Power Up Sequence Flexibility MA X II devices can accommodate any possible power up sequence m Power On Reset MAX II devices maintain a reset state until voltage is within Operating range This chapter con
200. boundary scan registers After loading the boundary scan registers with the appropriate values the EXTEST instruction is executed to clamp the I O pins to the specific values loaded into the boundary scan registers during SAMPLE PRELOAD If you choose to sample the existing state of a pin and hold the pin to that state when the device enters ISP clamp mode you must make sure that the signalis in steady state You need a steady state signal because you cannot control the sample set up time as it depends on the TCK frequency as well as the download cable and software You might not capture the correct value when sampling a signal that toggles or is not static for long periods of time Figure 12 5 shows the ISP clamp operation Figure 12 5 ISP Clamp Operation Before Programming 6 During Programming After Programming User Mode ISP Clamp Mode User Mode J TAG CFM Programming JTAG CFM JTAG CFM m Data i E SRA SRA SRA zl Core Logic I Core Logic l Core Logic l 1 05 Drive Out 1 05 Clamped to 1 05 Drive Out According to Design Specified States According to New Design Using ISP Clamp in the Quartus Il Software You have to define the states of the I O pins to use the ISP clamp feature There are two ways to define the pin states in the Quartus II software You can either
201. can cause overshoot problems When this combination occurs you must either reduce inductance on the trace or reduce the switching rate by selecting a transistor to transistor logic TTL driver chip with a slower slew rate Altera does not recommend using resistor and capacitor RC networks to slow down edge rates because they can violate the device s input specifications In most cases using a driver chip prevents the edge rate from being too slow Altera recommends using driver chips that do not glitch upon power up Programming via a Download Cable You can program MAX II devices using a MasterBlaster ByteBlasterMV ByteBlaster II or USB Blaster download cable Using a PC or UNIX workstation with the Quartus II software programmer Programmer Object File pof Jam TM Files jam or Jam Byte Code Files jbc can be downloaded to the MAX II devices via the download cable If you are using the download cables and your JTAG chain contains three or more devices Altera recommends adding a buffer to the chain You should select a buffer with slow transitions to minimize noise but be sure that the transition rates can still meet TCK performance requirements of your chain If you must extend the download cable you can attach a standard PC parallel or USB port cable to the download cable Do not extend the 10 pin header portion of the download cable extending this portion of the cable can cause noise and in system programming proble
202. ced Documents section December 2006 m Added document revision history version 1 4 June 2005 m Added text and Table 3 4 version 1 3 June 2005 m Updated text on pages 3 5 to 3 8 version 1 3 June 2004 m Corrected Figure 3 1 Added CFM acronym version 1 1 II Device Handbook October 2008 Altera Corporation 4 Hot Socketing and Power On Reset in S p AN e MAX II Devices MII51004 2 1 Introduction II devices offer hot socketing also known as hot plug in or hot swap and power sequencing support Designers can insert or remove a MAXII board in a system during operation without undesirable effects to the system bus The hot socketing feature removes some of the difficulties designers face when using components on printed circuit boards PCBs that contain a mixture of 3 3 2 5 1 8 and 1 5 V devices The MAX II device hot socketing feature provides m Board or device insertion and removal m Support for any power up sequence m Non intrusive I O buffers to system buses during hot insertion This chapter contains the following sections m MAX II Hot Socketing Specifications on page 4 1 m Power On Reset Circuitry on page 4 5 MAX II Hot Socketing Specifications MAX II devices offer all three of the features required for the hot socketing capability listed above without any external components or special design requirements The following are hot socketing specifications
203. ces Logic Array Interface Data Width Bits Interface Type fr t 8 SPI 8 or 16 Serial Parallel Options of 3 to 16 Parallel None 16 Serial II Device Handbook For more details about the logic array interface options in the altufm megafunction refer to Software Support for UFM Block on page 9 13 The UFM block is accessible through the logic array interface as well as the JTAG interface However the UFM logic array interface does not have access to the CFM block October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices UFM Functional Description UFM Functional Description Figure 9 1 is the block diagram of the MAX II UFM block and the interface signals Figure 9 1 UFM Block and Interface Signals 9 3 UFM Block PROGRAM Program P RTP BUSY ERASE L p gt Erase D BUSY Control OSC _ OSC l 4 OSC 9 UFM Sector 1 ARCLK 20 UFM Sector 0 Address Register 16 16 ARSHFT gt ARDin A DRDin Data Register gt DRDout DRCLK RENE DRSHFT Table 9 4 summarizes the MAX II UFM block input and output interface signals Table 9 4 UFM Interface Signals Part 1 of 2 Port Name DRDin Port Type Input Description Serial input to the data register It is used
204. ck Rates Table 5 32 and Table 5 33 show the maximum input and output clock rates for standard I O pins in MAX II devices Table 5 32 MAX II Maximum Input Clock Rate for 1 0 MAX II MAX IIG 112 3 Speed 4Speed 5Speed 6 Speed 7 Speed 8 Speed 1 0 Standard Grade Grade Grade Grade Grade Grade Unit 3 3 V LVTTL Without Schmitt 304 304 304 304 304 304 Trigger With Schmitt 250 250 250 250 250 250 MHz Trigger 3 3 V LVCMOS Without Schmitt 304 304 304 304 304 304 MHz Trigger With Schmitt 250 250 250 250 250 250 MHz Trigger 2 5 V LVTTL Without Schmitt 220 220 220 220 220 220 MHz Trigger With Schmitt 188 188 188 188 188 188 MHz Trigger 2 5 V 05 Without Schmitt 220 220 220 220 220 220 MHz Trigger With Schmitt 188 188 188 188 188 188 MHz Trigger 1 8 V LVTTL Without Schmitt 200 200 200 200 200 200 MHz Trigger 1 8 V LVCMOS Without Schmitt 200 200 200 200 200 200 MHz Trigger 1 5 V LVCMOS Without Schmitt 150 150 150 150 150 150 MHz Trigger 3 3 V PCI Without Schmitt 304 304 304 304 304 304 MHz Trigger MAX II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics 5 25 Timing Model and Specifications Table 5 33 MAX Il Maximum Output Clock Rate for 1 0 MAX II MAX IIG MAX 112 3 Speed 4 Speed 5 Speed 6 Speed Speed 8Speed 1 0 Standard Grade Grade Grade Grade Grade Grade 32VIVTL 304 34 34
205. ck that the processor uses Likewise a read involves enabling the tri state buffers and letting the TDO signal flow back to the processor The design also provides a hardware connection to read back the values in the TDI TMS and registers This optional feature is useful during the development phase allowing software to check the valid states of the registers in the interface PLD In addition multiplexer logic is included to permit a download cable to program the device chain This capability is useful during the prototype phase of development when programming must be verified Board Layout The following elements are important when laying out a board that programs via the IEEE Std 1149 1 JTAG chain m Treat the signal trace as a clock tree October 2008 Altera Corporation MAX II Device Handbook 14 4 Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Software Development m Usea pull down resistor on m Make the JTAG signal traces as short as possible m Add external resistors to pull outputs to a defined logic level TCK Signal Trace Protection and Integrity TCK is the clock for the entire JTAG chain of devices These devices are edge triggered on the TCK signal so it is imperative that TCK is protected from high frequency noise and has good signal integrity Ensure that the signal meets the rise time tg and fall time tp parameters in the appropriate device family data sheet The signal may a
206. cs and in system programming For more information or to receive BSDL files for IEEE Std 1149 1 compliant MAX II devices refer to the Altera website at ww w altera com The IEEE Std 1149 1 BST circuitry available in MAX II devices provides a cost effective and efficient way to test systems that contain devices with tight lead spacing Circuit boards with Altera and other IEEE Std 1149 1 compliant devices can use the EXTEST SAMPLE PRELOAD and BYPASSmodes to create serial patterns that internally test the pin connections between devices and check device operation Institute of Electrical and Electronics Engineers Inc IEEE Standard Test Access Port and Boundary Scan Architecture IEEE Std 1149 1 2001 New York Institute of Electrical and Electronics Engineers Inc 2001 Referenced Documents This chapter references the following documents m DC and Switching Characteristics chapter in the MAX II Device Handbook m In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook m JTAG and In System Programmability chapter in the MAX II Device Handbook m MAXII Architecture chapter in the MAX II Device Handbook October 2008 Altera Corporation MAX II Device Handbook 13 18 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Devices Document Revision History Document Revision History Table 13 4 shows the revision history for this chapter Table 13 4 Document Revision History
207. d Documents II Device Handbook This chapter references the following documents AN 39 IEEE 1149 1 JTAG Boudary Scan Testing in Altera Devices AN 111 Embedded Programming Using the 8051 amp Jam Byte Code AN 122 Using Jam STAPL for ISP amp ICR via an Embedded Processor DC and Switching Characteristics chapter in the MAX II Device Handbook In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Document Revision History Document Revision History Table 14 9 shows the revision history for this chapter Table 14 9 Document Revision History 14 19 Date and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 1 8 December 2007 m Added Referenced Documents section version 1 7 December 2006 m Added document revision history version 1 6 August 2006 m Updated Embedded Systems section version 1 5 August 2005 m Updated Tables 14 2 and 14 3 version 1 4 June 2005 m Removed Table 14 6 from v1 2 version 1 3 m Added a new section MAX II Jam JBC Actions and Procedure Commands January 2005 m Previously published as Chapter 15 No changes to content version 1 2 December 2004 m Changed document reference from AN 88 to AN 122 version 1 1 Octobe
208. d In System Programmability 3 7 Referenced Documents Real Time ISP Design Security For systems that require more than DC logic level control of I O pins the real time ISP feature allows you to update the CFM block with a new design image while the current design continues to operate in the SRAM logic array and I O pins A new programming file is updated into the MAX II device without halting the original design s operation saving down time costs for remote or field upgrades The updated block configures the new design into the SRAM upon the next power cycle It is also possible to execute an immediate configuration of the SRAM without a power cycle by using a specific sequence of ISP commands The configuration of SRAM without a power cycle takes a specific amount of time During this time the I O pins are tri stated and weakly pulled up to V c MAX II devices contain a programmable security bit that controls access to the data programmed into the CFM block When this bit is programmed design programming information stored in the CFM block cannot be copied or retrieved This feature provides a high level of design security because programmed data within flash memory cells is invisible The security bit that controls this function as well as all other programmed data is reset only when the device is erased The SRAM is also invisible and cannot be accessed regardless of the security bit setting The UFM block data
209. d Select the 1 0 standard for the input output or bidirectional pins in this module from the pull down list The calculated 1 0 power varies based on the 1 0 standard Clock Freq MHz Enter the clock frequency MHz The operating frequency for MAX II and MAX IIG is between 0 and 304 MHz For MAX IIZ the operating frequency is between 0 and 152 MHz A 100 MHz input clock with a 12 596 toggle means that each 1 0 pin toggles 12 5 million times per second 100 x 12 5 Output Pins Enter the number of output pins in this module Input Pins Enter the number of input pins in this module Bidir Pins Enter the number of bidirectional pins in this module 1 0 pin configured as bidirectional but used only as output consumes more power than one configured as an output only due to the toggling of the input buffer every time the output buffer toggles they share a common pin 0 Bank Select the 1 0 bank for the module If you do not know which 1 0 bank the pins will be assigned to leave the value as Assigning the 1 0 module to a bank checks whether your 1 0 voltage assignments are compatible or not allowing per bank lecio reporting The PowerPlay Early Power Estimator spreadsheet does not take any 1 0 placement constraints into consideration except for 1 0 standard and bank match and 1 0 voltage Toggle 96 Enter the average percentage of output bidirectional and input pins toggling on each clock cycle The toggle percentage range
210. d Systems Figure 14 1 Embedded System Block Diagram Embedded System Tb Interface Logic Pms Optional Download Cable TE Tb0 TDI Control Control TMS TOI TCK d 7 0 5 5 d 3 0 p gt 5 2 Any JTAG 50 099 ck Device adr 19 0 TO Embedded Processor TDI Control EPROM or tis System gt 8 dear Memory 6 ck MAX II Devices TDO adr19 0 229 20 adr 19 0 TDI SES Any JTAG Device TDO Both JTAG connection methods should include space for the MasterBlaster ByteBlaster II or USB Blaster header connection The header is useful during prototyping because it allows designers to quickly verify or modify the PLD s contents During production the header can be removed to decrease cost Example Interface PLD Design Figure 14 2 shows an example design schematic of an interface PLD A different design can be implemented however important points exemplified in this design are m TMS TCK and TDI should be synchronous outputs m Multiplexer logic should be included to allow board access for the MasterBlaster ByteBlaster II or USB Blaster download cable 57 This design example is for reference only of the inputs except data 3 0 are optional and included only to show how an interface PLD can act as an address decoder on an embedded data bus
211. d at the data register output toe Delay from OSC_ENA signal reaching UFM to rising clock of osc leaving the UFM loscs Maximum delay between the oSC_ENA rising edge to the ERASE PROGRAM signal rising edge toscu Minimum delay allowed from the ERASE PROGRAM signal going low to the 05 ENA signal going low Timing Models Timing models are simplified block diagrams that illustrate the delays through Altera devices Logic can be implemented on different paths You can trace the actual paths used in your design by examining the equations listed in the Quartus II Report File rpt for the project You can then add up the appropriate internal timing parameters to estimate the delays through the device The MAX II architecture has a globally routed clock The MultiTrack interconnect ensures predictable performance accurate simulation and accurate timing analysis across all MAX II device densities and speed grades Figure 16 1 shows the timing model for MAX II devices The timing model is the preliminary version which is subject to change The final version of the timing model will be released once available Figure 16 1 MAX II Device Timing Model Output and Output Enable 7 Data Delay
212. dded tcove information in Table 16 2 m Updated Figure 16 1 m Updated 1 to Figure 16 2 m Updated Calculating Timing Delays section m Added Referenced Documents section December 2006 m Added document revision history version 1 4 January 2005 m Previously published as Chapter 17 No changes to content version 1 3 December 2004 m Added section Programmable Input Delay version 1 2 June 2004 m Updated Table 16 1 Various parameter naming updates version 1 1 MAX II Device Handbook October 2008 Altera Corporation 17 Understanding and Evaluating Power S p AN in MAX Il Devices MII51018 2 1 Introduction Power consumption has become an important factor for CPLD applications with the increased use of CPLDs in low power designs Overall low standby static and dynamic power is becoming increasingly important to reduce system power and can be achieved with MAX devices which have low stand by and dynamic power This chapter contains the following sections m Powerin MAX II Devices on page 17 1 m MAX II Power Estimation Using the PowerPlay Early Power Estimator on page 17 3 m PowerPlay Early Power Estimator Inputs on page 17 3 m Power Estimation Summary on page 17 13 m Power Saving Techniques on page 17 15 Power in MAX II Devices Different from previous CPLD architectures MAX II logic does not use sense amplifiers that require bias currents to amplify
213. ded Jam Player is compatible with legacy Jam files that use version 1 1 syntax Both Players are backward compatible they can play version 1 1 files and Jam STAPL files For more information about Altera s support for version 1 1 syntax refer to AN 122 Using Jam STAPL for ISP amp ICR via an Embedded Processor The Jam STAPL Byte Code Player The Jam STAPL Byte Code Player is coded in the C programming language for 16 bit and 32 bit processors lt For more information about Altera s support for 8 bit processors refer to AN 111 Embedded Programming Using the 8051 amp Jam Byte Code The 16 bit and 32 bit source code is divided into two categories m Platform specific code that handles I O functions and applies to specific hardware jbistub c October 2008 Altera Corporation MAX II Device Handbook 14 8 II Device Handbook Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Software Development m Generic code that performs the Player s internal functions all other C files Figure 14 5 illustrates the organization of the source code files by function Keeping the platform specific code inside the jbistub c file simplifies the process of porting the Jam STAPL Byte Code Player to a particular processor Figure 14 5 Jam STAPL Byte Code Player Source Code Structure M Jam STAPL Player Error 7 Message 1
214. device family data sheet for the specification on input logic levels October 2008 Altera Corporation MAX II Device Handbook 15 8 Chapter 15 Using the Agilent 3070 Tester for In System Programming Development Flow for Agilent 3070 with PLD ISP Software If an overpower error on the TCK pin occurs check the value of the resistors because they may be too low for the test system to back drive for an extended period of time Ensure that the test execution order is correct If the tests are executed out of order the programming information is incorrect Also if the same test is executed twice in a row the target device will be out of sequence and will not receive the correct programming information Ensure that the actual vectors match the expected values for the input pins TMS and If they not the same the tests may need to be recompiled Ensure that the pcf order statement in the test matches the order of the PCF code generated in Step 2 Create a Serial Vector Format File on page 15 4 If they do not match the order must be changed and the tests recompiled If possible verify that the device is programmed correctly by using the Quartus II software the ByteBlaster II download cable and the POF that was used to generate the SVF File This action is not practical in a production situation but is useful during test development and debugging If you need to isolate an individual device you can genera
215. devices can operate up to 304 MHz Vecint 3 3 V Vecint 2 5 V Vecinr 1 8 V MAX Voc 1 8 V MAX IIZ The power consumed in MAX II devices is dependent on the design It is very important to complete a power evaluation early in the design process to ensure that the power dissipation by MAX II devices meets system requirements and specifications This chapter discusses how to evaluate and manage MAX II power using the MAX II PowerPlay Early Power Estimator spreadsheet available at www altera com II Device Handbook October 2008 Altera Corporation Chapter 17 Understanding and Evaluating Power in MAX II Devices 17 3 MAX II Power Estimation Using the PowerPlay Early Power Estimator MAX II Power Estimation Using the PowerPlay Early Power Estimator The PowerPlay Early Power Estimator spreadsheet allows you to enter information into sections based on architectural features The PowerPlay Early Power Estimator spreadsheet also provides a subtotal of power consumed by each architectural feature reported in each section in mWatts mW Figure 17 2 shows the overview of the MAX II PowerPlay Early Power Estimator summary worksheet Figure 17 2 MAX II PowerPlay Early Power Estimator PowerPlay Early Power Estimator Power Management MAX II Family RAD HUE Resource Center v72 Visit the Online Comments Device Package Errors Warnings Messages Input Parameters Power mW Therma
216. dimensional row and column based architecture to implement custom logic Row and column interconnects provide signal interconnects between the logic array blocks LABs The logic array consists of LABs with 10 logic elements LEs in each LAB An LE isa small unit of logic providing efficient implementation of user logic functions LABs are grouped into rows and columns across the device The MultiTrack interconnect provides fast granular timing delays between LABs The fast routing between LEs provides minimum timing delay for added levels of logic versus globally routed interconnect structures The MAX II device I O pins are fed by I O elements IOE located at the ends of LAB rows and columns around the periphery of the device Each IOE contains a bidirectional I O buffer with several advanced features 1 0 pins support Schmitt trigger inputs and various single ended standards such as 66 MHz 32 bit PCI and LVTTL MAX II devices provide a global clock network The global clock network consists of four global clock lines that drive throughout the entire device providing clocks for all resources within the device The global clock lines can also be used for control signals such as clear preset or output enable October 2008 Altera Corporation MAX II Device Handbook 2 2 Chapter 2 MAX II Architecture Functional Description Figure 2 1 shows a functional block diagram of the MAX II device Figure 2 1 MAX II Device Block Diagram
217. e Grade Grade Grade Standard Min Max Min Max Min Max Min Max Min Max Min Max Unit 3 3 V LVTTL 16mA 0 0 0 0 0 0 ps 8 mA 28 37 45 72 71 74 ps 3 3 V LVCMOS 8 mA 0 0 0 0 0 0 ps 4 mA 28 37 45 72 71 74 ps 2 5 14mA 14 19 23 75 87 90 ps LVCMOS 7 314 49 503 162 174 177 ps 1 8 VLVTTL 6mA 450 585 720 279 289 291 ps LVCMOS 1 443 1 876 2309 499 508 512 ps II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics 5 13 Timing Model and Specifications Table 5 17 tzx IOE Microparameter Adders for Fast Slew Rate Part 2 of 2 MAX Il MAX IIG MAX 112 3 Speed 4 Speed 5 Speed 6 Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade Standard Min Max Min Max Min Max Min Max Min Max Min Max Unit 1 5 VLVCMOS 4mA 1 118 1 454 1 789 580 588 588 ps 2mA 2410 3 133
218. e Quartus 11 Compilation Report under Fitter gt Resource Section gt Global amp Other Fast Signals gt Fanout Local Enable Enter the average percentage of time that clock enable is high for destination flipflops Local clock enables for flipflops in the LEs are promoted to logic array block LAB wide signals When given flipflop is disabled the LAB wide clock is also disabled cutting clock power in addition to power for downstream logic This sheet models only the impact on clock tree power Total Power mW Represents the total power dissipation due to clock distribution User Comments Enter any comments optional entry October 2008 Altera Corporation MAX II Device Handbook 11 6 Logic Section Chapter 17 Understanding and Evaluating Power in MAX II Devices PowerPlay Early Power Estimator Inputs A design is a combination of several design modules operating at different frequencies and toggle rates Each design module can have a different amount of logic For the most accurate power estimation partition the design into different design modules You can partition your design by grouping modules by clock frequency location hierarchy or entities Figure 17 5 shows the logic section in the PowerPlay Early Power Estimator spreadsheet Figure 17 5 Logic Section Logic Module Clock Freq Power mW Routing Block Total User Comments Toggle 12 5 0 00 12 5 0 00 0 0
219. e data register always proceeds from MSB to LSB The altufm megafunction always pads the remaining LSB of the data register with 1s if the user selects a data width of less than 16 bits ALTUFM Parallel Interface Timing Specification Figure 9 40 shows the timing specifications for the parallel interface Table 9 16 parallel interface instruction signals The nREAD nWRITE and nERASE signals are active low signals October 2008 Altera Corporation MAX II Device Handbook 9 38 Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Figure 9 40 Parallel Interface Timing Waveform a tCOMMAND gt i HNBUSY gt nBusy a tHBus gt Data or Address Bus Table 9 16 Parallel Interface Timing Parameters input and or address register port after the command signal has been asserted low Symbol Description Minimum ns Maximum ns The time required for the command signal 600 3 000 nREAD nWRI TE nERASE to be asserted and held low to initiate a read write erase sequence Es Maximum delay between command signal s falling edge to the 300 nBUSY signal s falling edge lusus The time that data and or address bus must be present at the data 600 Instantiating Parallel Interface Using Quartus Il altufm Megafunction Figure 9 41 shows the altufm megafunction symbol for a parallel interface instantiation in
220. e global clock network drive throughout the entire device The global clock network can provide clocks for all resources within the device including LEs LAB local interconnect IOEs and the UFM block The global clock lines can also be used for global control signals such as clock enables synchronous or asynchronous clears presets output enables or protocol control signals such as TRDY and IRDY for PCI Internal logic can drive the global clock network for internally generated global clocks and control signals Figure 2 13 shows the various sources that drive the global clock network II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 17 Global Signals Figure 2 13 Global Clock Generation GCLKO GCLK1 4 GCLK2 2 0 GCLK3 L gt _ ___ Logic Array 1 EIE 2 Global Clock Network Note to Figure 2 13 1 Any 1 0 pin can use a MultiTrack interconnect to route as a logic array generated global clock signal The global clock network drives to individual LAB column signals LAB column clocks 3 0 that span an entire LAB column from the top to the bottom of the device Unused global clocks or control signals in a LAB column are turned off at the LAB column clock buffers shown in Figure 2 14 The LAB column clocks 3 0 are multiplexed down to two LAB clock signals and one LAB clear signal Other control signal types route from the global clock netw
221. e is allowed to take place WREN must be issued to set WEN in the status register to 1 If the interface is in read only mode WREN does not have any effect on WEN since the status register does not exist Once the WEN is set to 1 it can be reset by the WRDI instruction the WRITE and SECTOR ERASE instruction will not reset the WEN bit WREN is issued through the following sequence as shown in Figure 9 33 1 nCSis pulled low 2 Opcode 00000110 is transmitted into the interface to set WEN to 1 in the status register 3 After the transmission of the eighth bit of WREN the interface is in wait state waiting for nCS to be pulled back to high Any transmission after this is ignored 4 nCS is pulled back to high October 2008 Altera Corporation MAX II Device Handbook 9 32 II Device Handbook Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Figure 9 33 WREN Operation Sequence nCS LN 0 1 2 3 4 5 6 7 SCK Il 8 bit Instruction XX MSB so High Impendance WRDI Write Disable After the is programmed WRDI be issued to set WEN back to 0 disabling WRITE and preventing inadvertent writing to the UFM WRDT is issued through the following sequence as shown in Figure 9 34 1 nCS is pulled low 2 Opcode 00000100 is transmitted to set WEN to 0 in the status
222. e is shown in Figure 2 16 The interface regions for EPM570 1270 and EPM2210 devices are shown in Figure 2 17 October 2008 Altera Corporation Chapter 2 MAX II Architecture User Flash Memory Block Figure 2 16 EPM240 UFM Block LAB Row Interface Note 1 2 21 Note to Figure 2 16 CFM Block UFM Block PROGRAM ERASE OSC ENA RTP BUSY DRDin DRCLK DRSHFT ARin ARCLK ARSHFT DRDout 056 BUSY LAB LAB LAB 1 The UFM block inputs and outputs can drive to from all types of interconnects not only DirectLink interconnects from adjacent row LABs October 2008 Altera Corporation MAX II Device Handbook 2 22 Figure 2 17 EPM570 1270 and EPM2210 UFM Block LAB Row Interface Chapter 2 MAX II Architecture MultiVolt Core CFM Block RTP BUSY BUSY 05 DRDout DRDin DRDCLK DRDSHFT ARDin LAB eee PROGRAM ERASE OSC_ENA ARCLK ARSHFT UFM Block LAB eee LAB eee MultiVolt Core The MAX architecture supports the MultiVolt core feature which allows MAX II devices to support multiple V levels on the Vecnr supply An internal linear voltage regulator provides the necessary 1 8 V internal voltage supply to the device The voltage regulator supports 3 3 V or 2 5 V supplies on its inputs to supply the 1 8 V internal voltage to the device as shown in Figure 2 18 The voltage regulator
223. eal time ISP operation for gated control of this self enabled OSC output condition 57 The internal oscillator is not enabled all the time The internal oscillator for the program erase operation is only activated when the flash memory block is being programmed or erased During the READ operation the internal oscillator is activated whenever the flash memory block is reading data Instantiating the Oscillator without the UFM You can use the IO MAX IT oscillator megafunction selection in the MegaWizard Plug In Manager to instantiate the UFM oscillator if you intend to use this signal without using the UFM memory block Figure 9 4 shows the altufm_osc megafunction instantiation in the Quartus II software Figure 9 4 The Quartus 11 altufm_osc Megafunction altufm osc This megafunction is in the I O folder on page 2a of the MegaWizard Plug In Manager as shown in Figure 9 5 You can start the MegaWizard Plug In Manager on the Tools menu October 2008 Altera Corporation MAX II Device Handbook 9 8 Chapter 9 Using User Flash Memory in MAX II Devices UFM Functional Description Figure 9 5 Selecting the altufm osc Megafunction in the MegaWizard Plug In Manager MegaWizard Plug In Manager page 2a Which megafunction would you like to customize which device family will you be MAX II ing Select a megafunction from the list below Gi Arithmetic Which type of output file do you want to create Commu
224. easured explicitly All internal parameters are shown in italic type Table 16 2 defines the internal timing microparameters for the MAX II device family Table 16 2 Internal Timing Microparameters Part 1 of 2 Parameter Description lur LE combinational LUT delay for data in to data out Combinational path delay The delay from the time when combinational logic signal from the LUT bypasses the LE register to the time it becomes available at the LE output tour LE register clear delay The delay from the assertion of the register s asynchronous clear input to the time the register output stabilizes at logical low tore LE register preset delay The delay from the assertion of the register s asynchronous preset input to the time the register output stabilizes at logical high tsu LE register setup time before clock The time required for a signal to be stable at the register s data and enable inputs before the register clock rising edge to ensure that the register correctly stores the input data ty LE register hold time after clock The time required for a signal to be stable at the register s data and enable inputs after the register clock s rising edge to ensure that the register correctly stores the input data too LE register clock to output delay The delay from the rising edge of the register s clock to the time the data appears at the register output tc Register control delay The time
225. ecember 2004 m Added a paragraph to page 2 15 version 1 2 June 2004 m Added CFM acronym Corrected Figure 2 19 version 1 1 October 2008 Altera Corporation MAX II Device Handbook 2 34 Chapter 2 MAX II Architecture Document Revision History MAX II Device Handbook October 2008 Altera Corporation 3 JTAG and In System Programmability ANU S n AN Introduction This chapter discusses how to use the IEEE Standard 1149 1 Boundary Scan Test BST circuitry in MAX II devices and includes the following sections m IEEE Std 1149 1 JTAG Boundary Scan Support on page 3 1 m In System Programmability on page 3 4 IEEE Std 1149 1 JTAG Boundary Scan Support All MAX II devices provide Joint Test Action Group boundary scan test BST circuitry that complies with the IEEE Std 1149 1 2001 specification JTAG boundary scan testing can only be performed at any time after Vo and all Veco banks have been fully powered and a tome amount of time has passed MAX II devices can also use the JTAG port for in system programming together with either the Quartus software or hardware using Programming Object Files pof JamTM Standard Test and Programming Language STAPL Files jam or Jam Byte Code Files jbc JTAG pins support 1 5 V 1 8 V 2 5 V or 3 3 V I O standards The supported voltage level and standard are determined by the V cio of the bank where it resides The dedicated JTAG pi
226. ect the configuration mode Base or Extended for SPI on this page You can specify the initial content of the UFM block in page 4 of the altufm MegaWizard Plug In Manager as discussed in Creating Memory Content File on page 9 40 October 2008 Altera Corporation MAX II Device Handbook 9 36 Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Figure 9 39 Page 3 altufm MegaWizard Plug In Manager MegaWizard Plug In Manager ALTUFM page 3 of 5 Currently selected device Family MAX II What is the interface protocol 2 None Interface type SPI Parallel Serial Peripheral Interface SPI 2 12C What is the access mode for the user Flash memory Read Write Read Only What is the configuration mode for SPI protocol 2 Base mode Uses 8 bit address and data Extended mode Uses 16 bit address and data C Use the oscillator output port 135 lut 1 maxii ufm 1 TRI Cancel lt Back Next gt Finish L gt The UFM block s internal oscillator is always running when the altufm spi megafunction is instantiated for read write interface UFM block s internal oscillator is disabled when the a1tu m spi megafunction is instantiated for read only interface Parallel Interface This interface allows for parallel communication between the UFM block and outside logic Once the READ request WRITE request or ERASE request is asserted act
227. ecture can test pin connections without using physical test probes and capture functional data while a device is operating normally Boundary scan cells in a device can force signals onto pins or capture data from pin or core logic signals Forced test data is serially shifted into the boundary scan cells Captured data is serially shifted out and externally compared to expected results Figure 13 1 shows the concept of boundary scan testing Figure 13 1 IEEE Std 1149 1 Boundary Scan Testing Boundary Scan Cell Serial Data In Pin Signal Serial Data Out Interconnection to Be Tested J TAG Device 1 TAG Device 2 This chapter discusses how to use the IEEE Std 1149 1 BST circuitry in MAX II devices The topics are as follows m IEEE Std 1149 1 BST Architecture on page 13 2 m IEEE Std 1149 1 Boundary Scan Register on page 13 3 TEEE Std 1149 1 BST Operation Control on page 13 6 I O Voltage Support in JTAG Chain on page 13 15 BST for Programmed Devices on page 13 15 Disabling IEEE Std 1149 1 BST Circuitry on page 13 16 Guidelines for IEEE Std 1149 1 Boundary Scan Testing on page 13 16 Boundary Scan Description Language BSDL Support on page 13 17 October 2008 Altera Corporation MAX II Device Handbook 13 2 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices IEEE Std 1149 1 BST Architecture In addition
228. ed 8Speed Grade Grade Grade Grade Grade Grade Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Min Max Unit loo Worst case pin 10pF 54 70 87 95 15 1 177 ns to pin delay through 1 look up table LUT looo Best case pin 10 pF 87 48 59 57 77 85 ns to pin delay through 1 LUT tsu Global clock 12 15 719 22 39 44 ns setup time ty Global clock 0 0 0 0 0 0 ns hold time too Global clock to 10 pF 2 0 45 20 58 2 0 7 1 2 0 67 2 0 82 20 8 7 ns output delay tou Global clock 166 216 266 253 335 1339 ps high time to Global clock 166 216 266 253 335 1339 ps low time lo Minimum 33 40 50 154 81 84 ns global clock period for 16 bit counter August 2009 Altera Corporation MAX II Device Handbook 5 20 Chapter 5 DC and Switching Characteristics Timing Model and Specifications Table 5 24 EPM570 Global Clock External 1 0 Timing Parameters Part 2 of 2 II MAX IIG 112 3 Speed 4 Speed 5 Speed 6 Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade Symbol Parameter Condition Min Max Min Min Max Min M
229. ed out of TDO on the falling edge of the same TCK pulse October 2008 Altera Corporation MAX II Device Handbook 13 14 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices IEEE Std 1149 1 BST Operation Control IDCODE Instruction Mode Ls The IDCODE instruction mode is used to identify the devices in an IEEE Std 1149 1 chain When IDCODE is selected the device identification register is loaded with the 32 bit vendor defined identification code The device ID register is connected between the TDI and TDO ports and the device IDCODE is shifted out IDCODE for MAX II devices are listed in the JTAG and In System Programmability chapter in the MAX II Device Handbook USERCODE Instruction Mode The USERCODE instruction mode is used to examine the user electronic signature UES within the devices along an IEEE Std 1149 1 chain When this instruction is selected the device identification register is connected between the TDI and TDO ports The user defined UES is shifted into the device ID register in parallel from the 32 bit USERCODE register The UES is then shifted out through the device ID register The USERCODE information is available to the user only after the device is configured successfully The non volatile USERCODE data is written to the configuration flash memory CFM block and then written to the SRAM at power up The USERCODE instruction reads the data values from the SRAM When u
230. ed to read 16 bit wide data You can use DRCLK to control the read time or disable the data register by discontinuing the DRCLK clock pulse Figure 9 7 shows the UFM control waveforms during read mode October 2008 Altera Corporation MAX II Device Handbook 9 10 Chapter 9 Using User Flash Memory in MAX II Devices UFM Operating Modes The UFM block can also perform stream read operation reading continuously from the UFM using the address increment feature Stream read mode is started by loading the base address into the address register DRSHFT must then be asserted low at the first rising edge of DRCLK to load data into the data register from the address pointed to by the address register DRSHFT will then assert high to shift out the 16 bit wide data with the MSB out first Figure 9 8 shows the UFM control waveforms during stream read mode Figure 9 7 UFM Read Waveforms ARSht 9 Address Bits tau tasun ARCIK Ne LX ARDin X X X DRShft ps Key 16 Data Bits top _ DRCIK DRDin bco DRDout X X XX SCEA XX XXX XXX XX X Erase Busy Figure 9 8 UFM Stream Read Waveforms ul EN ARS hft 9 Address Bits X A CN ON ff om ARDin X X X DRS hft 16 Data Bits aa DRDin DRDout x
231. efault DO REAL TIME ISP When set 1 the real time ISP feature is enabled for the ISP action being executed When set 0 the device uses normal ISP mode for any operations DO READ USERCODE When set 1 the player returns the JTAG USERCODE register information from the device II Device Handbook Executing the Jam file from a command prompt requires that an action is specified using the a option as shown in the following example jam aPROGRAM filename This command programs the entire MAX II device with the Jam file specified in the filename You can execute the optional procedures with its associated actions by using the d option as shown in the following example jam aPROGRAM dDO BYPASS UFM 1 dDO REAL TIME ISP 1 filename This command programs the MAX II block only with real time ISP enabled i e the device remains in user mode during the entire process The JBC player uses the same format except for the executable name The Player returns a status code of type JBI RETURN or integer This value indicates whether the action was successful returns 0 jbi_execute canreturn any one of the following exit codes in Table 14 8 as defined in the Jam Standard Test and Programming Language Specification October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor 14 17 Updating Devices Using Jam Table 14 8 Exit Codes
232. egaWizard Plug In Manager selecting none for the interface protocol By selecting none all the other options are grayed out or unavailable to you However you still can specify the initial content of the UFM block on page 4 of the altufm MegaWizard Plug In Manager as discussed in Creating Memory Content File on page 9 40 Figure 9 44 Page 3 altufm MegaWizard Plug In Manager None MegaWizard Plug In Manager ALTUFM page 3 of 5 Flash Memory Version 7 2 Currently selected device Family What is the interface protocol None Parallel 2 Serial Peripheral Interface SPI 2 c L Use arclkena port clock enable for arclk C Use drclkena port clock enable for drclk 1 MAX II Cancel lt Back Next gt Finish Creating Memory Content File You can initialize the content of the UFM through a memory content file Quartus II software supports two types of initial memory content file format Memory Initialization File mif and Hexadecimal File hex A new memory content file for the UFM block can be created by clicking New on the File menu Select the HEX file or MIF in the Other Files tab Figure 9 45 II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices Creating Memory Content File Figure 9 45 Create New File Dialog Box 9 41 Device Design Files Other Files AHDL Include File Block
233. eline FineLine 100 Pin 144 FineLine FineLine FineLine FineLine Device BGA 1 BGA 1 BGA TQFP TQFP BGA 1 BGA 1 BGA BGA 240 80 80 80 EPM240G EPM570 76 76 76 116 160 160 EPM570G EPM1270 116 212 212 EPM1270G EPM2210 204 272 EPM2210G EPM240Z 54 80 EPM570Z 76 116 160 Note to Table 1 3 1 Packages available in lead free versions only Table 1 4 MAX II TQFP FineLine BGA and Micro FineLine BGA Package Sizes 68 Pin 100 Pin 144 Pin 256 Pin Micro Micro 100 Pin Micro Micro 256 Pin 324 Pin FineLine FineLine FineLine 100 Pin 144 Pin FineLine Fineline FineLine FineLine Package BGA BGA BGA TQFP TQFP BGA BGA BGA BGA Pitch mm 0 5 0 5 1 0 5 0 5 0 5 0 5 1 1 Area mm2 25 36 121 256 484 49 121 289 361 Length x width 5x5 6 x6 11x11 16x16 22x22 7x7 11 x 11 17 x17 19 x 19 mm x mm August 2009 Altera Corporation MAX II Device Handbook 1 4 Chapter 1 Introduction Referenced Documents MAX II devices have an internal linear voltage regulator which supports external supply voltages of 3 3 V or 2 5 V regulating the supply down to the internal operating voltage of 1 8 V MAXIIG and MAX IIZ devices only accept 1 8 V as the external supply voltage MAXIIZ devices are pin compatible with MAX IIG devices in the 100 pin Micro FineLine
234. emory content file MAX II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory in MAX Il Devices 9 43 Creating Memory Content File Figure 9 48 Page 4 of the altufm Megafunction MegaWizard Plug In Manager ALTUFM page 4 of 6 Do you want to specify the initial content of the memory 2 No leave it blank Yes use this file For the memory content You can use a Hexadecimal Intel Format File hex or a Memory Initialization File rnif Interface type SPI File name data hex Browse 556MHz What is the oscillator frequency for the User Flash Memory for simulation only What is the erase time for the User Flash Memory for simulation only 500000 ns What is the program time for the User Flash Memory for simulation only 1600 ns 135 lut 1 maxii 1 TRI Cancel lt Back Next gt Finish Memory Initialization for the altufm parallel Megafunction For the parallel interface if a HEX file is used to initialize the memory content for the altufm megafunction you have to fully specify all 16 bits in each memory address regardless of the data width selected If your data width is less than 16 bits wide your data must be placed in the MSBs of the data word and the remaining LSBs must be padded with 1 s For an example if address width 3 and data width 8 are selected for the altufm parallel megafunction the HEX
235. entation Operating Conditions Each MAX II device has several parametric ratings or operating conditions that are required for proper operation Although MAX II devices can exceed these conditions when in user mode and still operate correctly these conditions should not be exceeded during in system programming Violating any of the operating conditions during in system programming can result in programming failures or incorrectly programmed devices V cio of all 1 0 banks V ecmr of the device must be fully powered up for ISP to function ISP Voltage The and Veco level specified in the device operating conditions table must be maintained on the Vcc and Veco pins during in system programming to ensure that the device s flash cells are programmed correctly The Veanr and V cio specification applies for both commercial and industrial temperature grade devices October 2008 Altera Corporation MAX II Device Handbook 11 2 Chapter 11 In System Programmability Guidelines for MAX II Devices General ISP Guidelines Input Voltages The MAX II Device Family Data Sheet lists the MAX II device input voltage specification in the absolute maximum ratings and the recommended operating conditions tables The input voltages in the absolute maximum rating table refers to the maximum voltage which the device can tolerate before risking permanent damage The recommended operating conditions table specify the voltage range for safe
236. es 6 0 TRI are shown in Courier 1 2 3 and Numbered steps are used in a list of items when the sequence of the items is 8 D C etc important such as the steps listed in a procedure Hm Bullets are used in a list of items when the sequence of the items is not important The checkmark indicates procedure that consists of one step only Ls The hand points to information that requires special attention A caution calls attention to a condition or possible situation that can damage or destroy the product or the user s work gt E gt gt ly gt J D 2 warning calls attention to a condition or possible situation that can cause injury to the user The angled arrow indicates you should press the Enter key The feet direct you to more information on a particular topic II Device Handbook August 2009 Altera Corporation Section MAX II Device Family Data p AN e Sheet This section provides designers with the data sheet specifications for MAX devices The chapters contain feature definitions of the internal architecture Joint Test Action Group JTAG and in system programmability ISP information DC operating conditions AC timing parameters and ordering information for MAX II devices This section includes the following chapters Chapter 1 Introduction Chapter 2 MAX Architecture Chapter 3 JTAG and I
237. es fast propagation delay and clock to output times Provides four global clocks with two clocks available per logic array block LAB UFM block up to 8 Kbits for non volatile storage MultiVolt core enabling external supply voltages to the device of either 3 3 V 2 5 V or 1 8 V m MultiVolt I O interface supporting 3 3 V 2 5 V 1 8 V and 1 5 V logic levels m Bus friendly architecture including programmable slew rate drive strength bus hold and programmable pull up resistors m Schmitt triggers enabling noise tolerant inputs programmable per pin m I Os are fully compliant with the Peripheral Component Interconnect Special Interest Group PCI SIG PCI Local Bus Specification Revision 2 2 for 3 3 V operation at 66 MHz m Supports hot socketing m Built in Joint Test Action Group JTAG boundary scan test BST circuitry compliant with IEEE Std 1149 1 1990 m ISPcircuitry compliant with IEEE Std 1532 August 2009 Altera Corporation MAX II Device Handbook Chapter 1 Introduction Features Table 1 1 shows the MAX II family features Table 1 1 MAX II Family Features 240 EPM570 EPM1270 EPM2210 Feature EPM240G 5706 EPM1270G 22106 2407 5707 LEs 240 570 1 270 2 210 240 570 Typical Equivalent Macrocells 192 440 980 1 700 192 440 Equivalent Macrocell Range 128 to 240 24010570 570 to 1 270 1 270 to 2 210 12810240 24010570 UFM Size bits 8 192 8 192 8 192 8 192 8 192 8
238. evice operation while tri stating all of the 1 0 pins October 2008 Altera Corporation MAX II Device Handbook 3 2 Chapter 3 JTAG and In System Programmability IEEE Std 1149 1 JTAG Boundary Scan Support Table 3 1 MAX II JTAG Instructions Part 2 of 2 JTAG Instruction Instruction Code Description CLAMP 1 00 0000 1010 Places the 1 bit bypass register between the TDI and TDo pins which allows the boundary scan test data to pass synchronously through selected devices to adjacent devices during normal device operation while holding 1 0 pins to a state defined by the data in the boundary scan register USERO 00 0000 1100 This instruction allows you to define the scan chain between TDI and in the MAX II logic array This instruction is also used for custom logic and JTAG interfaces USER1 00 0000 1110 This instruction allows you to define the scan chain between TDI and TDo in the MAX II logic array This instruction is also used for custom logic and JTAG interfaces IEEE 1532 2 IEEE 1532 ISC instructions used when programming a MAX II device instructions via the JTAG port Notes to Table 3 1 1 HIGHZ CLAMP and EXTEST instructions do not disable weak pull up resistors or bus hold features 2 These instructions are shown in the 1532 BSDL files which will be posted on the Altera website at www altera com when they are available Unsupported JTAG instructions should not be
239. evice Handbook October 2008 Altera Corporation 11 In System Programmability S R A Guidelines for MAX Il Devices MII51013 1 7 Introduction As time to market pressure increases design engineers require advanced system level products to ensure problem free development and manufacturing Programmable logic devices PLDs with in system programmability ISP can help accelerate development time facilitate in field upgrades simplify the manufacturing flow lower inventory costs and improve printed circuit board testing capabilities Altera ISP capable II devices be programmed and reprogrammed in system via the IEEE Std 1149 1 Joint Test Action Group JTAG interface This interface allows MAX II devices to be programmed and the PCB to be functionally tested in a single manufacturing step saving testing time and assembly costs This chapter describes guidelines you should follow to design successfully with ISP including m General ISP Guidelines on page 11 1 m IEEE Std 1149 1 Signals on page 11 4 Sequential versus Concurrent Programming on page 11 6 15 Troubleshooting Guidelines on page 11 7 ISP via Embedded Processors on page 11 9 ISP via In Circuit Testers on page 11 10 General ISP Guidelines This section provides guidelines that help you design successfully for ISP capable MAX II devices These guidelines should be used regardless of your specific design implem
240. f 2 are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device Interface Operating Size Voltage V Type Device Bits SCI SPI 2 Wire 3 Wire PC Microwire fmax 1 EEPROM M24C04 W 4 096 v 400 kHz 2 5 to 5 5 EEPROM M24C02 W 2 048 v 400 2 510 5 5 EEPROM M24C08 W 8 192 v 400 kHz 2 5 to 5 5 EEPROM M24C04 L 4 096 v 400 kHz 2 2t0 5 5 EEPROM M24C02 L 2 048 v 400 kHz 2 2t0 5 5 EEPROM M24C08 L 8 192 v 400 kHz 2 2t0 5 5 EEPROM M24C04 R 4 096 v 400 kHz 1 8 to 5 5 EEPROM M24C02 R 2 048 v 400 kHz 1 8 to 5 5 EEPROM M24C08 R 8 192 v 400 kHz 1 8 to 5 5 EEPROM ST24W04 4 096 100 kHz 3 0 to 5 5 EEPROM ST25W04 4 096 v 100 kHz 2 5 to 5 5 EEPROM ST24C04 4 096 v 100 kHz 3 0 to 5 5 EEPROM 5725604 4 096 v 100 kHz 2 5 to 5 5 EEPROM M93C76 W 8192 2 MHz 2 5 to 5 5 EEPROM M93C66 W 4 096 v 2 MHz 2 5 to 5 5 EEPROM M93C56 W 2 048 2 MHz 2 5 to 5 5 EEPROM M93C76 R 8 192 2 MHz 1 8 to 5 5 EEPROM M93C66 R 4
241. fastest Product Line Suffix Operating Temperature Indicates device type G 1 8 low power device C Commercial temperature T 0 C to 85 C gt 1 8 V Vecwr Zero power device I Industrial temperature T 40 C to 100 C Blank no identifier 2 5 V or 3 3 V Veciyq device A Automotive temperature tr 40 C to 125 C Package Type T Thin quad flat pack TQFP FineLine BGA M Micro FineLine BGA Pin Count Number of pins for a particular package August 2009 Altera Corporation MAX II Device Handbook 6 2 Referenced Documents Document Revision History Table 6 1 Document Revision History This chapter references the following document Table 6 1 shows the revision history for this chapter Chapter 6 Reference and Ordering Information Referenced Documents m Package Information chapter in the MAX II Device Handbook Date and Revision Changes Made Summary of Changes August 2009 m Updated Figure 6 1 Added information for speed version 1 6 grade 8 October 2008 m Updated New Document Format version 1 5 December 2007 m Added Referenced Documents section Updated document with version 1 4 Updated Figure 6 1 MAX 112 information December 2006 m Added document revision history version 1 3 October 2006 m Updated Figure 6 1 version 1 2 June 2005 m Removed Dual Marking section version 1 1
242. for one device chain running the utility allows you to specify the number of vectors per file The amount of memory used by the resulting files varies depending on the data The Agilent 3070 digital compiler looks for repeating patterns of vectors and optimizes the directory and sequences RAM on the tester control card to apply the maximum number of vectors before re loading the files The number of vectors ina compiled PCF File ranges from 100 000 to over one million depending on the size and density of the targeted devices You can download the svf2pcf conversion utility from the Agilent ISP Support website at www altera com Step 4 Create Executable Tests from Files Creating digital tests for programming a chain of devices with the Agilent 3070 tester requires the following steps 1 Create the library for the target device or scan chain 2 Run the Test Consultant 3 Create digital tests 4 Create the wirelist information for the tests 5 Modify the test plan Create the Library for the Target Device or Scan Chain The initial program development for the board contains a setup only node test library for the ISP boundary scan chain interface The test library ensures that Agilent 3070 tester resources are reserved in the test fixture for programming the targeted devices If only one target device is on the board and it is not part of a boundary scan chain isolated use a pin library otherwise use a node library If using a pi
243. g Among LEs in the LAB LUT Chain Register Chain Routing to Routing to Adjacent Adjacent LE LE s Register Input Local Interconnect The C4 interconnects span four LABs up or down from a source LAB Every LAB has its own set of C4 interconnects to drive either up or down Figure 2 12 shows the C4 interconnect connections from an LAB in a column The C4 interconnects can drive and be driven by column and row IOEs For LAB interconnection a primary LAB or its vertical LAB neighbor can drive a given C4 interconnect C4 interconnects can drive each other to extend their range as well as drive row interconnects for column to column connections October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 15 MultiTrack Interconnect Figure 2 12 C4 Interconnect Connections Note 1 64 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect Driving Up LAB Row Interconnect Adjacent LAB can drive onto neighboring LAB s C4 interconnect C4 Interconnect Driving Down Interconnect i i E Note to Figure 2 12 1 Each C4 interconnect can drive eithe
244. g the JTAG Chain to the Embedded Processor 14 1 Example Interface PLD Design 14 2 Board Layout eae Cbr ui done e FU det 14 3 Signal Trace Protection and Integrity 14 4 Pull Down Resistors on TCK eer csere red Y aperta s 14 4 JL AG Signal 14 4 External sense en ELE eret Dota bonae dieci end ndi ete eden 14 4 II Device Handbook August 2009 Altera Corporation Software Development ss eere Eee 14 4 Files Jam 14 5 ASCII Text Files jam te RP we Cie 14 5 Jam Byte Code Files JBC 4 eR EUR e E RR ERU d eb eq 14 5 Generating Jam Files osse sete ERROR ERU hee CER APER a de err HER a Ban 14 5 Using Jam Files with the MAX II User Flash Memory Block 14 7 Jam PLAYERS Gh Ur Prep dad ed doce taeda acute un 14 7 Jam Player Compatibility sssi 25 ie EE UR RT EE ec e Ee eq d end 14 7 Jam STAPL Byte Code Player 14 7 Porting the Jam STAPL Byte CodePlayer 14 8 Jam STAPL
245. gic gt Note to Figure 16 7 1 tsu tn N x tra 4 M X tc4 4 iur tacos te tsu Figure 16 8 Setup and Hold Time Note 1 2 4 Combinational D Logic Note to Figure 16 8 1 th tros te tin N x tgj A M X tp4 4 tur thy For Figure 16 4 through Figure 16 8 the constants and M are subject to change according to the position of LAB in the entire device for combinational logic implementation Programmable Input Delay The programmable input delay provides an option to add a delay to the input pin guaranteeing a zero hold time You can set this option in the Assignment Editor Assignments menu on a pin by pin basis The following procedure shows how to turn on the input delay for the selected input pin in the Quartus II software 1 Select input pin name in the design file 2 Right click and select Locate in the Assignment Editor 3 Double click the cell under Assignment Name and select Input Delay from Pin to Internal Cells in the pull down list 4 Double click the Value cell to the right of the assignment name just made and enter 1 5 On the File menu click Save Timing Model versus Quartus Il Timing Analyzer Hand calculations based on the timing model provide a good estimate of a design s performance However the Quartus II Timing Analyzer always provides the most accurate information on design performance because it takes into account secondary factors
246. gic SOCHON co seen piden occae ot uM td LE LI DA 17 6 UEM SGCHOD arnica A eere ER HEP CER teens See tebe ada RUP I tante 17 8 Section 5 onze recte estos Da teet Ec abe an ee did 17 8 Other Input Information 1 1 17 11 Set LOS OIC 17 11 Reset lm 17 12 Importing the Quartus II Early Power Estimator File 17 12 Power Estimation Summary 1 4 2 5 17 13 eei e E ERE RET E 17 13 Thermal Analysis pee teehee bes pq ROS eho ea 17 14 Power Supply C HEEeDE S oes cett eH tak te ee 17 15 Power Saving Techniques 17 15 Conclusion es 17 16 Referenced Documents be be E RUPES RR PRA 17 16 Document Revision History 2 17 17 II Device Handbook August 2009 Altera Corporation Chapter Revision Dates RYA Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 The chapters in this book MAX II Device Handbook were revised on the
247. gister Waveforms TCK heed lowe TMS 5 TDI TDO 4 LLL SHIFT IR X X X X is SHIFT_DR Y TAP STATE IR pu Data stored in After EXIT1 DR it register data has been Instruction Code UPDATE_IR CAPTURE DR Doundary scan Bera pis UPDATE DR register is shifted entered into TDI will out of TDO Shift out of TDO BYPASS Instruction Mode The BYPASS instruction mode is activated with an instruction code made up of only ones The waveforms in Figure 13 12 show how scan data passes through a device once the TAP controller is in the SHIFT DR state In this state data signals are clocked into the bypass register from TDI on the rising edge of TCK and out of TDO on the falling edge of the same clock pulse Figure 13 12 BYPASS Shift Data Register Waveforms TCK lose TMS Pn TDI Bit1 X Bit2 X Bit3 X eee TDO 1 X Bit2 X ee X Bitn A SHIFT_IR X X X X J SHIFT_DR X X 2 7 7 TAPESTATE EXIT SELECT DR SCAN Data shifted into TDI on DR Instruction Code UPDATE IR CAPTURE DR the rising edge of TCK is UPDATE DR shift
248. gnal setup to address register clock tan Address register shift signal hold from address register clock Tos Address register data in setup to address register clock Lou Address register data in hold from address register clock toss Data register shift signal setup to data register clock los Data register shift signal hold from data register clock toos Data register data in setup to data register clock ou Data register data in hold from data register clock toco Delay incurred from the data register clock to data register output when shifting the data out nm PROGRAM signal to data clock hold time Maximum delay between PROGRAM rising edge to UFM Busy signal rising edge Minimum delay allowed from UFM Busy signal going low to PROGRAM signal going low trex Maximum length of busy pulse during a program tee Minimum ERASE signal to address clock hold time October 2008 Altera Corporation MAX II Device Handbook 16 4 Chapter 16 Understanding Timing MAX II Devices Timing Models Table 16 3 Internal Timing Microparameters for MAX II UFM Part 2 of 2 Parameter Description tes Maximum delay between ERASE rising edge to UFM Busy signal rising edge toe Minimum delay allowed from UFM Busy signal going low to ERASE signal going low taux Maximum length ofbusy pulse during an erase Tu Maximum read access time The delay incurred between the DRSHF T signal going low to the first bit of data observe
249. he data register is 16 bits wide with four control signals DRSHFT DRCLK DRDin and DRDout DRSHFT distinguishes between clock edges that move data serially from DRDin or to DRDout and clock edges that latch parallel data from the sectors If the DRSHFT signal is high a clock edge moves data serially through the registers from DRDin to DRDout If the DRSHFT signal is low a clock edge captures data from the UFM sector pointed by the address register in parallel The MSB is the first bit that will be seen at DRDout The data register DRSHFT signal will also be used to enable the UFM for reading data When the DRSHFT signal is low the UFM latches data into the data register Figure 9 3 shows the UFM data register October 2008 Altera Corporation MAX II Device Handbook 9 6 Chapter 9 Using User Flash Memory in MAX II Devices UFM Functional Description Figure 9 3 UFM Data Register MAX II UFM Block Food Data Register P DRDout D14 015 DRDin P gt gt D1 D2 gt D3 D5 D6 on DN D9 oul D11 15 DRCLK MSB UFM Program Erase Control Block Oscillator II Device Handbook The UFM program erase control block is used to generate all the control signals necessary to program and erase the UFM block independently This reduces the number of LEs necessary to implement a UFM controller in t
250. he 1 0 standard on the clock input pin The 16 bit counter critical delay performs faster than this global clock input pin maximum frequency MAX II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics 5 21 Timing Model and Specifications Table 5 26 shows the external I O timing parameters for EPM2210 devices Table 5 26 2210 Global Clock External 1 0 Timing Parameters II MAX IIG 3 Speed Grade 4 Speed Grade 5 Speed Grade Symbol Parameter Condition Min Max Min Max Min Max Unit Too Worst case pin to pin delay 10 pF 7 0 9 1 11 2 ns through 1 look up table LUT Best case pin to pin delay 10 pF 3 7 4 8 5 9 ns through 1 LUT tsu Global clock setup time 1 2 1 5 1 9 ns ti Global clock hold time 0 0 0 ns tco Global clock to output delay 10 pF 2 0 4 6 2 0 6 0 2 0 7 4 ns Global clock high time 166 216 266 ps ter Global clock low time 166 216 266 ps tonr Minimum global clock 3 3 4 0 5 0 ns period for 16 bit counter Ton Maximum global clock 304 0 247 5 201 1 MHz frequency for 16 bit counter 1 Note to Table 5 26 1 The maximum frequency is limited by the 1 0 standard on the clock input pin The 16 bit counter critical delay performs faster than this global clock input pin maximum frequency External Timing 1 0 Delay Adders 3 3
251. he TMS are connected to Veco and Veco is not powered up the JTAG signals are left floating Thus any transition on TCK can cause the state machine to transition to an unknown JTAG state leading to incorrect operation when V c is finally powered up To disable the JTAG state during the power up sequence TCK should be pulled low to ensure that an inadvertent rising edge does not occur on TCK Power On Reset Conclusion II Device Handbook For information about Power On Reset POR refer to the Hot Socketing and Power On Reset in MAX II Devices chapter in the MAX II Device Handbook MAX II devices have MultiVolt I O support allowing 1 5 V 1 8 V 2 5 V and 3 3 V devices to interface directly with MAX II devices without causing voltage conflicts In addition MAX II devices can interface with 5 0 V devices by slightly modifying the external hardware interface and enabling I O clamp diodes via the Quartus II software This MultiVolt capability also enables the device core to run at its core voltage Vcany while maintaining I O pin compatibility with other devices Altera has taken further steps to make system design easier by designing devices that allow Veanr and Veco to power up in any sequence and by incorporating support for hot socketing October 2008 Altera Corporation Chapter 8 Using MAX II Devices Multi Voltage Systems Referenced Documents Referenced Documents This chapter references the follo
252. he address is received last As the UFM block can take only nine bits of address maximum the first seven address bits received are discarded 4 Data is transmitted for as many words as needed by the slave device through 50 for READ operation When the end of the UFM storage array is reached the address counter rolls over to the start of the UFM to continue the READ operation 5 nCSis pulled back to high to indicate the end of transmission For SPI Base mode the READ operation is always performed through the following sequence in SPI 1 nCSis pulled low to indicate the start of transmission 2 An8 bit READ opcode 00000011 is received from the master device followed by an 8 bit address If internal programming is in progress the READ operation is ignored and not accepted 3 Data is transmitted for as many words as needed by the slave device through 50 for READ operation The internal address pointer automatically increments until the highest memory address is reached address 255 only since the UFM sector 0 is used The address counter will not roll over once address 255 is reached The 50 output is set to high impedance Z once all the eight data bits from address 255 has been shifted out through the SO port 4 nCSis pulled back to high to indicate the end of transmission Figure 9 26 READ Operation Sequence for Extended Mode ncS E 0123 4567 8 91011 20 21 22 23 24 25 26 27 36 37 38 39
253. he logic array It also guarantees correct timing of the control signals to the UFM A rising edge on either PROGRAM or ERASE causes this control signal block to activate and begin sequencing through the program or erase cycle At this point for a program instruction whatever data is in the data register will be written to the address pointed to by the address register Only sector erase is supported by the UFM Once an ERASE command is executed this control block will erase the sector whose address is stored in the address register When the PROGRAM or ERASE command first activates the program erase control block the BUSY signal will be driven high to indicate an operation in progress in the UFM Once the program or erase algorithm is completed the BUSY signal will be forced low OSC ENA one of the input signals in the UFM block is used to enable the oscillator signal to output through the OSC output port You can use this OSC output port to connect with the interface logic in the logic array It can be routed through the logic array and fed back as an input clock for the address register ARCLK and the data register DRCLK The output frequency of the OSC port is one fourth that of the oscillator frequency As a result the frequency range of the OSC port is 3 3 to 5 5 MHz The maximum clock frequency accepted by ARCLK and DRCLK is 10 MHz and the duty cycle accepted by the DRCLK and ARCLK input ports is approximately 45
254. he most common causes for this error are listed below m After porting the Jam Player the TDO value may be read in reversed polarity This problem may occur because the default I O code in the Jam Player assumes the use of the PC parallel port m Although the TMS and TDI signals are clocked in on the rising edge of TCK outputs do not change until the falling edge of TCK This situation causes a half TCK clock cycle lag in reading out the values If the TDO transition is expected on the rising edge the data appears to be offset by one clock m Altera recommends using registers to synchronize the output transitions In addition some processor data ports use a register to synchronize the output signals For example reading and writing to the PC s parallel port is accomplished by reading and writing to registers The use of these registers must be taken into consideration when reading and writing to the JTAG chain Incorrect accounting of these registers can cause the values to either lead or lag the expected value ISP via In Circuit Testers Conclusion MAX II devices can also be in system programmed via in circuit testers For more information about using Agilent s 3070 in circuit tester to in system program MAX II devices refer to the Using Jam STAPL for ISP via an Embedded Processor chapter in the MAX II Device Handbook The information provided in this document is based on development experiences and customer issues resolved by Altera
255. ibraries page of the Settings d box Assignments menu Your current user library directories are 8 IP MegaStore Cancel lt Next gt The altufm MegaWizard Plug In Manager has separate pages that apply to the MAX II UFM block During compilation the Quartus II Compiler verifies the altufm parameters selected against the available logic array interface options and any specific assignments MAX II Device Handbook 9 14 Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Inter Integrated Circuit Inter Integrated Circuit DC is a bidirectional two wire interface protocol requiring only two bus lines a serial data address line SDA and a serial clock line SCL Each device connected to the DC bus is software addressable by a unique address The bus is a multi master bus where more than one integrated circuit IC capable of initiating a data transfer can be connected to it which allows masters to function as transmitters or receivers The altufm_i2c megafunction features a serial 8 bit bidirectional data transfer up to 100 Kbits per second With the altufm_i2c megafunction the MAX II UFM and logic can be configured as a slave device for the PC bus The altufm megafunction s PC interface is designed to function similar to PC serial EEPROMs The Quartus II software supports three different memory sizes m 128 x8 1Kbits m 256x8 2Kbits m 512x8 4Kbits
256. ices reliability limits when the trace voltage exceeds 4 0 V To limit large current draw from the 5 0 V device R should be small enough for a fast signal rise time and large enough so that it does not violate the high level output current specifications of the devices driving the trace To compute the required value of R first calculate the model of the pull up transistors on the 5 0 V device This output resistor R can be modeled by dividing the 5 0 V device supply voltage by the Ry Vec lou Figure 8 5 shows an example of typical output drive characteristics of a 5 0 V device Figure 8 5 Output Drive Characteristics of a 5 0 v Device 150 135 120 Typical lg 90 Output Current mA 60 30 1 2 3 4 5 Vg Output Voltage V October 2008 Altera Corporation Chapter 8 Using MAX II Devices in Multi Voltage Systems 8 7 Recommended Operating Condition for 5 0 V Compatibility As shown above 5 0 V 135 mA The values usually shown in data sheets reflect typical operating conditions Subtract 20 from the data sheet value for guard band This subtraction applied to the above example gives R a value of 30 Select R so that the MAX II device s specification is not violated For example if the above device has a maximum Ig of 8 mA given the I O clamp diode VX Veco 0 7 V 3 7 V Given that the maximum supply load of a 5 0 V device is 5 5 V the value
257. ie ror d teas 2 24 I OStandards and Banks 1 2 26 PEL Compliance beer rss Reb meee eb m me 2 28 Schmitt oM UP Dei MEET 2 29 Output Enable Signals 2 29 Programmable Drive Strength 2 29 Slew Rate ete titan ak Aaa ae edet bee pede 2 30 Drar Output o ceto cea ip outa na ES 2 30 Programmable Ground Pins 2 2 2 30 Bus Hold be 2 31 Programmable Pull Up 2 31 Programmable Input 2 31 Mult Volt I O Interface seirene ers ae re XN ERE RE branle dE 2 31 Referenced Documents ecu eC E RES nera e ete 2 32 Document Revision History 2 33 Chapter 3 JTAG and In System Programmability Introduction ii cuo yas e HESS isa e ad du pe pa ti RES 3 1 IEEE Std 1149 1 JTAG Boundary Scan Support
258. ificant bit LSB output couto has a toggle rate of 10096 because the signal toggles on every clock cycle The toggle rate for the second With output cout 1 is 50 since the signal only 1000165 on every two clock cycles Consequently the toggle rate for the third TFF with output cout 2 and fourth with output cout3 are 25 and 12 5 respectively Therefore the average toggle percentage for this 4 bit counter is 100 50 25 12 5 4 46 87 5 6 MAX II Device Handbook October 2008 Altera Corporation Chapter 17 Understanding and Evaluating Power MAX II Devices 17 7 PowerPlay Early Power Estimator Inputs Table 17 3 Logic Section Information Part 2 of 2 Column Heading Description Routing Represents the power dissipation due to estimated routing Routing power is highly dependent on placement and routing which itself is a function of design complexity The values shown are representative of routing power average based on experimentation on over 100 real world designs Use the Quartus PowerPlay Power Analyzer for detailed analysis based on the routing used in your design Block Represents the power dissipation due to internal toggling of the LEs Logic block power is a function of the function implemented and relative toggle rates of the various inputs The PowerPlay Early Power Estimator spreadsheet uses an estimate based on observed behavior across over 100 real world designs Use the Quartu
259. ing Characteristics Operating Conditions Symhol Parameter Conditions Minimum Maximum Unit Vccwr 1 3 3 V supply voltage for internal logic and MAX II devices 3 00 3 60 V ISP 2 5 V supply voltage for internal logic and MAX II devices 2 375 2 625 V ISP 1 8 V supply voltage for internal logic and IIG and MAX IIZ 1 71 1 89 V ISP devices Vecio 7 Supply voltage for 1 0 buffers 3 3 V 3 00 3 60 V operation Supply voltage for 1 0 buffers 2 5 V 2 375 2 625 V operation Supply voltage for 1 0 buffers 1 8 V 1 71 1 89 V operation Supply voltage for 1 0 buffers 1 5 V 1 425 1 575 V operation Vi Input voltage 2 3 4 0 5 4 0 V Vo Output voltage 0 Vecio V T Operating junction temperature Commercial range 0 85 C Industrial range 40 100 C Extended range 5 40 125 C Notes to Table 5 2 1 II device in system programming and or user flash memory UFM programming via JTAG or logic array is not guaranteed outside the recommended operating conditions for example if brown out occurs in the system during a potential write program sequence to the UFM users are recommended to read back UFM contents and verify against the intended write data 2 Minimum DC input is 0 5 V During transitions the inputs may undershoot to 2 0 V for input currents less than 100 mA and periods shorter than 20 ns 3 During transitions the inputs may oversh
260. input LUTs configurable as a dynamic adder subtractor The first two 2 input LUTs compute two summations based on possible carry in of 1 or 0 the other two LUTs generate carry outputs for the two chains of the carry select circuitry As shown in Figure 2 8 the LAB carry in signal selects either the carry in0 or carry in1 chain The selected chain s logic level in turn determines which parallel sum is generated as a combinational or registered output For example when implementing an adder the sum output is the selection of two possible calculated sums datal data2 carry in0 datal data2 carry inl MAX II Device Handbook 2 10 Chapter 2 MAX II Architecture Logic Elements The other two LUTS use the datal and data2 signals to generate two possible carry out signals one for a carry of 1 and the other for a carry of 0 The carry inO signal acts as the carry select for the carry out0 output and carry inl acts as the carry select for the carry out1 output LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output The dynamic arithmetic mode also offers clock enable counter enable synchronous up down control synchronous clear synchronous load and dynamic adder subtractor options The LAB local interconnect data inputs generate the counter enable and synchronous up down control signals The synchronous clear and synchronous load options are LAB wide signals that affect all registers in
261. ion Chapter 9 Using User Flash Memory MAX Il Devices 9 23 Software Support for UFM Block Figure 9 22 altufm Megafunction Symbol For the 126 Interface Instantiation in the Quartus 11 Software ize altufm i2c Interface type I2C Usable flash memory size 4096 bits Figure 9 23 shows page 3 of the altufm MegaWizard Plug In Manager when selecting as the interface On this page you can choose whether to implement the read write mode or read only mode for the You also have an option to choose the memory size for the altufm_i2c megafunction as well as defining the four MSBs of the slave address default 1010 Figure 9 23 Page 3 of the altufm MegaWizard Plug In Manager 12C MegaWizard Plug In Manager ALTUFM page 3 of 6 Currently selected device Family What is the interface protocol lt gt None wp Parallel 3 Interface type 2 Serial Peripheral Interface SPI Ic What is the access mode for the user Flash memory Read Write Read Only What is the 5 of the device address in binary 1010 What is the size of the memory 4K v Resource Usage compare 111 lut 2 maxii io 1 ufm C Use the oscillator output port Cancel lt Back Next gt Finish gt The UFM block s internal oscillator is always running when the altufm i2c megafunction is instantiated fo
262. ion then sending the correct slave address with the R W bit set to 0 to the slave If the slave address matches the altufm_i2c slave acknowledges on the ninth clock pulse The master then transfers an 8 bit byte address to the UFM which acknowledges the reception of the address The master transfers the 8 bit data to be written to the UFM Once the altufm_i2c logic acknowledges the reception of the 8 bit data the master generates a stop condition The internal write from the MAX II logic array to the begins only after the master generates a stop condition While the UFM internal write cycle is in progress the altufm i2c logic ignores any attempt made by the master to initiate a new transfer Figure 9 15 shows the Byte Write sequence October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX II Devices 9 17 Software Support for UFM Block Figure 9 15 Byte Write Sequence S Slave Address RW A Byte Address A Data A P S Start Condition O write From Master to Slave P Stop Condition A Acknowledge From Slave to Master Page Write Operation Page write operation has a similar sequence as the byte write operation except that a number of bytes of data are transmitted in sequence before the master issues a stop condition The internal write from the MAX II logic array to the UFM begins only after the master generates a stop condition While the UFM i
263. ion design example refer to AN 422 Power Management in Portable Systems Using MAX II CPLDs This chapter discusses how to evaluate and manage MAX II power by using the MAX II PowerPlay Early Power Estimator spreadsheet This power estimation tool estimates the power consumption for your design based on typical conditions The MAX II board level designer can exploit the power calculator before board design and layout The MAX II PowerPlay Early Power Estimator spreadsheet is available on the Altera website at www altera com Referenced Documents MAX II Device Handbook This chapter references the following documents m AN 422 Power Management in Portable Systems Using MAX II CPLDs m PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook October 2008 Altera Corporation Chapter 17 Understanding and Evaluating Power in MAX II Devices 17 17 Document Revision History Document Revision History Table 17 10 shows the revision history for this chapter Table 17 10 Document Revision History Date and Revision Changes Made Summary of Changes October 2008 Updated New Document Format version 2 1 December 2007 m Updated Figure 17 1 Figure 17 2 and Figure 17 3 Updated document version 2 0 m Updated Table 17 1 with information about power characteristics Hi 4 information m Updated Table 17 2 Table 17 3 and Table 17 6 m Added Referenced Documents section December 2006 m Added document re
264. ion designs in addition to these serial flash capabilities This chapter provides a comprehensive listing of 2 Kbit 4 Kbit and 8 Kbit non volatile memory devices that could be potentially replaced by MAX II UFM devices Table 10 1 shows the capacity for the UFM block for all MAX II devices Table 10 1 MAX II UFM Array Size Device Total Bits Sectors Address Bits Data Width EPM240 8 192 2 4096 bits per sector 9 16 EPM570 EPM1270 EPM2210 This chapter contains the following sections m Design Considerations on page 10 1 m List of Vendors and Devices on page 10 2 Design Considerations The MAX II can be programmed erased and verified through the Joint Test Action Group JTAG port or through connections to from the logic array in accordance with IEEE Std 1532 2002 There are 13 interface signals to and from the UFM block and logic array which allow the logic array to read or write to the UFM during device user mode A reference design or user logic can be used to interface the UFM to many standard interface protocols such as Serial Communication Interface SCI Serial Peripheral Interface SPI Inter Integrated Circuit DC Microwire or other proprietary protocols Altera s Quartus II altufm megafunction provides interface logic for a subset of these interfaces parallel and SPI Any interfaces not provided by the megafunction or design examples require you to create user logic to bridge the UFM
265. ion read into the data register BUSY Output Signal that indicates when the memory is BUS v performing a PROGRAM Or ERASE instruction When it is high the address and data register should not be clocked The new PROGRAM 0r ERASE instruction will not be executed until the BUS v signal is deasserted OSC Output Output of the internal oscillator It can be used to generate a clock to control user logic with the UFM It requires an osc enable input to produce an output RTP BUSY Output This output signal is optional and only needed if the real time ISP feature is used The signal is asserted high during real time ISP and stays in the RUN STATE for 500 ms before initiating real time ISP to allow for the final read erase write operation No read write erase or address and data shift operations are allowed to be issued once the BUSY signal goes high The data and address registers do not retain the contents of the last read or write operation for the UFM block during real time ISP see the interaction between the UFM block and the logic array of MAX II devices refer to the MAX II Architecture chapter in the MAX II Device Handbook Figure 2 16 for EPM240 devices and Figure 2 17 for EPM570 1270 and EPM2210 devices II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory in MAX Il Devices 9 5 UFM Functional Description UFM Address Register
266. is highly dependent on placement and routing which itself is a function of design complexity The values shown are representative of routing power based on experimentation on over 100 real world designs Use the Quartus Il PowerPlay Power Analyzer for detailed analysis based on the routing used in your design Block Represents the power dissipation due to internal and load toggling of the 1 0 Use the Quartus Il PowerPlay Power Analyzer for accurate analysis based on the exact 1 0 configuration of your design Total Represents the total power dissipation The total power dissipation is the sum of the routing and block power lecint lccio Represents the current drawn from the lI rail Powers internal digital circuitry and routing Represents the current drawn from this bank s Vecio rail User Comment Enter any comments optional entry Other Input Information October 2008 Altera Corporation There are three other buttons below the input parameters section Set Toggle Reset and Import Quartus File as shown Figure 17 12 Figure 17 12 The Three Buttons Set Toggle Reset Import Quartus File Set Toggle Sets the toggle rate for the Logic Module and I O Module MAX II Device Handbook 11 12 MAX II Device Handbook Chapter 17 Understanding and Evaluating Power in MAX II Devices PowerPlay Early Power Estimator Inputs Reset Clears all input values in the PowerPlay Early Powe
267. is powered up with the same trace as V cco its JTAG circuitry must stay in the test logic reset state Because all TMS and TCK signals are common they must be disabled for all devices in the chain Therefore the JTAG pins must be disabled by pulling TCK low and TMS high 1 0 Pins Tri Stated during In System Programming By default all device I O pins are tri stated during in system programming In addition the MAX II device provides a weak pull up resistor during ISP The purpose of this weak pull up resistor is to eliminate the need for external pull up resistors on tri stated I O pins For pins that are used to drive signals and require a particular value during in system programming for example output enable or chip enable signals you can use the in system programming clamp feature or the real time ISP feature available for MAX II devices These two features ensure that each I O pin is clamped to a specific state during in system programming For more information refer to the In System Programming Clamp and Real Time ISP sections in the JTAG and In System Programmability chapter in the MAX II Device Handbook October 2008 Altera Corporation MAX II Device Handbook 11 4 Chapter 11 In System Programmability Guidelines for MAX II Devices IEEE Std 1149 1 Signals Pull Up and Pull Down of JTAG Pins During In System Programming A MAX II device operating in in system programming mode requires four pins TDI TDO TMS a
268. ive low assertion the outside logic or device such as a microcontroller are free to continue their operation while the data in the UFM is retrieved written or erased During this time the nBUSY signal is driven low to indicate that it is not available to respond to any further request After the operation is complete the nBUSY signal is brought back to high to indicate that it is now available to service a new request If it was the Read request the DATA VALID is driven high to indicate that the data at the DO port is the valid data from the last read address Asserting READ WRITE and ERASE at the same time is not allowed Multiple requests are ignored and nothing is read from written to or erased in the UFM block There is no support for sequential read and page write in the parallel interface For both the read only and the read write modes of the parallel interface 05 ENA is always asserted enabling the internal oscillator Table 9 15 summarizes the parallel interface pins and functions MAX II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices Software Support for UFM Block Table 9 15 Parallel Interface Signals 9 37 Pin Description Function DI 15 0 16 bit data Input Receive 16 bit data in parallel You can select an optional width of 3 to 16 bits using the altufm megafunction 15 0 16 bit data Output Transmit 16 bit da
269. l Analysis Temperature Grade Commercial Power Characteristics Typical Vo Vecint Supply Voltage Voltage Regulator Ambient Temp Ta Proma Set Toggle Reset Import Quartus File Import EPE v6 1 Quartus Il Power Output File None File Load Date N A Junction Temp 270 Junction Ambient 51 20 Maximum Allowed T C Power Supply Current mA lccPoweRUP 55 00 lecint 12 00 AES Iccio Click lo for logo per Bank The power estimator results are based on estimated power data from device simulations and typical silicon measurements under nominal conditions Results obtained should only be used as an estimation of power not as a specification The actual must be verified during device operation as this measurement is sensitive to the actual pattern in the device and the environmental operating conditions PowerPlay Early Power Estimator Inputs October 2008 Altera Corporation The following sections of the chapter explain what values you need to enter for the PowerPlay Early Power Estimator spreadsheet The areas of entry in the PowerPlay Early Power Estimator spreadsheet include input parameters clock logic UFM and input output I O module MAX II Device Handbook 17 4 Chapter 17 Understanding and Evaluating Power in MAX II Devices PowerPlay Early Power Estimator Inputs Input Parameters Different MAX II devices cons
270. l Copper A1 0 05 0 15 Regular 855n 15Pb Typ A2 221021220 Lead Finish P lating Pb free Matte Sn i D 16 00 BSC J EDEC Outline Reference 5 026 Variation AED D1 14 00 BSC Maximum Lead 16 00 BSC Coplararity 0 003 inches 0 08mm Weight 0 6 g 1 14 00 BSC Moisture Sensitivity Level us on moisture barrier L 0 45 0 60 0 75 L1 1 00 REF S 0 20 C 0 09 0 20 e 0 50 BSC 0 0 3 59 19 II Device Handbook 1 6 Chapter 7 Package Information Package Outlines Figure 7 2 100 Pin TQFP Package Outline Pin 100 ES Pin 1 ID Pin 1 Pin 25 SEEEEEEEEDEELE See Detail X Al DETAIL A N s ES II Device Handbook October 2008 Altera Corporation Chapter 7 Package Information Package Outlines 100 Pin Micro FineLine Ball Grid Array MBGA dimensions and tolerances conform to ASME Y14 5 1994 Controlling dimension is in millimeters 1 1 Pin A1 may be indicated by an ID dot or a special feature in its proximity on package surface Package Information Package Outline Dimension Table Description Specification Millimeters Symbol Ordering Code Reference M Min Nom Max Package Acronym MBGA A 120 Substrate Material BT A1 0 15 Solder Ball Co
271. l self timed SECTOR ERASE cycle For SPI Extended mode the SE operation is performed in the following sequence as shown in Figure 9 30 1 nCSis pulled low 2 Opcode 00100000 is transmitted into the interface 3 The 16 bit address is sent The eighth bit the first seven bits will be discarded of the address indicates which sector is erased 0 means sector 0 UFMO is erased and a 1 means sector 1 UFM1 is erased October 2008 Altera Corporation MAX II Device Handbook 9 30 4 nCS is pulled back to high Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block For SPI Base mode the SE instruction erases UFM sector 0 As there are no choices of UFM sectors to be erased there is no address component to this instruction The SE operation is always done through the following sequence in SPI Base mode 1 nCSis pulled low 2 Opcode 00100000 is transmitted into the interface 3 nCS is pulled back to high Figure 9 30 SECTOR ERASE Operation Sequence for Extended Mode ncs 0 1 2 3 4 5 6 7 8 91011 SCK 20 2122 23 8 bit 16 bit gt Instruction a Y MSB 50 Address High Impendance II Device Handbook Figure 9 31 shows the SECTOR ERASE operation sequence for Base mode Figure 9 31 Sector ERASE Operation Sequence for Base Mode ncs 012
272. lculated with a 3 3 V Vecio A higher Vecio value will have a lower ley value with the same Vy October 2008 Altera Corporation MAX II Device Handbook 8 8 Chapter 8 Using MAX II Devices in Multi Voltage Systems Hot Socketing For signals with duty cycle greater than 3076 on MAX II input pins Altera recommends a Veco voltage of 3 0 V to guarantee long term I O reliability For signals with duty cycle less than 30 the Vcao voltage can be 3 3 V Hot Socketing For information about hot socketing refer to the Hot Socketing and Power On Reset in MAX II Devices chapter in the MAX II Device Handbook Power Up Sequencing MAX II devices are designed to operate in multiple voltage environments where it may be difficult to control power sequencing Therefore MAX II devices are designed to tolerate any possible power up sequence Either V4 or V cco can initially supply power to the device and 3 3 V 2 5 V 1 8 V or 1 5 V input signals can drive the devices without special precautions before V or is applied MAX II devices can operate with a VX voltage level that is higher than the V level When are supplied from different power sources to a MAX II device a delay between Veco and V c4 may occur Normal operation does not occur until both power supplies are in their recommended operating range When Vcr is powered up the IEEE Std 1149 1 Joint Test Action Group circuitry is active If t
273. led the programming algorithm used by the Quartus II software or the Jam jam Jam Byte Code jbc files will wait 500 ms before it begins any operation This is the same amount of time it takes for one UFM sector to be erased that is the real time ISP programming algorithm waits for what may have been a previously started UFM erase sequence to complete However if you are using a real time ISP feature no other UFM operations are allowed after that time no address shifting no data shifting and no read write or erase operations This can be controlled by monitoring the RTP BUSY signalon the altufm none megafunction When real time ISP is under way the BUSY output signal on the UFM block goes high You can monitor this signal and ensure that all UFM operations from the logic array cease until real time ISP is complete This user generated control logic is only necessary for the altufm none megafunction which provides no auto generated logic The other interfaces for the altufm megafunction altufm parallel altufm spi altufm i2c contain control logic that automatically monitors the BUSY signal and ceases operations to the UFM when a real time ISP operation is under way October 2008 Altera Corporation Chapter 11 In System Programmability Guidelines for MAX II Devices 11 3 General ISP Guidelines Interrupting In System Programming Altera does not recommend interrupting the programming process However
274. led versions of Jam files JBC files are compiled to a virtual processor architecture where the ASCII Jam commands are mapped to byte code instructions compatible with the virtual processor There are two types of JBC files Jam STAPL Byte Code compiled version of JEDEC Jam STAPL file m Jam Byte Code compiled version of Jam version 1 1 file Altera recommends using Jam STAPL Byte Code files in embedded applications because they use minimal memory Generating Jam Files The Quartus II software can generate both Jam and JBC file types In addition Jam files can be compiled into JBC files via a stand alone Jam Byte Code compiler The compiler produces a functionally equivalent JBC file Generating JBC files directly from the Quartus II software is simple The software tool supports the programming and configuration of multiple devices from single or multiple JBC files Figure 14 3 and Figure 14 4 show the dialog boxes that specify the device chain and JBC file generation in the Quartus software October 2008 Altera Corporation MAX II Device Handbook 14 6 Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Software Development Figure 14 3 Multi Device JTAG Chain s Name and Sequence in Programmer Window in the Quartus Software 1 Chaini cdf Hardware No Hardware Made Progress x 1 0_b190 epc4iconvert pof EPC4 D1AE75F3 FFFFFFF
275. loading and layout of the JTAG chain to determine whether to use discrete buffers or a termination technique For more information refer to the In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook Software Development II Device Handbook Altera s embedded programming uses the Jam file output from the Quartus II software tool with the standardized Jam Player software Designing these tools requires minimal developer intervention because Jam files contain all of the data for programming MAX II devices The bulk of development time is spent porting the Jam Player to the host embedded processor October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor 14 5 Software Development For more information about porting the Jam Byte Code Player see Porting the Jam STAPL Byte Code Player on page 14 8 Jam Files jam and jbc Altera supports the following types of Jam files m ASCII text files jam m Jam Byte Code files jbc ASCII Text Files jam Altera supports two types of Jam files JEDEC Jam STAPL format m Jam version 1 1 pre JEDEC format The JEDEC Jam STAPL format uses the syntax specified by the JEDEC Standard JESD 71A specification Altera recommends using JEDEC Jam STAPL files for all new projects In most cases Jam files are used in tester environments Jam Byte Code Files jbc JBC files are binary files that are compi
276. lso need termination to prevent overshoot undershoot or ringing This step is often overlooked since this signal is software generated and originates at a processor general purpose I O pin Pull Down Resistors on TCK TCK should be held low via a pull down resistor to keep the JTAG Test Access Port in a known state at power up missing pull down resistor can cause a device to power up in a JTAG BST state which may cause conflicts on the board A typical resistor value is 1 kO JTAG Signal Traces Short signal traces help eliminate noise and drive strength issues Special attention should be paid to the TCK and TMS pins Because TCK and TMS are connected to every device in the chain these traces will see higher loading than TDI or TDO Depending on the length and loading of the JTAG chain some additional buffering may be required to ensure that the signals propagate to and from the processor with integrity External Resistors You should add external resistors to output pins to pull outputs to a defined logic level during programming Output pins will tri state during programming Also on MAX II devices the pins will be pulled up by a weak internal resistor Altera recommends that outputs driving sensitive input pins be tied to the appropriate level by an external resistor Each preceding board layout element may require further analysis especially signal integrity In some cases you may need to analyze the
277. ltera Corporation MAX II Device Handbook 14 16 Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Updating Devices Using Jam Table 14 6 II Jam JBC Actions Part 2 of 2 Jam JBC Action ERASE Optional Procedures Off by Description Default Erases the programming content of the device You can DO BYPASS CFM optionally erase CFM and UFM separately DO BYPASS UFM DO REAL TIME ISP READ USERCODE Returns the JTAG USERCODE register information from the device READ USERCODE can be set to a specific value in the programming file in the Quartus II software by using the Assignments menu gt Device gt Device and Pin options gt General tab which has a USERCODE data entry Table 14 7 MAX Jam JBC Optional Procedure Definitions Procedure DO BYPASS CFM Description When set 21 DO BYPASS bypasses the CFM and performs the specified action on the UFM only When set 0 this option is ignored default DO BYPASS UFM When set 1 DO BYPASS bypasses the UFM and performs the specified action on the CFM only When set 0 this option is ignored default When set 1 the device CFM or is blank checked When set 0 this option is ignored DO BLANKCHECK default SECURE When set 1 the device s security bit is set The security bit only affects the CFM data The UFM cannot be protected When set 0 this option is ignored d
278. ly rails October 2008 Altera Corporation MAX II Device Handbook 11 14 Chapter 17 Understanding and Evaluating Power MAX II Devices Power Estimation Summary Thermal Analysis II Device Handbook In the Thermal Analysis part the PowerPlay Early Power Estimator spreadsheet considers the device s ambient temperature and the airflow to determine the junction temperature of the device in C The device can be considered a heat source and the junction temperature is the temperature at the device The thermal resistance of the path is referred to as the junction to ambient thermal resistance 6 Figure 17 14 shows the thermal model for the PowerPlay Early Power Estimator spreadsheet Figure 17 14 Thermal Model for the PowerPlay Early Power Estimator Heat Source Power P The PowerPlay Early Power Estimator spreadsheet determines the junction to ambient thermal resistance 054 based on the device package and airflow selected in the main input parameters The PowerPlay Early Power Estimator spreadsheet calculates the total power based on the device properties which provide and the ambient and junction temperature using the following equation Equation 17 1 T T p Figure 17 15 shows the Thermal Analysis section and Table 17 8 describes the thermal analysis parameters in the PowerPlay Early Power Estimator spreadsheet Figure 17 15 Thermal Analysis Section
279. m 1 024 x 8 8 Kbits Protocol The following defines the characteristics of the PC bus protocol m Only two bus lines are required SDA and SCL Both SDA and SCL bidirectional lines which remain high when the bus is free m Data transfer can be initiated only when the bus is free m The data on the SDA line must be stable during the high period of the clock The high or low state of the data line can only change when the clock signal on the SCL line is low m Any transition on the SDA line while the SCL is high is one such unique case which indicates a start or stop condition Table 9 5 summarizes the altufm i2c megafunction input and output interface signals Table 9 5 altufm 12 Interface Signals II Device Handbook Pin Description Function SDA Serial Data Address Line The bidirectional SDA port is used to transmit and receive serial data from the UFM The output stage of the SDA port is configured as an open drain pin to perform the wired AND function SCL Serial Clock Line The bidirectional SCL port is used to synchronize the serial data transfer to and from the UFM The output stage of the SCL port is configured as an open drain pin to perform a wired AND function WP Write Protect Optional active high signal that disables the erase and write function for read write mode The altufm i2c megafunction gives you an option to protect the entire UFM memory or only the upper half of memory
280. m TCK To prevent TCK from pulsing high the TCK pin is pulled low during power up Pulling TCK high is not recommended because an increase in the power supply to the pull up resistor causes the TCK to pulse high thus it is possible for the TAP controller to reach an unintended state IEEE Std 1149 1 Signals TCK Signal II Device Handbook This section provides guidelines for programming with the IEEE Std 1149 1 interface Most in system programming failures are caused by a noisy signal Noisy transitions on rising or falling edges can cause incorrect clocking of the IEEE Std 1149 1 Test Access Port TAP controller Incorrect clocking can cause the state machine to transition to an unknown state leading to in system programming failures October 2008 Altera Corporation Chapter 11 In System Programmability Guidelines for MAX II Devices 11 5 IEEE Std 1149 1 Signals Further because the TCK signal must drive all IEEE Std 1149 1 devices in the chain in parallel the signal may have a high fan out Like any other high fan out user mode clock you must manage a clock tree to maintain signal integrity Typical errors that result from clock integrity problems are invalid ID messages blank check errors or verification errors Altera recommends pulling the signal low through the internal weak pull down resistor or an external 1 resistor Fast TCK edges combined with board inductance
281. maximum ratings for the MAX II device family Table 5 1 MAX II Device Absolute Maximum Ratings Note 1 2 Symbol Parameter Conditions Minimum Maximum Unit Vecint Internal supply voltage 3 With respect to ground 0 5 4 6 V Vecio 1 0 supply voltage 0 5 46 V Vi DC input voltage 0 5 46 V lour DC output current per pin 4 25 25 mA Tere Storage temperature No bias 65 150 C Tams Ambient temperature Under bias 5 65 135 C Junction temperature TQFP and BGA packages 135 C under bias Notes to Table 5 1 1 Referto the Operating Requirements for Altera Devices Data Sheet 2 Conditions beyond those listed in Table 5 1 may cause permanent damage to a device Additionally device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device 3 Maximum for MAX II devices is 4 6 V For MAX IIG and MAX IIZ devices it is 2 4 V 4 Referto AN 286 Implementing LED Drivers in MAX amp MAX II Devices for more information about the maximum source and sink current for MAX II devices 5 Referto Table 5 2 for information about under bias conditions August 2009 Altera Corporation MAX II Device Handbook 5 2 Recommended Operating Conditions Table 5 2 shows the MAX II device family recommended operating conditions Table 5 2 MAX Device Recommended Operating Conditions Chapter 5 DC and Switch
282. mposition Pb free n 3Ag 0 5Cu Typ A2 1 00 October 2008 Altera Corporation Outline Reference MO 195 Variation AC A3 0 60 REF Maximum Lead D 6 00 BSC Coplanarity 0 003 inches 0 08 mm Weight 0 1g E 6 00 BSC Moisture Sensitivity Level us on moisture barrier b 0 25 0 30 0 35 e 0 50 BSC MAX II Device Handbook 1 8 Chapter 7 Package Information Package Outlines Figure 7 3 100 Pin Micro FineLine BGA Package Outline TOP VIEW BOTTOM VIEW D 1110 9 8 7 6 5 4 3 2 1 E OOOOO O QOO oe Oc 6 oc m O0 0 6 OO 00000 OO l ec ER ae 5 5 gt 000000000 F 100 Pin FineLine Ball Grid Array FBGA m dimensions and tolerances conform to ASME 14 5 1994 m Controlling dimension is in millimeters m Pin A1 may be indicated by an ID dot or a special feature in its proximity on package surface Package Information Package Outline Dimension Table Description Specification Millimeters Symbol Ordering Code Reference F Min Nom Max Package Acronym FBGA A 1 55 Substrate Material BT A1 0 25 MAX II Device Handbook October 2008 Altera Corporation gt Pin A1 Corner
283. ms Different download cables will have different programming times For more information about the MasterBlaster ByteBlasterMV ByteBlaster II or USB Blaster download cable refer to the MasterBlaster Serial USB Communications Cable User Guide ByteBlasterMV Download Cable User Guide ByteBlaster II Download Cable User Guide or USB Blaster Download Cable User Guide Disabling IEEE Std 1149 1 Circuitry By default the JTAG circuitry in MAX II devices is always enabled because they have dedicated JTAG pins and circuitry The JTAG circuitry must be enabled during ISP and boundary scan testing but disabled at all other times If your design does not use ISP or boundary scan test BST circuitry Altera recommends disabling the IEEE Std 1149 1 circuitry To disable the JTAG circuitry Altera recommends pulling TMS high and TCK low Pulling TCK low ensures that a rising edge does not occur on TCK during the power up sequence You can pull TCK high but you must first pull TMS high Pulling TMS high first ensures that the rising edge or edges on do not cause the JTAG state machine to leave the test logic reset state October 2008 Altera Corporation MAX II Device Handbook 11 6 Chapter 11 In System Programmability Guidelines for MAX II Devices Sequential versus Concurrent Programming La For more information about disabling the IEEE 1149 1 circuitry refer to the Disabling IEEE Std 1149 1 BST Circuitry section of the IEEE
284. n Millimeters Symbol Ordering Code Reference T Min Nom Max Package Acronym TQFP A 1 60 Leadframe Material Copper A1 0 05 0 15 Regular 85Sn 15Pb Typ 2 few ae em Lead Finish P lating Pb free Matte Sn D 22 00 BSC J EDEC Outline Reference MS 026 Variation BF B D1 20 00 BSC Maximum Lead 22 00 BSC Coplararity 0 003 inches 0 08 mm Weight 11g 1 20 00 BSC Moisture Sensitivity Level us on moisture barrier L 0 45 0 60 0 75 L1 1 00 REF S 0 20 C 0 09 0 20 e 0 50 BSC 0 0 3 59 19 October 2008 Altera Corporation Chapter 7 Package Information Package Outlines Figure 7 5 144 TQFP Package Outline 1 11 ES Pin 1 ID El E Pin 36 EER es A2 FUN See Detail A lige Y p DETAIL A B N T u Ds H 1 i 0 25mm ES L1 221 October 2008 Altera Corporation M
285. n System Programmability Chapter 4 Hot Socketing and Power On Reset in MAX II Devices Chapter 5 DC and Switching Characteristics Chapter 6 Reference and Ordering Information Revision History Refer to each chapter for its own specific revision history For information about when each chapter was updated refer to the Chapter Revision Dates section which appears in the complete handbook August 2009 Altera Corporation MAX II Device Handbook r2 Section I MAX II Device Family Data Sheet Revision History MAX II Device Handbook August 2009 Altera Corporation N DTE SYN 1 Introduction Introduction The MAX II family of instant on non volatile CPLDs is based 0 18 um 6 layer metal flash process with densities from 240 to 2 210 logic elements LEs 128 to 2 210 equivalent macrocells and non volatile storage of 8 Kbits MAX II devices offer high I O counts fast performance and reliable fitting versus other CPLD architectures Featuring MultiVolt core a user flash memory UFM block and enhanced in system programmability ISP MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging I O expansion power on reset POR and sequencing control and device configuration control Features The MAX II CPLD has the following features m Low cost low power CPLD m Instant on non volatile architecture m Standby current as low as 25 pA Provid
286. n library you must describe every device pin Do not include test vectors in a test library The following code example shows a setup only node test library Setup only test for the boundary scan chain assign TCK to nodes TCK Node name for the TCK pin assign TMS to nodes TMS Node name for the TMS pin assign TDI to nodes TDI Node name for the TDI pin assign TDO to nodes TDO Node name for the TDO pin inputs CK TMS TDI outputs TDO pcf order is TCK TMS TDI TDO The order is defined by the program that generates the PCF files Mark the and TMS boundary scan nodes as CRITICAL in the Board Consultant This critical attribute minimizes the nodes wire length in the test fixture October 2008 Altera Corporation MAX II Device Handbook 15 6 II Device Handbook Chapter 15 Using the Agilent 3070 Tester for In System Programming Agilent 3070 Development Flow without the PLD ISP Software Run the Test Consultant Run the Test Consultant to create all of the files for new board development Once the Test Consultant finishes running with this setup only test library it creates an executable test without vectors with the correct fixture wiring resource information Use this file as a template to create the executable test s source code Create Digital Tests Create the digital tests which are required to program the device s by copying the executable template to the desired program
287. nable real time ISP to allow background programming for MAX II devices Blank Security ISP Erase camp IPS File Start Checksum Usercode Verify Check Examine Bit D AMSXIMBrarTimeIGE 12707144 nneorr r Eia m r1 a a You can also enable the real time ISP feature in the Quartus II software through the following steps 1 On the Tools menu click Options 2 Under Category select Programmer 3 Turn on Enable real time ISP to allow background programming for MAX II devices and click OK The MAX II device will go into real time ISP mode when the Quartus II programmer starts programming it with any one of the three types of programming files October 2008 Altera Corporation MAX II Device Handbook 12 4 Figure 12 4 Chapter 12 Real Time ISP and ISP Clamp for MAX II Devices ISP Clamp Figure 12 4 shows the Programmer options in the Options menu Programmer Options in the Options Menu CE Show checksum without usercode Category E General EDA Tool Options Internet Connectivity License Setup Processing Er Assignment Editor Colors Er Block Symbol E ditor Colors Fonts Er Chip Editor Colors Fonts E Floorplan Editor Colors JT Initiate configuration after programming Display message when programming finishes M Enable real time ISP to allow background programming Fonts LogicLock Regions Window
288. nager options and example MegaWizard screen shots Refer to Quartus II Help for the altufm megafunction AHDL functional prototypes applicable to Verilog HDL VHDL component declaration and parameter descriptions Figure 9 11 shows altufm megafunction selection Flash Memory in the MegaWizard Plug In Manager This megafunction is in the memory compiler directory on page 2a of the MegaWizard Plug In Manager You can start the MegaWizard Plug In Manager on the Tools menu Figure 9 11 altufm Megafunction Selection in the MegaWizard Plug In Manager MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Which device family will you be MAX II ing Select a megafunction from the list below Und 184 Installed Plug Ins Which type of output file do you want to create Altera SOPC Builder C AHDL Arithmetic C VHDL Communications aj DSP Verilog HDL J Gates 2 xi 1 0 What name do you want for the output file Browse Interfaces jiles Projects MAX HB extract AT_ISP_Download Gll_Design c Sj JTAG accessible Extensions Memory Compiler E FIFO Return to this page for another create operation Li ee IUD L RAM 1 PORT RAM 2 PORT Note To compile a project successfully in the Quartus Il sc your design files must be in the project directory in the glot libraries specified in the Options dialog box Tools menu o library specified in the User L
289. nals Once 5 is pulled back to high the interface is back to normal ncs should be pulled low again for a new service request October 2008 Altera Corporation MAX II Device Handbook 9 26 Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Table 9 10 Instruction Set for SPI Name Opcode Operation WREN 00000110 Enable Write to UFM WRDI 00000100 Disable Write to UFM RDSR 00000101 Read Status Register WRSR 00000001 Write Status Register READ 00000011 Read data from UFM WRITE 00000010 Write data to UFM SECTOR ERASE 00100000 Sector erase UFM ERASE 01100000 Erase the entire UFM block both sectors The READ and WRITE opcodes are instructions for transmission which means the data will be read from or written to the UFM WREN WRDI RDSR and WRSR are instructions for the status register where they do not have any direct interaction with UFM but read or set the status register within the interface logic The status register provides status on whether the block is available for any READ or WRITE operation whether the interface is WRITE enabled and the state of the UFM WRITE protection The status register format is shown in Table 9 11 For the read only implementation of ALTUFM SPI Base or Extended mode the status register does not exist saving LE resources Table 9 11 Status Register Format
290. names For example if svf2pcf created four PCF Files copy the template file to four executable tests for example prog a prog b prog c and prog in the digital directory Add these test names to your testorder file and mark them permanent using the following syntax test digital prog a permanent test digital prog b permanent test digital prog c permanent test digital prog d permanent Create the Wirelist Information for the Tests Compile these executable tests to generate object files see Modify the Test Plan for the setup only versions of the tests Run Module Pin Assignment to create the necessary entries in the wirelist file Next modify the executable tests so that they contain the vectors to program the target device An include statement can be used in the executable test or the vectors can be merged into the file Use the following syntax for the include statement which should be the last statement in the executable test include pcfi Remember that the PCF File must reside in the digital directory and must be a digital file To ensure that the digital file is in the correct directory run the following command on the BT Basic command line load digital digital pcfi re save You can also use the chtype command at a shell prompt to verify the location of the file chtype n6 digital pcfl Repeat this step for each PCT File Modify the Test Plan Add the test statements to the test plan using
291. ncoming signals SO output the content of the status register Bit 7 first and Bit 0 last 4 If nCs is kept low repeat step 3 5 is pulled back to high to terminate the transmission Figure 9 35 RDSR Operation Sequence nCS 4 m 0123 4 5 6 7 8 91011 12 13 M 15 16 17 18 19 20 21 22 23 4 8 bit Instruction XX s OO MSB MSB High I d SO icai di dao Status Register Out 5 5 WRSR Write Status Register The block protection bits BP 1 and are the status bits used to protect certain sections of the UFM from inadvertent write The BP1 and BPO status are updated by WRSR During WRSR only BP1 and BPO in the status register can be written with valid information The rest of the bits in the status register are ignored and not updated When both BP1 and BPO are 0 there is no protection for the UFM When both BP1 and BPO are 1 there is full protection for UFM and BP1 are set to 0 upon power up Table 9 12 describe more on the Block Write Protect Bits for Extended mode while Table 9 13 describes more on the Block Write Protect Bits for Base mode WRSR is issued through the following sequence as shown in Figure 9 36 1 ncs is pulled low 2 Opcode 00000001 is transmitted into the interface 3 An 8 bit status is transmi
292. ncy for ARCLK is 10 MHz ARSHFT Input Signal that determines whether to shift the address register or increment it on an ARCLK edge A high value shifts the data from Serially into the address register A low value increments the current address by 1 The address register rolls over to 0 when the address space is at the maximum PROGRAM Input Signal that initiates a program sequence On the rising edge the data in the data register is written to the address pointed to by the address register The BUS v signal asserts until the program sequence is completed ERASE Input Signal that initiates an erase sequence On a rising edge the memory sector indicated by the MSB of the address register will be erased The BUSY signal asserts until the erase sequence is completed OSC ENA Input This signal turns on the internal oscillator in the UFM block and is optional but required when the osc output is used If 05 ENA is driven high the internal oscillator is enabled and the osc output will toggle If oSc_ENA is driven low the internal oscillator is disabled and the osc output drives constant low DRDout Output Serial output of the data register Each time the DRCLK signal is applied a new value is available The DRDout data depends on the DRSHFT signal When the DRSHFT signal is high DRDout value is the new value that is shifted into the MSB of the data register If the DRSHFT is low DRDout would contain the MSB of the memory locat
293. nd TCK The detailed description and function of each pin can be found in the IEEE 1149 1 JTAG Boundary Scan Testing for MA X II Devices chapter in the MAX Device Handbook Three of the four JTAG pins have internal weak pull up or pull down resistors The TDI and TMS pins have internal weak pull up resistors while the TCK pin has an internal weak pull down resistor However for device programming in a JTAG chain there might be devices that do not have internal pull up or pull down resistors Altera recommends to externally pull TMS high through 10 kO and TCK low through 1 kQ resistors Pulling up the TDI signal externally for the MAX II device is optional Figure 11 1 shows the external pull up and pull down for TMS and TCK of the JTAG chain The TDO pin does not have internal pull up or pull down resistors and does not require external pull up or pull down resistors Figure 11 1 Fxternal Pull Up and Pull Down Resistors for TMS and TCK of a JTAG Chain 10 Pin Male Header Top View vec VCC Other ISP Capable OtherISP Capable Device Device gt eee 3J TDI TDO 5 5 E 5 is pulled high so that the controller will remain in the TEST LOGIC RESET state even if there is input fro
294. ngth Setting mA S 8 3 3 V LVCMOS 8 4 2 5 V LVTTL LVCMOS 14 7 1 8 V LVTTL LVCMOS 6 3 1 5 V LVCMOS 4 2 Note to Table 2 6 1 The current strength numbers shown are for a condition of a Voy Vo minimum where the Vo minimum is specified by the 1 0 standard The lo current strength numbers shown are for a condition of a Vor maximum where the Vo maximum is specified by the 1 0 standard For 2 5 V LVTTL LVCMOS the lon condition is Voy 1 7 V and the lo condition is Vour 0 7 V Slew Rate Control The output buffer for each MAX II device I O pin has a programmable output slew rate control that can be configured for low noise or high speed performance A faster slew rate provides high speed transitions for high performance systems However these fast transitions may introduce noise transients into the system A slow slew rate reduces system noise but adds a nominal output delay to rising and falling edges The lower the voltage standard for example 1 8 V LVTTL the larger the output delay when slow slew is enabled Each I O pin has an individual slew rate control allowing the designer to specify the slew rate on a pin by pin basis The slew rate control affects both the rising and falling edges Open Drain Output MAX II devices provide an optional open drain equivalent to open collector output for each I O pin This open drain output enables the device to provide system level c
295. nications C AHDL m DSP C VHDL Gates 1 0 Verilog HDL What name do you want for the output file Browse iles Projects MAX I HB extract RT_ISP_Download Qll_Design c Retum to this page for another create operation Note To compile a project successfully in the Quartus Il software your design files must be in the project directory in the global user libraries specified in the Options dialog box Tools menu or a user library specified in the User Libraries page of the Settings dialog box Assignments menu Your current user library directories are II oscillator ig Interfaces Cancel lt Back Next gt F Figure 9 6 shows page 3 of the IO MAX II oscillator megafunction You have an option to choose to simulate the OSC output port at its maximum or minimum frequency during the design simulation The frequency chosen is only used as a timing parameter simulation and does not affect the real MAX II device OSC output frequency Figure 9 6 Page 3 of the OSC Megafunction MegaWizard Plug In Manager MegaWizard Plug In Manager IO MAX II Oscillator page of 5 10 MAX II Oscillator Currently selected device Family MAX II controller altufm osc The oscillator output is derived from the User Flash Memory When the oscillator function is used the User Flash Memory feature is not available What is the oscillator frequency for the osc 5 56 MHz output
296. not supported in these devices and banks Figure 2 22 MAX II 1 0 Banks for 240 and EPM570 Note 1 2 1 0 Bank 1 1 0 Bank 2 All 1 0 Banks Support W 3 3 VLVITL LVCMOS 25 VLIVITLLVCMOS 7 8 VLVITL LVCMOS 7 5 VLVCMOS Notes to Figure 2 22 1 Figure 2 22 is a top view of the silicon die 2 Figure 2 22 is a graphical representation only Refer to the pin list and the Quartus Il software for exact pin locations The EPM1270 and EPM2210 devices support four I O banks as shown in Figure 2 23 Each of these banks support all of the LVTTL and LVCMOS standards shown in Table 2 4 PCI compliant I O is supported in Bank 3 Bank 3 supports the PCI clamping diode on inputs and PCI drive compliance on outputs You must use Bank3 for designs requiring PCI compliant I O pins The Quartus II software automatically places I O pins in this bank if assigned with the PCI I O standard October 2008 Altera Corporation MAX II Device Handbook 2 28 Chapter 2 MAX II Architecture 1 0 Structure Figure 2 23 MAX II 1 0 Banks for EPM1270 and EPM2210 Note 1 2 1 0 Bank 2 21 I Also Supports All 1 0 Banks Support the 3 3 V PCI 3 3 V LVTTL LVCMOS 1 0 Standard W 25 VLVTTL LVCMOS 1 8 VLVTTL LVCMOS 1 5 V LVCMOS 1 0 Bank 1 1 0 Bank 3 Notes to Figure 2 23 1 0 Bank 4 1 Fig
297. ns reside in Bank 1 of all MAX II devices MAX II devices support the JTAG instructions shown in Table 3 1 Table 3 1 MAX II JTAG Instructions Part 1 of 2 JTAG Instruction SAMPLE PRELOAD Instruction Code Description 00 0000 0101 Allows a snapshot of signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins EXTEST 1 00 0000 1111 Allows the external circuitry and board level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins BYPASS USERCODE 11 1111 1111 Places the 1 bit bypass register between the and pins which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation 00 0000 0111 Selects the 32 bit USERCODE register and places it between the TDI and pins allowing the USERCODE to be serially shifted out of TDO This register defaults to all 1 s if not specified in the Quartus II software IDCODE 00 0000 0110 Selects the IDCODE register and places it between TDI and allowing the IDCODE to be serially shifted out of TDO HIGHZ 1 00 0000 1011 Places the 1 bit bypass register between the and pins which allows the boundary scan test data to pass synchronously through selected devices to adjacent devices during normal d
298. nt and fan out Figure 16 2 External Timing Parameter tpp Note 1 MAXI LUT gt Device Note to Figure 16 2 1 tppi tin Nx tr4 4 Mx tey 4 tiur tcomp trasrio Atop Table 16 4 lists the numbers of LABs according to device density Table 16 4 Numbers of LABs According to Device Density Device Density N LAB Rows M LAB Columns 240 4 6 570 7 12 1270 10 16 2210 13 20 Dtop is the adder delay see note to Figure 16 2 for the top microparameter when using an I O standard other than 3 3 V LVTTL with 16 mA current strength Ss Refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook for adder delay values The following is an example for the EPM240 device using an I O standard of 3 3 V LVTTL fast slew rate witha drive strength of 16 mA tm 4 X tu 4 6X tc 4 ttur trasrio op a for the EPM240 device using an I O standard of 2 5 V LVTTL fast slew rate witha drive strength of 7 mA a Dtop of 2 5 V LVTTL fast slew 7 mA October 2008 Altera Corporation MAX II Device Handbook 16 6 II Device Handbook Chapter 16 Understanding Timing in MAX II Devices Calculating Timing Delays Figure 16 3 External Timing Parameter tpp Note 1 MAX 11 Device TRI E gt Note to Figure 16 3 1
299. nternal write cycle is in progress the altufm i2c logic ignores any attempt made by the master to initiate a new transfer The altufm i2c megafunction allows you to choose the page size of 8 bytes 16 bytes or 32 bytes for the page write operation as shown in Figure 9 24 on page 9 24 A write operation is only possible on an erased UFM block or word location The block differs from serial EEPROMs requiring an erase operation prior to writing new data in the UFM block A special erase sequence is required as discussed in Erase Operation on page 9 18 Acknowledge Polling The master can detect whether the internal write cycle is completed by polling for an acknowledgement from the slave The master can resend the start condition together with the slave address as soon as the byte write sequence is finished The slave does not acknowledge if the internal write cycle is still in progress The master can repeat the acknowledge polling and can proceed with the next instruction after the slave acknowledges Write Protection The altufm_i2c megafunction includes an optional Write Protection WP port available on page 4 of the altufm MegaWizard Plug In Manager see Figure 9 24 on page 9 24 In the MegaWizard Plug In Manager you can choose the WP port to protect either the full or upper half memory When WP is set to 1 the upper half or the entire memory array depending on the write protection level selected is protected and the
300. ntial and concurrent programming is similar only the programming algorithms are different Sequential Programming Sequential programming is the process of programming multiple devices in a chain one device at a time After the first device in the chain is finished being programmed the next device is programmed This sequence continues until all specified devices in the JTAG chain are programmed After a device is programmed it will be in bypass mode to allow data to be passed to the subsequent devices in the chain The devices in the chain do not go into user mode until all the devices are programmed Concurrent Programming II Device Handbook Concurrent programming is used to program devices from the same family for example the MAX II family in parallel The programming time is slightly longer than the time needed to program the largest device in the chain resulting in considerably faster programming times than sequential programming where programming time is equal to the sum of individual programming times for all devices Higher clock rates for shifting data result in even greater time savings Concurrent programming of devices can be done using Serial Vector Format files svf Jam files or JBC files created from the Quartus II software See Figure 11 2 1 On the Tools menu click Programmer 2 Click Add File and select programming files for the respective devices October 2008 Altera Corporation Chapter 11
301. o TDI and replace the contents of the capture registers During the update phase data in the capture registers is transferred to the update registers This data can then be used in the EXTEST instruction mode Refer to EXTEST Instruction Mode on page 13 11 for more information Figure 13 9 shows the SAMPLE PRELOAD waveforms The SAMPLE PRELOAD instruction code is shifted in through the TDI pin The TAP controller advances to the CAPTURE DR state and then to the 5 DR state where it remains if TMS is held low The data shifted out of the TDO pin consists of the data that was present in the capture registers after the capture phase New test data shifted into the TDI pin appears atthe TDO pin after being clocked through the entire boundary scan register Figure 13 9 shows that the test data that shifted into TDI does not appear at the TDO pin until after the capture register data that is shifted out If TMS is held high on two consecutive TCK clock cycles the TAP controller advances to the UPDATE DR state for the update phase If the device output enable feature is enabled but the OE pin is not asserted during boundary scan testing the OE boundary scan registers of the boundary scan cells capture data from the core of the device during SAMPLE PRELOAD These values are not high impedance although the I O pins are tri stated Figure 13 9 SAMPLE PRELOAD Shift Data Register Waveforms
302. o right LE7 Local Interconnect LE9 Logic Element LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs The control signals include two clocks two clock enables two asynchronous clears a synchronous clear an asynchronous preset load a synchronous load and add subtract control signals providing a maximum of 10 control signals at a time Although synchronous load and clear signals are generally used when implementing counters they can also be used with other functions Each LAB can use two clocks and two clock enable signals Each LAB s clock and clock enable signals are linked For example any LE in a particular LAB using the 1 1 1 signal also uses labclkenal If the LAB uses both the rising and falling edges of a clock it also uses both LAB wide clock signals Deasserting the clock enable signal turns off the LAB wide clock Each LAB can use two asynchronous clear signals and an asynchronous load preset signal By default the Quartus II software uses a NOT gate push back technique to achieve preset If you disable the NOT gate push back option or assign a given register to power up high using the Quartus II software the preset is then achieved using the asynchronous load signal with asynchronous load data input tied high With the LAB wide addnsub control signal a single LE can implement a one bit adder and subtracto
303. ober 2008 Altera Corporation Section V Design Considerations ANU S n AN This section provides information for MA Xe design considerations This section includes the following chapters m Chapter 16 Understanding Timing in MAX II Devices m Chapter 17 Understanding and Evaluating Power in MAX II Devices Revision History Refer to each chapter for its own specific revision history For information on when each chapter was updated refer to the Chapter Revision Dates section which appears in the complete handbook October 2008 Altera Corporation MAX II Device Handbook v2 II Device Handbook Section V Design Considerations Revision History October 2008 Altera Corporation 16 Understanding Timing in MAX Il ANU S RYAN Devices MII51017 2 1 Introduction Altera devices provide predictable device performance that is consistent from simulation to application Before programming a device you can determine the worst case timing delays for any design You can approximate propagation delays with either the Quartus II Timing Analyzer or the timing models given in this chapter and the timing parameters listed in individual device data sheets La For the most precise timing results you should use the Quartus II Timing Analyzer which accounts for the effects of the secondary factors as mentioned later in this chapter This chapter defines external and internal timing parameters and illustra
304. occurs because the integrated program generator IPG looks at the entire vector set of the library object to determine if vectors need to be commented out due to conflicts Library object compiles are different from executable compiles Additionally the IPG may fail due to the large library object file m To save time and disk space generate SVF Files that include a verify in the programming operation This process integrates verification vectors into one step minimizing the amount of work in the test development process This integrated verify accurately captures any programming errors therefore it is not necessary to add an additional stand alone verify in the test sequence m While this document describes how to generate a test to apply vectors to the device for programming a boundary scan description language BSDL file is required to functionally test the device If you need to perform a boundary scan test or functional test generate a BSDL file for the programmed state of the target device that contains the pin configuration information for example which pins are inputs outputs or bidirectional pins Use the Agilent 3070 boundary scan software to generate a test For more information about Altera s support for boundary scan testing refer to the IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices chapter in the MAX II Device Handbook October 2008 Altera Corporation Chapter 15 Using the Agilent 3070 Tester fo
305. ocking logic high on TMS Once in the EXIT1_IR state TDO becomes tri stated again TDO is always tri stated except in the SHIFT_IR and SHIFT_DR states After an instruction code is entered correctly the TAP controller advances to perform the serial shifting of test data in one of three modes SAMPLE PRELOAD EXTEST or BYPASS that are described below For MAX II devices there are weak pull up resistors for TDI and TMS and pull down resistors for TCK However in a JTAG chain there might be some devices that do not have internal pull up or pull down resistors In this case Altera recommends pulling the TMS pin high through an external 10 resistor and pulling low through an external 1 k Qresistor during BST or in system programmability ISP to prevent the TAP controller from going into an unintended state Pulling up the TDI signal externally for the MAX II device is optional For more information about the pull up and pull down resistors refer to the In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook SAMPLE PRELOAD Instruction Mode The SAMPLE PRELOAD instruction mode allows you to take a snapshot of device data without interrupting normal device operation However this instruction mode is most often used to preload the test data into the update registers prior to loading the EXTEST instruction Figure 13 8 shows the capture shift and update phases of the S
306. ods shown on page 4 of the altufm MegaWizard Plug In Manager m Full Erase Device Slave Address Triggered m Sector Erase Byte Address Triggered m Sector Erase A Triggered m No Erase These erase options only work as described if that particular option is selected in the MegaWizard Plug In Manager before compiling the design files and programming the device Only one option is possible for the altufm i2c megafunction Erase options are discussed in more detail in the following sections Full Erase Device Slave Address Erase The full erase option uses the A A A bits of the slave address to distinguish between erase or read write operation This slave operation decoding occurs when the master transfers the slave address to the slave after generating the start condition If the A A and A slave address bits transmitted to the slave equals 111 and the four remaining MSBs match the rest of the slave addresses then the Full Erase operation is selected If the A A A A A and A slave address bits transmitted to the UFM match its unique slave address setting the read write operation is selected and functions as expected As a result this erase option utilizes two slave addresses on the bus reserving A A A 1 1 1 as the erase trigger Both sectors of the UFM block will be erased when the Full Erase operation is executed This operation requires acknowledge polling The internal UFM erase function only
307. of R can be calculated as follows Equation 8 2 R C95V 37V 8mA x 309 _ ig 2 8 mA This analysis assumes worst case conditions If your system does not see a wide variation in voltage supply levels you can adjust these calculations accordingly Because 5 0 V device tolerance in MAX II devices requires use of the I O clamp and this clamp is activated only after power up 5 0 V signals may not be driven into the device until it is configured The I O clamp diode is only supported in the EPM1270 and EPM2210 devices I O Bank 3 An external protection diode is needed for other I O banks for EPM1270 and EPM2210 devices and all I O pins in EPM240 and EPM570 devices Recommended Operating Condition for 5 0 V Compatibility As mentioned earlier 5 0 V tolerance can be supported with the I O clamp diode enabled with external series pull up resistance To guarantee long term reliability of the device s I O buffer there are restrictions on the signal duty cycle that drive the MAX I I O which is based on the maximum clamp current Table 8 3 shows the maximum signal duty cycle for 3 3 V given a PCI clamp current handling capability Table 8 3 Maximum Signal Duty Cycle V V 1 mA 2 Max Duty Cycle 4 0 5 00 100 4 1 11 67 90 4 2 18 33 50 4 3 25 00 30 4 4 31 67 17 4 5 38 33 10 4 6 45 00 5 Notes to Table 8 3 1 V is the voltage at the package pin 2 The is ca
308. of data to be left untouched while the other sector is erased and programmed with new data October 2008 Altera Corporation MAX II Device Handbook 2 20 Chapter 2 MAX II Architecture User Flash Memory Block Internal Oscillator As shown in Figure 2 15 the dedicated circuitry within the UFM block contains an oscillator The dedicated circuitry uses this internally for its read and program operations This oscillator s divide by 4 output can drive out of the UFM block as a logic interface clock source or for general purpose logic clocking The typical 05 output signal frequency ranges from 3 3 to 5 5 MHz and its exact frequency of operation is not programmable Program Erase and Busy Signals The UFM block s dedicated circuitry automatically generates the necessary internal program and erase algorithm once the PROGRAM or ERASE input signals have been asserted The PROGRAM or ERASE signal must be asserted until the busy signal deasserts indicating the internal program or erase operation has completed The UFM block also supports JTAG as the interface for programming and or reading For more information about programming and erasing the UFM block refer to the Using User Flash Memory in MAX II Devices chapter in the MAX II Device Handbook Auto Increment Addressing Serial Interface The UFM block supports standard read or stream read operations The stream read is supported with an auto increment address feature Deasser
309. oller unit to communicate with peripheral devices and is also capable of inter processor communications in a multiple master system The SPI bus consists of masters and slaves The master device initiates and controls the data transfers and provides the clock signal for synchronization The slave device responds to the data transfer request from the master device The master device in an SPI bus initiates a service request with the slave devices responding to the service request With the altufm megafunction the UFM and MAX II logic can be configured as a slave device for the SPI bus The 05 ENA is always asserted to enable the internal oscillator when the SPI megafunction is instantiated for both read only and read write interfaces The Quartus II software supports both the Base mode which uses 8 bit address and data and the Extended mode which uses 16 bit address and data Base mode uses only UFM sector 0 2 048 bits whereas Extended mode uses both UFM sector 0 and sector 1 8 192 bits There are only four pins in SPI SI SO SCK and nCs Table 9 9 describes the SPI pins and functions II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 25 Software Support for UFM Block Table 9 9 SPI Interface Signals Pin Description Function SI Serial Data Input Receive data serially 50 Serial Data Output Transmit data serially SCK Serial Dat
310. on Chapter 5 DC and Switching Characteristics 5 11 Timing Model and Specifications Internal Timing Parameters Internal timing parameters are specified on a speed grade basis independent of device density Table 5 15 through Table 5 22 describe the MAX II device internal timing microparameters for logic elements LEs input output elements IOEs UFM blocks and MultiTrack interconnects The timing values for 23 4 and 5 speed grades shown in Table 5 15 through Table 5 22 are based on an EPM1270 device target while 6 7 and 8 speed grade values are based on an EPM570Z device target For more explanations and descriptions about each internal timing microparameters symbol refer to the Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook Table 5 15 LE Internal Timing Microparameters MAX Il MAX IIG liZ 8Speed 4Speed 5 Speed 6 Speed 7 Speed 8 Speed Grade Grade Grade Grade Grade Grade Symbol Parameter Min Min Max Min Max Min Max Min Max Min Max Unit lur LE combinational 571 742 914 1 215 2247 2 247 ps LUT delay Combinational 147 192 236 243 305 309 ps path delay lun LE register clear 238 309 381 401 541 545 ps delay tone LE register preset 238 309 381 401
311. onsumption Temperature Grade Commercial devices have a maximum junction operating temperature of 85 C Industrial devices offer 100 C operation while the MAX II automotive grade devices can operate up to 125 C This field affects the maximum junction temperature used in thermal calculations Power Characteristics For IIZ devices you can select either typical or maximum power characteristics for the power estimation The power characteristics are based on typical and theoretical worst case silicon process Maximum should be used for thermal design while Typical gives you the estimation of the average use of the devices MAX II Device Handbook October 2008 Altera Corporation Chapter 17 Understanding and Evaluating Power in MAX Il Devices 17 5 PowerPlay Early Power Estimator Inputs Table 17 1 Input Parameter Section Information Part 2 of 2 Input Parameter Voanr Supply Description The voltage of the Vect power supply For MAX and MAX IIZ devices the supply voltage must be 1 8 V For other devices it can be either 2 5 V or 3 3 V Devices with lower Vcc have lower total standby power consumption Ambient Temperature Enter the air temperature near the CPLD This value can range from 40 C to 125 C depending on the device temperature grade This parameter is used to compute junction temperature based on power dissipation and thermal resistances through the top of the chip
312. ontal LAB neighbor can drive a given R4 interconnect For R4 interconnects that drive to the right the primary LAB and right neighbor can drive on to the interconnect For R4 interconnects that drive to the left the primary LAB and its left neighbor can drive on to the interconnect R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive R4 interconnects can also drive C4 interconnects for connections from one row to another Figure 2 10 R4 Interconnect Connections Notes to Figure 2 10 Adjacent LAB can Interconnect drive onto another C4 Column Interconnects 1 Driving Right LABS R4 Interconnect R4 Interconnect Driving Left gt 1 5 gt gt gt gt 4 5 gt lt gt gt e e e e e e e e e gt gt gt i LAB Primary LAB Neighbor LAB 2 Neighbor 1 C4 interconnects can drive R4 interconnects 2 This pattern is repeated for every LAB in the LAB row
313. ontrol signals for example interrupt and write enable signals that can be asserted by any of several devices This output can also provide an additional wired OR plane Programmable Ground Pins Each unused I O pin on MAX II devices can be used as an additional ground pin This programmable ground feature does not require the use of the associated LEs in the device In the Quartus II software unused pins can be set as programmable GND on a global default basis or they can be individually assigned Unused pins also have the option of being set as tri stated input pins II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 31 VO Structure Each MAX II device I O pin provides an optional bus hold feature The bus hold circuitry can hold the signal on an I O pin at its last driven state Since the bus hold feature holds the last driven state of the pin until the next input signal is present an external pull up or pull down resistor is not necessary to hold a signal level when the bus is tri stated The bus hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high frequency switching The designer can select this feature individually for each I O pin The bus hold output will drive no higher than Veco to prevent overdriving signals If the bus hold feature is enabled the device cannot use the programmable pull up option The bus hold circuitry
314. ook October 2008 Altera Corporation Chapter 15 Using the Agilent 3070 Tester for In System Programming 15 3 Agilent 3070 Development Flow without the PLD ISP Software Step 1 Create a PCB and Test Fixture Before starting test development the first step to successful in system programming is the proper layout of the board and the subsequent creation of the test fixture Creating the PCB The following recommendations highlight important areas of PCB design issues m The TCK signal trace should be treated as carefully as a clock tree is the clock for the entire Joint Test Action Group chain of devices These devices edge triggered on the TCK signal so itis imperative that this signal be protected from high frequency noise and have good signal integrity Ensure that the signal meets the tR and tF parameters specified in the device data sheet m Add a pull down resistor to The signal should be held low through a pull down resistor in between PCF downloads For more information about pattern capture format PCF downloads refer to Step 2 Create a Serial Vector Format File You should hold low because the Agilent 3070 drivers go into a high Z state in between tests and briefly drive low as the next PCF is applied When the TCK line floats the programming data stream is corrupted and the device is not programmed correctly m Provide VCC and GND test access points for the nails of
315. oot to the voltages shown in the following table based upon input duty cycle The DC case is equivalent to 100 duty cycle For more information about 5 0 V tolerance refer to the Using MAX II Devices in Multi Voltage Systems chapter in the MAX II Device Handbook Vin 40V 4 1 4 2 4 8 44 4 5 A Z TZ Max Duty Cycle 100 DC 90 50 30 17 10 pins including clock 1 0 and JTAG pins be driven before Vocwr and Vecio are powered For the extended temperature range of 100 to 125 C MAX II UFM programming erase write is only supported via the JTAG interface UFM programming via the logic array interface is not guaranteed in this range II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics Operating Conditions Programming Erasure Specifications Table 5 3 shows the MAX II device family programming erasure specifications Table 5 3 MAX II Device Programming Erasure Specifications 5 3 Parameter Typical Maximum Unit Erase and reprogram cycles 100 1 Cycles Note to Table 5 3 1 This specification applies to the UFM and configuration fl DC Electrical Characteristics ash memory CFM blocks Table 5 4 shows the MAX II device family DC electrical characteristics Table 5 4 MAX II Device DC Electrical Characteristics Note 1 Part 1 of 2
316. or the altufm_i2c megafunction of 8 Kbit memory The altufm i2c megafunction of 8 Kbit memory fully utilizes all the memory locations in the UPM block October 2008 Altera Corporation MAX II Device Handbook Chapter 9 Using User Flash Memory in MAX II Devices Simulation Parameters Figure 9 52 Memory Map for 8 Kbit Memory Initialization 8 Kbit altufm i2c Megafunction Logical Memory Contents MIF or HEX File Contents to representthe actual data and address size for the UFM Block The mid upper quarter of logical memory maps Upper Quarter Addresses 300h to 3FFh e upper byte of sector 1 Address 300h in logical memory to the lower byte of sector 1 Address 200h in logical memory maps to address 100h 3FFh 300h in physical memory in physical memory 2FFh and all addresses and all addresses follow the order in follow the order in Mid Upper Quarter Addresses logical memory logical memory 200h to 2FFh 100h gt 200 1FFh oFFh Mid Lower Quarter Addresses 100h to 1FFh maps to address 100h t The mid l ical memory maps to the lower byte of sector 0 Address 100h arter of The lower quarter of logical memory maps to the lower byte of 100h sector 0 Address 000 Lower Quarter Addresses 100h to 1FFh OFFh in logical memory maps to address 000h in physical memory and all addresses follow the order in m
317. ork into the LAB local interconnect See LAB Control Signals on page 2 5 for more information October 2008 Altera Corporation MAX II Device Handbook 2 18 Chapter 2 MAX II Architecture User Flash Memory Block Figure 2 14 Global Clock Network Note 1 LAB Column clock 3 0 1 0 Block Region gt 4 LAB Column clock 3 0 USES 1 0 Block Region UFM Block 2 1 0 Block Region CFM Block Notes to Figure 2 14 1 LAB column clocks 1 0 block regions provide high fan out output enable signals 2 LAB column clocks drive to the UFM block User Flash Memory Block MAX II devices feature a single UFM block which can be used like a serial EEPROM for storing non volatile information up to 8 192 bits The UFM block connects to the logic array through the Multilrack interconnect allowing any LE to interface to the UFM block Figure 2 15 shows the UFM block and interface signals The logic array is used to create customer interface or protocol logic to interface the UFM block data outside of the device The UFM block offers the following features m Non volatile storage up to 16 bit wide and 8 192 total bits m Two sectors for partitioned sector erase m Built in internal oscillator that optionally drives logic array Program erase and busy signals II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 19 U
318. ory costs Updating Devices Using Jam Updating a device in the field means downloading a new JBC file and running the Jam STAPL Byte Code Player with what in most cases is the program action The main entry point for execution of the Playeris jbi execute This routine passes specific information to the Player When the Player finishes it retums an exit code and detailed error information for any run time errors The interface is defined by the routine s prototype definition JBI RETURN TYPE jbi execute PROGRAM PTR program long program size char workspace long workspace size action char init list long error line init exit code The code within main in jbistub c determines the variables that will be passed to jbi execute In most cases this code is not applicable to an embedded environment therefore this code can be removed and the jbi execute routine can be set up for the embedded environment Table 14 5 describes each parameter Table 14 5 Parameters Note 1 Part 1 of 2 Parameter program Status Description Mandatory A pointer to the JBC file For most embedded systems setting up this parameter is as easy as assigning an address to the pointer before calling 3bi execute program size Mandatory Amount of memory in bytes that the JBC file occupies workspace Optional A pointer to dynamic memory that can be used by the JBC Player to perform its necess
319. ory in MAX Il Devices 9 47 Referenced Documents Referenced Documents This chapter references the following documents m In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook m MAXII Architecture chapter in the MAX II Device Handbook Document Revision History Table 9 17 shows the revision history for this chapter Table 9 17 Document Revision History Date and Revision Changes Made Summary of Changes October 2008 m Updated Using and Accessing UFM Storage Oscillator UFM version 1 8 Operating Modes ALTUFM SPI Timing Specification and ALTUFM Parallel Interface Timing Specification sections m Updated New Document Format December 2007 m Corrected Figure 9 3 version 1 7 m Added Referenced Documents December 2006 m Changed signal format in Table 9 4 Added Revision History section version 1 6 August 2005 m Added PC row to Table 9 3 version 1 5 m Added a new nter Integrated Circuit section m Added a new Memory Initialization for the altufm i2c Megafunction section m Updated Figure 9 39 June 2005 m Added the Instantiating the Oscillator without the UFM section version 1 4 Updated Figure 9 14 January 2005 m Previously published as Chapter 10 No changes to content version 1 3 October 2008 Altera Corporation MAX II Device Handbook Chapter 9 Using User Flash Memory in MAX II Devices Table 9 17 Document
320. own the to 0 V for a minimum of 10 us before powering and Veco again Once Vecnr rises from 0 V back to approximately 1 55 V the SRAM download restarts and the device begins to operate after tconrg time has passed Figure 4 5 shows the voltages for POR of MAX MAX and MAX IIZ devices during power up into user mode and from user mode to power down or brown out Veonrand Veco pins of all banks must be powered on MAX II devices before entering user mode October 2008 Altera Corporation Chapter 4 Hot Socketing and Power On Reset MAX II Devices 4 7 Power On Reset Circuitry Figure 4 5 Power Up Characteristics for MAX II MAX IIG and MAX IIZ Devices Note 1 2 VccINT MAX II Device Approximate Voltage for SRAM Download Start Device Resets the SRAM and Tri States 1 0 Pins 14V edd gt 0v User Mode Operation Tri State oe Tri S tate Vecint MAX IIG Device 3 3 V Approximate Voltage bod for SRAM Download Start Device Resets EE E the SRAM and NAE Tri States 1 0 Pins 1 55 V 14V MM meme K iconric OV User Mode gt lt gt pe Tri State MAX IIZ Device Approximate Voltage i Vociyr must be powered down for SRAM Download Start to 0 V if the i dips below this level
321. poration MAX II Device Handbook 1 18 Chapter 7 Package Information Document Revision History Document Revision History Table 7 3 shows the revision history for this chapter Table 7 3 Document Revision History Date and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 2 1 December 2007 m Updated Table 7 1 and Table 7 2 m Updated document with Added 68 Pin Micro FineLine Ball Grid MBGA IIZ information Wire Bond and 144 Pin Micro FineLine Ball Grid Array Added information about MBGA Wire Bond sections 68 Pin Micro FineLine Ball Grid Array and 144 Pin Micro FineLine Ball Grid Array m Replaced Figure 7 9 with correct diagram December 2006 m Added document revision history version 1 4 July 2006 m Updated packaging information version 1 3 August 2005 m Updated the 100 pin plastic thin quad flat pack TQFP version 1 2 information December 2004 m Updated Board Decoupling Guidelines section changed version 1 1 the 0 2 value to 0 1 II Device Handbook October 2008 Altera Corporation 8 Using MAX II Devices in Multi Voltage S R A Systems MII51009 1 7 Introduction Technological advancements in deep submicron processes have lowered the supply voltage levels of semiconductor devices creating a design environment where devices on a system
322. r This saves LE resources and improves performance for logic functions such as correlators and signed multipliers that alternate between addition and subtraction depending on data The LAB column clocks 3 0 driven by the global clock network and LAB local interconnect generate the LAB wide control signals The MultiTrack interconnect structure drives the LAB local interconnect for non global control signal generation The MultiTrack interconnect s inherent low skew allows clock and control signal distribution in addition to data Figure 2 5 shows the LAB control signal generation circuit October 2008 Altera Corporation MAX II Device Handbook 2 6 Chapter 2 MAX II Architecture Logic Elements Figure 2 5 LAB Wide Control Signals Dedicated 4 LAB Column Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclkenal labclkena2 syncload labclr2 addnsub Y Y M M labcik1 labclk2 asyncload labcirl synclr or labpre Local Interconnect Sars ae CR CR E CR CR CR UR Logic Elements The smallest unit of logic in the MAX II architecture the LE is compact and provides advanced features with efficient logic utilization Each LE contains a four input LUT which is a function generator that can implement any function of four v
323. r they only read and understand the syntax defined by the Jam file specification In field changes are confined to the Jam file not the Jam Player As result you do not need to modify the Jam Player source code for each in field upgrade There are two types of Jam Players to accommodate the two types of Jam files an ASCII Jam STAPL Player and a Jam STAPL Byte Code Player Both ASCII Jam STAPL Player and Jam STAPL Byte Code Player are coded in the C programming language for 16 bit and 32 bit processors lt For guidelines on UFM operation during ISP refer to the In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices Software Support for UFM Block Software Support for UFM Block 9 13 October 2008 Altera Corporation The Altera Quartus II software includes sophisticated tools that fully utilize the advantages of UFM block in MAX II device while maintaining simple easy to use procedures that accelerate the design process The following section describes how the altufm megafunction supports a simple design methodology for instantiating standard interface protocols for the UFM block such as m Parallel m None Altera Serial Interface This section includes the megafunction symbol the input and output ports a description of the MegaWizard Plug In Ma
324. r 2008 Altera Corporation MAX II Device Handbook 14 20 Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Document Revision History II Device Handbook October 2008 Altera Corporation 15 Using the Agilent 3070 Tester for In ANU RYA System Programming Introduction In system programming is a mainstream feature in programmable logic devices PLDs offering system designers and test engineers significant cost benefits by integrating PLD programming into board level testing These benefits include reduced inventory of pre programmed devices lower costs fewer devices damaged by handling and increased flexibility in engineering changes Altera provides software and device support that integrates in system programmability ISP into the existing test flows for the Agilent 3070 system This chapter discusses how to use the Agilent 3070 test system to achieve faster programming times for Altera s MAXe II devices This chapter contains the following sections m New PLD Product for Agilent 3070 on page 15 1 m Device Support on page 15 1 m Agilent 3070 Development Flow without the PLD ISP Software on page 15 2 m Development Flow for Agilent 3070 with PLD ISP Software on page 15 8 Programming Times on page 15 10 m Guidelines on page 15 10 New PLD Product for Agilent 3070 Agilent Technologies the manufacturer of the Agilent 3070 tester has introduced a new PLD ISP software product
325. r Estimator spreadsheet Importing the Quartus Early Power Estimator File If you have created the user design you can use the Quartus II software to generate the PowerPlay Early Power Estimator file and then import this file into the PowerPlay Early Power Estimator spreadsheet This power estimation report file contains the device resource information and importing this file saves you time and effort otherwise spent manually entering information into the PowerPlay Early Power Estimator spreadsheet You can manually change any of the values after importing the file To generate the PowerPlay Early Power Estimator file first compile your design in the Quartus II software After that on the Project menu click Generate PowerPlay Early Power Estimator File The Quartus II software creates a PowerPlay Early Power Estimator file with the name revision name early pwr csv For more information about generating the PowerPlay Early Power Estimator file in the Quartus II software refer to the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook To import data into the PowerPlay Early Power Estimator spreadsheet perform the following steps 1 Click Import Quartus File in the PowerPlay Early Power Estimator spreadsheet 2 Browse to a power estimation file generated from the Quartus II software Click OK Clicking OK clears any user entered values in the PowerPlay Early Power Estimator spreadsheet and populates the
326. r In System Programming Conclusion Conclusion 15 11 Altera provides complete solutions for programming all MAX II devices using the Agilent 3070 test system All MAX II devices can be programmed together with other ISP capable devices With software and device support the opportunity for cutting costs and increasing manufacturing productivity is available to any Agilent 3070 user Referenced Documents This chapter references the following documents m IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices chapter in the MAX Device Handbook m In System Programmability Guidelines for MAX II Devices chapter in the MAX II Device Handbook Document Revision History Table 15 1 shows the revision history for this chapter Table 15 1 Document Revision History Date and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 1 5 December 2007 m Added Referenced Documents section version 1 4 December 2006 m Added document revision history version 1 3 June 2005 m Text edit to the Programming Times section 25 MHz to 18 MHz version 1 2 January 2005 m Previously published as Chapter 16 No changes to content version 1 1 October 2008 Altera Corporation MAX II Device Handbook 15 12 Chapter 15 Using the Agilent 3070 Tester for In System Programming Document Revision History II Device Handbook Oct
327. r both read only and read write interfaces Figure 9 24 shows page 4 of the altufm MegaWizard Plug In Manager You can select the optional write protection and erase operation methods on this page October 2008 Altera Corporation MAX II Device Handbook 9 24 Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Figure 9 24 Page 4 of the altufm MegaWizard Plug In Manager 12C MegaWizard Plug In Manager ALTUFM page 4 of 7 wp Interface type I2C Resource Usage 3lpm compare 111 lut 2 maxii io 1 ufm about Documentation What is the write configuration For the I2C protocol 2 Page write Write protect Use the wp write protect input Write protect applies to the full memory Write protect applies only to the upper half of the memory What erase method should be used in I2C protocol 2 Device Slave Address Full Erase 3 LSBs are 111 Sector Erase Triggered by Byte Address Sector 0 Trigger erase when writing to binary 000000000 address MSB is always 0 Sector 1 Trigger erase when writing to binary 100000000 address MSB is always 1 2 Sector Erase Triggered by a2 bit 2 No Erase Cancel lt Back Next gt Einish Serial Peripheral Interface Serial peripheral interface SPI is a four pin serial communication subsystem included on the Motorola 6805 and 68HC11 series microcontrollers It allows the microcontr
328. r for In System Programming Agilent 3070 Development Flow without the PLD ISP Software Step 2 Create a Serial Vector Format File The Quartus II software generates SVF Files for programming one or more devices When targeting multiple devices in the same MAX II CPLD family the Quartus II software automatically generates one SVF File to program the devices concurrently Therefore the programming time for all of the devices approaches the programming time for the largest CPLD device in the IEEE Std 1149 1 JTAG chain Figure 15 2 shows the Create JAM SVF or ISC File dialog box File menu which is used to generate the SVF File Figure 15 2 Create JAM SVF or ISC File Dialog Box Create JAM SYF or ISC File File name D Data Example svf rl File format Serial Vector Format svf m peration r Programming options Program Blank check C Verify Verity r Clock frequency TCK frequency 10 0 MHz Supply voltage volts m Before creating the SVF File you must open the Programmer in the Quartus II and add the Programmer Object File pof for all the devices in the chain into the programmer Each POF corresponds to a targeted device respectively In the Create JAM SVE or ISC File dialog box the value in the frequency box should match the frequency that TCK runs at during the test If you enter a different frequency from the one used in actual testing p
329. r up or down four rows October 2008 Altera Corporation MAX II Device Handbook 2 16 Chapter 2 MAX II Architecture Global Signals The UFM block communicates with the logic array similar to LAB to LAB interfaces The UFM block connects to row and column interconnects and has local interconnect regions driven by row and column interconnects This block also has DirectLink interconnects for fast connections to and from a neighboring LAB For more information about the UFM interface to the logic array see User Flash Memory Block on page 2 18 Table 2 2 shows the MAX II device routing scheme Table 2 2 MAX Device Routing Scheme Source LUT Chain Destination LUT Chain Register Chain Local 1 DirectLink 1 R4 1 C4 1 Register Chain Local Interconnect SISIS m DirectLink Interconnect R4 Interconnect C4 Interconnect LE UFM Block SIS SEAIS Column IOE Row IOE SIS SS SS Note to Table 2 2 1 These categories are interconnects Global Signals Each MAX II device has four dual purpose dedicated clock pins GCLK 3 0 two pins on the left side and two pins on the right side that drive the global clock network for clocking as shown in Figure 2 13 These four pins can also be used as general purpose I O if they are not used to drive the global clock network The four global clock lines in th
330. rameters Parameter Description Pin to pin delay for the worst case 1 0 placement with a diagonal path across the device with combinational logic implemented in a single look up table LUT in a logic array block LAB adjacent to output pin Fast 1 0 Connection is used from the adjacent logic element LE to the output pin Pin to pin delay for the best case 1 0 placement with combinational logic 2 input AND gate implemented in a single edge LE adjacent to the input pin The longest pin path of the two inputs is shown Fast 1 0 Connection is used from the adjacent LE to the output pin tour Time to clear register delay The time required for a low signal to appear at the external output measured from the input transition tsu Global clock setup time The time that data must be present at the input pin before the global synchronous clock signal is asserted at the clock pin ty Global clock hold time The time that data must be present at the input pin after the global clock signal is asserted at the clock pin tco Global clock to output delay The time required to obtain a valid output after the global clock is asserted at the clock pin tent Minimum global clock period The minimum period maintained by a globally clocked counter Internal Timing Parameters Within a device the timing delays contributed by individual architectural elements are called internal timing parameters which cannot be m
331. ramming and erasing can only be performed a limited number of times over the life of the device so they do not contribute to average power User Comments Enter any comments optional entry 1 0 Section MAX II Device Handbook MAX II devices feature programmable 1 pins that support a wide range of industry I O standards for increased design flexibility The I O section in the PowerPlay Early Power Estimator spreadsheet allows you to estimate the I O pin power consumption based on the pin s I O standards The total thermal power is the sum of the thermal power consumed by the device based on each power rail Thermal Power Thermal Pyr Thermal October 2008 Altera Corporation Chapter 17 Understanding and Evaluating Power in MAX Il Devices 17 9 PowerPlay Early Power Estimator Inputs Figure 17 9 shows a graphical representation of the thermal power consumption Figure 17 9 Thermal Power Representation VCCINT Vccio MAX II Device Thermal P iNT The PowerPlay Early Power Estimator spreadsheet estimates the current for each I O bank based on the V o settings if you specify the I O bank for I O pins in the I O section Figure 17 10 shows the I O bank parameter settings Thermal Pig ANN Figure 17 10 1 0 Bank Parameter Settings Vecio lccio mA VOBank2 15 50 TEN 21050 Unassigned 000 Table 17
332. rcuit monitors Vecnr and begins SRAM download at an approximate voltage of 1 7 V or 1 55 V for MAX IIG and MAX IIZ devices From this voltage reference SRAM download and entry into user mode takes 200 to 450 us maximum depending on device density This period of time is specified as in the power up timing section of the DC and Switching Characteristics chapter in the MAX II Device Handbook Entry into user mode is gated by whether all V cco banks are powered with sufficient operating voltage and Veco are powered simultaneously the device enters user mode within the tconr specifications If Veco is powered more than tco 4c after Vcanr the device does not enter user mode until 2 us after all Vecio banks are powered For MAX II and MAX IIG devices when in user mode the POR circuitry continues to monitor the Veqnr but not Veco voltage level to detect a brown out condition If there is a Vccwr voltage sag at or below 1 4 V during user mode the POR circuit resets the SRAM and tri states the I O pins Once rises back to approximately 1 7 V or 1 55 V for MAX IIG devices the SRAM download restarts and the device begins to operate after tco 44 time has passed For MAX IIZ devices the POR circuitry does not monitor the Ver and Veco voltage levels after the device enters user mode If there is a Vc voltage sag below 1 4 V during user mode the functionality of the device will not be guaranteed and you must power d
333. ring the acknowledge clock pulse the receiver sends a not acknowledge condition indicating that it is unable to process the last byte of data If the receiver is busy for example executing an internally timed erase or write operation it will not acknowledge any new data transfer Figure 9 13 shows the acknowledge condition on the bus Figure 9 13 Acknowledge on the 12C Bus Data Output 2 By Transmitter Not Acknowledge TM x Data Output By Receiver Acknowledge 4 SCL From Master Clock Pulse For Start Condition Acknowledgement October 2008 Altera Corporation MAX II Device Handbook 9 16 II Device Handbook Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block Device Addressing After the start condition the master sends the address of the particular slave device it is requesting The four most significant bits MSBs of the 8 bit slave address are usually fixed while the next three significant bits A A are device address bits and define which device the master is accessing The last bit of the slave address specifies whether a read or write operation is to be performed When this bit is set to 1 a read operation is selected When this bit is set to 0 a write operation is selected The four MSBs of the slave address A Ay are programmable be defined on page 3 of the altufm MegaWizard Plug In Manager The defaul
334. rmation and do not need any IPS file Always use the POF file with pin state information to create the Jam or JBC files The pin state information can be stored into the POF through the Assignment Editor or saving the pin state information to the POF as mentions earlier The Jam or JBC files be used with the Quartus II programmer or with the Jam or JBC player respectively Conclusion With the real time ISP and ISP clamp features in MAX II devices you can set the I O pins of a device to certain states while programming the device Through real time ISP you can program a MAX II device at any time without affecting the functionality of your system The ISP clamp feature allows you to hold the I O pins of a device to specific states when programming the device Referenced Documents This chapter references the following document m DC and Switching Characteristics chapter in the MAX II Device Handbook MAX II Device Handbook October 2008 Altera Corporation Chapter 12 Real Time ISP and ISP Clamp for MAX Il Devices Document Revision History Document Revision History Table 12 1 shows the revision history for this chapter Table 12 1 Document Revision History 12 11 Date and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 1 6 December 2007 m Added Referenced Documents section version 1 5 December 2006 m Added document revision histo
335. rogramming may fail or you may experience an excessively long programming time You can also select whether to perform a program or verify operation and optionally verify or blank check the device by turning on programming options Altera recommends generating SVF Files that include verify vectors which ensure that programming failures are identified and a limited amount of additional programming time is used You can generate the necessary SVF File based on the scan chain topology of the board and the Altera devices to be programmed Once the SVF File is generated it can be given to test engineers for development If a device must be programmed independently you can generate individual SVF Files for each Altera devicein the chain When creating the SVF File for a single device in the chain specify the POF for the device and leave the rest of the devices set to none This can be done by selecting Add Device in the Programmer These devices are bypassed during programming Repeat this process until all targeted devices have an SVF File II Device Handbook October 2008 Altera Corporation Chapter 15 Using the Agilent 3070 Tester for In System Programming 15 5 Agilent 3070 Development Flow without the PLD ISP Software Step 3 Convert SVF Files to PCF Files You must convert the SVF Files to PCF Files for use with the Agilent 3070 tester with the Altera svf2pcf conversion utility The svf2pcf utility can create multiple PCF Files
336. rry in of 1 in parallel The carry in0 and carry in1 signals from a lower order bit feed forward into the higher order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain Carry select chains can begin in any LE within an LAB October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 11 Logic Elements The speed advantage of the carry select chain is in the parallel precomputation of carry chains Since the LAB carry in selects the precomputed carry chain not every LE is in the critical path Only the propagation delays between LAB carry in generation LE 5 and LE 10 are now part of the critical path This feature allows the MAX II architecture to implement high speed counters adders multipliers parity functions and comparators of arbitrary width Figure 2 9 shows the carry select circuitry in an LAB for a 10 bit full adder One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry in bit the sum is routed to the output of the LE The register can be bypassed for simple adders or used for accumulator functions Another portion of the LUT generates carry out bits An LAB wide carry in bit selects which chain is used for the addition of given inputs The carry in signal for each chain carry in0 or carry inl selects the carry out to carry forward to the carry in signal of the next higher order bit The final carry out signal is routed to
337. rs directory names project names disk drive names file names file name extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters Example AN 75 High Speed Board Design Italic type Internal timing parameters and variables are shown in italic type Examples 1 Variable names are enclosed in angle brackets and shown in italic type Example file name project name pot file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions August 2009 Altera Corporation MAX II Device Handbook Typographic Conventions Visual Cue Courier type Signal and port names are shown in lowercase Courier type Examples aata1 tai input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files 6 0 the AHDL keyword SUBDESIGN as well as logic function nam
338. ry version 1 4 February 2006 m Updated the Real Time ISP with the Quartus I Software section Added Figure 12 3 m Updated Figure 12 9 12 10 2005 m Updated the first paragraph of the How ISP Clamp Works section version 1 2 January 2005 m Previously published as Chapter 13 No changes to content version 1 1 October 2008 Altera Corporation MAX II Device Handbook 12 12 Chapter 12 Real Time ISP and ISP Clamp for MAX II Devices Document Revision History II Device Handbook October 2008 Altera Corporation 13 IEEE 1149 1 JTAG Boundary Scan S p AN Testing for MAX Il Devices MII51014 1 7 Introduction As printed circuit boards PCBs become more complex the need for thorough testing becomes increasingly important Advances in surface mount packaging and PCB manufacturing have resulted in smaller boards making traditional test methods for example external test probes and bed of nails test fixtures harder to implement As a result cost savings from PCB space reductions are sometimes offset by cost increases in traditional testing methods In the 19806 the Joint Test Action Group JTAG developed a specification for boundary scan testing that was later standardized as the IEEE Std 1149 1 specification This boundary scan test BST architecture offers the capability to efficiently test components on PCBs with tight lead spacing This BST archit
339. s 1 PowerPlay Power Analyzer for an accurate analysis based on the exact synthesis of your design Total Represents the total power dissipation The total power dissipation is the sum of the routing and block power User Comments Enter any comments optional entry Figure 17 6 T Flipflop Figure 17 7 4 Bit Counter October 2008 Altera Corporation MAX II Device Handbook 17 8 UFM Section Chapter 17 Understanding and Evaluating Power in MAX II Devices PowerPlay Early Power Estimator Inputs When the design utilizes the UFM the PowerPlay Early Power Estimator spreadsheet considers the time spent during read operations into the power estimation Figure 17 8 shows the UFM section in the PowerPlay Early Power Estimator spreadsheet Figure 17 8 UFM Section User Comments Table 17 4 describes the parameters in the UFM section of the PowerPlay Early Power Estimator spreadsheet Tahle 17 4 UFM Section Information Column Heading Description UFM Module Enter a name for the UFM module in this column optional entry Read Enter the percentage of time the UFM spends in Read mode It takes 16 clock cycles to shift the serial data out after an internal UFM read so the read operation occurs less than 1 17 or about 6 of the time The clock in this calculation is the UFM block s DRCLK signal Total Power mW Total power dissipation due to reading from the UFM block mW Prog
340. s designed to meet the proprietary protocol Proprietary protocol by Microchip Technology Inc The MAX II device supports two different Vccnr of operating voltage ranges Table 10 9 Philips Semiconductors Device Characteristics which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device Interface Operating Size Voltage V Type Device bits SCI SPI 2 Wire 3 Wire 126 Microwire fux 1 EEPROM PCF8582C 2 2048 100kHz 2 5t06 0 EEPROM PCF8594C 2 v 100kHz 2 5to 6 0 EEPROM PCF8598C 2 8 192 v 100kHz 2 5to 6 0 EEPROM PCF85102C 2 2 048 100kHz 2 5t06 0 EEPROM PCF85103C 2 2 048 100kHz 2 5t06 0 Note to Table 10 9 1 The MAX II device supports two different Voc of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to 3 6 V the MAX IIG device supports the 1 71 to 1 89 V operating voltage range II Device Handbook October 2008 Altera Corporation Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory 10 7 List of Vendors and Devices Table 10 10 Rohm Co Ltd Device Characteristics Part 1 of 2 Interface Operating Size 2 3 Voltage V Type Device Bits SCI SPI Wire Wire FC Microwire fmax 1 EEPROM B
341. s from 0 to 100 for output pins and can be up to 200 for input pins used as clocks because clocks toggle at twice the clock frequency Typically the toggle percentage is 12 596 To be more conservative you can use a higher toggle percentage MAX II Device Handbook October 2008 Altera Corporation Chapter 17 Understanding and Evaluating Power in MAX II Devices 17 11 PowerPlay Early Power Estimator Inputs Table 17 6 O Section Information Part 2 of 2 Column Heading OE 96 Description Enter the average percentage of time that m The output 1 0 pins are enabled m Bidirectional 1 0 pins are outputs and enabled During the remaining time m Output 1 0 pins are tri stated m Bidirectional 1 0 pins are inputs This number must be a percentage between 0 and 100 Load pF Enter the pin loading external to the chip pF This parameter only applies to output and bidirectional pins Pin and package capacitance is already included in the 1 0 model Therefore you only need to include off chip capacitance in the Load parameter Bank 1 0 Std Check Indicates whether the selected 1 0 standard is available on the selected 1 0 bank or not Not all 1 0 banks can implement every 1 0 standard Bank Voltage Check Indicates whether the selected 1 0 bank has a voltage compatible with the selected 1 0 standard or not Routing Represents the power dissipation due to estimated routing Routing power
342. s into account the pin capacitance but not board trace and external loading capacitance Additional capacitance for trace connector and loading must be taken into consideration separately The peak current duration due to power up transients is 10 ns or less The DC specification applies when all Vec supplies to the device are stable in the powered up or powered down conditions Hot Socketing Feature Implementation in MAX II Devices II Device Handbook The hot socketing feature turns off tri states the output buffer during the power up event either or Vao supplies or power down event The hot socket circuit generates an internal HOTSCKT signal when either Vc or V cco is below the threshold voltage during power up or power down The HOTSCKT signal cuts off the output buffer to make sure that no DC current except for weak pull up leaking leaks through the pin When Vec ramps up very slowly during power up Vcc may still be relatively low even after the power on reset POR signal is released and device configuration is complete October 2008 Altera Corporation Chapter 4 Hot Socketing and Power On Reset MAX II Devices 4 3 Hot Socketing Feature Implementation in MAX Il Devices a Make sure that the V ccwr is Within the recommended operating range even though SRAM download has completed Each I O and clock pin has the circuitry shown in Figure 4 1 Figure 4 1 Hot Socketing Circuit Block Diagram for MAX
343. s of general purpose user storage The UFM provides programmable port connections to the logic array for reading and writing There are three LAB rows adjacent to this block with column numbers varying by device Table 2 1 shows the number of LAB rows and columns in each device as well as the number of LAB rows and columns adjacent to the flash memory area in the EPM570 EPM1270 and EPM2210 devices The long LAB rows are full LAB rows that extend from one side of row I O blocks to the other The short LAB rows are adjacent to the block their length is shown as width in LAB columns October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 3 Functional Description Table 2 1 MAX 11 Device Resources LAB Rows Short LAB Rows Devices UFM Blocks LAB Columns Long LAB Rows Width 1 Total LABs EPM240 1 6 4 24 EPM570 1 12 4 3 3 57 EPM1270 1 16 7 3 5 127 EPM2210 1 20 10 3 7 221 Vote to Table 2 1 1 The width is the number of LAB columns in length Figure 2 2 shows a floorplan of a MAX II device Figure 2 2 MAX II Device Floorplan Note 1 1 0 Blocks 1 I I I I 1 0 Blocks gt Logic Array S Logic Array Blocks Blocks 2601 8 2 GCL
344. sage on page 14 11 The amount of RAM used by the Jam Player is the size of the JBC file plus the sum of the data required for each device that is targeted If the JBC file is generated using compressed data some RAM is used by the Player to uncompress the data and temporarily store it The uncompressed data sizes are provided in Table 14 3 If an uncompressed JBC file is used use the following equation Equation 14 4 RAM Size JBC File Size October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor 14 13 Software Development Ls The memory requirements for the stack and heap are negligible with respect to the total amount of memory used by the Jam STAPL Byte Code Player The maximum depth of the stack is set by the STACK SIZE parameter in the jbimain c file Estimating Memory Example The following example uses a 16 bit Motorola 68000 processor to program an EPM7128AE device and an EPM7064AE device in an IEEE Std 1149 1 chain via a JBC file that uses compressed data To determine memory usage first determine the amount of ROM required and then estimate the RAM usage Use the following steps to calculate the amount of DRAM required by the Jam Byte Code Player 1 Determine the JBC file size Use the following multi device equation to estimate the JBC file size Because JBC files use compressed data use the compressed data file size information listed in Table 14
345. sed on the speed of the host processor Once the Jam STAPL Byte Code Player is ported and working verify the timing and speed of the JTAG port at the target device Timing parameters in MAX II devices should comply with the values given in the DC and Switching Characteristics chapter in the MAX II Device Handbook If the Jam STAPL Byte Code Player does not operate within the timing specifications the code should be optimized with the appropriate delays Timing violations can occur if the processor is very powerful and can generate TCK at a rate faster than 18 MHz October 2008 Altera Corporation Chapter 14 Using Jam STAPL for ISP via an Embedded Processor 14 11 Software Development La Other than the jbistub c file Altera strongly recommends keeping source code in other files unchanged from their default state Altering the source code in these files will result in unpredictable Jam Player operation Jam STAPL Byte Code Player Memory Usage The Jam STAPL Byte Code Player uses memory in a predictable manner This section documents how to estimate both ROM and RAM memory usage Estimating ROM Usage Use the following equation to estimate the maximum amount of ROM required to store the Jam Player and JBC file Equation 14 1 ROM JBC file size Jam player size The JBC file size can be separated into two categories the amount of memory required to store the programming data and the space required for the programming
346. ser Flash Memory Block m Auto increment addressing m Serial interface to logic array with programmable interface Figure 2 15 UFM Block and Interface Signals UFM Block PROGRAM p gt Program P RTP BUSY ERASE gt Erase D BUSY Control OSC _ gt OSC 4 OSC 9 UFM Sector 1 ARCLK gt UFM Sector 0 Address Register 16 16 ARSHFT gt AR Din _ 4 DR Din Data Register gt DRDout DRCLK 8B DRSHFT UFM Storage Each device stores up to 8 192 bits of data in the UFM block Table 2 3 shows the data size sector and address sizes for the UFM block Table 2 3 UFM Array Size Device Total Bits Sectors Address Bits Data Width EPM240 8 192 2 9 16 EPM570 4 096 bits sector EPM1270 EPM2210 There are 512 locations with 9 bit addressing ranging from 000h to 1FFh Sector 0 address space is 000h to OFFh and Sector 1 address space is from 100h to 1FFh The data width is up to 16 bits of data The Quartus II software automatically creates logic to accommodate smaller read or program data widths Erasure of the UFM involves individual sector erasing that is one erase of sector 0 and one erase of sector 1 is required to erase the entire UFM block Since sector erase is required before a program or write having two sectors enables a sector size
347. ser Flash Memory in MAX II Devices IntroducHOD ot bee RR 9 1 Array Description ere ne s abe 9 1 Memory Organization Map 9 1 Using and Accessing Storage 9 2 UFM Functional Description 9 3 UFM Address s nt aes LEE E LEE 9 5 UFM Data Register issus neue wake eg he P RE ee kee 9 5 Program Erase Control Block 9 6 OscillatOE eco rre de Rene d base eqq pega bes ge eee ale a 9 6 Instantiating the Oscillator without the UFM 9 7 Operating Modes 9 9 Read Str am Read 5 22 der LEY Y REI TD e mE m E eai 9 9 Programi ega EP bte 9 10 Erase PM 9 11 Programming and Reading the UFM 9 12 Jam Files ee ERU E RR DERI EE RR RE REN UR CRAT SPREE ees Rd ER 9 12 Jam Players cessa iret but Rosen benda presets dieses Sera peg 9 12 Software Support for Block
348. sh memory block in II devices This section includes the following chapters m Chapter 9 Using User Flash Memory in MAX II Devices m Chapter 10 Replacing Serial EEPROMs with MAX II User Flash Memory Revision History Refer to each chapter for its own specific revision history For information on when each chapter was updated refer to the Chapter Revision Dates section which appears in the complete handbook October 2008 Altera Corporation MAX II Device Handbook 2 Section Ill User Flash Memory Revision History MAX II Device Handbook October 2008 Altera Corporation ANU 8 RYA MII51010 1 8 9 Using User Flash Memory in MAX II Devices Introduction MAX e II devices feature a user flash memory block that can be used similar to a serial EEPROM for storing non volatile information up to 8 Kbits The UFM provides an ideal storage solution supporting any possible protocol for interfacing parallel and other protocols through bridging logic designed into the MAX II logic array This chapter provides guidelines for UFM applications by describing the features and functionality of the MAX II UFM block and the Quartus II altufm megafunction This chapter contains the following sections m UPM Array Description on page 9 1 UFM Functional Description on page 9 3 Operating Modes on page 9 9 Programming and Reading the UFM with JTAG on page 9 12 Software Support
349. sible for you to perform byte writes since the array is 16 bits for each location October 2008 Altera Corporation MAX II Device Handbook 9 12 Chapter 9 Using User Flash Memory in MAX II Devices Programming and Reading the UFM with JTAG Figure 9 10 UFM Erase Waveforms ABS ity su E 9 Address RET A ARCIk NEN SON ARDin X x X DRShft lt on DRDin DRDout OSC ENA diss t iv Program i 05 Busy Y o wes N tbe le Programming and Reading the UFM with JTAG In Altera MAX II devices you can write or read data to from the UFM using the IEEE Std 1149 1 JTAG interface You can use a PC or UNIX workstation the Quartus II Programmer and the ByteBlaster MV or ByteBlaster I parallel port download cable to download Programmer Object File pof Jam Standard Test and Programming Language STAPL Files jam or Jam Byte Code Files jbc from the Quartus II software targeting the MAX II device UFM block The POF Jam File or JBC File can be generated using the Quartus II software Jam Files Both Jam STAPL and JBC files support programming for the UFM block Jam Players Jam Players read the descriptive information in Jam files and translate them into data that programs the target device Jam Players do not program a particular device architecture or vendo
350. sign when there is a power cycle to the device i e powering down and powering up again This feature enables you to perform in field updates to the MAX II device at any time without affecting the operation of the whole system How Real Time ISP Works For normal ISP operation downloading the new design data from the configuration flash memory CFM to the SRAM begins after the completion of CFM programming During the process of CFM programming and subsequent downloading of CFM data to SRAM I O pins will remain tri stated After the CFM download to the SRAM the device resets and enters user mode operation Figure 12 1 shows the flow of normal programming Figure 12 1 MAX II Device with Normal ISP Operation Programming gt JTAG gt CFM Data p SRAM Logic Array October 2008 Altera Corporation MAX II Device Handbook 12 2 Chapter 12 Real Time ISP and ISP Clamp for MAX II Devices Real Time ISP In real time ISP mode the user flash memory UFM programmable logic and I O pins remain operational while programming of the CFM is in progress The contents of the will not download into the SRAM after the successful programming of the Instead the device waits for a power cycle to occur The normal power up sequence occurs CFM downloads to SRAM at power up and the device enters user mode after time Figure 12 2 shows the flow of real time
351. sing real time ISP to update the CFM block and write new USERCODE data executing the USERCODE instruction returns the current running design s USERCODE stored in the SRAM not the new USERCODE data The new design s USERCODE stored in the CFM can only be read back correctly if a power cycle or forced SRAM download has transpired after the real time ISP update In the Quartus software there is an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code If selected the checksum will be automatically loaded to the USERCODE register On the Assignments menu click Device In the Device dialog box click Device and Pin Options and click the General tab Turn on Auto Usercode CLAMP Instruction Mode The CLAMP instruction mode is used to allow the state of the signals driven from the pins to be determined from the boundary scan register while the bypass register is selected as the serial path between the TDI and TDO ports The state of all signals driven from the output pins will be completely defined by the data held in the boundary scan register However CLAMP will not override the I O weak pull up resistor or the I O bus hold if you have any of them selected HIGHZ Instruction Mode II Device Handbook The HIGHZ instruction mode is used to set all of the user I O pins to an inactive drive state These pins are tri stated until a new JTAG instruction is executed
352. state In addition the TAP controller may be forced to the TEST LOGIC RESET state by holding TMS high for five TCK clock cycles Once in the TEST LOGIC RESET state the TAP controller remains in this state as long as TMS continues to be held high while TCK is clocked Figure 13 6 shows the timing requirements for the IEEE Std 1149 1 signals October 2008 Altera Corporation MAX II Device Handbook 13 8 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices IEEE Std 1149 1 BST Operation Control Figure 13 6 IEEE Std 1149 1 Timing Waveforms Note 1 top E psu um 5 CH riety cL TCK il xz issu sq e I Y X Captured szxi sco 48 28 Signal i to Be X gt Driven i Note to Figure 13 6 1 For timing parameter values refer to the DC and Switching Characteristics chapter in the MAX II Device Handbook To start IEEE Std 1149 1 operation select an instruction mode by advancing the TAP controller to the shift instruction register SHIFT_IR state and shift the appropriate instruction code on the TDI pin The waveform diagram in Figure 13 7 represents the entry of the instruction code into the instruction register It shows the values of TCK TMS TDI and TDO and the states of the TAP controller From the RESET state TMS is clocked with the pattern
353. ster length in MAX II devices IEEE Std 1149 1 boundary scan testing is controlled by a TAP controller which is described in IEEE Std 1149 1 BST Operation Control on page 13 6 The TMS and TCK pins operate the TAP controller and the TDI and TDO pins provide the serial path for the data registers The TDI pin also provides data to the instruction register which then generates control logic for the data registers IEEE Std 1149 1 Boundary Scan Register The boundary scan register is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output The boundary scan register consists of 3 bit peripheral elements that are associated with I O pins of the MAX II devices You can use the boundary scan register to test external pin connections or to capture internal data Refer to the JTAG and In System Programmability chapter in the MAX II Device Handbook for the boundary scan register length of MAX II devices October 2008 Altera Corporation MAX II Device Handbook 13 4 Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices IEEE Std 1149 1 Boundary Scan Register Figure 13 3 shows how test data is serially shifted around the periphery of the IEEE Std 1149 1 device Figure 13 3 Boundary Scan Register Each peripheral element is either an 1 0 pin dedicated input pin or dedicated config
354. story 1 10 12 Section IV In System Programmability Revision History eseri rede segue Diy teehee a a M RR Bend IV 1 Chapter 11 In System Programmability Guidelines for MAX II Devices bie ge en rene d esce bete dirette deed qued 11 1 General ISP Guidelines 11 1 Operating Conditions e CHER tC Cen IR e pace b sin edt e eg ids 11 1 ISP Voltag M e 11 1 Input Voltages edere pepe ete terque ie calito ge eps 11 2 Operations During In System Programming 11 2 Interrupting In System Programming 11 3 MultiVolt Devices and Power Up 11 3 Vee Powered before pee Ra a eee 11 3 I O Pins Tri Stated during In System Programming 1 11 3 Pull Up and Pull Down of JTAG Pins During In System Programming 11 4 IEEE Std prore tithe ebbe pd debet Les 11 4 TOK DIBA Ove 11 4 Programming via a Download Cable
355. t a device with a higher V level drives to a device with an equal or lower Veco level By building the chain in this manner a level shifter may be required only to shift the TDO level to a level acceptable to the tester Figure 13 13 shows the chain of mixed voltages and how a level shifter is inserted in the chain Figure 13 13 JTAG Chain of Mixed Voltages Must be 5 0 V Must be 3 3 V Tolerant Tolerant TDI 5 0 V 3 3 V 2 5 V gt Vccio Vccio TDO Level 1 5 1 8 V Shifter Vccio Vccio lt Shift TDO to Level Must be 1 8 V Must be 2 5 V Accepted by Tester Tolerant Tolerant if Necessary BST for Programmed Devices For a programmed device the input buffers are turned off by default for I O pins that are set as output only in the design file You cannot sample on the programmed device output pins with the default BSDL file when the input buffers are turned off You can set the Quartus II software to always enable the input buffers on a programmed device so it behaves the same as an unprogrammed device for boundary scan testing allowing sample function on output pins in the design This aspect can cause slight increase in standby current as the unused input buffer is always on 1 On the Assignments menu click Settings 2 Under Category select Assembler 3 Turn on Always Enable Input Buffers October 2008 Altera Corporation
356. t is the width of the data bus C Use the osc oscillator output port 1 Ipm_compare 85 lut 1 ufm Cancel lt Back Next gt Finish gt The UFM block s internal oscillator is always running when the altufm parallel magafunction is instantiated for read write interface The UFM block s internal oscillator is disabled when the altufm parallel megafunction is instantiated for read only interface None Altera Serial Interface None means using the dedicated UFM serial interface The built in UFM interface uses 13 pins for the communication The functional description of the 13 pins are described in Table 9 4 on page 9 3 You can produce your own interface design to communicate to from the dedicated UFM interface and implement it in the logic array Instantiating None Using Quartus altufm Megafunction Figure 9 43 shows the altufm megafunction symbol for None instantiation in the Quartus II software Figure 9 43 altufm Megafunction Symbol for None Instantiation none i altufm none i program busy erase osc oscena drdout H arclk rtphusy H arshft ardin ark drdin Interface type NONE Usable flash memory size 8192 bits October 2008 Altera Corporation MAX II Device Handbook 9 40 Chapter 9 Using User Flash Memory in MAX II Devices Creating Memory Content File Figure 9 44 shows page 3 of the altufm M
357. t the maximum power supply is 5 5 V the value of Rexr can be calculated as follows Equation 8 1 Reyr 5 50 45 _ 315 60 16 mA This resistor value computation assumes worst case conditions You can adjust the value according to the device configuration drive strength Additionally if your system does not see a wide variation in voltage supply levels you can adjust these calculations accordingly Because MAX II devices are 3 3 V 32 bit 66 MHz PCI compliant the input circuitry accepts a maximum high level input voltage Vm of 4 0 V To drive MAX II device with a 5 0 V device you must connect a resistor R between the MAX II device and the 5 0 V device See Figure 8 4 October 2008 Altera Corporation MAX II Device Handbook 8 6 II Device Handbook Chapter 8 Using MAX II Devices in Multi Voltage Systems 5 0 V Device Compatibility Figure 8 4 Driving a MAX II PCI Compliant Device with a 5 0 V Device MAX II Device 5 0 V Device Vcc A 7 Modelas R4 we Adi 5 0V 0 5 V Le Vccio PU 7 Vccio Note to Figure 8 4 1 This diode is only active after power up MAX II devices require an external diode if driven by 5 0 V before power up If Vccio for MAX II devices is 3 3 V and theI O clamp diode is enabled the voltage at point B in Figure 8 4 is 4 0 V which meets the MAX II dev
358. t value for these four MSBs is 1010 The next three significant bits are defined using the three A A A input ports of the altufm i2c megafunction You can connect these ports to input pins in the design file and connect them to switches on the board The other option is to connect them to V and GND primitives in the design file which conserves pins Figure 9 14 shows the slave address bits Figure 9 14 Slave Address Bits 1 or 2 Kbit Memory Size 1 0 1 0 Ap Aq Ag RW 4 Kbit Memory Size 7 1 0 1 0 A Aq a8 RW 8 Kbit Memory Size 2 1 0 1 0 a8 R W Notes to Figure 9 14 1 For the 4 Kbit memory size the location in the slave address becomes the MSB a8 of the memory byte address 2 For the 8 Kbit memory size the location in the slave address becomes a8 of the memory byte address while the A location in the slave address becomes the MSB a9 of the memory byte address After the master sends a start condition and the slave address byte the altufm_i2c logic monitors the bus and responds with an acknowledge on the SDA line when its address matches the transmitted slave address The altufm_i2c megafunction then performs a read or write operation to from the UFM depending on the state of the bit Byte Write Operation The master initiates a transfer by generating a start condit
359. ta in parallel You can select an optional width of 3 to 16 bits using the altufm megafunction ADDR 8 0 Address Register Operation sequence refers to the data that is pointed to by the address register You can determine the address bus width using the altufm megafunction nREAD READ Instruction Signal Initiates a read sequence nWRITE WRITE Instruction Signal Initiates a write sequence nERASE ERASE Instruction Signal Initiates a SECTOR ERASE sequence indicated by the MSB of the ADDR port nBUSY BUS Y Signal Driven low to notify that it is not available to respond to any further request DATA VALID Data Valid Driven high to indicate that the data at the port is the valid data from the last read address for read request Even though the altufm megafunction allows you to select the address widths range from 3 bits to 9 bits the UFM block always expects full 9 bits width for the address register Therefore the altufm megafunction will always pad the remaining LSB of the address register with 06 if the register width selected is less than 9 bits The address register will point to sector 0 if the address received at the address register starts with a 0 The address register will point to sector 1 if the address received starts with a 1 Even though you can select an optional data register width of 3 to 16 bits using the altufm megafunction the UFM block always expects full 16 bits width for the data register Reading from th
360. tains the following sections m I O Standards on page 8 2 MultiVolt Core and I O Operation on page 8 3 5 0 V Device Compatibility on page 8 3 Recommended Operating Condition for 5 0 V Compatibility on page 8 7 Hot Socketing on page 8 8 Power Up Sequencing on page 8 8 Power On Reset on page 8 8 October 2008 Altera Corporation MAX II Device Handbook 8 2 1 0 Standards Chapter 8 Using MAX II Devices Multi Voltage Systems 1 0 Standards The I O buffer of MAX II devices is programmable and supports a wide range of I O voltage standards Each I O bank in a MAX II device can be programmed to comply with a different I O standard I O banks can be configured with the following standards 3 3 V LVTIL LVCMOS 2 5 V LVTIL LVCMOS 1 8 V LVTTL LVCMOS 1 5 V LVCMOS The Schmitt trigger input option is supported by the 3 3 V and 2 5 V I O standards The I O Bank 3 also includes 3 3 V PCI1 O standard interface capability on the EPM1270 and EPM2210 devices See Figure 8 1 Figure 8 1 1 0 Standards Supported by MAX II Device Note 1 2 3 4 5 1 0 Bank 1 1 0 Bank 2 1 0 Bank 3 also supports the 3 3 V PCI 1 0 Standard All 1 0 Banks support 3 3 V LVTTL LVCMOS E 2 5 V LVITL LVCMOS 1 0 Bank 3 7 8 V LVTTL LVCMOS 7 5 VLVCMOS Individual Power Bus Notes to Figure 8 1 0 Bank 4 1 Figure 8 1 is a
361. tates in the Assignment Editor and compile the design the programming file generated will have all the pin state information in it The following are the assignment editor states 1 Click Start Analysis and Synthesis on the toolbar 2 On the Assignments menu click Assignment Editor 3 In the Assignment Editor under Category select I O Features 4 List down all the pins you wish to clamp when the device is in ISP clamp mode under the To column You can use the Node Finder to help you select the pins 5 Select In System Programming Clamp State for all the pins under Assignment Name after you have listed down the pins you wish to set state values 6 Define the states for each of the pins under Value You can also choose to clamp the pins to high low tri state or sample and sustain the pin state By default the pins are tri stated when the device enters ISP clamp mode Figure 12 11 shows how to define the states of the pins in the Assignment Editor Figure 12 11 Assignment Editor Assignment Editor 15 xi x Logic Options Advance Global Signals Timing Synthesis Check All Uncheck All Delete All From To Assignment Name D output In System Programmi lt lt new gt gt lt lt new gt gt lt lt new gt gt 1 Save the assignments and recompile your design After you have recompiled the design the ISP clamp state information will be stored in the POF You
362. te an individual SVF File for each targeted Altera device in the chain The process of generating the SVF Files is explained in Step 2 Create a Serial Vector Format File on page 15 4 This process is useful when a verification error occurs and more than one Altera device is programmed in the chain If you still have problems look at the boundary scan chain definition Make sure that the number of bits for the instruction register are specified correctly for each device in the chain If an incorrect number of bits have been defined for any device in the chain the programming test will fail Once the test is running smoothly the board is ready for production programming Altera recommends saving the PCF Files and object code for back up purposes Use a compression program to minimize the size of the stored binaries and files Development Flow for Agilent 3070 with PLD ISP Software II Device Handbook Programming devices with the Agilent 3070 tester and PLD ISP software is slightly different than the steps in Figure 15 1 Figure 15 3 shows the development flow using the Agilent 3070 tester with Agilent s optional PLD ISP software October 2008 Altera Corporation Chapter 15 Using the Agilent 3070 Tester for In System Programming Development Flow for Agilent 3070 with PLD ISP Software 15 9 Figure 15 3 Agilent 3070 Development Flow for In System Programming with Agilent s PLD ISP Software Designer Test Engineer d
363. te and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 1 5 December 2007 m Added Referenced Documents section version 1 4 December 2006 m Added document revision history version 1 3 January 2005 m Previously published as Chapter 11 No changes to version 1 2 content December 2004 m Updated text to Design Considerations section version 1 1 II Device Handbook October 2008 Altera Corporation Section IV In System Programmability S RYAN This section provides information and guidelines for in system programmability ISP and Joint Test Action Group JTAG boundary scan testing BST This section includes the following chapters m Chapter 11 In System Programmability Guidelines for MAX II Devices Chapter 12 Real Time ISP and ISP Clamp for MAX II Devices Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX II Devices Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Chapter 15 Using the Agilent 3070 Tester for In System Programming Revision History Refer to each chapter for its own specific revision history For information about when each chapter was updated refer to the Chapter Revision Dates section which appears in the complete handbook October 2008 Altera Corporation MAX II Device Handbook Iv 2 Section IV In System Programmability Revision History MAX II D
364. terconnect e LEO gt e gt Fast 1 0 connection to IOE 1 LE1 to IOE 1 LE2 DirectLink DirectLink lt interconnect from interconnect from LE3 gt lt gt adjacent LAB adjacent LAB or IOE or IOE gt e LE4 gt 4 e E5 LE6 DirectLink DirectLink interconnect to lt LE7 P interconnect to adjacent LAB adjacent LAB or IOE LE8 or IOE AWN 2 Logic Bement LA Local Interconnect Note to Figure 2 3 1 Only from LABs adjacent to IOEs LAB Interconnects The LAB local interconnect can drive LEs within the same LAB The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB Neighboring LABs from the left and right can also drive an LAB s local interconnect through the DirectLink connection The DirectLink connection feature minimizes the use of row and column interconnects providing higher performance and flexibility Each LE can drive 30 other LEs through fast local and DirectLink interconnects Figure 2 4 shows the DirectLink connection II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 5 Logic Array Blocks Figure 2 4 DirectLink Connection DirectLink interconnect from DirectLink interconnect from left LAB or IOE output right LAB or IOE output LEO LE1 LE2 LE3 6 gt LE4 LES DirectLink DirectLink interconnect lt LE6 p gt interconnect to left t
365. tes the timing models for the MAX II device family I gt Familiarity with device architecture and characteristics is assumed Refer to specific device or device family data sheets in this handbook for a complete description of the architecture and for the specific values of the timing parameters listed in this chapter This chapter contains the following sections m External Timing Parameters on page 16 1 Internal Timing Parameters on page 16 2 m Internal Timing Parameters for MAX II UFM on page 16 3 Timing Models on page 16 4 Calculating Timing Delays on page 16 5 Programmable Input Delay on page 16 7 Timing Model versus Quartus II Timing Analyzer on page 16 7 External Timing Parameters External timing parameters represent actual pin to pin timing characteristics Each external timing parameter consists of a combination of internal timing parameters You can find the values of the external timing parameters in the DC and Switching Characteristics chapter in the MAX II Device Handbook These external timing parameters are worst case values derived from extensive performance measurements and ensured by testing All external timing parameters are shown in bold type Table 16 1 defines external timing parameters for the MAX II family October 2008 Altera Corporation MAX II Device Handbook 16 2 Chapter 16 Understanding Timing MAX II Devices Internal Timing Parameters Table 16 1 External Timing Pa
366. that influence the routing microparameters such as m Fan out for each signal in the delay path m Positions of other loads relative to the signal source and destination October 2008 Altera Corporation MAX II Device Handbook 16 8 Chapter 16 Understanding Timing MAX II Devices Conclusion m Distance between the signal source and destination m Various interconnect lengths where some interconnects are truncated at the edge of the device Conclusion The MAX II device architecture has predictable internal timing delays that can be estimated based on signal synthesis and placement The Quartus II Timing Analyzer provides the most accurate timing information However you can use the timing model along with the timing parameters listed in the DC and Switching Characteristics chapter in the MAX II Device Handbook to estimate a design s performance before compilation Both methods enable you to accurately predict your design s in system timing performance Referenced Documents This chapter references the following document m DC and Switching Characteristics chapter in the MAX II Device Handbook Document Revision History Table 16 5 shows the revision history for this chapter Table 16 5 Document Revision History Date and Revision Changes Made Summary of Changes October 2008 m Updated New Document Format version 2 1 December 2007 m Updated 15 information in Table 16 1 version 2 0 m A
367. that must be programmed or configured Jam STAPL simplifies in field upgrades and revolutionizes the programming of PLDs This chapter describes II device programming support using Jam STAPL in embedded systems This chapter contains the following sections m Embedded Systems on page 14 1 m Software Development on page 14 4 m Updating Devices Using Jam on page 14 14 Embedded Systems embedded systems are made up of both hardware and software components When designing an embedded system the first step is to layout the printed circuit board The second step is to develop the firmware that manages the board s functionality Connecting the JTAG Chain to the Embedded Processor There are two ways to connect the JTAG chain to the embedded processor The most straightforward method is to connect the embedded processor directly to the JTAG chain In this method four of the processor pins are dedicated to the JTAG interface thereby saving board space but reducing the number of available embedded processor pins Figure 14 1 illustrates the second method which is to connect the JTAG chain to an existing bus via an interface PLD In this method the JTAG chain becomes an address on the existing bus The processor then reads from or writes to the address representing the JTAG chain October 2008 Altera Corporation MAX II Device Handbook 14 2 Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Embedde
368. the MAX II device timing models Preliminary status means the timing model is subject to change Initially timing numbers are created using simulation results process data and other known parameters These tests are used to make the preliminary numbers as close to the actual timing parameters a s possible Final timing numbers are based on actual device operation and testing These numbers reflect the actual performance of the device under the worst case voltage and junction temperature conditions Table 5 13 MAX II Device Timing Model Status Part 1 of 2 Device Preliminary Final EPM240 EPM240Z 1 v EPM570 v EPM570Z 1 August 2009 Altera Corporation MAX II Device Handbook Chapter 5 DC and Switching Characteristics Timing Model and Specifications 5 10 Table 5 13 MAX II Device Timing Model Status Part 2 of 2 Device Preliminary Final EPM1270 2210 v Note to Table 5 13 1 The MAX IIZ device timing models are only available in the Quartus II software version 8 0 and later Performance Table 5 14 shows the MAX II device performance for some common designs performance values were obtained with the Quartus II software compilation of megafunctions Performance values for 3 4 and speed grades are based on an EPM1270 device target while 6 7 and 8 speed grades are based on an EPM570Z device target Table 5 14 M
369. the PowerPlay Early Power Estimator spreadsheet Table 17 9 Power Supply Current Information Column Heading Description lcceowenue Represents the maximum current drawn during power up l oir Represents the total current drawn from the supply 1546 Represents the total current drawn from the leco power rail s Refer to the 1 0 Section on page 17 8 for details about the current drawn from each 0 rail Power Saving Techniques The following guidelines reduce power consumption for an application m Slow the operation in portions of the circuit is proportional to the frequency of operation Slowing parts of a circuit lowers the and therefore reduces the power MAX II devices provide global or array clock source for all registers Signals that do not require high speed operation can use a slower array clock that reduces the system power consumption m Reducethe number of outputs Standby and dynamic current are required to support all I O pins on the device Reducing the number of I O pins can reduce current necessary for the device and thereby reduce the power October 2008 Altera Corporation MAX II Device Handbook 11 16 Conclusion Chapter 17 Understanding and Evaluating Power MAX II Devices Conclusion Reduce the loading and or external capacitance on the outputs Excessive loading and capacitance of printed circuit board PCB traces and other ICs on the output pins significantl
370. the Quartus II software Figure 9 41 altufm Megafunction Symbol for Parallel Interface Instantiation Parallel altufm parallel data valid Interface type PARALLEL Usable flash memory size 8192 bits Figure 9 42 shows page 3 of the altufm MegaWizard Plug In Manager selecting the Parallel Interface as the interface On this page you can choose whether to implement the Read Write mode or Read Only mode for the UFM You also have an option to choose the width for address bus up to 9 bits and for the data bus up to 16 bits You can specify the initial content of the UFM block on page 4 of the altufm MegaWizard Plug In Manager as discussed in Creating Memory Content File on page 9 40 II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 39 Software Support for UFM Block Figure 9 42 Page 3 altufm MegaWizard Plug In Manager Parallel MegaWizard Plug In Manager ALTUFM page 3 of 5 Flash Memory gt Flash Memory settings 5 Currently selected device Family MAX II 2 Parallel aitutm parallel addr 8 0 dataout 15 0 datain 15 0 nbusy nread data valid nwrite nerase L Match project default What is the interface protocol N 2 Serial Peripheral Interface SPI 2 pc Interface type PARALLEL What is the access mode for the user flash memory Read Write 2 Read Only What is the width of the address bus Wha
371. the SPI Base mode both read only and read write nCS signal and SCK are not allowed to toggle at the same time Table 9 14 shows the timing parameters which only apply to the SPI Extended mode read write Figure 9 37 SPI Timing Waveform Lb IuNCSHIGH nCS ISCKNCS 1 INCS2SCK J Ld II Device Handbook October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices Software Support for UFM Block Table 9 14 SPI Timing Parameters for Extended Mode 9 35 edge to SCK signal rising edge Symbol Description Minimum ns Maximum ns Licences The time required for the sck signal falling 50 edge to ncs signal rising edge Vues The time thatthe ncs signal must be held 600 high Vlucsasck The time required for the ncs signal falling 750 Instantiating SPI Using Quartus altufm Megafunction Figure 9 38 shows the altufm megafunction symbol for SPI instantiation in the Quartus II software Figure 9 38 altufm Megafunction Symbol for SPI Instantiation Interface type SPI inst You can select the desired logic array interface on page 3 of the altufm MegaWizard Plug In Manager Figure 9 39 shows page 3 of the altufm MegaWizard Plug In Manager selecting SPI as the interface protocol On this page you can choose whether to implement the Read Write or Read Only mode as the access mode for the You can also sel
372. the following syntax test digital prog a test digital prog b test digital prog c test digital prog d First program file Second program file Third program file Fourth program file October 2008 Altera Corporation Chapter 15 Using the Agilent 3070 Tester for In System Programming 15 7 Agilent 3070 Development Flow without the PLD ISP Software Keep the test execution in the same order in which the SVF File was split For example if the SVF File was split into four files pcf1 pcf2 pcf3 and pcf4 the tests must be executed in the order that they split execute prog a followed by prog b followed by prog c followed by prog If the order is not preserved the device s will fail to program correctly Step 5 Compile the Executable Tests Altera recommends batch driven compilation using either BT Basic or a UNIX shell See the following batch file code in assuming four executable tests to program the target device and generation of debugging object code compile digital prog a debug compile digital prog b debug compile digital prog c debug compile digital prog d debug This file should be saved in the board directory to allow engineering changes to take place at a later date See the corresponding shell script D option generates debugging information dcomp D digital prog_a dcomp D digital prog_b dcomp D digital prog_c dcomp D digital prog d a
373. their devices which be replaced by the MAX II UFM block The operating condition range for the UFM block and MAX II devices are within the range of the devices listed Interface Operating Size 1 2 3 fux Voltage V Type Device Bits SCI Wire Wire Wire Microwire MHz 1 EEPROM AK93C75AV 8 192 1 8105 5 EEPROM AK93C75BH 8 192 1 8105 5 EEPROM AK6480AF M 8 192 v 1 1 8 to 5 5 EEPROM AK6480BH L 8 192 1 1 8105 5 EEPROM AK93C65AFV 4 096 v 1 8 to 5 5 EEPROM AK93C65BH 4 096 v 1 8t0 5 5 EEPROM AK93C61 AV 4 096 v 0 9 to 3 6 EEPROM AK6440AF M 4 096 1 1 8t0 5 5 EEPROM AK6440BH L 4 096 v 1 1 8t0 5 5 EEPROM AK6004AF 4 096 v 1 8t0 5 5 EEPROM AK93C55AFV 2 048 1 810 5 5 EEPROM AK93C55BH 2 048 1 8 to 5 5 EEPROM AK93C51 AV 2 048 v 0 9 to 3 6 EEPROM AK6420AF M 2 048 1 1 8t0 5 5 EEPROM AK6420BH 2 048 1 1 8t0 5 5 EEPROM AK6003AV 2 048 v 1 8t0 5 5 Note to Table 10 2 1 The MAX II device supports two different of operating voltage ranges which are 2 375 to 2 625 V and 3 0 to
374. ting the ARSHIFT signal while clocking the ARCLK signal increments the address register value to read consecutive locations from the UFM array The UFM block supports a serial interface with serial address and data signals The internal shift registers within the UFM block for address and data are 9 bits and 16 bits wide respectively The Quartus II software automatically generates interface logic in LEs for a parallel address and data interface to the UFM block Other standard protocol interfaces such as SPI are also automatically generated in LE logic by the Quartus II software For more information about the UFM interface signals and the Quartus II LE based alternate interfaces refer to the Using User Flash Memory in MAX II Devices chapter in the MAX II Device Handbook UFM Block to Logic Array Interface II Device Handbook The UFM block is a small partition of the flash memory that contains the CFM block as shown in Figure 2 1 and Figure 2 2 The UFM block for the EPM240 device is located on the left side of the device adjacent to the left most LAB column The UFM block for the EPM570 EPM1270 and EPM2210 devices is located at the bottom left of the device The UFM input and output signals interface to all types of interconnects R4 interconnect C4 interconnect and DirectLink interconnect to from adjacent LAB rows signals can also be driven from global clocks GCLK 3 0 The interface region for the EPM240 devic
375. to 50 When the OSC_ENA input signal is asserted the oscillator is enabled and the output is routed to the logic array through the OSC output When the OSC_ENA is set low the OSC output drives constant low The routing delay from the OSC port of the UFM block to OSC output pin depends on placement You can analyze this delay using the Quartus II timing analyzer October 2008 Altera Corporation Chapter 9 Using User Flash Memory MAX Il Devices 9 7 UFM Functional Description The undivided internal oscillator which is not accessible operates in a frequency range from 13 33 to 22 22 MHz The internal oscillator is enabled during power up in system programming and real time ISP At all other times the oscillator is not running unless the UFM is instantiated in the design and the OSC_ENA port is asserted To see how specific operating modes of ALTUFM handle OSC and the oscillator refer to Software Support for UFM Block on page 9 13 For user generated logic interfacing to the UFM the oscillator must be enabled during PROGRAM or ERASE operations but not during READ operations 05 ENA can be tied low if you are not issuing any PROGRAM or ERASE commands 5 During real time ISP operation the internal oscillator automatically enables and outputs through the OSC output port if this port is instantiated even though the OSC_ENA signal is tied low You can use the RTP_BUSY signal to detect the beginning and ending of the r
376. to BST you can use the IEEE Std 1149 1 controller for in system programming for MAX II devices MAX II devices support IEEE 1532 programming which utilizes the IEEE Std 1149 1 Test Access Port interface However this chapter only discusses the BST feature of the IEEE Std 1149 1 circuitry IEEE Std 1149 1 BST Architecture A MAX II device operating in IEEE Std 1149 1 BST mode uses four required pins TDI TDO TMS and TCK Table 13 1 summarizes the functions of each of these pins MAX II devices do not have a TRST pin Table 13 1 EEE Std 1149 1 Pin Descriptions Pin Description Function TDI 7 Test data input Serial input pin for instructions as well as test and programming data Data is shifted in on the rising edge of TDO Test data output Serial data output pin for instructions as well as test and programming data Data is shifted out on the falling edge of TCK The pin is tri stated if data is not being shifted out of the device TMS 1 Test mode select Input pin that provides the control signal to determine the transitions of the TAP controller state machine Transitions within the state machine occur at the rising edge of Therefore TMS must be set up before the rising edge of TMS is evaluated on the rising edge of TCK 2 Test clock input The clock input to the BST circuitry Some operations occur at the rising edge while others occur at the falling edge
377. tpm tn ttur tcome trasto top Atop Figure 16 4 External Timing Parameter too Note 1 2 LE gt Register Notes to Figure 16 4 1 tco tc Nx try 4 664 4 OF top Atop 2 The constants N and M are subject to change according to the position of the LAB in the entire device Figure 16 5 LE Register Clear and Preset Time teur Note 7 LE gt Register Note to Figure 16 5 1 torr tero tc terr N x tr4 4 M x tc4 4 trope or tiopr top Atop Figure 16 6 LE Register Clear and Preset Time tpa Note 1 EE LE gt Register Note to Figure 16 6 1 trocar tc N x 4 4 M x tc4 4 or top Atop Setup and Hold Time from an 1 0 Data and Clock Input The Quartus II software might insert additional routing delays from the input pin to the register input to ensure a zero hold time for the LE register Altera recommends that you use the Quartus II Timing Analyzer to obtain the setup time and hold time See Figure 16 7 and Figure 16 8 October 2008 Altera Corporation Chapter 16 Understanding Timing in MAX II Devices 16 7 Programmable Input Delay Figure 16 7 Setup and Hold Time tsu Note 1 2 4 Combinational o Lo
378. truction to generate the read pulse and shifting out the data for comparison This process is repeated for each CFM and UFM address 6 Exit ISP An exit ISP stage ensures that the I O pins transition smoothly from ISP mode to user mode October 2008 Altera Corporation MAX II Device Handbook 3 6 Chapter 3 JTAG and In System Programmability In System Programmability Table 3 4 shows the programming times for MAX II devices using in circuit testers to execute the algorithm vectors in hardware Software based programming tools used with download cables are slightly slower because of data processing and transfer limitations Table 3 4 MAX 11 Device Family Programming Times EPM240 EPM570 EPM240G EPM570G EPM1270 2210 Description 2407 EPM570Z 12706 EPM2210G Unit Erase Program 1 MHz 1 72 2 16 2 90 3 92 Sec Erase Program 10 MHz 1 65 1 99 2 58 3 40 Sec Verify 1 MHz 0 09 017 0 30 0 49 sec Verify 10 MHz 0 01 0 02 0 03 0 05 sec Complete Program Cycle 1 MHz 1 81 2 33 3 20 4 41 sec Complete Program Cycle 10 MHz 1 66 2 01 2 61 3 45 sec UFM Programming The Quartus II software with the use of POF Jam or JBC files supports programming of the user flash memory UFM block independent of the logic array design pattern stored in the CFM block This allows updating or reading UFM contents through ISP without altering the current logic array design or vice versa By
379. ts should be set to all 1 for addresses 080h to 17Fh Lower Half Addresses 00h to 7Fh Address 00h in logical memory maps to address 000h in the MIF HEX file Address 7Fh in logical memory maps to 07Fh in the MIF HEX file and all data in between follows the order in the logical memory Memory Map for 4 Kbit Memory Initialization Figure 9 49 shows the memory map initialization for the altufm_i2c megafunction of 4 Kbit memory The altufm 12 megafunction byte address location of 00h to FFh is mapped to the block address location of 000h to OFFh The altufm 12 megafunction byte address location of 100h to 1FFh is mapped to the UFM block address location of 100h to 1FFh Figure 9 51 Memory Map for 4 Kbit Memory Initialization 4 Kbit altufm i2c Megafunction MIF or HEX File Contents to represent Logical Memory Contents the data and address size for the UFM block Address 100h in logical memory maps to 100h in the MIF HEX file Address 1FFh in logical Upper Half Addresses memory maps to 1FFh in the MIF HEX file and all 100h to 1FFh data in between follows the order in the logical memory Address 00h in logical memory maps to 000h in the MIF HEX file Address FFh in logical memory maps to OFFh in the MIF HE X file and all data in between follows the order in the logical memory Lower Half Addresses 00h to FFh Memory Map for 8 Kbit Memory Initialization Figure 9 52 shows the memory map initialization f
380. tted into the interface to update BP1 and BPO of the status register 4 If ncS is pulled high too early before all the eight bits in Step 2 or Step 3 are transmitted or too late the ninth bit or more is transmitted WRSR is not executed October 2008 Altera Corporation MAX II Device Handbook 9 34 Chap ter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block 5 nCSis pulled back to high to terminate the transmission Figure 9 36 WRSR Operation Sequence ncs E SCK 012345678 91011 12 131 15 iil 4 800 Instruction SI Status Register In X 50 5 High Impendance Table 9 12 Block Write Protect Bits for Extended Mode Status Register Bits UFM Array Address Level BP1 BPO Protected 0 No protection 0 0 None 3 Full protection 1 1 000 to 1FF Table 9 13 Block Write Protect Bits for Base Mode Status Register Bits UFM Array Address Level BP1 BPO Protected 0 No protection 0 0 None 3 Full protection 1 1 000 to OFF ALTUFM SPI Timing Specification Figure 9 37 shows the timing specification needed for the SPI Extended mode read write These nCS timing specifications do not apply to the SPI Extended read only mode nor any of the SPI Base modes However for the SPI Extended mode read only and
381. ultilrack interconnect structure The MultiTrack interconnect consists of continuous performance optimized routing lines used for inter and intra design block connectivity The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance The MultiTrack interconnect consists of row and column interconnects that span fixed distances A routing structure with fixed length resources for all devices allows predictable and short delays between logic levels instead of large delays associated with global or long routing lines Dedicated row interconnects route signals to and from LABs within the same row These row resources include m DirectLink interconnects between LABs m Rh4interconnects traversing four LABs to the right or left The DirectLink interconnect allows an LAB to drive into the local interconnect of its left and right neighbors The DirectLink interconnect provides fast communication between adjacent LABs and or blocks without using row interconnect resources October 2008 Altera Corporation Chapter 2 MAX Il Architecture 2 13 MultiTrack Interconnect The R4 interconnects span four LABs and are used for fast row connections in a four LAB region Every LAB has its own set of R4 interconnects to drive either left or right Figure 2 10 shows R4 interconnect connections from an LAB R4 interconnects can drive and be driven by row IOEs For LAB interfacing a primary LAB or horiz
382. ume different amounts of power for the same design The larger the device the more power it consumes because of a larger clock tree In the Main section you can enter the following parameters for the device and design m Device m Package m Temperature grade m Power characteristics B Vecnr Supply m Ambient temperature m Airflow Figure 17 3 shows the Input Parameter section in the PowerPlay Early Power Estimator spreadsheet Figure 17 3 Input Parameter Section Input Parameters Device EPM240 Package F100 4 Temperature Grade Commercial Typical Power Characteristics dade Vecint Supply Voltage 3 37 Table 17 1 describes the values that must be specified in the Input Parameter section of the PowerPlay Early Power Estimator spreadsheet Table 17 1 Input Parameter Section Information Part 1 of 2 Input Parameter Description Device Select your MAX II device Larger devices have slightly higher clock dynamic power MAX IIZ devices have the lowest lc compared to the MAX II and 116 devices because MAX IIZ devices have optimized circuitry to reduce ln Compared to MAX II devices MAX IIG devices use less power because they do not use the on chip voltage regulator Package Select the package that will be used Larger packages provide a larger cooling surface and more contact points to the circuit board leading to lower thermal resistance Package selection does not affect power c
383. umn or row I O block interfaces with its adjacent LAB and Multilrack interconnect to distribute signals throughout the device The row I O blocks drive row column or DirectLink interconnects The column I O blocks drive column interconnects II Device Handbook October 2008 Altera Corporation Chapter 2 MAX II Architecture 1 0 Structure Figure 2 20 shows how a row I O block connects to the logic array Figure 2 20 Row 1 0 Block Connection to the Interconnect Note 1 2 25 R4 Interconnects 4 Interconnects 0 Block Local Interconnect to Adjacent LAB LAB Local Interconnect Note to Figure 2 20 Interconnect data out 6 0 7 OE 6 0 7 fast out 6 0 7 pum data in 6 0 7 Direct Link Interconnect from Adjacent LAB AB Column clock 3 0 Row 1 0 Block Row 1 0 Block Contains up to Seven IOEs 1 Each of the seven IOEs in the row 1 0 block can have one data out Or fast out output one output and one data in input October 2008 Altera Corporation MAX II Device Handbook 2 26 Chapter 2 MAX II Architecture 1 0 Structure Figure 2 21 shows how a column I O block connects to the logic array Figure 2 21 Column 1 0 Block Connection to the Interconnect Note 7 Column 1 0 Column 1 0 Block Block Contains Up To 4 IOEs data out OE fast out E 3 0
384. uration pin 114 Controller TDI TMS TCK TDO Boundary Scan Cells of a MAX II Device 1 0 Pin II Device Handbook Except for the four JTAG pins and power pins all pins of a MAX II device including clock pins be used as user I O pins and have a boundary scan cell BSC The 3 bit BSC consists of a set of capture registers and a set of update registers The capture registers can connect to internal device data via the OUTJ and OEJ signals while the update registers connect to external data through the PIN OUT and PIN signals The global control signals for the IEEE Std 1149 1 BST registers for example SHIFT CLOCK and UPDATE are generated internally by the TAP controller the MODE signal is generated by a decode of the instruction register The data signal path for the boundary scan register runs from the serial data in SDI signal to the serial data out SDO signal The scan register begins at the TDI pin and ends at the pin of the device October 2008 Altera Corporation Chapter 13 IEEE 1149 1 JTAG Boundary Scan Testing for MAX Il Devices 13 5 IEEE Std 1149 1 Boundary Scan Register Figure 13 4 shows the User I O Boundary Scan Cell of MAX devices Figure 13 4 MAX II Device s User 1 0 BSC with IEEE Std 1149 1 BST Circuitry
385. ure 2 23 is a top view of the silicon die 2 Figure 2 23 is a graphical representation only Refer to the pin list and the Quartus II software for exact pin locations II Device Handbook Each I O bank has dedicated Veco pins that determine the voltage standard support in that bank A single device can support 1 5 V 1 8 V 2 5 V and 3 3 V interfaces each individual bank can support a different standard Each I O bank can support multiple standards with the same Vo for input and output pins For example when Veco is 3 3 V Bank 3 can support LVTTL LVCMOS and 3 3 V PCI Ve powers both the input and output buffers in MAX II devices TheJTAG pins for MAX II devices are dedicated pins that cannot be used as regular I O pins The pins TMS TDI TDO and TCK support all the I O standards shown in Table 2 4 on page 2 27 except for PCI These pins reside in Bank 1 for all MAX II devices and their I O standard support is controlled by the Vecio setting for Bank 1 PCI Compliance The MAX II EPM1270 and EPM2210 devices are compliant with PCI applications as well as all 3 3 V electrical specifications in the PCI Local Bus Specification Revision 2 2 These devices are also large enough to support PCI intellectual property IP cores Table 2 5 shows the MAX II device speed grades that meet the PCI timing specifications October 2008 Altera Corporation Chapter 2 MAX II Architecture 2 29 VO Structure Schmitt Trigger Ls Table 2
386. uses a resistor to pull the signal level to the last driven state The DC and Switching Characteristics chapter in the MAX II Device Handbook gives the specific sustaining current for each V cco voltage level driven through this resistor and overdrive current used to identify the next driven input level The bus hold circuitry is only active after the device has fully initialized The bus hold circuit captures the value on the pin present at the moment user mode is entered Programmable Pull Up Resistor Ls Each MAX II device I O pin provides an optional programmable pull up resistor during user mode If the designer enables this feature for an I O pin the pull up resistor holds the output to the V level of the output pin s bank The programmable pull up resistor feature should not be used at the same time as the bus hold feature on a given I O pin Programmable Input Delay The MAX II IOE includes a programmable input delay that is activated to ensure zero hold times A path where a pin directly drives a register with minimal routing between the two may require the delay to ensure zero hold time However a path where a pin drives a register through long routing or through combinational logic may not require the delay to achieve a zero hold time The Quartus II software uses this delay to ensure zero hold times when needed MultiVolt 1 0 Interface The MAX II architecture supports the MultiVolt I O interface feature which allows MAX I
387. ut voltage IOL 2 mA 7 0 45 Table 5 9 1 5 1 0 Specifications Symbol Parameter Conditions Minimum Maximum Unit Vecio 0 supply voltage 1 425 1 575 V High level input voltage 0 65 x Vecio Vecio 0 3 2 V Vi Low level input voltage 0 3 0 35 x Vecio V Von High level output voltage 2 mA 1 0 75 x Vecio V Vor Low level output voltage IOL 2 mA 1 0 25 x Vecio V Notes to Table 5 5 through Table 5 9 1 This specification is supported across all the programmable drive strength settings available for this 1 0 standard as shown in the MAX II Architecture chapter 1 0 Structure section in the MAX Device Handbook 2 This maximum Vn reflects the specification The MAX II input buffer can tolerate a Vi maximum of 4 0 as specified by the V parameter in Table 5 2 II Device Handbook August 2009 Altera Corporation Chapter 5 DC and Switching Characteristics Operating Conditions Table 5 10 3 3 V PCI Specifications Note 1 5 7 Symbol Parameter Conditions Minimum Typical Maximum Unit Vecio 1 0 supply 3 0 3 3 3 6 V voltage High level input E 0 5 x Vecio i Vecio 0 5 V voltage Vi Low level input 0 5 0 3 x Vecio V voltage Vou High level 500 0 9 Vecio output voltage Vo Low level IOL 1 5 mA 0 1 x Veco V output voltage Note to Table 5 10 1 3 3 V PCI
388. veform for the altufm_i2c megafunction read write mode Figure 9 21 Timing Waveform for the altufm i2c Megafunction Chapter 9 Using User Flash Memory in MAX II Devices Software Support for UFM Block tow tsu sTO lt gt lt tBUF Table 9 6 through Table 9 8 list the timing specification needed for the altufm i2c megafunction read write mode Table 9 6 12C Interface Timing Specification Symbol Parameter Min Max Unit SCL clock frequency 100 kHz tscusoa SCL going low to SDA data out 15 ns lur Bus free time between a stop and start condition 4 7 us thos Repeated start condition hold time 4 us teu sta Repeated start condition setup time 47 us Low SCL clock low period 47 us SCL clock high period 4 us tuovat SDA data in hold time 0 ns loos SDA data in setup time 20 ns tsu sto STOP condition setup time 4 ns Table 9 7 UFM Write Cycle Time Parameter Min Max Unit Write Cycle Time 110 us Table 9 8 UFM Erase Cycle Time Parameter Min Max Unit Sector Erase 501 ms Cycle Time Full Erase Cycle 1 002 ms Time Instantiating the 126 Interface Using the Quartus Il altufm Megafunction Figure 9 22 shows the altufm megafunction symbol for a PC interface instantiation in the Quartus II software II Device Handbook October 2008 Altera Corporat
389. vision history version 1 5 July 2006 m Minor content update version 1 4 August 2005 m Updated the entire MAX Power Estimation Using the PowerPlay Early version 1 3 Power Estimator section January 2005 m Previously published as Chapter 18 No changes to content version 1 2 December 2004 m Added Excel Macro General 1 0 AC Power and General 1 0 DC Power version 1 1 sections m Updated figures m Updated Table 17 1 October 2008 Altera Corporation MAX II Device Handbook
390. wide signals control the logic for the register s clear and preset signals The LE directly supports an asynchronous clear and preset function The register preset is achieved through the asynchronous load of a logic high MAX II devices support simultaneous preset asynchronous load and clear signals An asynchronous clear signal takes precedence if both signals are asserted simultaneously Each LAB supports up to two clears and one preset signal In addition to the clear and preset ports MAX II devices provide a chip wide reset pin DEV_CLRn that resets all registers in the device An option set before compilation in the Quartus II software controls this pin This chip wide reset overrides all other control signals and uses its own dedicated routing resources that is it does not use any of the four global resources Driving this signal low before or during power up prevents user mode from releasing clears within the design This allows you to control when clear is released on a device that has just been powered up If not set for its chip wide reset function the DEV_CLRn pin is a regular I O pin By default all registers in MAX II devices are set to power up low However this power up state can be set to high on individual registers during design entry using the Quartus II software MultiTrack Interconnect II Device Handbook In the MAX II architecture connections between LEs the UFM and device I O pins are provided by the M
391. wing documents m DC and Switching Characteristics chapter in the MAX II Device Handbook m Hot Socketing and Power On Reset in MAX II Devices chapter in the MAX II Device Handbook Document Revision History Table 8 4 shows the revision history for this chapter Table 8 4 Document Revision History 8 9 Date and Revision Changes Made Summary of Changes October 2008 m Updated Figure 8 2 version 1 7 m Updated 5 0 V Device Compatibility and Conclusion sections m Updated New Document Format December 2007 m Updated Introduction section Updated document with version 1 6 MultiVott Core and 1 0 Operation section MAX IIZ information m Updated Note 1 to Figure 8 2 m Added Referenced Documents section December 2006 m Added document revision history version 1 5 August 2006 m Updated 5 0 V Device Compatibility section version 1 4 February 2006 m Updated Figure 8 3 version 1 3 January 2005 m Previously published as Chapter 9 No changes to content version 1 2 December 2004 m Corrected typographical errors in Note 3 of Figure 8 2 version 1 1 October 2008 Altera Corporation MAX II Device Handbook 8 10 Chapter 8 Using MAX II Devices Multi Voltage Systems Document Revision History II Device Handbook October 2008 Altera Corporation Section 111 User Flash Memory S RAN This section provides information on the user fla
392. y increases the power Keeping excess load and external capacitance to a minimum on the outputs pins whenever possible will significantly reduce the current necessary for the device Reduce the amount of circuitry in the device Power depends on the amount of internal logic that switches at any given time Reducing the amount of logic in a device reduces the current in the device and thus reduces the power Modify the design to reduce power Identify areas in the design that can be revised to reduce the power requirements Common solutions include reducing the number of switching nodes and or required logic and removing redundant unnecessary signals Modify I O Locations Grouping I O pins from common logic blocks allows the Quartus II software to place the associated logic closer together The more compact a logic block and I O the lower its dynamic power especially true of low utilization designs with I O spread around the device Increase the performance requirements in the constraint file Improving the performance that is beyond the need for operation reduces the power dissipation The Quartus II software optimizes the design and places logic closer together uses shorter routing and fewer logic levels and lowers dynamic power and improves performance MAX II devices offer a power down capability that conserves battery life for portable applications For more information about the power down capability in MAX II devices and an applicat
393. ze jtag hardware jtag hardware initialized TRUE data tdi 0x40 0 tms 0x2 0 TDI TMS write byteblaster 0 data if read tdo tdo read byteblaster 1 amp 0x80 9 0 1 TDO write_blaster 0 data 0x01 TCK write blaster 0 data return tdo In the previous code the PC parallel port inverts the actual value of TDO The jbi jtag io source code inverts it again to retrieve the original data The line which inverts the TDO value is as follows tdo read byteblaster 1 amp 0x80 0 1 October 2008 Altera Corporation MAX II Device Handbook 14 10 II Device Handbook Chapter 14 Using Jam STAPL for ISP via an Embedded Processor Software Development If the target processor does not invert TDO the code should look like tdo read byteblaster 1 amp 0x80 1 0 map the signals to the correct addresses use the left shift lt lt or right shift gt gt operators For example if TMS and TDI are at ports 2 and 3 respectively the code would be as follows data tdi 0x40 0 gt gt 3 ms 0x02 0 1 Apply the same process to TCK and TDO The read byteblaster and write byteblaster signals use the and outp functions from the conio h library respectively to read and write to the port If these functions are not available equivalent functions should be substituted Step 3 Handle Text Messages from jbi export The jbi export

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