ALTERA Hot Socketing Manual
Contents
1. 4 Hot Socketing amp A DTE P YA n Power On Reset Stratix Il Hot Socketing Specifications Altera Corporation May 2007 Stratix II devices offer hot socketing which is also known as hot plug in or hot swap and power sequencing support without the use of any external devices You can insert or remove a Stratix II board in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system The hot socketing feature also removes some of the difficulty when you use Stratix II devices on printed circuit boards PCBs that also contain a mixture of 5 0 3 3 2 5 1 8 1 5 and 1 2 V devices With the Stratix II hot socketing feature you no longer need to ensure a proper power up sequence for each device on the board The Stratix II hot socketing feature provides E Board or device insertion and removal without external components or board manipulation E Support for any power up sequence E Non intrusive I O buffers to system buses during hot insertion This chapter also discusses the power on reset POR circuitry in Stratix II devices The POR circuitry keeps the devices in the reset state until the Vcc is within operating range Stratix II devices offer hot socketing capability with all three features listed above without any external components or special design requirements The hot socketing feature in Stratix IT devices allows E The devic2. triggered After the Stratix II device enters user mode the POR circuit continues to monitor the Vccmr voltage level so that a brown out condition during user mode can be detected If there is a Vccmr voltage sag below the Stratix IT operational level during user mode the POR circuit resets the device When power is applied to a Stratix II device a power on reset event occurs if Vcc reaches the recommended operating range within a certain period of time specified as a maximum Vcc rise time The maximum Vcc rise time for Stratix II device is 100 ms Stratix II devices provide a dedicated input pin PORSEL to select POR delay times of 12 or 100 ms during power up When the PORSEL pin is connected to ground the POR time is 100 ms When the PORSEL pin is connected to Vcc the POR time is 12 ms 4 5 Stratix II Device Handbook Volume 1 Document Revision History Document Table 4 1 shows the revision history for this chapter Revision History Table 4 1 Document Revision History Date and Document Version May 2007 v3 2 Changes Made Moved the Document Revision History section to the end of the chapter Summary of Changes April 2006 v3 1 May 2005 v3 0 e Updated Signal Pins Do Not Drive the VCCIO VCCINT or VCCPD Power Supplies section e Updated Signal Pins Do Not Drive the VCCIO VCCINT or VCCPD Power Supplies section e Removed information on ESD protection e Updated hot socke
3. and nSTATUS pins fail to respond as the output buffer can not flip from the state set by the hot socketing circuit at this low Vcc voltage Therefore the hot socketing circuit has been removed on these configuration pins to make sure that they are able to operate during configuration It is expected behavior for these pins to drive out during power up and power down sequences Each I O pin has the following circuitry shown in Figure 4 1 4 3 Stratix II Device Handbook Volume 1 Hot Socketing Feature Implementation in Stratix II Devices Figure 4 1 Hot Socketing Circuit Block Diagram for Stratix II Devices Power On REA Reset Output i Monitor Weak R l Pull Up gt Output Enable Resistor Voltage Hot Socket Tolerance Control Output Pre Driver Input Buffer to Logic Array The POR circuit monitors Vccmr voltage level and keeps I O pins tri stated until the device is in user mode The weak pull up resistor R from the I O pin to Veco is present to keep the I O pins from floating The 3 3 V tolerance control circuit permits the I O pins to be driven by 3 3 V before Vecio and or Vecinr and or Vecpp are powered and it prevents the I O pins from driving out when the device is not in user mode The hot socket circuit prevents I O pins from internally powering Vccio Veciny and Vecpp when driven by external signals before the device is po
4. e can be driven before power up without any damage to the device itself E I O pins remain tri stated during power up The device does not drive out before or during power up thereby affecting other buses in operation E Signal pins do not drive the Vecio Vecpp oF Vecinr power supplies External input signals to I O pins of the device do not internally power the Vecio or Vecinr power supplies of the device via internal paths within the device Stratix II Hot Socketing Specifications Devices Can Be Driven Before Power Up You can drive signals into the I O pins dedicated input pins and dedicated clock pins of Stratix II devices before or during power up or power down without damaging the device Stratix II devices support any power up or power down sequence Vecio Veciny and Vecpp in order to simplify system level design 1 0 Pins Remain Tri Stated During Power Up A device that does not support hot socketing may interrupt system operation or cause contention by driving out before or during power up In a hot socketing situation Stratix II device s output buffers are turned off during system power up or power down Stratix II device also does not drive out until the device is configured and has attained proper operating conditions Signal Pins Do Not Drive the Vecio Vecint OF Vecpp Power Supplies Devices that do not support hot socketing can short power supplies together when powered up through the device signal pins This irr
5. egular power up can damage both the driving and driven devices and can disrupt card power up Stratix II devices do not have a current path from I O pins dedicated input pins or dedicated clock pins to the Vecio Vecinr Or Vecpp pins before or during power up A Stratix II device may be inserted into or removed from a powered up system board without damaging or interfering with system board operation When hot socketing Stratix II devices may have a minimal effect on the signal integrity of the backplane Ls You can power up or power down the Veco Vecinr and Vecpp pins in any sequence The power supply ramp rates can range from 100 Ls to 100 ms All Vcc supplies must power down within 100 ms of each other to prevent I O pins from driving out During hot socketing the I O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF Stratix II devices meet the following hot socketing specification E The hot socketing DC specification is hopm lt 300 uA E The hot socketing AC specification is hop lt 8 mA for 10 ns or less 4 2 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Hot Socketing amp Power On Reset Hot Socketing Feature Implementation in Stratix Il Devices Altera Corporation May 2007 Torin is the current at any user I O pin on the device This specification takes into account the pin capacitance but not board trace and external loading capacitance Additio
6. nal capacitance for trace connector and loading needs must be considered separately For the AC specification the peak current duration is 10 ns or less because of power up transients For more information refer to the Hot Socketing amp Power Sequencing Feature amp Testing for Altera Devices white paper A possible concern regarding hot socketing is the potential for latch up Latch up can occur when electrical subsystems are hot socketed into an active system During hot socketing the signal pins may be connected and driven by the active system before the power supply can provide current to the device s Vcc and ground planes This condition can lead to latch up and cause a low impedance path from Vcc to ground within the device As a result the device extends a large amount of current possibly causing electrical damage Nevertheless Stratix II devices are immune to latch up when hot socketing The hot socketing feature turns off the output buffer during the power up event either Vecinn Vecio or Vecpp supplies or power down The hot socket circuit will generate an internal HOTSCKT signal when either Veanr Vecio Or Vecpp is below threshold voltage The HOTSCKT signal will cut off the output buffer to make sure that no DC current except for weak pull up leaking leaks through the pin When Vcc ramps up very slowly Vcc is still relatively low even after the POR signal is released and the configuration is finished The CONF_DONE nCEO
7. ting AC specification Reset Circuitry sections January 2005 Updated input rise and fall time v2 1 January 2005 Updated the Hot Socketing Feature Implementation in _ v2 0 Stratix II Devices ESD Protection and Power On July 2004 v1 1 e Updated all tables e Added tables February 2004 v1 0 Added document to the Stratix II Device Handbook 4 6 Stratix II Device Handbook Volume 1 Altera Corporation May 2007
8. wered Figure 4 2 shows a transistor level cross section of the Stratix II device I O buffers This design ensures that the output buffers do not drive when Vccio is powered before Vecinr or if the I O pad voltage is higher than Vccjo This also applies for sudden voltage spikes during hot insertion There is no current path from signal I O pins to Vecint or Vecio or Vccpp during hot insertion The Vpap leakage current charges the 3 3 V tolerant circuit capacitance 4 4 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Hot Socketing amp Power On Reset Figure 4 2 Transistor Level Diagram of FPGA Device 1 0 Buffers Logic Array VpaD Signal 1 2 p substrate Notes to Figure 4 2 1 This is the logic array signal or the larger of either the Vecio or Vpap signal 2 This is the larger of either the Vecio or Vpap signal Power On Reset Circuitry Altera Corporation May 2007 Stratix II devices have a POR circuit to keep the whole device system in reset state until the power supply voltage levels have stabilized during power up The POR circuit monitors the Vecinp Vecio and Vecpp voltage levels and tri states all the user I O pins while Vcc is ramping up until normal user levels are reached The POR circuitry also ensures that all eight I O bank Vcco voltages Vecpp voltage as well as the logic array Vecint Voltage reach an acceptable level before configuration is
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