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ALTERA Stratix II Architecture Stratix II Device Family Data Sheet

1. ee a oT ao o 4 oc fa ia QO r nu 2 Q r N Q oOo 0 0 oO 0 0 9 D 9 goat 3 gt x ira NI 0 N x x 5 lt P lt eh a i amp z X Xx 5 aes o S x lt b G s x St rs aa a o p o gt me amp oe o e gt 2 4 amp amp O g e d o t rs 0 g o gt O o g oe o o o o gt e o gt 1 2 5 x x O q e e H a ir y x x O t G O ot re 5 SS C s i T a e Na s lt a o gt iv ra QO r nun 2 ar Nu Q oO 0 0 oOo 0 0 ay a5 4 fg Eg FE FE a fe O 4 a a a ir rm Note to Figure 2 42 1 The corner fast PLLs can also be driven through the global or regional clock networks The global or regional clock input can be driven by an output from another PLL a pin driven dedicated global or regional clock or through a clock control block provided the clock control block is fed by an output from another PLL or a pin driven dedicated global or regional clock An internally generated global signal cannot drive the PLL 2 62 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 43 shows the global and regional clocking from enhanced PLL outputs and top and bottom CLK pins The connections to the global and regional clocks from the top clock pins and enhanced PLL outputs is shown in Table 2 11 The
2. See the TriMatrix Embedded Memory Blocks in Stratix II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information on TriMatrix memory 2 39 Stratix II Device Handbook Volume 1 Digital Signal Processing Block Digital Signal Processing Block 2 40 The most commonly used DSP functions are FIR filters complex FIR filters IIR filters fast Fourier transform FFT functions direct cosine transform DCT functions and correlators All of these use the multiplier as the fundamental building block Additionally some applications need specialized operations such as multiply add and multiply accumulate operations Stratix II devices provide DSP blocks to meet the arithmetic requirements of these functions Each Stratix II device has from two to four columns of DSP blocks to efficiently implement DSP functions faster than ALM based implementations Stratix IT devices have up to 24 DSP blocks per column see Table 2 5 Each DSP block can be configured to support up to m Eight 9 x 9 bit multipliers E Four 18 x 18 bit multipliers E One 36 x 36 bit multiplier As indicated the Stratix II DSP block can support one 36 x 36 bit multiplier in a single DSP block This is true for any combination of signed unsigned or mixed sign multiplications c This list only shows functions that can fit into a single DSP block Multiple DSP blocks
3. Local Interconnect Local Interconnect AJ E at a a a y t y i Local Interconnect Local Interconnect Local Interconnect Local Interconnect clocken_a renwe_a aclr_b clock_b y N clock_a aclr_a renwe_b clocken_b Local Interconnect Local Interconnect 1 LL Liira The R4 R24 C4 and direct link interconnects from adjacent LABs on either the right or left side drive the M RAM block local interconnect Up to 16 direct link input connections to the M RAM block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB M RAM block outputs can also connect to left and right LABs through direct link interconnect Figure 2 24 shows an example floorplan for the EP2S130 device and the location of the M RAM interfaces Figures 2 25 and 2 26 show the interface between the M RAM block and the logic array Altera Corporation 2 35 May 2007 Stratix Il Device Handbook Volume 1 TriMatrix Memory Figure 2 24 EP2S130 Device with M RAM Interface Locations Note 1 M RAM blocks interface to LABs on right and left sides for easy access to horizontal I 0 pins A y i i M RAM Block i i i i M RAM Block V NZ M4K M512 DSP LABs Blo
4. The clock input pins supporting LVDS on banks 3 4 7 and 8 use Vecinr for LVDS input operations and have no dependency on the Vecio level of the bank 4 1 2 V HSTL is only supported in I O banks 4 7 and 8 Altera Corporation May 2007 For more information on I O standards supported by Stratix II I O banks refer to the Selectable I O Standards in Stratix II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook Stratix II devices contain eight I O banks and four enhanced PLL external clock output banks as shown in Figure 2 57 The four I O banks on the right and left of the device contain circuitry to support high speed differential I O for LVDS and HyperTransport inputs and outputs These banks support all Stratix II I O standards except PCI or PCI X I O pins and SSTL 18 Class II and HSTL outputs The top and bottom I O banks support all single ended I O standards Additionally enhanced PLL external clock output banks allow clock output capabilities such as differential support for SSTL and HSTL 2 87 Stratix II Device Handbook Volume 1 I O Structure Figure 2 57 Stratix II 1 0 Banks Notes 1 2 3 4 DassT VREFOBS VREF1B3 VREF2B3 VREF3B3 VREF4B3 PEE pte z e X a PLL8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREFOBS VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREFOB7 PLL12 PLL6 DQS8B DQS7B DQS6B DQS5B Notes t
5. a For more information on series on chip termination supported by Stratix II devices refer to the Selectable I O Standards in Stratix II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook 2 92 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Altera Corporation May 2007 For more information on tolerance specifications for on chip termination with calibration refer to the DC amp Switching Characteristics chapter in volume 1 of the Stratix II Device Handbook On Chip Parallel Termination with Calibration Stratix II devices support on chip parallel termination with calibration for column I O pins only There is one calibration circuit for the top I O banks and one circuit for the bottom I O banks Each on chip parallel termination calibration circuit compares the total impedance of each I O buffer to the external 50 Q resistors connected to the RUP and RDN pins and dynamically enables or disables the transistors until they match Calibration occurs at the end of device configuration Once the calibration circuit finds the correct impedance it powers down and stops changing the characteristics of the drivers L gt On chip parallel termination with calibration is only supported for input pins For more information on on chip termination supported by Stratix II devices refer to the Selectable I O Standards in Stratix
6. address Direct link interconnect 2 M512 RAM Block Local LAB Row Clocks Interconnect Region 2 32 M4K RAM Blocks The M4K RAM block includes support for true dual port RAM The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code implementing lookup schemes and implementing larger memory applications Each block contains 4 608 RAM bits including parity bits M4K RAM blocks can be configured in the following modes True dual port RAM Simple dual port RAM Single port RAM FIFO ROM Shift register When configured as RAM or ROM you can use an initialization file to pre load the memory contents Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture The M4K RAM blocks allow for different clocks on their inputs and outputs Either of the two clocks feeding the block can clock M4K RAM block registers renwe address byte enable datain and output registers Only the output register can be bypassed The six labc1k signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block ALMs can also control the clock_a clock_b renwe_a renwe_b clr_a clr_b clocken_a and clocken_b signals as shown in Figure 2 21 The R4 C4 and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect The M4K RAM blocks can communicate with LABs on either the
7. E Direct link interconnects between LABs and adjacent blocks E R4 interconnects traversing four blocks to the right or left E R24 row interconnects for high speed access across the length of the device Altera Corporation Stratix Il Device Handbook Volume 1 May 2007 Stratix Il Architecture The direct link interconnect allows an LAB DSP block or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself This provides fast communication between adjacent LABs and or blocks without using row interconnect resources The R4 interconnects span four LABs three LABs and one M512 RAM block two LABs and one M4K RAM block or two LABs and one DSP block to the right or left of a source LAB These resources are used for fast row connections in a four LAB region Every LAB has its own set of R4 interconnects to drive either left or right Figure 2 16 shows R4 interconnect connections from an LAB R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row IOEs For LAB interfacing a primary LAB or LAB neighbor can drive a given R4 interconnect For R4 interconnects that drive to the right the primary LAB and right neighbor can drive on to the interconnect For R4 interconnects that drive to the left the primary LAB and its left neighbor can drive on to the interconnect R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive R
8. gt RCLK13 e gt RCLK14 h gt RCLK15 o oo PLL6_OUT 2 0 p t t TT PLL6_OUT 2 0 n PLL12_FB CLK4 LI cake J PLL6_FB CLK5 CLK7 EP2S15 and EP2S30 devices only have two enhanced PLLs 5 and 6 but the connectivity from these two PLLs to the global and regional clock networks remains the same as shown If the design uses the feedback input you lose one or two if FBIN is differential external clock output pin The enhanced PLLs can also be driven through the global or regional clock netowrks The global or regional clock input can be driven by an output from another PLL a pin driven dedicated global or regional clock or through a clock control block provided the clock control block is fed by an output from another PLL or a pin driven dedicated global or regional clock An internally generated global signal cannot drive the PLL 2 64 Stratix Il Device Handbook Volume 1 Altera Corporation May 2007 Stratix Il Architecture Table 2 11 Global amp Regional Clock Connections from Top Clock Pins amp Enhanced PLL Outputs Part 1 of 2 Top Side Global amp Regional Clock Network Connectivity DLLCLK CLK12 CLK13 CLK14 CLK15 RCLK24 RCLK25 RCLK26 RCLK27 RCLK28 RCLK29 RCLK30 RCLK31 Clock pins CLK12p T S S YS S S CLK13p CLK14p SUNAS X CLK15p S E SN CLK12n Ya VA Y CLK13n y Y Y CLK14n re
9. 1 Device Package a ea augue x1 ai Han Peh cai EP2S15_ 484 pin FineLine BGA 8 4 0 0 672 pin FineLine BGA 18 8 4 0 EP2S30 484 pin FineLine BGA 8 4 0 0 672 pin FineLine BGA 18 8 4 0 EP2S60 484 pin FineLine BGA 8 4 0 0 672 pin FineLine BGA 18 8 4 0 1 020 pin FineLine BGA 36 18 8 4 Altera Corporation May 2007 2 81 Stratix II Device Handbook Volume 1 I O Structure Table 2 14 DOS amp DQ Bus Mode Support Part 2 of 2 Note 1 ee e EP2S90 484 pin Hybrid FineLine BGA 8 4 0 0 780 pin FineLine BGA 18 8 4 0 1 020 pin FineLine BGA 36 18 8 4 1 508 pin FineLine BGA 36 18 8 4 EP2S130 780 pin FineLine BGA 18 8 4 0 1 020 pin FineLine BGA 36 18 8 4 1 508 pin FineLine BGA 36 18 8 4 EP2S180 1 020 pin FineLine BGA 36 18 8 4 1 508 pin FineLine BGA 36 18 8 4 Notes to Table 2 14 1 Check the pin table for each DQS DQ group in the different modes 2 82 A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals The DQS signals drive a local DQS bus in the top and bottom I O banks This DQS bus is an additional resource to the I O clocks and is used to clock DQ input registers with the DQS signal The Stratix II device has two phase shifting reference circuits one on the top and one on the bottom of the device The circuit on the top controls the compensate
10. Ic4 LA A A Ww Ic5 From Adjacent PLL 4 Global Clocks 8 Regional Clocks I O Buffers 3 to I O or general Clock Switchover Ss d Circuitry Phase Frequency prea Detector Spectrum INCLK 3 0 oe Dx n L Charge Loop LS PFD Pump Filter vco Global or m Regional Clock 4 A m 2 Lock Detect ock Detec FEIN amp Filter 7 VCO Phase Selection Shaded Portions of the h PLL are Reconfigurable Affecting All Outputs Notes to Figure 2 44 routing 1 Each clock source can come from any of the four clock pins that are physically located on the same side of the device as the PLL 2 Ifthe feedback input is used you lose one or two if FBIN is differential external clock output pin 3 Each enhanced PLL has three differential external clock outputs or six single ended external clock outputs 4 The global or regional clock input can be driven by an output from another PLL a pin driven dedicated global or regional clock or through a clock control block provided the clock control block is fed by an output from another PLL or a pin driven dedicated global or regional clock An internally generated global signal cannot drive the PLL 2 68 Stratix Il Device Handbook Volume 1 Altera Corporation May 2007 Stratix Il Architecture Fast PLLs Stratix II devices contain up to eight fast PLLs with high speed serial interfacing ability Figure 2 45 shows
11. Stratix II nCEO Vecio Voltage Level in 1 0 Bank 7 nCE Input Buffer Power in 1 0 Bank 3 Vecio Vecio Vecio Vecio Vecio 3 3 V 2 5 V 1 8 V 1 5V 1 2 V VCCSEL high 1 2 V 3 4 V 5 Y Y Vecio Bank 3 1 5 V VCCSEL high 1 2 V 3 4 Y Y Level shifter Vecio Bank 3 1 8 V required VCCSEL low Y x 4 v 6 Level shifter Level shifter nCE Powered by Vecpp 3 3V required required For JTAG chains the TDO pin of the first device drives the TDI pin of the second device in the chain The Vecsgr input on JTAG input I O cells TCK TMS TDI and TRST is internally hardwired to GND selecting the 3 3 V 2 5 V input buffer powered by Vccpp The ideal case is to have the Vecio of the TDO bank from the first device to match the Vccsgr settings for TDI on the second device but that may not be possible depending on the application Table 2 20 contains board design recommendations to ensure proper JTAG chain operation Table 2 20 Supported TDO TDI Voltage Combinations Part 1 of 2 Stratix II TDO Vecio Voltage Level in 1 0 Bank 4 Device TDI Input Buffer Power Vecio 3 3V Vecio 2 5V Vecio 1 8V Vecio 1 5V Vecio 1 2V Stratix II Always v 1 v 2 v 3 Level shifter Level shifter Vocpp 3 3V required required Altera Corporation 2 95 May 2007 Stratix II Device Handbook Volume 1 High Speed Differential I O with DPA Support Table 2 20 Support
12. clk_out io_clk gt io_dataouta ad io_dataoutb b gt Each IOE contains its own control signal selection for the following control signals oe ce_in ce_out aclr apreset sclr spreset clk_in and clk_out Figure 2 50 illustrates the control signal selection 2 74 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 50 Control Signal Selection per IOE Dedicated I O Clock 7 0 Local gt _ io_oe Interconnect A Local _ io_selr Interconnect gt ise L cal M io acr Interconnect a Local M io_ce_out Interconnect 4 re Local MN io_ce_in LJ a x a tJ W J Interconnect lt v v y Local a ies io_clk clk_out ce_out sclr spreset Interconnect 43 y y v y clk_in ce_in aclr apreset oe Notes to Figure 2 50 1 Control signals ce_in ce_out aclr apreset sclr spreset and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk 7 0 signals The ioe_c1k signals can drive the I O local interconnect which then drives the control selection multiplexers In normal bidirectional operation the input register can be used for input data requiring fast setup times The input register can have its own clock input and clock enable separate from the OE and output registers The output register can be used for data requiring fast clock to ou
13. 23 23 23 23 23 3 46 46 46 46 1 508 pin Transmitter 156 2 37 41 41 37 37 41 41 37 FineLine BGA 3 78 78 78 78 7 Receiver 156 2 37 41 41 37 37 41 41 37 3 78 78 78 78 Table 2 26 EP2S180 Differential Channels Note 1 ak Transmitter Total Center Fast PLLs Corner Fast PLLs 4 acae Receiver Channels pii 1 pLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 1 020 pin Transmitter 88 2 22 22 22 22 22 22 22 22 FineLine BGA 3 44 44 44 44 7 J Receiver 92 2 23 23 23 23 23 23 23 23 3 46 46 46 46 1 508 pin Transmitter 156 2 37 41 41 37 37 41 41 37 FineLine BGA 3 78 78 78 78 s z Receiver 156 2 37 41 41 37 37 41 41 37 3 78 78 78 78 Notes to Tables 2 21 to 2 26 1 The total number of receiver channels includes the four non dedicated clock channels that can be optionally used as data channels 2 3 This is the maximum number of channels the PLLs can directly drive This is the maximum number of channels if the device uses cross bank channels from the adjacent center PLL 4 The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL Therefore the total number of channels is not the addition of the number of channels accessible by PLLs 1 2 3 and 4 with the number of channels accessible by PLLs 7 8 9 and 10 Altera Corporation May 2007 2 99 Stratix II Device Handbook Volume 1 High Speed Differentia
14. 4 es ZF CLK15n Y v Y Drivers from internal logic GCLKDRVO se GCLKDRV1 wv GCLKDRV2 7 GCLKDRV3 F RCLKDRVO A Y RCLKDRV1 Y va RCLKDRV2 7 J RCLKDRV3 Y v RCLKDRV4 es Z RCLKDRV5 va Y RCLKDRV6 Y Y RCLKDRV7 vw ff Enhanced PLL 5 outputs co AS SS ci c2 c3 KILU S SIS SIS Altera Corporation 2 65 May 2007 Stratix II Device Handbook Volume 1 PLLs amp Clock Networks Table 2 11 Global amp Regional Clock Connections from Top Clock Pins amp Enhanced PLL Outputs Part2 of 2 Top Side Global amp Regional Ssleclele S F FS S S F sls Clock Network Connectivity 3 3 alala l l l al al l l c4 Y v Y Y v c5 Y v Y Y Y Enhanced PLL 11 outputs cO Va Y4 cl VRA Y Y c2 Z lay Y Y c3 VERVA Y Y c4 vA Y v Y c5 A Y Y Y Table 2 12 Global amp Regional Clock Connections from Bottom Clock Pins amp Enhanced PLL Outputs Part1 of 2 i o N m lt uw regional ciocketwonr S 2 S S S S SlE E E EIE Connectivity air liPfl Pl Plelel ele l ekliz amp l e e2 Clock pins CLK4p VIL Y vA CLK5p PF e Y Y CLK6p Y VRA Y V CLK7p Y VARA Y Y CLK4n wv Y CLK5n ig Ti va CLK6n zZ Y v CLK7n z y 4 Drivers from internal log
15. 672 pin FineLine BGA Transmitter 38 2 10 9 9 10 3 19 19 19 19 Receiver 42 2 11 10 10 11 3 21 21 21 21 Table 2 22 EP2S30 Device Differential Channels Note 1 akato Transmitter Total Center Fast PLLs Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4 484 pin FineLine BGA Transmitter 38 2 10 9 9 10 3 19 19 19 19 Receiver 42 2 11 10 10 11 3 21 21 21 21 672 pin FineLine BGA Transmitter 58 2 16 13 13 16 3 29 29 29 29 Receiver 62 2 17 14 14 17 3 31 31 31 31 Altera Corporation May 2007 2 97 Stratix II Device Handbook Volume 1 High Speed Differential I O with DPA Support Table 2 23 EP2S60 Differential Channels Note 1 AA Transmitter Total Center Fast PLLs Corner Fast PLLs 4 acae Receiver Channels pit pLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 484 pin Transmitter 38 2 10 9 9 10 10 9 9 10 FineLine BGA 3 19 19 19 19 E 7 R Receiver 42 2 11 10 10 11 11 10 10 11 3 21 21 21 21 z 672 pin Transmitter 58 2 16 13 13 16 16 13 13 16 FineLine BGA 3 29 29 29 29 5 Receiver 62 2 17 14 14 17 17 14 14 17 3 31 31 31 31 1 020 pin Transmitter 84 2 21 21 21 21 21 21 21 21 FineLine BGA 3 42 42 42 42 Receiver 84 2 21 21 21 21 21 21 21 21 3 42 42 42 42 Table 2 24
16. DSP blocks A shared arithmetic chain can continue as far as a full column Similar to the carry chains the shared arithmetic chains are also top or bottom half bypassable This capability allows the shared arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other half available for narrower fan in functionality Every other LAB column is top half bypassable while the other LAB columns are bottom half bypassable See the MultiTrack Interconnect on page 2 22 section for more information on shared arithmetic chain interconnect Register Chain In addition to the general routing outputs the ALMs in an LAB have register chain outputs The register chain routing allows registers in the same LAB to be cascaded together The register chain interconnect allows an LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift register implementation These resources speed up connections between ALMs while saving local interconnect resources see Figure 2 15 The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 15 Register Chain within an LAB Note 1 e e 3 From Previous ALM Within The LAB reg_chain_in To general or local
17. EP2S90 Differential Channels Note 1 ii Transmitter Total Center Fast PLLs Corner Fast PLLs 4 a Receiver Channels PLL 4 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 484 pin Hybrid Transmitter 38 2 10 9 9 10 z FineLine BGA 3 19 19 19 19 F F Receiver 42 2 11 10 10 11 3 21 21 21 21 g 780 pin Transmitter 64 2 16 16 16 16 FineLine BGA 3 32 32 32 32 z z Receiver 68 2 17 17 17 17 3 34 34 34 34 g 1 020 pin Transmitter 90 2 23 22 22 23 23 22 22 23 FineLine BGA 3 45 45 45 45 R 7 T Receiver 94 2 23 24 24 23 23 24 24 23 3 46 46 46 46 1 508 pin Transmitter 118 2 30 29 29 30 30 29 29 30 FineLine BGA 3 59 59 59 59 Receiver 118 2 30 29 29 30 30 29 29 30 3 59 59 59 59 5 2 98 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Table 2 25 EP2S130 Differential Channels Note 1 M Transmitter Total Center Fast PLLs Corner Fast PLLs 4 acae Receiver Channels pit pLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 780 pin Transmitter 64 2 16 16 16 16 FineLine BGA 3 32 32 32 32 E z Receiver 68 2 17 17 17 17 3 34 34 34 34 1 020 pin Transmitter 88 2 22 22 22 22 22 22 22 22 FineLine BGA 3 44 44 44 44 Receiver 92 2 23 23 23
18. Each global clock regional clock and PLL external clock output has its own clock control block The control block has two functions E Clock source selection dynamic selection for global clocks E Clock power down dynamic clock enable disable Altera Corporation May 2007 2 53 Stratix II Device Handbook Volume 1 PLLs amp Clock Networks L When using the global or regional clock control blocks in Stratix II devices to select between multiple clocks or to enable and disable clock networks be aware of possible narrow pulses or glitches when switching from one clock signal to another A glitch or runt pulse has a width that is less than the width of the highest frequency input clock signal To prevent logic errors within the FPGA Altera recommends that you build circuits that filter out glitches and runt pulses Figures 2 37 through 2 39 show the clock control block for the global clock regional clock and PLL external clock output respectively Figure 2 37 Global Clock Control Blocks CLKp Pins PLL Counter Outputs era Internal CLKSELECT 1 0 p Logic 1 uBR Static Clock Select 2 This multiplexer supports User Controllable Dynamic Switching Enable Disable o Internal Logic vy GCLK Notes to Figure 2 37 1 These clock select signals can be dynamically controlled through internal logic when the device is operating in user mode 2 These clock select signals
19. II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook For more information on tolerance specifications for on chip termination with calibration refer to the DC amp Switching Characteristics chapter in volume 1 of the Stratix II Device Handbook MultiVolt 1 0 Interface The Stratix II architecture supports the MultiVolt I O interface feature that allows Stratix IT devices in all packages to interface with systems of different supply voltages The Stratix II VCCINT pins must always be connected to a 1 2 V power supply With a 1 2 V Veqnz level input pins are 1 5 1 8 2 5 and 3 3 V tolerant The VCCIO pins can be connected to either a 1 5 1 8 2 5 or 3 3 V power supply depending on the output requirements The output levels are compatible with systems of the same voltage as the power supply for example when VCCIO pins are connected to a 1 5 V power supply the output levels are compatible with 1 5 V systems The Stratix II VCCPD power pins must be connected to a 3 3 V power supply These power pins are used to supply the pre driver power to the output buffers which increases the performance of the output pins The VCCPD pins also power configuration input pins and JTAG input pins 2 93 Stratix II Device Handbook Volume 1 I O Structure Table 2 18 summarizes Stratix II MultiVolt I O support Table 2 18 Stratix II MultiVolt
20. N D TE PYA 2 Stratix Il Architecture Functional Description Altera Corporation May 2007 Stratix II devices contain a two dimensional row and column based architecture to implement custom logic A series of column and row interconnects of varying length and speed provides signal interconnects between logic array blocks LABs memory block structures M512 RAM M4K RAM and M RAM blocks and digital signal processing DSP blocks Each LAB consists of eight adaptive logic modules ALMs An ALM is the Stratix II device family s basic building block of logic providing efficient implementation of user logic functions LABs are grouped into rows and columns across the device M512 RAM blocks are simple dual port memory blocks with 512 bits plus parity 576 bits These blocks provide dedicated simple dual port or single port memory up to 18 bits wide at up to 500 MHz M512 blocks are grouped into columns across the device in between certain LABs M4K RAM blocks are true dual port memory blocks with 4K bits plus parity 4 608 bits These blocks provide dedicated true dual port simple dual port or single port memory up to 36 bits wide at up to 550 MHz These blocks are grouped into columns across the device in between certain LABs M RAM blocks are true dual port memory blocks with 512K bits plus parity 589 824 bits These blocks provide dedicated true dual port simple dual port or single port memory up to 144 bits wide
21. a diagram of the fast PLL Figure 2 45 Stratix II Device Fast PLL Notes 1 2 3 Post Scale VCO Phase Selection Counters cick Selectable at each PLL Oe Output Port x Switchover Paa N diffioclkO 2 Global or Circuitry 4 quency NS regional clock 7 Detector k loaden 3 He c0 p 5 3 Charge Loop 7 load_en1 3 Clock X 4 L i ot PRD Pump Filter veo k vS Input X A diffioclk1 2 Global clocks lat Global or Regional clocks regional clock 1 to DPA block Shaded Portions of the PLL are Reconfigurable Notes to Figure 2 45 1 The global or regional clock input can be driven by an output from another PLL a pin driven dedicated global or regional clock or through a clock control block provided the clock control block is fed by an output from another PLL or a pin driven dedicated global or regional clock An internally generated global signal cannot drive the PLL 2 In high speed differential I O support mode this high speed PLL clock feeds the SERDES circuitry Stratix II devices only support one rate of data transfer per fast PLL in high speed differential I O support mode 3 This signal is a differential I O SERDES control signal 4 Stratix II fast PLLs only support manual clock switchover 5 If the de
22. automatically For enhanced fitting a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks A carry chain can continue as far as a full column To avoid routing congestion in one small area of the device when a high fan in arithmetic function is implemented the LAB can support carry chains that only utilize either the top half or the bottom half of the LAB before connecting to the next LAB This leaves the other half of the ALMs in the LAB available for implementing narrower fan in functions in normal mode Carry chains that use the top four ALMs in the first LAB carry into the top half of the ALMs in the next LAB within the column Carry chains that use the bottom four ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column Every other column of LABs is top half bypassable while the other LAB columns are bottom half bypassable See the MultiTrack Interconnect on page 2 22 section for more information on carry chain interconnect Shared Arithmetic Mode In shared arithmetic mode the ALM can implement a three input add In this mode the ALM is configured with four 4 input LUTs Each LUT either computes the sum of three inputs or the carry of three inputs The output of the carry computation is fed to the next adder either to adder1 in the same ALM or to adder0 of the next ALM in the LAB via a dedicated connection called the shared arithmetic ch
23. can only be set through a configuration file sof or pof and cannot be dynamically controlled during user mode operation 2 54 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Altera Corporation May 2007 Figure 2 38 Regional Clock Control Blocks CLKp CLKn Pin Pin 2 PLL Counter 2 l Internal Outputs 3 Logic Static Clock Select 1 Enable Disable Internal Logic y RCLK Notes to Figure 2 38 1 These clock select signals can only be set through a configuration file sof or pof and cannot be dynamically controlled during user mode operation 2 Only the CLKn pins on the top and bottom of the device feed to regional clock select blocks The clock outputs from corner PLLs cannot be dynamically selected through the global clock control block 3 The clock outputs from corner PLLs cannot be dynamically selected through the global clock control block 2 55 Stratix II Device Handbook Volume 1 PLLs amp Clock Networks Figure 2 39 External PLL Output Clock Control Blocks PLL Counter Outputs c 5 0 6 Static Clock Select 1 Enable Disable Internal Logic IOE 2 Internal Logic Static Clock Select 1 PLL_OUT Pin Notes to Figure 2 39 1 These clock select signals can only be set through a configuration file sof or pof and cannot be dynamically controlled during use
24. clock regions Figure 2 35 EP2S15 amp EP2S30 Device I O Clock Groups 10_CLKA 7 0 10_CLKB 7 0 8 8 F 1 0 Clock Regions 8 24 Clocks in i 24 Clocks in the Quadrant the Quadrant 10_CLKH Z7 0 0_CLKC 7 0 8 8 i 10_CLKG 7 0 t 0_CLKD 7 0 24 Clocks in i 24 Clocks in the Quadrant the Quadrant 8 8 8 10_CLKF 7 0 10_CLKE 7 0 9 52 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 36 EP2S60 EP2S90 EP2S130 amp EP2S180 Device 1 0 Clock Groups 10_CLKA 7 0 10_CLKB 7 0 10_CLKC 7 0 10_CLKD 7 0 7 1 0 Clock Regions 10_CLKP 7 0 24 Clocks in the Quadrant 10_CLKO 7 0 vs 8 0_CLKE 7 0 24 Clocks in the Quadrant 0_CLKF 7 0 10_CLKN 7 0 t 0_CLKG 7 0 24 Clocks in the 24 Clocks in the Quadrant Quadrant 8 8 10_CLKM 7 0 0_CLKH 7 0 8 8 8 10_CLKL 7 0 10_CLKK 7 0 10_CLKJ 7 0 10_CLKI 7 0 You can use the Quartus II software to control whether a clock input pin drives either a global regional or dual regional clock network The Quartus II software automatically selects the clocking resources if not specified Clock Control Block
25. connections to the clocks from the bottom clock pins is shown in Table 2 12 Altera Corporation 2 63 May 2007 Stratix Il Device Handbook Volume 1 PLLs amp Clock Networks Figure 2 43 Global amp Regional Clock Connections from Top amp Bottom Clock Pins amp Enhanced PLL Outputs Notes 1 2 and 3 PLL11_OUT 2 0 p PLL11_OUT 2 0 n RCLK27 Regional RCLK26 Clocks RCLK25 RCLK24 Global Clocks Clocks RCLK10 RCLK8 amp Regional RCLK9 RCLK11 PLL12_OUT 2 0 p PLL12_OUT 2 0 n Notes to Figure 2 43 1 2 3 CLK13 CLK15 CLK12 PLL11_FB cLK14 PLL5_FB PLL 11 c0 c1 c2 c3 c4 c5 PLL5 cO c1 c2 c3 c4 c5 PLL5_OUT 2 0 p c0 c1 c2 c3 c4 c5 PLL 12 c0 c1 c2 c3 c4 c5 PLL 6 r a es a i a oF 99 99 gt PLL5_OUTI2 0 n hd ad j hd gt RCLK31 o 9 BP RCLK30 gt RCLK29 gt RCLK28 4 qe kd kd lt lt b b 4 o oe G15 4 Oe o gt Gi4 lt G13 4 I i i et gt G12 4 p G4 4 Ty gt c5 lt 4 s G6 lt tt TT a qo J lt 4 s lt 4 lt 4 gt p RCLK12 e
26. datai datae _ _____ i i i dataf1 i datafO i datae0 i datac pingut i combout0 datafo d LUT i datae0 aaa dataa 1 _____ 6 Input datab i datab ae LUT combout0O datac _ datad datad datae1 ite comboutt oo yl aa dataf1 E datafo aaa E aa datae0 i dataa e 6 Input datafo 1___ datab LUT eemboun dataeo 1 i datac datace Snput combout0 datad LUT dataa e _ i datab H datad i ey combout1 datae1 combout1 datae1 dataft dataf1 Note to Figure 2 7 1 Combinations of functions with fewer inputs than those shown are also supported For example combinations of functions with the following number of inputs are supported 4 and 3 3 and 3 3 and 2 5 and 2 etc The normal mode provides complete backward compatibility with four input LUT architectures Two independent functions of four inputs or less can be implemented in one Stratix II ALM In addition a five input function and an independent three input function can be implemented without sharing inputs Altera Corporation 2 11 May 2007 Stratix Il Device Handbook Volume 1 Adaptive Logic Modules For the packing of two five input functions into one ALM the functions must have at least two common inputs The common inputs are dataa and datab The combination of a four input function with a five input func
27. information specification e Added new On Chip Parallel Termination with Calibration e Changed RCLK section names to match the e Updated Figure 2 44 Quartus II software in Table 2 13 December Updated Clock Control Block section 2005 v4 0 July 2005 v3 1 e Updated HyperTransport technology information in Table 2 18 e Updated HyperTransport technology information in Figure 2 57 Added information on the asynchronous clear signal May 2005 v3 0 Updated Functional Description section Updated Table 2 3 Updated Clock Control Block section Updated Tables 2 17 through 2 19 Updated Tables 2 20 through 2 22 Updated Figure 2 57 March 2005 2 1 Updated Functional Description section Updated Table 2 3 2 104 Stratix II Device Handbook Volume 1 Altera Corporation May 2007 Stratix Il Architecture Table 2 27 Document Revision History Part 2 of 2 Date and Document Changes Made Summary of Changes Version January 2005 e Updated the MultiVolt I O Interface and TriMatrix Memory v2 0 sections e Updated Tables 2 3 2 17 and 2 19 October 2004 e Updated Tables 2 9 2 16 2 26 and 2 27 v1 2 July 2004 v1 1 e Updated note to Tables 2 9 and 2 16 e Updated Tables 2 16 2 17 2 18 2 19 and 2 20 e Updated Figures 2 41 2 42 and 2 57 e Removed 3 from list of SERDES factor J e Updated High S
28. left or right side through these row resources or with LAB columns on either the right or left with the column resources Up to 16 direct link input connections to the M4K RAM Block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB M4K RAM block outputs can also connect to left and right LABs through direct link interconnect Figure 2 22 shows the M4K RAM block to logic array interface Figure 2 21 M4K RAM Block Control Signals Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect 6 ed dt ee EP a 3 W z GF y y eee eae b renwe_b aclr_b y y y vy he E ERE clock_a clocken_a renwe_a aclr_a Altera Corporation May 2007 2 33 Stratix II Device Handbook Volume 1 TriMatrix Memory Figure 2 22 M4K RAM Block LAB Row Interface C4 Interconnect Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB R4 Interconnect 36 interconnect to adjacent LAB dataout M4K RAM Block Direct link interconnect datain from adjacent LAB byte control enable signals clocks address M4K RAM Block Local LAB Ro
29. operations Differential HSTL and differential SSTL standards are supported for both input and output operations Bank 7 Das4B Das3B Das2B DQS1B DQS0B PLL10 PUES 1 Figure 2 57 is a top view of the silicon die that corresponds to a reverse view for flip chip packages It is a graphical representation only 2 Depending on the size of the device different device members have different numbers of Vggr groups Refer to the pin list and the Quartus II software for exact locations 3 Banks 9 through 12 are enhanced PLL external clock output banks These PLL banks utilize the adjacent Var group when voltage referenced standards are implemented For example if an SSTL input is implemented in PLL bank 10 the voltage level at VREFB7 is the reference voltage level for the SSTL input 4 Horizontal I O banks feature SERDES and DPA circuitry for high speed differential I O standards See the High Speed Differential I O Interfaces in Stratix II amp Stratix II GX Devices chapter of the Stratix II Device Handbook Volume 2 or the Stratix II GX Device Handbook Volume 2 for more information on differential I O standards 2 88 Stratix Il Device Handbook Volume 1 Altera Corporation May 2007 Stratix Il Architecture Each I O bank has its own VCCIO pins A single device can support 1 5 1 8 2 5 and 3 3 V interfaces each bank can support a different Vccio level independently Each bank also has dedicated VREF pins to supp
30. pin to input register Output pin delay Delay from output register to output pin Output enable register tco delay Delay to output enable pin The IOE registers in Stratix II devices share the same source for clear or preset You can program preset or clear for each individual IOE You can also program the registers to power up high or low after configuration is complete If programmed to power up low an asynchronous clear can control the registers If programmed to power up high an asynchronous preset can control the registers This feature prevents the inadvertent activation of another device s active low input upon power up If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear Additionally a synchronous reset signal is available for the IOE registers Double Data Rate 1 0 Pins Stratix II devices have six registers in the IOE which support DDR interfacing by clocking data on both positive and negative clock edges The IOEs in Stratix II devices support DDR inputs DDR outputs and bidirectional DDR modes 2 77 Stratix II Device Handbook Volume 1 O Structure When using the IOE for DDR inputs the two input registers clock double rate input data on alternating edges An input latch is also used in the IOE for DDR input acquisition The latch holds the data that is present during the clock high times This allows both bits of data t
31. pins PLL outputs or internal logic Dynamic clock source selection v 1 Dynamic enable disable v Y Note to Table 2 8 1 Dynamic source clock selection is supported for selecting between CLKp pins and PLL outputs only Global Clock Network These clocks drive throughout the entire device feeding all device quadrants The global clock networks can be used as clock sources for all resources in the device IOEs ALMs DSP blocks and all memory blocks These resources can also be used for control signals such as clock enables and synchronous or asynchronous clears fed from the external pin The Altera Corporation May 2007 Stratix Il Architecture global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears clock enables or other control signals with large fanout Figure 2 31 shows the 16 dedicated CLK pins driving global clock networks Figure 2 31 Global Clocking CLK 15 12 Global Clock 15 0 CLK S 0 Global Clock 15 0 CLK 11 8 CLK 7 4 Regional Clock Network There are eight regional clock networks RCLK 7 0 in each quadrant of the Stratix II device that are driven by the dedicated CLK 15 0 input pins by PLL outputs or by internal logic The regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant The CLK clock pins s
32. routing adder0 a e gt To general or local routing gt regO Combinational Logic adder1 D qlee To general or local routing gt reg1 To general or local routing Vv To general or local routing adderO D qhe To general or local routing gt regO Combinational Logic adder1 D alte To general or local routing gt reg1 To general or i local routing reg_chain_out To Next ALM e within the LAB Note to Figure 2 15 1 The combinational or adder logic can be utilized to implement an unrelated un registered function See the MultiTrack Interconnect on page 2 22 section for more information on register chain interconnect Altera Corporation 2 21 May 2007 Stratix Il Device Handbook Volume 1 MultiTrack Interconnect Multitrack Interconnect 2 22 Clear amp Preset Logic Control LAB wide signals control the logic for the register s clear and load preset signals The ALM directly supports an asynchronous clear and preset function The register preset is achieved through the asynchronous load of a logic high The direct asynchronous preset does not require a NOT gate push back technique Stratix II devices support simultaneous asynchronous load preset and clear signals An asynchronous clear signal takes precedence if both signals are asserted simultaneously Each LAB supports up to two clears and one load preset signal In addition to the clear and load preset ports Stratix II devices prov
33. shift registers for FIR filter applications and DSP blocks support Q1 15 format rounding and saturation Figure 2 28 shows the top level diagram of the DSP block configured for 18 x 18 bit multiplier mode Altera Corporation Stratix Il Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 28 DSP Block Diagram for 18 x 18 Bit Configuration Optional Serial Shift Register Inputs from Previous DSP Block Adder Output Block Output Multiplier Block Selection sai Q1 15 A j Round Optional Stage Configurable Saturate ENA as Accumulator or Dynamic From the row CLRN Adder Subtractor interface block T 2 Adder Subtractor Si a Accumulator 1 Saturate PRN Q115 DG Round Saturate ENA CLRN Summation Block Adder gt UG ENA CLRN y PRN D Q Q115 poma ena Summation Stage CLRN for Adding Four b Multipliers Together Adder Q1 15 Subtractor Round eet Saturate PRN Q Optional Serial Shift ENA Register Outputs to CLRN Optional Pipline Next DSP Block F Register Stage in the Column ena Optional Input Register IN CLRN Stage with Parallel Input or SO ___ Shift Register Configuration to Mul
34. shift is determined by the voltage controlled oscillator VCO period divided by 8 For degree increments Stratix II devices can shift all output frequencies in increments of at least 45 Smaller degree increments are possible depending on the frequency and divide parameters 5 Stratix II fast PLLs only support manual clock switchover 6 channel to generate txclkout Fast PLLs can drive to any I O pin as an external clock For high speed differential I O pins the device uses a data 7 If the feedback input is used you lose one or two if FBIN is differential external clock output pin 8 Every Stratix II device has at least two enhanced PLLs with one single ended or differential external feedback input per PLL Altera Corporation May 2007 2 59 Stratix II Device Handbook Volume 1 PLLs amp Clock Networks Figure 2 40 shows a top level diagram of the Stratix II device and PLL floorplan Figure 2 40 PLL Locations CLK 15 12 11 5 FPLL7CLK 7 10 FPLL10CLK ciKs o H E E E AE 4 cLKI8 11 2 3 PLLs FPLL8CLK 8 9 FPLL9CLK 1216 CLK 7 4 Figures 2 41 and 2 42 shows the global and regional clocking from the fast PLL outputs and the side clock pins 2 60 Altera Corporation Stratix Il Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 41 Global amp Regional Clock Connections from Center Clock
35. 007 Stratix Il Architecture The number of M512 RAM M4K RAM and DSP blocks varies by device along with row and column numbers and M RAM blocks Table 2 1 lists the resources available in Stratix II devices Table 2 1 Stratix II Device Resources M512 RAM M4K RAM M RAM DSP Block LAB device Columns Blocks Columns Blocks Blocks Columns Blocks Columns LAB ROWS EP2S15 4 104 3 78 0 2 12 30 26 EP2S30 6 202 4 144 1 2 16 49 36 EP2S60 7 329 5 255 2 3 36 62 51 EP2S90 8 488 6 408 4 3 48 71 68 EP2S130 9 699 7 609 6 3 63 81 87 EP2S180 11 930 8 768 9 4 96 100 96 Log i H Array Each LAB consists of eight ALMs carry chains shared arithmetic chains LAB control signals local interconnect and register chain connection B ocks lines The local interconnect transfers signals between ALMs in the same LAB Register chain connections transfer the output of an ALM register to the adjacent ALM register in an LAB The Quartus II Compiler places associated logic in an LAB or adjacent LABs allowing the use of local shared arithmetic chain and register chain connections for performance and area efficiency Figure 2 2 shows the Stratix II LAB structure Altera Corporation 2 3 May 2007 Stratix II Device Handbook Volume 1 Logic Array Blocks Figure 2 2 Stratix II LAB Structure Direct link interconnect from adjacent block Direct link interconnect to adjacent block Row Interco
36. 128 4K x 144 Notes to Table 2 3 1 The M RAM block does not support memory initializations However the M RAM block can emulate a ROM function using a dual port RAM bock The Stratix II device must write to the dual port memory once and then disable the write enable ports afterwards Altera Corporation May 2007 Memory Block Size TriMatrix memory provides three different memory sizes for efficient application support The Quartus II software automatically partitions the user defined memory into the embedded memory blocks using the most efficient size combinations You can also manually assign the memory to a specific block size or a mixture of block sizes When applied to input registers the asynchronous clear signal for the TriMatrix embedded memory immediately clears the input registers However the output of the memory block does not show the effects until the next clock edge When applied to output registers the asynchronous clear signal clears the output registers and the effects are seen immediately 2 29 Stratix II Device Handbook Volume 1 TriMatrix Memory 2 30 M512 RAM Block The M512 RAM block is a simple dual port memory block and is useful for implementing small FIFO buffers DSP and clock domain transfer applications Each block contains 576 RAM bits including parity bits M512 RAM blocks can be configured in the following modes Simple dual port RAM Single port RAM FIFO ROM Shi
37. 4 interconnects can also drive C4 and C16 interconnects for connections from one row to another Additionally R4 interconnects can drive R24 interconnects Figure 2 16 R4 Interconnect Connections Notes 1 2 3 Adjacent LAB can C4 and C16 R4 Interconnect Drive onto Another Column Interconnects 1 Driving Right LAB s R4 Interconnect R4 Interconnect Driving Left 7 7 LB Primary ub Neighbor LAB 2 Neighbor Notes to Figure 2 16 1 C4and C16 interconnects can drive R4 interconnects 2 This pattern is repeated for every LAB in the LAB row 3 The LABs in Figure 2 16 show the 16 possible logical outputs per LAB Altera Corporation 2 23 May 2007 Stratix Il Device Handbook Volume 1 MultiTrack Interconnect 2 24 R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs TriMatrix memory DSP blocks and Row
38. 8 pairs on the left side of the DQS phase shift circuitry 2 The At module represents the DQS logic block 3 Clock pins CLK 15 12 p feed the phase shift circuitry on the top of the device and clock pins CLK 7 4 p feed the phase circuitry on the bottom of the device You can also use a PLL clock output as a reference clock to the phase shift circuitry 4 You can only use PLL 5 to feed the DQS phase shift circuitry on the top of the device and PLL 6 to feed the DQS phase shift circuitry on the bottom of the device These dedicated circuits combined with enhanced PLL clocking and phase shift ability provide a complete hardware solution for interfacing to high speed memory bie For more information on external memory interfaces refer to the External Memory Interfaces in Stratix II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook Programmable Drive Strength The output buffer for each Stratix II device I O pin has a programmable drive strength control for certain I O standards The LVTTL LVCMOS SSTL and HSTL standards have several levels of drive strength that the user can control The default setting used in the Quartus II software is the maximum current strength setting that is used to achieve maximum I O performance For all I O standards the minimum setting is the lowest drive strength that guarantees the Iop lor of the standard Using minimum settings p
39. AB LAB LAB LAB Local C4 amp C16 Interconnect Interconnects Note to Figure 2 48 1 The 32 data and control signals consist of eight data out lines four lines each for DDR applications io_dataouta 3 0 and io_dataoutb 3 0 four output enables io_oe 3 0 four input clock enables io_ce_in 3 0 four output clock enables io_ce_out 3 0 fourclocks io_clk 3 0 four asynchronous clear and preset signals io_aclr apreset 3 0 and four synchronous clear and preset signals io_sclr spreset 3 0 Altera Corporation 2 73 May 2007 Stratix Il Device Handbook Volume 1 I O Structure There are 32 control and data signals that feed each row or column I O block These control and data signals are driven from the logic array The row or column IOE clocks io_clk 7 0 provide a dedicated routing resource for low skew high speed clocks I O clocks are generated from global or regional clocks see the PLLs amp Clock Networks section Figure 2 49 illustrates the signal paths through the I O block Figure 2 49 Signal Path through the 1 0 Block Row or Column To Other io_clk 7 0 IOEs io_dataina lt To Logic Array io_datainb lt q oe ce_in io_oce gt ce_out io_ce_in gt gt Control aclr apreset IOE io_ce_out gt Signal Selection sclr spreset io_aclr From Logic Ik j clk_in Array io_sclr gt gt
40. I O Support Note 1 Input Signal V Output Signal V Vecio V 1 2 1 5 1 8 2 5 3 3 1 2 1 5 1 8 2 5 3 3 5 0 1 2 4 v 2 v 2 v 2 v 2 s 4 1 5 4 s Y ZI Z O SZS x 1 8 4 v Y v 2 v 2 x 3 Y 3 Y 2 5 4 va vA Z 3 Y 3 3 va 3 3 4 v v4 ZONON EN A Notes to Table 2 18 1 To drive inputs higher than Vccio but less than 4 0 V disable the PCI clamping diode and select the Allow LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II software 2 The pin current may be slightly higher than the default value You must verify that the driving device s Vor maximum and Voy minimum voltages do not violate the applicable Stratix II Vj maximum and Vy minimum voltage specifications 3 Although Vccio specifies the voltage necessary for the Stratix II device to drive out a receiving device powered at a different level can still interface with the Stratix II device if it has inputs that tolerate the Vecio value 4 Stratix II devices do not support 1 2 V LVTTL and 1 2 V LVCMOS Stratix II devices support 1 2 V HSTL The TDO and nCEO pins are powered by Vccio of the bank that they reside in TDO is in I O bank 4 and nCEO is in I O bank 7 Ideally the Vcc supplies for the I O buffers of any two connected pins are at the same voltage level This may not always be possible depending on the Vecio level of TDO and nCEO pins on master devices and the con
41. IOEs The R24 row interconnects can cross M RAM blocks R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects R24 interconnects can drive R24 R4 C16 and C4 interconnects The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs TriMatrix memory DSP blocks and IOEs Each column of LABs is served by a dedicated column interconnect These column resources include Shared arithmetic chain interconnects in an LAB Carry chain interconnects in an LAB and from LAB to LAB Register chain interconnects in an LAB C4 interconnects traversing a distance of four blocks in up and down direction C16 column interconnects for high speed vertical routing through the device Stratix II devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers These ALM to ALM connections bypass the local interconnect The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance Figure 2 17 shows the shared arithmetic chain carry chain and register chain
42. Interconnect Driving Up k LAB Row Interconnect Adjacent LAB can drive onto neighboring LAB s C4 interconnect Interconnect C4 Interconnect Driving Down Note to Figure 2 18 1 Each C4 interconnect can drive either up or down four rows 2 26 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs TriMatrix memory blocks DSP blocks and IOEs C16 interconnects can cross M RAM blocks and also drive to row and column interconnects at every fourth LAB C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly All embedded blocks communicate with the logic array similar to LAB to LAB interfaces Each block that is TriMatrix memory and DSP blocks connects to row and column interconnects and has local interconnect regions driven by row and column interconnects These blocks also have direct link interconnects for fast connections to and from a neighboring LAB All blocks are fed by the row LAB clocks labc1k 5 0 Table 2 2 shows the Stratix II device s routing scheme Table 2 2 Stratix Il Device Routing
43. Pins amp Fast PLL Outputs Note 1 1 cLK9 cLKs PLL co Ci Fast c2 cy co CI Fast c ca ig RCK22 RCK20 RCKIS Y RCKIS Gck1o M Gacke cLko oe ak o cLk2 c CLK3 Notes to Figure 2 41 1 EP2S15 and EP2S30 devices only have four fast PLLs 1 2 3 and 4 but the connectivity from these four PLLs to the global and regional clock networks remains the same as shown 2 The global or regional clocks in a fast PLL s quadrant can drive the fast PLL input The global or regional clock input can be driven by an output from another PLL a pin driven dedicated global or regional clock or through a clock control block provided the clock control block is fed by an output from another PLL or a pin driven dedicated global or regional clock An internally generated global signal cannot drive the PLL Altera Corporation 2 61 May 2007 Stratix Il Device Handbook Volume 1 PLLs amp Clock Networks Figure 2 42 Global amp Regional Clock Connections from Corner Clock Pins amp Fast PLL Outputs Note 1 a FPLL9CLK ao FPLL10CLK
44. R24 Interconnects M RAM Block al dataout_a datain_al addressa Direct Link Up to 28 addr_ena_a Interconnects r nwe_a byteenaal clocken_a clock_a aclr_a Row Interface Block M RAM Block to LAB Row Interface Block Interconnect Region Table 2 4 shows the input and output data signal connections along with the address and control signal input connections to the row unit interfaces LO to L5 and RO to R5 2 38 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Altera Corporation May 2007 Table 2 4 M RAM Row Interface Unit Signals Unit Interface Block Input Signals Output Signals LO datain_a 14 0 dataout_a 11 0 byteena_a 1 0 L1 datain_a 29 15 dataout_a 23 12 byteena_a 3 2 L2 datain_a 35 30 dataout_a 35 24 addressa 4 0 addr_ena_a clock_a clocken_a renwe_a aclr_a L3 addressa 15 5 dataout_a 47 36 datain_a 41 36 L4 datain_a 56 42 dataout_a 59 48 byteena_a 5 4 L5 datain_a 71 57 dataout_a 71 60 byteena_al 7 6 RO datain_b 14 0 dataout_b 11 0 byteena_b 1 0 R1 datain_b 29 15 dataout_b 23 12 byteena_b 3 2 R2 datain_b 35 30 dataout_b 35 24 addressb 4 0 addr_ena_b clock_b clocken_b renwe_b aclr_b R3 addressb 15 5 dataout_b 47 36 datain_b 41 36 R4 datain_b 56 42 dataout_b 59 48 byteena_b 5 4 R5 datain_b 71 57 dataout_b 71 60 byteena_b 7 6
45. Scheme Part 1 of 2 Destination 5 s f z b a c o 5 o iaai oO gle s 2 2 2 2 2 2 l gls Source 2 O 8 2 s 8 s slelselel alislzie ElisislslEle s e lSl elZlsla zle z l 2 ejz lt lt 2 elo 5 8 alslai_ Si E z2 z nile l elaloa a e s z e 3ls 2 o 9 9 S s Tlae ole a a Shared arithmetic chain Y Carry chain Y Register chain v Local interconnect ARARA RAKAA Direct link interconnect Y R4 interconnect Y ARARE R24 interconnect VISIS C4 interconnect Y va Y C16 interconnect ARARA ALM RARA ERARA Y M512 RAM block RARA Y M4K RAM block ARARA Y M RAM block VIM IYI SY DSP blocks VERA Y Altera Corporation May 2007 2 27 Stratix Il Device Handbook Volume 1 TriMatrix Memory Table 2 2 Stratix Il Device Routing Scheme Part 2 of 2 Destination Pen ks x x lt Source 5 s s 8 s 5 5 Zlals 2is g l8 9le 2 S 2 S 28 s s s s z 2 S Sl siel Zl ls l slal glaz a g ez EL E S E Z 2 EB 2 e T Tlejzlia eie 3 O 2 8i rlisiais e Bifl Sl elec l sis Fle o ls a a Column IOE va VARA Row IOE AEAT AIEA TriMatrix TriMatrix memory consists of three types of RAM blocks M512 M4K and M RAM Although these memory blocks are different they can all Me mo ry implement various types of memory with or without parity including true dual
46. ain This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree Figure 2 13 shows the ALM in shared arithmetic mode Altera Corporation 2 17 May 2007 Stratix II Device Handbook Volume 1 Adaptive Logic Modules Figure 2 13 ALM in Shared Arithmetic Mode shared_arith_in carry_in 4 Input To general or LUT local routing To general or D gt 2 local routing datae0 E datac 4 Input regO datab LUT dataa ______ 9 e 4 Input To general or datad m LUT local routing datae1 D Q gt To general or local routing 4 Input reg1 LUT carry_out shared_arith_out Note to Figure 2 13 1 Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode Adder trees can be found in many different applications For example the summation of the partial products in a logic based multiplier can be implemented in a tree structure Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de spread data which was transmitted utilizing spread spectrum technology An example of a three bit add operation utilizing the shared arithmetic mode is shown in Figure 2 14 The partial sum S 2 0 and the partial carry C 2 0 is obtaine
47. al PCI clamp is only available on column I O pins ENA CLRN PRN Circuit 2 76 Stratix Il Device Handbook Volume 1 Altera Corporation May 2007 Stratix Il Architecture Altera Corporation May 2007 The Stratix II device IOE includes programmable delays that can be activated to ensure input IOE register to logic array register transfers input pin to logic array register transfers or output IOE register to pin transfers A path in which a pin directly drives a register may require the delay to ensure zero hold time whereas a path in which a pin drives a register through combinational logic may not require the delay Programmable delays exist for decreasing input pin to logic array and IOE input register delays The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time Programmable delays can increase the register to pin delays for output and or output enable registers Programmable delays are no longer required to ensure zero hold times for logic array register to IOE register transfers The Quartus II Compiler can create the zero hold time for these transfers Table 2 13 shows the programmable delays for Stratix II devices Table 2 13 Stratix II Programmable Delay Chain Programmable Delays Quartus II Logic Option Input pin to logic array delay Input delay from pin to internal cells Input pin to input register delay Input delay from
48. al bus hold feature The bus hold circuitry can weakly hold the signal on an I O pin at its last driven state Since the bus hold feature holds the last driven state of the pin until the next input signal is present you do not need an external pull up or pull down resistor to hold a signal level when the bus is tri stated 2 84 Stratix II Device Handbook Volume 1 Altera Corporation May 2007 Stratix Il Architecture Altera Corporation May 2007 The bus hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high frequency switching You can select this feature individually for each I O pin The bus hold output drives no higher than Vccio to prevent overdriving signals If the bus hold feature is enabled the programmable pull up option cannot be used Disable the bus hold feature when the I O pin has been configured for differential signals The bus hold circuitry uses a resistor with a nominal resistance Rgp of approximately 7 kQto weakly pull the signal level to the last driven state See the DC amp Switching Characteristics chapter in the Stratix II Device Handbook Volume 1 for the specific sustaining current driven through this resistor and overdrive current used to identify the next driven input level This information is provided for each Vecio voltage level The bus hold circuitry is active only after configuration When going into user mode the bus hold circuit c
49. aptures the value on the pin present at the end of configuration Programmable Pull Up Resistor Each Stratix II device I O pin provides an optional programmable pull up resistor during user mode If you enable this feature for an I O pin the pull up resistor typically 25 kQ weakly holds the output to the Vccio level of the output pin s bank Programmable pull up resistors are only supported on user I O pins and are not supported on dedicated configuration pins JTAG pins or dedicated clock pins Advanced 1 0 Standard Support Stratix II device IOEs support the following I O standards 3 3 V LVTTL LVCMOS 2 5 V LVTTL LVCMOS 1 8 V LVITTL LVCMOS 1 5 V LVCMOS 3 3 V PCI 3 3 V PCI X mode 1 LVDS LVPECL on input and output clocks only HyperTransport technology Differential 1 5 V HSTL Class I and II Differential 1 8 V HSTL Class I and II Differential SSTL 18 Class I and II Differential SSTL 2 Class I and II 2 85 Stratix II Device Handbook Volume 1 I O Structure 1 2 V HSTL 1 5 V HSTL Class I and II 1 8 V HSTL Class I and II SSTL 2 Class I and II SSTL 18 Class I and II Table 2 16 describes the I O standards supported by Stratix II devices Table 2 16 Stratix II Supported 1 0 Standards Part 1 of 2 vost te tet toe ae LVTTL Single ended 3 3 LVCMOS Single ended 3 3 2 5V Single ended 2 5 1 8V Single ended 1 8 1 5 V LVCMOS Single
50. at up to 420 MHz Several M RAM blocks are located individually in the device s logic array DSP blocks can implement up to either eight full precision 9 x 9 bit multipliers four full precision 18 x 18 bit multipliers or one full precision 36 x 36 bit multiplier with add or subtract features The DSP blocks support Q1 15 format rounding and saturation in the multiplier and accumulator stages These blocks also contain shift registers for digital signal processing applications including finite impulse response FIR and infinite impulse response IIR filters DSP blocks are grouped into columns across the device and operate at up to 450 MHz 2 1 Functional Description Each Stratix II device I O pin is fed by an I O element IOE located at the end of LAB rows and columns around the periphery of the device I O pins support numerous single ended and differential I O standards Each IOE contains a bidirectional I O buffer and six registers for registering input output and output enable signals When used with dedicated clocks these registers provide exceptional performance and interface support with external memory devices such as DDR and DDR2 SDRAM RLDRAM II and QDR II SRAM devices High speed serial interface channels with dynamic phase alignment DPA support data transfer at up to 1 Gbps using LVDS or HyperTransport technology I O standards Figure 2 1 shows an overview of the Stratix II device Figure 2 1 Stratix II B
51. ation SSTL 2 Class and II SSTL 18 Class and II 1 8 V HSTL Class 1 8 V HSTL Class II 1 5 V HSTL Class and II 1 2 V HSTL SSNS SSIS SEINS ET PN NS NG Differential termination 7 LVDS HyperTransport technology V V Note to Table 2 17 1 Clock pins CLK1 CLK3 CLK9 CLK11 and pins FPLL 7 10 Altera Corporation May 2007 CLK do not support differential on chip termination Clock pins CLK0 CLK2 CLK8 and CLK10 do support differential on chip termination Clock pins in the top and bottom banks CLK 4 7 12 15 do not support differential on chip termination 2 91 Stratix II Device Handbook Volume 1 I O Structure Differential On Chip Termination Stratix II devices support internal differential termination with a nominal resistance value of 100 Qfor LVDS or HyperTransport technology input receiver buffers LVPECL input signals supported on clock pins only require an external termination resistor Differential on chip termination is supported across the full range of supported differential data rates as shown in the DC amp Switching Characteristics chapter in volume 1 of the Stratix II Device Handbook 2 For more information on differential on chip termination refer to the High Speed Differential I O Interfaces with DPA in Stratix II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handb
52. can support larger multiplication functions Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 27 shows one of the columns with surrounding LAB rows Figure 2 27 DSP Blocks Arranged in Columns 4 LAB Rows DSP Block Column DSP Block Altera Corporation May 2007 2 41 Stratix Il Device Handbook Volume 1 Digital Signal Processing Block 2 42 Table 2 5 shows the number of DSP blocks in each Stratix II device Table 2 5 DSP Blocks in Stratix II Devices Note 1 Device DSP Blocks Muhiptiers Multipliers Multipliers EP2S15 12 96 48 12 EP2S30 16 128 64 16 EP2S60 36 288 144 36 EP2S90 48 384 192 48 EP2S130 63 504 252 63 EP2S180 96 768 384 96 Note to Table 2 5 1 Each device has either the numbers of 9 x 9 18 x 18 or 36 x 36 bit multipliers shown The total number of multipliers for each device is not the sum of all the multipliers DSP block multipliers can optionally feed an adder subtractor or accumulator in the block depending on the configuration This makes routing to ALMs easier saves ALM routing resources and increases performance because all connections and blocks are in the DSP block Additionally the DSP block input registers can efficiently implement
53. cks Blocks Blocks Note to Figure 2 24 M RAM Block i i M RAM Block DSP Blocks 1 The device shown is an EP25130 device The number and position of M RAM blocks varies in other devices 2 36 Stratix Il Device Handbook Volume 1 Altera Corporation May 2007 Stratix Il Architecture Figure 2 25 M RAM Block LAB Row Interface Note 1 Row Unit Interface Allows LAB Row Unit Interface Allows LAB Rows to Drive Port A Datain Rows to Drive Port B Datain Dataout Address and Control Dataout Address and Control Signals to and from M RAM Block Signals to and from M RAM Block i 4 LO RO gt lt tr Li R1 be eee eee M RAM Block lt tr 2 Port A Port B R2 gt lt r L3 R3 e gt lt p L4 R4 e gt A L5 R5 gt LAB Interface i Blocks j LABs in Row LABs in Row M RAM Boundary M RAM Boundary Note to Figure 2 25 1 Only R24 and C16 interconnects cross the M RAM block boundaries Altera Corporation 2 37 May 2007 Stratix II Device Handbook Volume 1 TriMatrix Memory Figure 2 26 M RAM Row Unit Interface to Interconnect C4 Interconnect R4 and
54. clock 2 100 Each Stratix II receiver channel features a DPA block for phase detection and selection a SERDES a synchronizer and a data realigner circuit You can bypass the dynamic phase aligner without affecting the basic source synchronous operation of the channel In addition you can dynamically switch between using the DPA block or bypassing the block via a control signal from the logic array Figure 2 59 shows the block diagram of the Stratix II receiver channel Altera Corporation Stratix Il Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 59 Stratix II Receiver Channel Up to 1 Gbps Data to R4 R24 C4 or direct link interconnect D Q Data Realignment Circuitry data retimed_data Dedicated DPA Synchronizer Interface Receiver gt HH DPA_clk eooo o Eight Phase Clocks refclk gt diffioclk load_en Regional or global clock Altera Corporation May 2007 An external pin or global or regional clock can drive the fast PLLs which can output up to three clocks two multiplied high speed clocks to drive the SERDES block and or external pin and a low speed clock to drive the logic array In addition eight phase shifted clocks from the VCO can feed to the DPA c
55. configured to clock two data paths from ALMs on rising clock edges These output registers are multiplexed by the clock to drive the output pin at a x2 rate One output register clocks the first bit out on the clock high time while the other output register clocks the second bit out on the clock low time Figure 2 54 shows the IOE configured for DDR output Figure 2 55 shows the DDR output timing diagram Altera Corporation 2 79 May 2007 Stratix Il Device Handbook Volume 1 I O Structure Figure 2 54 Stratix II IOE in DDR Output 1 0 Configuration Notes 1 2 ioe_clk 7 0 Column Row or Local Interconnect oe a OE Register D Qe gt clkout ENA a CLRN PRN OE Register ce_out 7 tco Delay acir apreset Vecio 9 pt Z PCI Clamp 3 Chip Wide Reset OE Register D Q Vecio sclr spreset Programmable e Used for lt Pull Up ENA DDR DDR2 Resistor CLRN PRN SDRAM NS Output Register D Q ip Output R On Chip Pin Delay Termination on ed ENA clk CLRN PRN 5 Drive Strength Control 7 Open Drain Output e AW Output Register A D Q 5 gt Bus Hold ENA Circuit CLRN PRN Notes to Figure 2 54 1 All input signals to the IOE can be invert
56. d delay elements for all DQS pins on the top The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom Each phase shifting reference circuit is driven by a system reference clock which must have the same frequency as the DQS signal Clock pins CLK 15 12 p feed the phase circuitry on the top of the device and clock pins CLK 7 4 p feed the phase circuitry on the bottom of the device In addition PLL clock outputs can also feed the phase shifting reference circuits Figure 2 56 illustrates the phase shift reference circuit control of each DQS delay shift on the top of the device This same circuit is duplicated on the bottom of the device Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 56 DQS Phase Shift Circuitry Notes 1 2 3 4 m From PLL 5 3 CLK 15 12 p 2 Dasn Das Dasn pas Das Dasn bas Dasn Pin Pin Pin Pin Xb Pin Pin Pin Pin xX Xx Xl Xx Xx Xx X Xx DaS l At At sea At Phase Shift At Als ee At at 298 Logic Circuitry Blocks to IOE to IOE to IOE to IOE to IOE to IOE to IOE to IOE eee eee Notes to Figure 2 56 1 There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device There are up to 10 pairs on the right side and
57. d using the LUTs while the result R 2 0 is computed using the dedicated adders 2 18 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 14 Example of a 3 bit Add Utilizing Shared Arithmetic Mode 3 Bit Add Example Binary Add 1 fo 0 0 1st stage add is implemented in LUTs 2nd stage add is implemented in adders X2 X1 X0 Y2Y1Y0 Z2 Z1 Z0 S2 S1 S0 C2 C1 C0 R3 R2 R1 RO Decimal Equivalents ALM Implementation shared_arith_in 0 carry_in 0 Altera Corporation May 2007 Shared Arithmetic Chain In addition to the dedicated carry chain routing the shared arithmetic chain available in shared arithmetic mode allows the ALM to implement a three input add This significantly reduces the resources necessary to implement large adder trees or correlator functions The shared arithmetic chains can begin in either the first or fifth ALM in an LAB The Quartus II Compiler creates shared arithmetic chains longer than 16 8 ALMs in arithmetic or shared arithmetic mode by linking LABs together automatically For enhanced fitting a long shared 2 19 Stratix II Device Handbook Volume 1 Adaptive Logic Modules 2 20 arithmetic chain runs vertically allowing fast horizontal connections to TriMatrix memory and
58. device s high speed differential I O circuitry provides dedicated data realignment circuitry for user controlled byte boundary shifting This simplifies designs while saving ALM resources You can use an ALM based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment Fast PLL amp Channel Layout The receiver and transmitter channels are interleaved such that each I O bank on the left and right side of the device has one receiver channel and one transmitter channel per LAB row Figure 2 60 shows the fast PLL and channel layout in the EP2515 and EP2S30 devices Figure 2 61 shows the fast PLL and channel layout in the EP2S60 to EP2S180 devices Figure 2 60 Fast PLL amp Channel Layout in the EP2S15 amp EP2S30 Devices Note 1 4 LVDS DPA DPA Clock Clock Clock Quadrant Quadrant 4 Fast asi J PLL 1 L lt J any Fast PLL2 Ee 2 Quadrant Quadrant LVDS DPA DPA 4 Clock Clock Clock Note to Figure 2 60 1 See Table 2 21 for the number of channels each device supports 2 102 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 61 Fast PLL amp Channel Layout in the EP2S60 to EP2S180 Devic
59. e M512 RAM block has up to 16 direct link input connections from the left adjacent LABs and another 16 from the right adjacent LAB M512 RAM outputs can also connect to left and right LABs through direct link interconnect The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side Figure 2 20 shows the M512 RAM block to logic array interface Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 19 M512 RAM Block Control Signals Dedicated Row LAB Clocks Local nterconnect L Local nterconnect 4 Local nterconnect 3 Local N nterconnect ll Local nterconnect pes Local N nterconnect paa Local N nterconnect J Local rs nterconnect lL if ot it af ZEURE ELSAN y y y inclocken outclocken wren y y y vy inclock outclock rden outclr Altera Corporation May 2007 2 31 Stratix II Device Handbook Volume 1 TriMatrix Memory Figure 2 20 M512 RAM Block LAB Row Interface C4 Interconnect Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB R4 Interconnect interconnect to adjacent LAB dataout M512 RAM Block from adjacent LAB clocks control signals I l datain
60. ed TDO TDI Voltage Combinations Part 2 of 2 Diiis TDI Input Stratix II TDO Veco Voltage Level in 1 0 Bank 4 Buffer Power Vecio 3 3V Vecio 2 5V Vecio 1 8V Vecio 1 5V Vecio 1 2V Non Stratix Il VCC 3 3 V v 1 v 2 v 3 Level shifter Level shifter required required VCC 2 5 V vV 1 4 v 2 V 3 Level shifter Level shifter required required VCC 1 8V x 1 4 v 2 5 Y Level shifter Level shifter required required VCC 1 5V 1 4 v 2 5 6 V v Notes to Table 2 20 1 2 3 4 5 6 High Speed Differential 1 0 with DPA Support 2 96 Stratix Il Device Handbook Volume 1 The TDO output buffer meets Voy MIN 2 4 V The TDO output buffer meets Voy MIN 2 0 V An external 250 Q pull up resistor is not required but recommended if signal levels on the board are not optimal Input buffer must be 3 3 V tolerant Input buffer must be 2 5 V tolerant Input buffer must be 1 8 V tolerant Stratix II devices contain dedicated circuitry for supporting differential standards at speeds up to 1 Gbps The LVDS and HyperTransport differential I O standards are supported in the Stratix II device In addition the LVPECL I O standard is supported on input and output clock pins on the top and bottom I O banks The high speed differential I O circuitry supports the following high speed I O interconnect standards and applications SPI 4 Phase 2 POS PHY Lev
61. ed at the IOE 2 The tri state buffer is active low The DDIO megafunction represents the tri state buffer as active high with an inverter at the OE register data port Similarly the aclr and apreset signals are also active high at the input ports of the DDIO megafunction 3 The optional PCI clamp is only available on column I O pins 2 80 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 55 Output Timing Diagram in DDR Mode From Internal Registers DDR output The Stratix II IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations The negative edge clocked OE register holds the OE signal inactive until the falling edge of the clock This is done to meet DDR SDRAM timing requirements External RAM Interfacing In addition to the six I O registers in each IOE Stratix II devices also have dedicated phase shift circuitry for interfacing with external memory interfaces Stratix II devices support DDR and DDR2 SDRAM QDR II SRAM RLDRAM II and SDR SDRAM memory interfaces In every Stratix II device the I O banks at the top banks 3 and 4 and bottom banks 7 and 8 of the device support DQ and DOS signals with DQ bus modes of x4 x8 x9 x16 x18 or x32 x36 Table 2 14 shows the number of DQ and DQS buses that are supported per device Table 2 14 DOS amp DQ Bus Mode Support Part 1 of 2 Note
62. el 4 SFI 4 Parallel RapidIO HyperTransport technology There are four dedicated high speed PLLs in the EP2S15 to EP2S30 devices and eight dedicated high speed PLLs in the EP2560 to EP25180 devices to multiply reference clocks and drive high speed differential SERDES channels Tables 2 21 through 2 26 show the number of channels that each fast PLL can clock in each of the Stratix II devices In Tables 2 21 through 2 26 the first row for each transmitter or receiver provides the number of channels driven directly by the PLL The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL For example in the 484 pin FineLine BGA EP2S15 Altera Corporation May 2007 Stratix Il Architecture device PLL 1 can drive a maximum of 10 transmitter channels in I O bank 1 or a maximum of 19 transmitter channels in I O banks 1 and 2 The Quartus II software may also merge receiver and transmitter PLLs when a receiver is driving a transmitter In this case one fast PLL can drive both the maximum numbers of receiver and transmitter channels Table 2 21 EP2S15 Device Differential Channels Note 1 Package Transmitter Total Center Fast PLLs Receiver Channels pitt PLL2 PLL3 PLL4 484 pin FineLine BGA Transmitter 38 2 10 9 9 10 3 19 19 19 19 Receiver 42 2 11 10 10 11 3 21 21 21 21
63. ended 1 5 3 3 V PCI Single ended 3 3 3 3 V PCI X mode 1 Single ended 3 3 LVDS Differential 2 5 3 LVPECL 1 Differential 3 3 HyperTransport technology Differential 2 5 Differential 1 5 V HSTL Differential 0 75 1 5 0 75 Class and Il 2 Differential 1 8 V HSTL Differential 0 90 1 8 0 90 Class and Il 2 Differential SSTL 18 Class Differential 0 90 1 8 0 90 and II 2 Differential SSTL 2 Class Differential 1 25 2 5 1 25 and II 2 1 2 V HSTL 4 Voltage referenced 0 6 1 2 0 6 1 5 V HSTL Class and II Voltage referenced 0 75 1 5 0 75 1 8 V HSTL Class and II Voltage referenced 0 9 1 8 0 9 SSTL 18 Class and II Voltage referenced 0 90 1 8 0 90 2 86 Stratix II Device Handbook Volume 1 Altera Corporation May 2007 Stratix Il Architecture Table 2 16 Stratix II Supported 1 0 Standards Part 2 of 2 Input Reference Output Supply Board Termination yeaa Type Voltage Vaer V Voltage Vecio V Voltage Vry V SSTL 2 Class and II Voltage referenced 1 25 2 5 1 25 Notes to Table 2 16 1 This I O standard is only available on input and output column clock pins 2 This I O standard is only available on input clock pins and DQS pins in I O banks 3 4 7 and 8 and output clock pins in I O banks 9 10 11 and 12 3 Vecio is 3 3 V when using this I O standard in input and output column clock pins in I O banks 9 10 11 and 12
64. es Note 1 DPA DPA Clock Quadrant Quadrant Clock eT n e L J L J DPA DPA Clock Quadrant Quadrant Clock Note to Figure 2 61 1 See Tables 2 22 through 2 26 for the number of channels each device supports Altera Corporation 2 103 May 2007 Stratix Il Device Handbook Volume 1 Document Revision History Document Table 2 27 shows the revision history for this chapter Revision History Table 2 27 Document Revision History Part 1 of 2 Date and Document Version May 2007 v4 3 Changes Made Updated Clock Control Block section Summary of Changes Updated note in the Clock Control Block section Deleted Tables 2 11 and 2 12 Updated notes to e Figure 2 41 e Figure 2 42 e Figure 2 43 e Figure 2 45 Updated notes to Table 2 18 Moved Document Revision History to end of the chapter August 2006 Updated Table 2 18 with note v4 2 April 2006 e Updated Table 2 13 e Added parallel on v4 1 e Removed Note 2 from Table 2 16 chip termination e Updated On Chip Termination section and Table 2 19 to description and include parallel termination with calibration
65. ese PLLs increase performance and provide advanced clock interfacing and clock frequency synthesis With features such as clock switchover spread spectrum clocking reconfigurable bandwidth phase control and reconfigurable phase shifting the Stratix IT device s enhanced PLLs provide you with complete control of clocks and system timing The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high speed outputs for high speed differential I O support Enhanced and fast PLLs work together with the Stratix II high speed I O and advanced clock architecture to provide significant improvements in system performance and bandwidth 2 57 Stratix II Device Handbook Volume 1 PLLs amp Clock Networks The Quartus II software enables the PLLs and their features without requiring any external devices Table 2 9 shows the PLLs available for each Stratix II device and their type Table 2 9 Stratix II Device PLL Availability Fast PLLs Enhanced PLLs Device 1 2 3 4 7 8 9 10 5 6 11 12 EP2S15 va Y Y Y Y v EP2S30 v Y v Y Y Y EP2S60 1 v Y Y Y Y Y Y Y v Y Y Y EP2S90 2 Y Y Y Y Y Y Y Y Y Y Y Y EP2S130 3 v v v Y va Y Y Y Y Y Y v EP2S180 Y Y Y Y Y v Y Y Y Y v Y Notes to Table 2 9 1 EP2S60 devices in the 1020 pin package contain 12 PLLs EP2S60 devices in the 484 pin and 672 pin packages contain fast PLLs 1 4 and enha
66. figuration voltage level chosen by VCCSEL on slave devices Master and slave devices can be in any position in the chain Master indicates that it is driving out TDO or nCEO to a slave device For multi device passive configuration schemes the nCEO pin of the master device drives the nCE pin of the slave device The VCCSEL pin on the slave device selects which input buffer is used for nCE When VCCSEL is logic high it selects the 1 8 V 1 5 V buffer powered by Vccio When VCCSEL is logic low it selects the 3 3 V 2 5 V input buffer powered by Vecpp The ideal case is to have the Vecio of the nCEO bank in a master device match the VCCSEL settings for the nCE input buffer of the slave device it is connected to but that may not be possible depending on the application Table 2 19 contains board design recommendations to ensure that nCEO can successfully drive nCE for all power supply combinations 2 94 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Table 2 19 Board Design Recommendations for nCEO Notes to Table 2 19 1 2 3 4 5 6 Input buffer is 3 3 V tolerant The nCEO output buffer meets Voy MIN 2 4 V Input buffer is 2 5 V tolerant The nCEO output buffer meets Voy MIN 2 0 V Input buffer is 1 8 V tolerant An external 250 Q pull up resistor is not required but recommended if signal levels on the board are not optimal
67. ft register c Violating the setup or hold time on the memory block address registers could corrupt memory contents This applies to both read and write operations When configured as RAM or ROM you can use an initialization file to pre load the memory contents M512 RAM blocks can have different clocks on its inputs and outputs The wren datain and write address registers are all clocked together from one of the two clocks feeding the block The read address rden and output registers can be clocked by either of the two clocks driving the block This allows the RAM block to operate in read write or input output clock modes Only the output register can be bypassed The six labc1k signals or local interconnect can drive the inclock outclock wren rden and outclr signals Because of the advanced interconnect between the LAB and M512 RAM blocks ALMs can also control the wren and rden signals and the RAM clock clock enable and asynchronous clear signals Figure 2 19 shows the M512 RAM block control signal generation logic The RAM blocks in Stratix II devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks The M512 RAM block local interconnect is driven by the R4 C4 and direct link interconnects from adjacent LABs The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects Th
68. gional Clocks Clock Pins or PLL Clock Outputs Can Drive Dual Regional Network N Clock Pins or PLL Clock CLK 15 12 Outputs Can Drive CLK 15 12 X Dual Regional Network CLKI3 0 CLK 11 8 CLK 3 0 _ cLKj1 8 a PLis l Pls l i y wy CLK 7 4 CLK 7 4 Combined Resources Within each quadrant there are 24 distinct dedicated clocking resources consisting of 16 global clock lines and eight regional clock lines Multiplexers are used with these clocks to form busses to drive LAB row clocks column IOE clocks or row IOE clocks Another multiplexer is used at the LAB level to select three of the six row clocks to feed the ALM registers in the LAB see Figure 2 34 Figure 2 34 Hierarchical Clock Networks Per Quadrant Clocks Available to a Quadrant or Half Quadrant gt Column I O Cell IO_CLK 7 0 Global Clock Network 15 0 Clock 23 0 l l P Lab Row Clock 5 0 Regional Clock Network 7 0 Row 1 0 Cell gt 10 CLKI7 0 Altera Corporation 2 51 May 2007 Stratix II Device Handbook Volume 1 PLLs amp Clock Networks IOE clocks have row and column block regions that are clocked by eight I O clock signals chosen from the 24 quadrant clock resources Figures 2 35 and 2 36 show the quadrant relationship to the I O
69. he asynchronous load preset signal is used the labclkena0 signal is no longer available The LAB row clocks 5 0 and LAB local interconnect generate the LAB wide control signals The MultiTrack interconnect s inherent low skew allows clock and control signal distribution in addition to data Figure 2 4 shows the LAB control signal generation circuit Figure 2 4 LAB Wide Control Signals Dedicated Row LAB Clocks There are two unique clock signals per LAB Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect m L a 7 2 L oe AE A ae ee ee A p FOGN ee aed y y y y labcik0 y labcik1 v labcik2 Y syncload VW labclr1 y Adaptive Logic Modules 2 6 The basic building block of logic in the Stratix II architecture the adaptive logic module ALM provides advanced features with efficient logic utilization Each ALM contains a variety of look up table LUT based resources that can be divided between two adaptive LUTs ALUTs With up to eight inputs to the two ALUTs one ALM can implement various combinations of two functions This adaptability allows the ALM to be Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture completely backward com
70. ibration Series termination Rs with calibration Parallel termination Ry with calibration Altera Corporation 2 89 May 2007 Stratix II Device Handbook Volume 1 O Structure Table 2 17 shows the Stratix II on chip termination support per I O bank Table 2 17 On Chip Termination Support by I O Banks Part 1 of 2 On Chip Termination Support 1 0 Standard Support Top amp Bottom Banks Left amp Right Banks Series termination without 3 3 V LVTTL calibration 3 3 V LVCMOS 2 5 V LVTTL 2 5 V LVCMOS 1 8 V LVTTL 1 8 V LVCMOS 1 5 V LVTTL 1 5 V LVCMOS SSTL 2 Class and II SSTL 18 Class SSTL 18 Class II 1 8 V HSTL Class 1 8 V HSTL Class II SINISI Se S 1 5 V HSTL Class 1 2 V HSTL eS hy SISAS NISA el NS 2 90 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Table 2 17 On Chip Termination Support by I O Banks Part 2 of 2 On Chip Termination Support Series termination with calibration 1 0 Standard Support 3 3 V LVTTL Top amp Bottom Banks Left amp Right Banks 3 3 V LVCMOS 2 5 V LVTTL 2 5 V LVCMOS 1 8 V LVTTL 1 8 V LVCMOS 1 5 V LVTTL 1 5 V LVCMOS SSTL 2 Class and II SSTL 18 Class and II 1 8 V HSTL Class 1 8 V HSTL Class II 1 5 V HSTL Class 1 2 V HSTL Parallel termination with calibr
71. ic GCLKDRVO a GCLKDRV1 7 GCLKDRV2 z 2 66 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Table 2 12 Global amp Regional Clock Connections from Bottom Clock Pins amp Enhanced PLL Outputs Part 2 of 2 i x o r N m tT uw regional ciocketwonr S Z 8 g8 s 3 3 5 5 Connectivity aloj S9 Sj j ejgjzlzlzlzlgz GCLKDRV3 Z RCLKDRVO Y Ti RCLKDRV1 Y Y RCLKDRV2 a Y RCLKDRV3 Y Y RCLKDRV4 Y Y RccxDAVs T E E E E OT Uf TT RCLKDRV6 Ti Ta RCLKDRV7 vA i Enhanced PLL 6 outputs co AR AAE Y Y ci VIL Y Y c2 Y RA Y Y c3 d y Y V c4 Y Y vA Y Y c5 wv v Y Y Y Enhanced PLL 12 outputs c0 VRA Y vA ci viv v Y c2 VARA Y Y c3 Yi vA Y c4 Y Y Y Y c5 Y Y Y Y Altera Corporation 2 67 May 2007 Stratix II Device Handbook Volume 1 PLLs amp Clock Networks Enhanced PLLs Stratix II devices contain up to four enhanced PLLs with advanced clock management features Figure 2 44 shows a diagram of the enhanced PLL Figure 2 44 Stratix II Enhanced PLL Note 1 VCO Phase Selection Selectable at Each PLL Output Port Post Scale Counters cO ict Ic2 Ic3
72. ide a device wide reset pin DEV_CLRn that resets all registers in the device An option set before compilation in the Quartus II software controls this pin This device wide reset overrides all other control signals In the Stratix II architecture connections between ALMs TriMatrix memory DSP blocks and device I O pins are provided by the MultiTrack interconnect structure with DirectDrive technology The MultiTrack interconnect consists of continuous performance optimized routing lines of different lengths and speeds used for inter and intra design block connectivity The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block based designing by eliminating the re optimization cycles that typically follow design changes and additions The MultiTrack interconnect consists of row and column interconnects that span fixed distances A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities Dedicated row interconnects route signals to and from LABs DSP blocks and TriMatrix memory in the same row These row resources include
73. interconnects Altera Corporation Stratix Il Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 17 Shared Arithmetic Chain Carry Chain amp Register Chain Interconnects Local Interconnect Routing Among ALMs in the LAB Carry Chain amp Shared ALM 1 Register Chain Arithmetic Chain z 4 3 Routing to Adjacent outing to Adjacent ALM y ALM s Register Inpu ALM 2 Local ALM 3 Interconnect The C4 interconnects span four LABs M512 or M4K blocks up or down from a source LAB Every LAB has its own set of C4 interconnects to drive either up or down Figure 2 18 shows the C4 interconnect connections from an LAB in a column The C4 interconnects can drive and be driven by all types of architecture blocks including DSP blocks TriMatrix memory blocks and column and row IOEs For LAB interconnection a primary LAB or its LAB neighbor can drive a given C4 interconnect C4 interconnects can drive each other to extend their range as well as drive row interconnects for column to column connections Altera Corporation 2 25 May 2007 Stratix Il Device Handbook Volume 1 MultiTrack Interconnect Figure 2 18 C4 Interconnect Connections Note 1 C4 Interconnect Drives Local and R4 Interconnects up to Four Rows C4
74. ion May 2007 LAB Control Signals Each LAB contains dedicated logic for driving control signals to its ALMs The control signals include three clocks three clock enables two asynchronous clears synchronous clear asynchronous preset load and synchronous load control signals This gives a maximum of 11 control signals at a time Although synchronous load and clear signals are generally used when implementing counters they can also be used with other functions Each LAB can use three clocks and three clock enable signals However there can only be up to two unique clocks per LAB as shown in the LAB control signal generation circuit in Figure 2 4 Each LAB s clock and clock enable signals are linked For example any ALM in a particular LAB using the labclk1 signal also uses labclkenal If the LAB uses both the rising and falling edges of a clock it also uses two LAB wide clock signals De asserting the clock enable signal turns off the corresponding LAB wide clock Each LAB can use two asynchronous clear signals and an asynchronous load preset signal By default the Quartus II software uses a NOT gate push back technique to achieve preset If you disable the NOT gate push up option or assign a given register to power up high using the Quartus II software the preset is achieved using the asynchronous load 2 5 Stratix II Device Handbook Volume 1 Adaptive Logic Modules signal with asynchronous load data input tied high When t
75. ircuitry For more information on the fast PLL see the PLLs in Stratix II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook The eight phase shifted clocks from the fast PLL feed to the DPA block The DPA block selects the closest phase to the center of the serial data eye to sample the incoming data This allows the source synchronous circuitry to capture incoming data correctly regardless of the channel to channel or clock to channel skew The DPA block locks to a phase closest to the serial data phase The phase aligned DPA clock is used to write the data into the synchronizer The synchronizer sits between the DPA block and the data realignment and SERDES circuitry Since every channel utilizing the DPA block can have a different phase selected to sample the data the synchronizer is needed to synchronize the data to the high speed clock domain of the data realignment and the SERDES circuitry 2 101 Stratix II Device Handbook Volume 1 High Speed Differential I O with DPA Support For high speed source synchronous interfaces such as POS PHY 4 Parallel RapidIO and HyperTransport the source synchronous clock rate is not a byte or SERDES rate multiple of the data rate Byte alignment is necessary for these protocols since the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate not one eighth The Stratix II
76. ized functions such as library of parameterized modules LPM functions automatically choose the appropriate mode for common functions such as counters adders subtractors and arithmetic functions If required you can also create special purpose functions that specify which ALM operating mode to use for optimal performance Normal Mode The normal mode is suitable for general logic applications and combinational functions In this mode up to eight data inputs from the LAB local interconnect are inputs to the combinational logic The normal mode allows two functions to be implemented in one Stratix IT ALM or an ALM to implement a single function of up to six inputs The ALM can support certain combinations of completely independent functions and various combinations of functions which have common inputs Figure 2 7 shows the supported LUT combinations in normal mode Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 7 ALM in Normal Mode Note 1 datafo ____ i datafo datae0 _ _ 4 Input datae0 3 i datac LUT i a ombou datac __ red i combout0 dataa De dataa e i f datab datab S i i L 4 Input i datad npu Le ombou datae1 LUT datad Sie combo t
77. l I O with DPA Support Dedicated Circuitry with DPA Support Stratix II devices support source synchronous interfacing with LVDS or HyperTransport signaling at up to 1 Gbps Stratix IT devices can transmit or receive serial channels along with a low speed or high speed clock The receiving device PLL multiplies the clock by an integer factor W 1 through 32 For example a HyperTransport technology application where the data rate is 1 000 Mbps and the clock rate is 500 MHz would require that W be set to 2 The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters The SERDES factor J can be set to 4 5 6 7 8 9 or 10 and does not have to equal the PLL clock multiplication W value A design using the dynamic phase aligner also supports all of these J factor values For a J factor of 1 the Stratix II device bypasses the SERDES block For a J factor of 2 the Stratix II device bypasses the SERDES block and the DDR input and output registers are used in the IOE Figure 2 58 shows the block diagram of the Stratix II transmitter channel Figure 2 58 Stratix II Transmitter Channel refclk gt Data from R4 R24 C4 or direct link interconnect A id gt Up to 1 Gbps 10 10 c Local Dedicated Interconnect lt Transmitter Interface diffioclk rani load_en PLL f gt Regional or global
78. lock Diagram M4K RAM Blocks IOEs Support DDR PCI PCI X M512 RAM Blocks for DSP Blocks for for True Dual Port SSTL 3 SSTL 2 HSTL 1 HSTL 2 Dual Port Memory Shift Multiplication and Full Memory amp Other Embedded LVDS HyperTransport amp other Registers amp FIFO Buffers Implementation of FIR Filters Memory Functions 1 0 Standards IOEs IOEs IOEs OES iS __ Ce Acs AEs OES LABS LABs OES EE H TOES LL OEST E EE a I OES LABS LABs L OES EE F OE o a s N o a o l cs _ SE aa H OET H E RAN Biog IOEs LABs LABs LABs L OEA O i OES EE aa H OES L I IOEs LABs LABs LABs OES LABS LABs OES E aa SS e e e e e e e e e e e e e e e e e e e e DSP e e e e Block 2 2 Altera Corporation Stratix II Device Handbook Volume 1 May 2
79. me 1 2 8 Stratix Il Architecture Altera Corporation May 2007 One ALM contains two programmable registers Each register has data clock clock enable synchronous and asynchronous clear asynchronous load data and synchronous and asynchronous load preset inputs Global signals general purpose I O pins or any internal logic can drive the register s clock and clear control signals Either general purpose I O pins or internal logic can drive the clock enable preset asynchronous load and asynchronous load data The asynchronous load data input comes from the datae or dataf input of the ALM which are the same inputs that can be used for register packing For combinational functions the register is bypassed and the output of the LUT drives directly to the outputs of the ALM Each ALM has two sets of outputs that drive the local row and column routing resources The LUT adder or register output can drive these output drivers independently see Figure 2 6 For each set of output drivers two ALM outputs can drive column row or direct link routing connections and one of these ALM outputs can also drive local interconnect resources This allows the LUT or adder to drive one output while the register drives another output This feature called register packing improves device utilization because the device can use the register and the combinational logic for unrelated functions Another special packing mode allows the register outp
80. me 1 May 2007 Stratix Il Architecture Altera Corporation May 2007 The Stratix II clock networks can be disabled powered down by both static and dynamic approaches When a clock net is powered down all the logic fed by the clock net is in an off state thereby reducing the overall power consumption of the device The global and regional clock networks can be powered down statically through a setting in the configuration sof or pof file Clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by the Quartus II software The dynamic clock enable disable feature allows the internal logic to control power up down synchronously on GCLK and RCLK nets and PLL_OUT pins This function is independent of the PLL and is applied directly on the clock network or PLL_OUT pin as shown in Figures 2 37 through 2 39 The following restrictions for the input clock pins apply CLKO pin gt inclk 0 of CLKCTRL CLK1 pin gt inclk 1 of CLKCTRL CLK2 pin gt inclk 0 of CLKCTRL CLK3 pin gt inclk 1 of CLKCTRL In general even CLK numbers connect to the inclk 0 port of CLKCTRL and odd CLK numbers connect to the inc1k 1 port of CLKCTRL Failure to comply with these restrictions will result in a no fit error Enhanced amp Fast PLLs Stratix II devices provide robust clock management and synthesis using up to four enhanced PLLs and eight fast PLLs Th
81. nced PLLs 5 and 6 2 EP2S90 devices in the 1020 pin and 1508 pin packages contain 12 PLLs EP2S90 devices in the 484 pin and 780 pin packages contain fast PLLS 1 4 and enhanced PLLs 5 and 6 3 EP2S130 devices in the 1020 pin and 1508 pin packages contain 12PLLs The EP2S130 device in the 780 pin package contains fast PLLs 1 4 and enhanced PLLs 5 and 6 2 58 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Table 2 10 shows the enhanced PLL and fast PLL features in Stratix II devices Table 2 10 Stratix II PLL Features Feature Clock multiplication and division Enhanced PLL m n x post scale counter 7 Fast PLL m n x post scale counter 2 Phase shift Down to 125 ps increments 3 4 Down to 125 ps increments 3 4 Clock switchover va v 5 PLL reconfiguration Y Y Reconfigurable bandwidth va Y Spread spectrum clocking Y Programmable duty cycle Y v Number of internal clock outputs 6 4 Number of external clock outputs Three differential six single ended 6 Number of feedback clock inputs One single ended or differential 7 8 Notes to Table 2 10 1 cycle 2 3 4 For enhanced PLLs m ranges from 1 to 256 while n and post scale counters range from 1 to 512 with 50 duty For fast PLLs m and post scale counters range from 1 to 32 The n counter ranges from 1 to 4 The smallest phase
82. nd saturation control signals and accumulator synchronous loads The clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface 2 46 Altera Corporation Stratix Il Device Handbook Volume 1 May 2007 Stratix Il Architecture Altera Corporation May 2007 The LAB row source for control signals data inputs and outputs is shown in Table 2 7 Table 2 7 DSP Block Signal Sources amp Destinations LAB Row at Interface 0 Control Signals Generated clockO aclrO ena0 mult01_saturate addnsub1_round accum_round addnsub1 signa sourcea sourceb clock1 aclr1 enal accum_saturate mult01_round accum_sload sourcea sourceb mode0 Data Inputs A1 17 0 B1 17 0 A2 17 0 B2 17 0 Data Outputs OAI17 0 OB 17 0 OC 17 0 OD 17 0 clock2 aclr2 ena2 mult23_ saturate addnsub3_round accum_round addnsub3 sign_b sourcea sourceb A3 17 0 B3 17 0 OE 17 0 OF 17 0 clock3 aclr3 ena3 accum_saturate mult23_ round accum_sload sourcea sourceb mode1 A4 17 0 B4 17 0 OG 17 0 OH 17 0 See the DSP Blocks in Stratix II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information on DSP blocks 2 47 Stratix II Device Handbook Volume 1 PLLs amp Clock Networks PLLs amp Clock Netwo
83. nnects of Variable Speed amp Length Direct link interconnect from adjacent block Direct link gt interconnect to adjacent block Local Interconnect LAB Local Interconnect is Driven Column Interconnects of from Either Side by Columns amp LABs Variable Speed amp Length amp from Above by Rows 2 4 LAB Interconnects The LAB local interconnect can drive ALMs in the same LAB It is driven by column and row interconnects and ALM outputs in the same LAB Neighboring LABs M512 RAM blocks M4K RAM blocks M RAM blocks or DSP blocks from the left and right can also drive an LAB s local interconnect through the direct link connection The direct link connection feature minimizes the use of row and column interconnects providing higher performance and flexibility Each ALM can drive 24 ALMs through fast local and direct link interconnects Figure 2 3 shows the direct link connection Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 3 Direct Link Connection Direct link interconnect from Direct link interconnect from left LAB TriMatrix memory block DSP block or IOE output interconnect lt q to left Direct link right LAB TriMatrix memory block DSP block or IOE output vy gt ALMs lt _ _ gt Direct link e interconnect as to right Local Interconnect Altera Corporat
84. o Figure 2 57 DQS7T DQS6T DQS5T DQS4T Das3T Das2T pasit pDasoT PLL11 PLL5 VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4 nee Bank 3 This I O bank supports LVDS and LVPECL standards for input clock operations Differential HSTL and differential SSTL standards are supported for both input and output operations This I O bank supports LVDS and LVPECL standards for input clock operations Differential HSTL and differential SSTL standards are supported for both input and output operations Bank 8 I O banks 3 4 9 amp 11 support all single ended I O standards and differential I O standards except for HyperTransport technology for both input and output operations O banks 1 2 5 amp 6 support LVTTL LVCMOS 2 5 V 1 8 V 1 5 V SSTL 2 SSTL 18 Class HSTL 18 Class HSTL 15 Class I LVDS and HyperTransport standards for input and output operations HSTL 18 Class II HSTL 15 Class II SSTL 18 Class II standards are only supported for input operations 1 O banks 7 8 10 amp 12 support all single ended I O standards and differential I O standards except for HyperTransport technology for both input and output operations AN Bank 12 Bank 10 This I O bank supports LVDS and LVPECL standards for input clock operations Differential HSTL and differential SSTL standards are supported for both input and output operations This I O bank supports LVDS and LVPECL standards for input clock
85. o be synchronous with the same clock edge either rising or falling Figure 2 52 shows an IOE configured for DDR input Figure 2 53 shows the DDR input timing diagram Figure 2 52 Stratix II IOE in DDR Input I O Configuration Notes 1 2 3 ioe_clk 7 0 VCCIO Column Row es or Local To DQS Logic 4S PCI Clamp 4 Interconnect DQS Local Block 3 Bus 2 VCCIO Programmable 1 lt Pull Up L Resistor Input Pin to 4 y On Chip Input RegisterDelay Termination sclr spreset Bb Input Register D Q e clkin r SEREN ENA Y ce_in CLRN PRN Bus Hold aclr apreset Circuit LT L Ho Chip Wide Reset Input Register Latch D Q D Q e o gt ENA ENA CLRN PRN CLRN PRN Notes to Figure 2 52 1 All input signals to the IOE can be inverted at the IOE 2 This signal connection is only allowed on dedicated DQ function pins 3 This signal is for dedicated DQS function pins only 4 The optional PCI clamp is only available on column I O pins 2 78 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 53 Input Timing Diagram in DDR Mode tean EAIA Kae XaeXeaXne Ke KX XX CLK Input To Logic Array When using the IOE for DDR outputs the two output registers are
86. o the left LAB through direct link interconnects and eighteen can drive to the right LAB though direct link interconnects All 36 outputs can drive to R4 and C4 routing interconnects Outputs can drive right or left column routing Figures 2 29 and 2 30 show the DSP block interfaces to LAB rows Figure 2 29 DSP Block Interconnect Interface DSP Block OA 17 0 R4 C4 amp Direct gt Sane a gt R4 C4 amp Direct Link Interconnects Link Interconnects D gt A1 17 0 B1 17 0 OC 17 0 _ OD 17 0 cr Cy nor7 01 B2 17 0 OE 17 0 OF 17 0 cro ra B3 17 0 OG 17 0 _ OH 17 0 cr Cae B4 17 0 2 45 Stratix II Device Handbook Volume 1 Digital Signal Processing Block Figure 2 30 DSP Block Interface to Interconnect Direct Link Interconnect Direct Link Outputs Direct Link Interconnect C4 Interconnect from Adjacent LAB R4 Interconnect to Adjacent LABs from Adjacent LAB DSP Block LAB Row Structure LAB 12 Control 26 A 17 0 OA 17 0 3 B 17 0 OB 17 0 Row Interface Block DSP Block to 36 Inputs per Row 36 Outputs per Row LAB Row Interface Block Interconnect Region A bus of 44 control signals feeds the entire DSP block These signals include clocks asynchronous clears clock enables signed unsigned control signals addition and subtraction control signals rounding a
87. ook 2 For more information on tolerance specifications for differential on chip termination refer to the DC amp Switching Characteristics chapter in volume 1 of the Stratix II Device Handbook On Chip Series Termination Without Calibration Stratix II devices support driver impedance matching to provide the I O driver with controlled output impedance that closely matches the impedance of the transmission line As a result reflections can be significantly reduced Stratix II devices support on chip series termination for single ended I O standards with typical Rs values of 25 and 50 Q Once matching impedance is selected current drive strength is no longer selectable Table 2 17 shows the list of output standards that support on chip series termination without calibration On Chip Series Termination with Calibration Stratix II devices support on chip series termination with calibration in column I O pins in top and bottom banks There is one calibration circuit for the top I O banks and one circuit for the bottom I O banks Each on chip series termination calibration circuit compares the total impedance of each I O buffer to the external 25 or 50 Q resistors connected to the RUP and RDN pins and dynamically enables or disables the transistors until they match Calibration occurs at the end of device configuration Once the calibration circuit finds the correct impedance it powers down and stops changing the characteristics of the drivers
88. ort the voltage referenced standards such as SSTL 2 The PLL banks utilize the adjacent VREF group when voltage referenced standards are implemented For example if an SSTL input is implemented in PLL bank 10 the voltage level at VREFB7 is the reference voltage level for the SSTL input I O pins that reside in PLL banks 9 through 12 are powered by the VCC_PLL lt 5 6 11 or 12 gt _OUT pins respectively The EP2S60F484 EP2S60F780 EP2S90H484 EP2S90F780 and EP2S130F780 devices do not support PLLs 11 and 12 Therefore any I O pins that reside in bank 11 are powered by the VCCIO3 pin and any I O pins that reside in bank 12 are powered by the VCCIO8 pin Each I O bank can support multiple standards with the same Vecio for input and output pins Each bank can support one Vpgr voltage level For example when Vecio is 3 3 V a bank can support LVTTL LVCMOS and 3 3 V PCI for inputs and outputs On Chip Termination Stratix II devices provide differential for the LVDS or HyperTransport technology I O standard series and parallel on chip termination to reduce reflections and maintain signal integrity On chip termination simplifies board design by minimizing the number of external termination resistors required Termination can be placed inside the package eliminating small stubs that can still lead to reflections Stratix II devices provide four types of termination Differential termination Rp Series termination Rs without cal
89. patible with four input LUT architectures One ALM can also implement any function of up to six inputs and certain seven input functions In addition to the adaptive LUT based resources each ALM contains two programmable registers two dedicated full adders a carry chain a shared arithmetic chain and a register chain Through these dedicated resources the ALM can efficiently implement various arithmetic functions and shift registers Each ALM drives all types of interconnects local row column carry chain shared arithmetic chain register chain and direct link interconnects Figure 2 5 shows a high level block diagram of the Stratix IT ALM while Figure 2 6 shows a detailed view of all the connections in the ALM Figure 2 5 High Level Block Diagram of the Stratix Il ALM datafo dataeO dataa datab datac datad datae1 dataf1 Combinational Logic carry_in shared_arith_in reg_chain_in To general or E gt local routing adder0 N D ale To general or _ J local routing gt regO adder1 Ba D abe To general or L local routing regi To general or gt local routing M y carry_out shared_arith_out reg_chain_out Altera Corporation May 2007 2 7 Stratix II Device Handbook Volume 1 Adaptive Logic Modules Figure 2 6 Stratix II ALM Details yoauuooe U ye007 Buynos
90. peed Differential I O with DPA Support section e In Dedicated Circuitry with DPA Support section removed XSBI and changed RapidlO to Parallel RapidlO February 2004 v1 0 Added document to the Stratix II Device Handbook Altera Corporation May 2007 2 105 Stratix II Device Handbook Volume 1 Document Revision History 2 106 Altera Corporation Stratix II Device Handbook Volume 1 May 2007
91. port simple dual port and single port RAM ROM and FIFO buffers Table 2 3 shows the size and features of the different RAM blocks Table 2 3 TriMatrix Memory Features Part 1 of 2 Memory Feature spats 128x36Bis 4K x 144 Bits Maximum performance 500 MHz 550 MHz 420 MHz True dual port memory va Y Simple dual port memory Y Y v Single port memory Y Y Y Shift register va Y ROM Y v 1 FIFO buffer Y Y v Pack mode Y Y Byte enable Y Y Y Address clock enable Y Y Parity bits va v va Mixed clock mode Y Y Y Memory initialization mif z Y 2 28 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Table 2 3 TriMatrix Memory Features Part 2 of 2 Memory Feature M512 RAM Block M4K RAM Block M RAM Block y 32 x 18 Bits 128 x 36 Bits 4K x 144 Bits Simple dual port memory va Y Y mixed width support True dual port memory Y Y mixed width support Power up conditions Outputs cleared Outputs cleared Outputs unknown Register clears Output registers Output registers Output registers Mixed port read during write Unknown output old data Unknown output old data Unknown output Configurations 512 x 1 4K x 1 64K x 8 256 x 2 2K x2 64K x 9 128 x 4 1Kx 4 32K x 16 64x 8 512x8 32K x 18 64x9 512x9 16K x 32 32 x 16 256 x 16 16K x 36 32 x 18 256 x 18 8K x 64 128 x 32 8K x 72 128 x 36 4K x
92. r mode operation 2 The clock control block feeds to a multiplexer within the PLL_OUT pin s IOE The PLL_OUT pin is a dual purpose pin Therefore this multiplexer selects either an internal signal or the output of the clock control block For the global clock control block the clock source selection can be controlled either statically or dynamically The user has the option of statically selecting the clock source by using the Quartus II software to set specific configuration bits in the configuration file sof or pof or the user can control the selection dynamically by using internal logic to drive the multiplexor select inputs When selecting statically the clock source can be set to any of the inputs to the select multiplexor When selecting the clock source dynamically you can either select between two PLL outputs such as the CO or C1 outputs from one PLL between two PLLs such as the CO C1 clock output of one PLL or the C0 C1 clock output of the other PLL between two clock pins such as CLKO or CLK1 or between a combination of clock pins or PLL outputs The clock outputs from corner PLLs cannot be dynamically selected through the global control block For the regional and PLL_OUT clock control block the clock source selection can only be controlled statically using configuration bits Any of the inputs to the clock select multiplexor can be set as the clock source 2 56 Altera Corporation Stratix II Device Handbook Volu
93. r register packing 2 The dataf1 input is available for register packing only if the six input function is un registered Extended LUT Mode The extended LUT mode is used to implement a specific set of seven input functions The set must be a 2 to 1 multiplexer fed by two arbitrary five input functions sharing four inputs Figure 2 10 shows the template of supported seven input functions utilizing extended LUT mode In this mode if the seven input function is unregistered the unused eighth input is available for register packing Functions that fit into the template shown in Figure 2 10 occur naturally in designs These functions often appear in designs as if else statements in Verilog HDL or VHDL code Altera Corporation 2 13 May 2007 Stratix Il Device Handbook Volume 1 Adaptive Logic Modules Figure 2 10 Template for Supported Seven Input Functions in Extended LUT Mode dataeO datac dataa datab datad datafO datae1 dataf1 os To general or local routing comboutO D Q To general or local routing 5 Input LUT reg0 1 Note to Figure 2 10 This input is available for register packing 1 Ifthe seven input function is unregistered the unused eighth input is available for register packing The second register reg1 is not available 2 14 Arithmetic Mode The arithmetic mode is ideal for implementing adders counters acc
94. rks 2 48 Stratix Il Device Handbook Volume 1 Stratix II devices provide a hierarchical clock structure and multiple PLLs with advanced features The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution Global amp Hierarchical Clocking Stratix II devices provide 16 dedicated global clock networks and 32 regional clock networks eight per device quadrant These clocks are organized into a hierarchical clock structure that allows for up to 24 clocks per device region with low skew and delay This hierarchical clocking scheme provides up to 48 unique clock domains in Stratix II devices There are 16 dedicated clock pins CLK 15 0 to drive either the global or regional clock networks Four clock pins drive each side of the device as shown in Figures 2 31 and 2 32 Internal logic and enhanced and fast PLL outputs can also drive the global and regional clock networks Each global and regional clock has a clock control block which controls the selection of the clock source and dynamically enables disables the clock to reduce power consumption Table 2 8 shows global and regional clock features Table 2 8 Global amp Regional Clock Features quadrant Feature Global Clocks Regional Clocks Number per device 16 32 Number available per 16 8 Sources CLK pins PLL outputs or internal logic CLK
95. rovides signal slew rate control to reduce system noise and signal overshoot Altera Corporation 2 83 May 2007 Stratix Il Device Handbook Volume 1 O Structure Table 2 15 shows the possible settings for the I O standards with drive strength control Table 2 15 Programmable Drive Strength Note 1 lon lo Current Strength lo lo Current Strength 1 0 Standard Setting mA for Column Setting mA for Row 1 0 1 0 Pins Pins 3 3 V LVTTL 24 20 16 12 8 4 12 8 4 3 3 V LVCMOS 24 20 16 12 8 4 8 4 2 5 V LVTTL LVCMOS 16 12 8 4 12 8 4 1 8 V LVTTL LVCMOS 12 10 8 6 4 2 8 6 4 2 1 5 V LVCMOS 8 6 4 2 4 2 SSTL 2 Class 12 8 12 8 SSTL 2 Class II 24 20 16 16 SSTL 18 Class 12 10 8 6 4 10 8 6 4 SSTL 18 Class II 20 18 16 8 HSTL 18 Class 12 10 8 6 4 12 10 8 6 4 HSTL 18 Class II 20 18 16 HSTL 15 Class 12 10 8 6 4 8 6 4 HSTL 15 Class II 20 18 16 Note to Table 2 15 1 The Quartus II software default current setting is the maximum setting for each I O standard Open Drain Output Stratix II devices provide an optional open drain equivalent to an open collector output for each I O pin This open drain output enables the device to provide system level control signals e g interrupt and write enable signals that can be asserted by any of several devices Bus Hold Each Stratix II device I O pin provides an option
96. ructure Figure 2 47 Row I O Block Connection to the Interconnect Note 1 R4 amp R24 Interconnects t C4 Interconnect 1 0 Block Local Interconnect 32 Data amp Control Signals from Logic Array 1 iB 32 Pa Horizontal I O Block io_dataina 3 0 io_datainb 3 0 l Direct Link ee ak t Interconnect to Adjacent LAB to Adjacent LAB Horizontal 10 io_clk 7 0 Block Contains LAB Local up to Four IOEs Interconnect Note to Figure 2 47 1 The 32 data and control signals consist of eight data out lines four lines each for DDR applications io_dataouta 3 0 and io_dataoutb 3 0 four output enables io_oe 3 0 four input clock enables io_ce_in 3 0 four output clock enables io_ce_out 3 0 fourclocks io_clk 3 0 four asynchronous clear and preset signals io_aclr apreset 3 0 and four synchronous clear and preset signals io_sclr spreset 3 0 2 72 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 48 Column I O Block Connection to the Interconnect Note 1 32 Data amp Control Signals Vertical 1 0 from Logic Array 1 Vertical I O Block le Block Contains up to Four IOEs 32 0_dataina 3 0 io_clk 7 0 0_datainb 3 0 1 0 Block Local Interconnect R4 amp R24 Interconnects e e a y y a a L
97. sign enables this 2 counter then the device can use a VCO frequency range of 150 to 520 MHz 2 See the PLLs in Stratix II amp Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information on enhanced and fast PLLs See High Speed Differential I O with DPA Support on page 2 96 for more information on high speed differential I O support 0 Structure The Stratix II IOEs provide many features including Dedicated differential and single ended I O buffers 3 3 V 64 bit 66 MHz PCI compliance 3 3 V 64 bit 133 MHz PCI X 1 0 compliance Joint Test Action Group JTAG boundary scan test BST support On chip driver series termination On chip parallel termination On chip termination for differential standards Programmable pull up during configuration Altera Corporation 2 69 May 2007 Stratix Il Device Handbook Volume 1 V O Structure 2 70 Output drive strength control Tri state buffers Bus hold circuitry Programmable pull up resistors Programmable input and output delays Open drain outputs DQ and DQS I O pins Double data rate DDR registers The IOE in Stratix II devices contains a bidirectional I O buffer six registers and a latch for a complete embedded bidirectional single data rate or DDR transfer Figure 2 46 shows the Stratix II IOE structure The IOE contains two input registers plus a latch two output registers and two outpu
98. t enable registers The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs Additionally the design can use the output enable OE register for fast clock to output enable timing The negative edge clocked OE register is used for DDR SDRAM interfacing The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 46 Stratix II IOE Structure Logic Array OE Register OE gt D Q ps OE Register E Y Output CLK l l Output Register l C Output Input Register i D ao Input A lt Input B lt Input Register Input Latch The IOEs are located in I O blocks around the periphery of the Stratix II device There are up to four IOEs per row I O block and four IOEs per column I O block The row I O blocks drive row column or direct link interconnects The column I O blocks drive column interconnects Figure 2 47 shows how a row I O block connects to the logic array Figure 2 48 shows how a column I O block connects to the logic array Altera Corporation 2 71 May 2007 Stratix II Device Handbook Volume 1 I O St
99. tiTrack Interconnect Altera Corporation 2 43 May 2007 Stratix Il Device Handbook Volume 1 Digital Signal Processing Block Modes of Operation The adder subtractor and accumulate functions of a DSP block have four modes of operation Simple multiplier Multiply accumulator Two multipliers adder Four multipliers adder Table 2 6 shows the different number of multipliers possible in each DSP block mode according to size These modes allow the DSP blocks to implement numerous applications for DSP including FFTs complex FIR FIR and 2D FIR filters equalizers IIR correlators matrix multiplication and many other functions The DSP blocks also support mixed modes and mixed multiplier sizes in the same block For example half of one DSP block can implement one 18 x 18 bit multiplier in multiply accumulator mode while the other half of the DSP block implements four 9 x 9 bit multipliers in simple multiplier mode Table 2 6 Multiplier Size amp Configurations per DSP Block DSP Block Mode Multiplier 9x9 18 x 18 36 x 36 Four multipliers with four One multiplier with one product outputs product output Eight multipliers with eight product outputs Multiply accumulator Two 52 bit multiply accumulate blocks Two multipliers adder Four two multiplier adder Two two multiplier adder two 9 x 9 complex one 18 x 18 complex multiply multiply Four multipliers adder Two fo
100. tion requires one common input either dataa or datab In the case of implementing two six input functions in one ALM four inputs must be shared and the combinational function must be the same For example a 4 x 2 crossbar switch two 4 to 1 multiplexers with common inputs and unique select lines can be implemented in one ALM as shown in Figure 2 8 The shared inputs are dataa datab datac and datad while the unique select lines are dataeO and datafo for functiono and datael and datafil for function1 This crossbar switch consumes four LUTs in a four input LUT based architecture Figure 2 8 4 x 2 Crossbar Switch Example 4 x 2 Crossbar Switch Implementation in 1 ALM selO 1 0 datafo inputa dataeO inputb Six Input L outo a LUT comboutO j f inputc hg P datac e FunctionO inputd datad outi sel1 1 0 oT Six Input LUT combout1 datae1 Function1 dataf1 2 12 Ina sparsely used device functions that could be placed into one ALM may be implemented in separate ALMs The Quartus II Compiler spreads a design out to achieve the best possible performance As a device begins to fill up the Quartus II software automatically utilizes the full potential of the Stratix II ALM The Quartus IT Compiler automatically searches for functions of common inputs or completely independent func
101. tions to be placed into one ALM and to make efficient use of the device resources In addition you can manually control resource usage by setting location assignments Any six input function can be implemented utilizing inputs dataa datab datac datad and either datae0 and datafoO or datael and dataf1 If dataeo and dataf0 are utilized the output is driven to register0 and or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers see Figure 2 9 If Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture datael and dataf1 are utilized the output drives to register1 and or bypasses register1 and drives to the interconnect using the bottom set of output drivers The Quartus II Compiler automatically selects the inputs to the LUT Asynchronous load data for the register comes from the datae or dataf input of the ALM ALMs in normal mode support register packing Figure 2 9 6 Input Function in Normal Mode Notes 1 2 To general or datafo gt dataeO local routing dataa 6 Input datab LUT N D Q gt To general or datac n gt local routing datad reg0 datae1 dataf1 1 T 2 D Q p TO general or b local routing These inputs are available for register packing reg1 Notes to Figure 2 9 1 Ifdatae1 and dataf1 are used as inputs to the six input function then datae0 and dataf0 are available fo
102. tput performance The OE register can be used for fast clock to output enable timing The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB dedicated I O clocks and the column and row interconnects Altera Corporation 2 75 May 2007 Stratix Il Device Handbook Volume 1 1 0 Structure Figure 2 51 shows the IOE in bidirectional configuration Figure 2 51 Stratix II IOE in Bidirectional 1 0 Configuration Note 1 ioe_clk 7 0 Column Row or Local Interconnect oe OE Register D Q clkout gt BREN OE Register ce_out tco Delay aclr apreset _ m Chip Wide Reset Output Register Veco PGI Clamp 2 Vecio Programmable lt Pull Up Resistor He Output et LV sclr spreset D Q ENA CLRN PRN 4 5 Pin Delay Drive Strength Control Open Drain Output Input Pin to r Logic Array Delay Ly Input Pin to 3 On Chip o Termination eo eeM y A Bus Hold clkin D Q ce_in nput Register Input Register Delay Notes to Figure 2 51 1 All input signals to the IOE can be inverted at the IOE 2 The option
103. umulators wide parity functions and comparators An ALM in arithmetic mode uses two sets of two four input LUTs along with two dedicated full adders The dedicated adders allow the LUTs to be available to perform pre adder logic therefore each adder can add the output of two four input functions The four LUTs share the dataa and datab inputs As shown in Figure 2 11 the carry in signal feeds to adder0 and the carry out from adder0 feeds to carry in of adder1 The carry out from adder1 drives to adder0 of the next ALM in the LAB ALMs in arithmetic mode can drive out registered and or unregistered versions of the adder outputs Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 11 ALM in Arithmetic Mode carry_in datae0 adder0 4 Input To general or LUT local routing To general or D gt i local routing datafO gt datac 4 Input regO datab e LUT dataa ____ 9 eo adder 4 Input To general or datad LUT local routing datae1 mn ar To general or N local routing 4 Input regi LUT dataf1 carry_out While operating in arithmetic mode the ALM can support simultaneous use of the adder s carry output along with combinational logic outputs In this operation the adder output is ignored This usage of the adder with the combinational logic output provides reso
104. ur multiplier adder One four multiplier adder 2 44 Stratix Il Device Handbook Volume 1 DSP Block Interface Stratix II device DSP block input registers can generate a shift register that can cascade down in the same DSP block column Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains You can cascade registers within multiple DSP blocks for 9 x 9 or 18 x 18 bit FIR filters larger than four taps with additional adder stages implemented in ALMs If the DSP block is configured as 36 x 36 bits the adder subtractor or accumulator stages are implemented in ALMs Each DSP block can route the shift register chain out of the block to cascade multiple columns of DSP blocks Altera Corporation May 2007 Stratix Il Architecture Altera Corporation May 2007 The DSP block is divided into four block units that interface with four LAB rows on the left and right Each block unit can be considered one complete 18 x 18 bit multiplier with 36 inputs and 36 outputs A local interconnect region is associated with each DSP block Like an LAB this interconnect region can be fed with 16 direct link interconnects from the LAB to the left or right of the DSP block in the same row R4 and C4 routing resources can access the DSP block s local interconnect region The outputs also work similarly to LAB outputs as well Eighteen outputs from the DSP block can drive t
105. urce savings of up to 50 for functions that can use this ability An example of such functionality is a conditional operation such as the one shown in Figure 2 12 The equation for this example is R X lt Y Y X To implement this function the adder is used to subtract Y from X If X is less than Y the carry_out signal is 1 The carry_out signal is fed to an adder where it drives out to the LAB local interconnect It then feeds to the LAB wide syncload signal When asserted syncload selects the syncdata input In this case the data Y drives the syncdata inputs to the registers If X is greater than or equal to Y the syncload signal is de asserted and X drives the data port of the registers Altera Corporation 2 15 May 2007 Stratix Il Device Handbook Volume 1 Adaptive Logic Modules Figure 2 12 Conditional Operation Example Adder output is not used E DA A Xo Comb amp jo i Adder a e RIO To general or Y 0 Logic i local routing regO syncdata syncload i X 1 Comb amp xi i i Adder E R RI a To general or Y 1 TT Logic T N i local routing regi Carry Chain syncload x 2 4 Comb amp ra l l Adder B R 2 p To general or Y 2 T N i local routing regO i syncload Comb amp i To local routing amp Adder carry_o
106. ut then to LAB wide Logic syncload The arithmetic mode also offers clock enable counter enable synchronous up down control add subtract control synchronous clear synchronous load The LAB local interconnect data inputs generate the clock enable counter enable synchronous up down and add subtract control signals These control signals are good candidates for the inputs that are shared between the four LUTs in the ALM The synchronous clear and synchronous load options are LAB wide signals that affect all registers in the LAB The Quartus II software automatically places any registers that are not used by the counter into other LABs Carry Chain The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode Carry chains can begin in either the first ALM or the fifth ALM in an LAB The final carry out signal is routed to an ALM where it is fed to local row or column interconnects 2 16 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture The Quartus II Compiler automatically creates carry chain logic during design processing or you can create it manually during design entry Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions The Quartus II Compiler creates carry chains longer than 16 8 ALMs in arithmetic or shared arithmetic mode by linking LABs together
107. ut to feed back into the LUT of the same ALM so that the register is packed with its own fan out LUT This provides another mechanism for improved fitting The ALM can also drive out registered and unregistered versions of the LUT or adder output See the Performance amp Logic Efficiency Analysis of Stratix II Devices White Paper for more information on the efficiencies of the Stratix II ALM and comparisons with previous architectures ALM Operating Modes The Stratix II ALM can operate in one of the following modes E Normal mode m Extended LUT mode E Arithmetic mode Shared arithmetic mode Each mode uses ALM resources differently In each mode eleven available inputs to the ALM the eight data inputs from the LAB local interconnect carry in from the previous ALM or LAB the shared arithmetic chain connection from the previous ALM or LAB and the register chain connection are directed to different destinations to implement the desired logic function LAB wide signals provide clock asynchronous clear asynchronous preset load synchronous clear 2 9 Stratix II Device Handbook Volume 1 Adaptive Logic Modules 2 10 synchronous load and clock enable control for the register These LAB wide signals are available in all ALM modes See the LAB Control Signals section for more information on the LAB wide control signals The Quartus II software and supported third party synthesis tools in conjunction with parameter
108. w Clocks Interconnect Region 2 34 M RAM Block The largest TriMatrix memory block the M RAM block is useful for applications where a large volume of data must be stored on chip Each block contains 589 824 RAM bits including parity bits The M RAM block can be configured in the following modes True dual port RAM Simple dual port RAM Single port RAM FIFO You cannot use an initialization file to initialize the contents of an M RAM block All M RAM block contents power up to an undefined value Only synchronous operation is supported in the M RAM block so all inputs are registered Output registers can be bypassed Altera Corporation Stratix Il Device Handbook Volume 1 May 2007 Stratix Il Architecture Similar to all RAM blocks M RAM blocks can have different clocks on their inputs and outputs Either of the two clocks feeding the block can clock M RAM block registers renwe address byte enable datain and output registers The output register can be bypassed The six labclk signals or local interconnect can drive the control signals for the A and B ports of the M RAM block ALMs can also control the clock_a clock_b renwe_a renwe_b clr_a clr_b clocken_a and clocken_b signals as shown in Figure 2 23 Figure 2 23 M RAM Block Control Signals Dedicated Row LAB Clocks 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect
109. ymmetrically drive the RCLK networks in a particular quadrant as shown in Figure 2 32 2 49 Altera Corporation Stratix Il Device Handbook Volume 1 May 2007 PLLs amp Clock Networks Figure 2 32 Regional Clocks RCLK 31 28 RCLK 27 24 CLK 15 12 RCLK 3 0 RCLK 23 20 CLK 3 0 CLK 11 8 RCLK 7 4 l RCLK 19 16 CLK 7 4 Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins PLLs or Core Logic within that Quadrant RCLK 11 8 RCLK 15 12 Dual Regional Clock Network A single source CLK pin or PLL output can generate a dual regional clock by driving two regional clock network lines in adjacent quadrants one from each quadrant This allows logic that spans multiple quadrants to utilize the same low skew clock The routing of this clock signal on an entire side has approximately the same speed but slightly higher clock skew when compared with a clock signal that drives a single quadrant Internal logic array routing can also drive a dual regional clock Clock pins and enhanced PLL outputs on the top and bottom can drive horizontal dual regional clocks Clock pins and fast PLL outputs on the left and right can drive vertical dual regional clocks as shown in Figure 2 33 Corner PLLs cannot drive dual regional clocks 2 50 Altera Corporation Stratix II Device Handbook Volume 1 May 2007 Stratix Il Architecture Figure 2 33 Dual Re
110. yur 49811p 3 ULIN OD MOH Bugnoa yur 2011p lt lo zhio ov L108 yno ureyo Bas yno Aueo yno ye pareys Heyep 3 UWIN OD MOH p uuou u e207 Buynos yu 49811p 3 ULUNIOD MOH Buynos yul jesIp lt 3 ULUNJOO MOY Leeyep r l 994 kal LL 4m 1 induy e pea L ai im a H D duj T hd e Liew a L a Zi peep L MVINYa 5 yL lt lt im _ yndu y E L_ Lt qap L a L 1m al He p L e andui eejep S C l NYTO im Ne aa j lt ynduj M ae 4 viva eo a L A PMPP viNud be N ke H a int indur y me ee oaeiep ce gyerep o zjeue peojouAs ur Aurea peojousse apos ur_ureyo Bar uye pareys yOSUUOTI9 U e207 2 uuo2134U e207 JSUUOIE U je007 yO UU0N 9 u 12207 2 uu0913 U e207 yOSUUOTI9 U e207 19 uuo0019 4U e207 O9UUOTI9 U 12207 May 2007 Altera Corporation Stratix II Device Handbook Volu

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