FAIRCHILD 74VHCT04A handbook
Contents
1. ASHS8AUT X H VVOLOHAPZ Physical Dimensions Continued 5 0 0 1 0 43 TYP Li INE O on TU ame JUN PIN 1 IDENT 7 45 LAND PATTERN RECOMMENDATION 6 10 ALL LEAD TIPS 045 S SEE DETAIL A PURE AIO reso es SS E i ier a 7 0 65 0 19 0 30 0 130 A BO CO 12 00 TOP amp BOTTOM R0 09 min NOTES A CONFORMS TO JEDEC REGISTRATION MO 153 VARIATION AB REF NOTE 6 1 00 B DIMENSIONS ARE IN MILLIMETERS DETAIL A C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D DIMENSIONING AND TOLERANCES PER ANSI Y14 5M 1982 E LANDPATTERN STANDARD SOP65P640X110 14M F DRAWING FILE NAME MTC14REV6 SEATING PLANE R0 09min Figure 3 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision andlor date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http www fairchildsemi com lpackaging 1997 Fairchild Semiconductor Corporation www fairchildsemi com T4AVHC2. FAIRCHILD EE SEMICONDUCTOR 74VHCTO4A Hex Inverter Features E High speed tpp 4 7ns Typ at Ta 25 C E High noise immunity Vip 2 0V V 0 8V m Power down protection is provided on all inputs and outputs E Low noise Vo p 1 0V Max E Low power dissipation lcc 2HA Max Ta 25 C E Pin and function compatible with 74HCT04 Ordering Information Package Number Package Description M14A 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow Order Number 74VHCTO4AM 74VHCTO4ASJ TAVHCTO4AMTC December 2007 General Description The VHCTO4A is an advanced high speed CMOS Inverter fabricated with silicon gate CMOS technology It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation The internal circuit is composed of 3 stages including buffer output which provide high noise immunity and stable output Protection circuits ensure that OV to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with Vcc OV These circuits prevent device destruction due to mismatched supply and input output voltages This device can be used to interface 3V to 5V systems and two supply systems such as battery backup M14D 14 Lead Small Outline Package SOP EIAJ TYPE Il 5 3mm Wide MTC14 14 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide D
3. Average operating current can be obtained from the equation loc Opr Cpp Vec fin lec 6 per gate 1997 Fairchild Semiconductor Corporation www fairchildsemi com T4VHCTO4A Rev 1 4 0 4 ASHS8AUT X H VVOLOHAPZ Physical Dimensions ST DUDDUUL 5 60 4 00 3 80 PIN ONE B pi ee a 0 51 INDICATOR 0 35 LAND PATTERN RECOMMENDATION 610 25 c B A 0 34 Ea c B a 1 75 MAX l 0 25 0 25 eei 0 19 SLT NOTES UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC 0 50 MS 012 VARIATION AB ISSUE C 0 36 B ALL DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D LANDPATTERN STANDARD SOIC127P600X145 14M ASHS8AUT X H YYOLOHAYZ E DRAWING CONFORMS TO ASME Y14 5M 1994 F DRAWING FILE NAME M14AREV13 SEATING PLANE DETAIL A SCALE 20 1 Figure 1 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the mo
4. ION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support which a are intended for surgical implant into the body or device or system whose failure to perform can be b support or sustain life and c whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system or to affect its safety or effectiveness provided in the labeling can be reasonably expected to result in a significant injury of the user PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition This datasheet contains the design specifications for product Advance Information Formative or In Design development Specifications may change in any manner without notice This da
5. Input Voltage OV OTS OV Vout Output Voltage Note 2 OV to Vec Note 3 OV to 5 5V LE Input Rise and Fall Time Vcc 5 0V 0 5V Ons V 20ns V Notes 1 HIGH or LOW state lour absolute maximum rating must be observed 2 Vec OV 3 VouT lt GND VOUT gt Vec Outputs Active 4 Unused inputs must be held HIGH or LOW They may not float 1997 Fairchild Semiconductor Corporation www fairchildsemi com T4AVHCTO4A Rev 1 4 0 3 ASHS8AUT X H VVOLOHAPZ DC Electrical Characteristics Ta 40 C to 85 C Symbol Parameter Vec V Conditions Voltage Vi LOW Level Input LOW Level Output Vin Vin lo 50uA 00 o1 o Input Leakage 0 5 5 Vin 5 5V or GND tO 1 0 UA Current Quiescent Supply 9 5 Vin Vcc or GND 2 0 20 0 UA Current Maximum Icc Input 5 5 Vin 3 4V Other 1 35 1 50 mA Inputs Vec or GND a CRT Noise Characteristics Current Power Ta 25 C Symbol Parameter Conditions Vcc V Down State Minimum HIGH Level Dynamic Input Voltage C_ 50pF 5 0 20 v Maximum LOW Level Dynamic Input Voltage C 50pF 50 08 V Note 5 Parameter guaranteed by design AC Electrical Characteristics Ta 40 C to 85 C Propagation Delay g0 OS Cy AIS RE Input Capacitance Cpp Power Dissipation 6 Capacitance Note 6 Cpp Is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load
6. TO4A Rev 1 4 0 7 ASHS8AUT X H YYOLOHAYZ NOPE tax Sete FAIRCHILD EEE SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such trademarks ACEx FPSTM PDP SPM SyncFET Build it Now FRFET Power220 SYSTEM CorePLUS Global Power Resource Power247 Th naar ai chise CROSSVOLT Green FPS POWEREDGE CTLM Green FPS e Series Power SPM Ps Current Transfer Logic GTO PowerTrench TinyBoost EcoSPARK i Lo Programmable Active Droop TinyBuck EZSWITCH intelli MAX QFET TinyLogic ETI ISOPLANAR QS TINYOPTO MegaBuck QT Optoelectronics TinyPower f MICROCOUPLER Quiet Series TinyPWM Fairchild MicroFET RapidConfigure TinyWire Fairchild Semiconductor MicroPak SMART START uSerDes FACT Quiet Series MillerDrive SPM UHC FACT Motion SPM STEALTH Ultra FRFET FAST OPTOLOGIC SuperFET ee FastvCore OPTOPLANAR SuperSOT 3 vox FlashWriter g SuperSOT 6 SuperSOT 8 EZSWITCH and FlashWriter are trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCT
7. evice also available in Tape and Reel Specify by appending suffix letter X to the ordering number OIN packages are lead free per JEDEC J STD 020B standard 1997 Fairchild Semiconductor Corporation 74VHCTO4A Rev 1 4 0 www fairchildsemi com ASHS8AUT X H YYOLOHAYZ Logic Symbol Connection Diagram 1997 Fairchild Semiconductor Corporation T4AVHCTO4A Rev 1 4 0 www fairchildsemi com ASHS8AUT X H YYOLOHAYZ Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended In addition extended exposure to stresses above the recommended operating conditions may affect device reliability The absolute maximum ratings are stress ratings only Parameter Rating Supply Voltage 0 5V to 7 0V DC Input Voltage 0 5V to 7 0V DC Output Voltage Note 1 0 5V to Vcc 0 5V 0 5V to 7 0V Storage Temperature 65 C to 150 C Lead Temperature Soldering 10 seconds 260 C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications Fairchild does not recommend exceeding them or designing to absolute maximum ratings Supply Voltage 4 5V to 5 5V
8. st recent package drawings http www fairchildsemi com packaging 1997 Fairchild Semiconductor Corporation www fairchildsemi com T4VHCTO4A Rev 1 4 0 5 Physical Dimensions Continued 6 7 2 13 TYP ALL LEAD TIPS i j O o 2 c e a 7 ALL LEAD TIPS D a M 1 27 TYP 0 6 TYP LAND PATTERN RECOMMENDATION PIN 1 IDENT SEE DETAIL A 1 8 0 1 0 15 0 05 0 15 0 25 DIMENSIONS ARE IN MILLIMETERS GAGE PLANE NOTES 0 8 0 25 A CONFORMS TO EIAJ EDR 7320 REGISTRATION ESTABLISHED IN DECEMBER 1998 B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS 0 60 0 15 SEATING PLANE DETAIL A M14DREVC Figure 2 14 Lead Small Outline Package SOP EIAJ TYPE Il 5 3mm Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings htto www fairchildsemi com packaging 1997 Fairchild Semiconductor Corporation www fairchildsemi com T4AVHCTO4A Rev 1 4 0 6
9. tasheet contains preliminary data supplementary data will be Preliminary First Production published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design This datasheet contains final specifications Fairchild Semiconductor No Identification Needed Full Production reserves the right to make changes at any time without notice to improve the design This datasheet contains specifications on a product that has been Obsolete Not In Production discontinued by Fairchild Semiconductor The datasheet is printed for reference information only Rev 132 1997 Fairchild Semiconductor Corporation www fairchildsemi com T4AVHCTO4A Rev 1 4 0 8 ASHS8AUT X H VVOLOHAPZ
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FAIRCHILD 74VHCT04A handbook