TEXAS INSTRUMENTS CDCU877 CDCU877A handbook
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1. 4204967 C 11 04 NOTES A All linear dimensions are in millimeters Dimensioning and tolerancing per ASME Y14 5M 1994 A The package thermal pad must be soldered to the board for uo b c thermal and mechanical performance See the Product Data B This drawing is subject to change without notice Sheet for detail ding th dh I bad di A C QFN Quad Flatpack No Lead Package configuration Set LOT CELA SEG Orang the expose T AU sions 3 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TTS terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or custome2. CDCUS8 1 E NES CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 1 8 V Phase Lock Loop Clock Driver for External Feedback Pins FBIN FBIN are Double Data Rate DDR Il Applications Used to Synchronize the Outputs to the Spread Spectrum Clock Compatible Input Clocks Operating Frequency 10 MHz to 400 MHz Single Ended Input and Single Ended E IE e p JESD82 8 PLL Standard Low Jitter Cycle Cycle 30 ps for PC2 3200 4300 Low Output Skew 35 ps Fail Safe Inputs Low Period Jitter 20 ps Low Dynamic Phase Offset 15 ps Low Static Phase Offset 50 ps Distributes One Differential Clock Input to Ten Differential Outputs 6 52 Ball uBGA MicroStar Junior BGA 0 65 mm pitch and 40 Pin MLF description The CDCU877 is a high performance low jitter low skew zero delay buffer that distributes a differential clock input pair CK CK to ten differential pairs of clock outputs Yn Yn and to one differential pair of feedback clock outputs FBOUT FBOUT The clock outputs are controlled by the input clocks CK CK the feedback clocks FBIN FBIN the LVCMOS control pins OE OS and the analog power input AVpp When OE is low the clock outputs except FBOUT FBOUT are disabled while the internal PLL continues to maintain its locked in frequency OS output select is a program pin that must be tied to GND or Vpp When OS is high OE functions a
3. 52 1000 None Call TI Level 3 235C 168 HR CDCU877AGQLT ACTIVE VFBGA GQL 52 250 None Call TI Level 3 235C 168 HR CDCU877ARTBR ACTIVE QFN RTB 40 2500 None CU SNPB Level 3 235C 168 HR CDCU877ARTBT ACTIVE QFN RTB 40 250 None CU SNPB Level 3 235C 168 HR CDCU877AZQLR ACTIVE VFBGA ZQL 52 1000 Green RoHS amp SNAGCU Level 2 260C 1 YEAR no Sb Br CDCU877AZQLT ACTIVE VFBGA ZQL 52 250 Green ROHS amp SNAGCU Level 2 260C 1 YEAR no Sb Br CDCU877GQLR ACTIVE VFBGA GQL 52 1000 None Call TI Level 3 235C 168 HR CDCU877GQLT ACTIVE VFBGA GQL 52 250 None Call TI Level 3 235C 168 HR CDCU877RTBR ACTIVE QFN RTB 40 2500 None CU SNPB Level 3 235C 168 HR CDCU877RTBT ACTIVE QFN RTB 40 250 None CU SNPB Level 3 235C 168 HR CDCU877ZQLR ACTIVE VFBGA ZQL 52 1000 Green RoHS amp SNAGCU Level 2 260C 1 YEAR no Sb Br CDCU877ZQLT ACTIVE VFBGA ZQL 52 250 ae amp SNAGCU Level 2 260C 1 YEAR no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan May not be currently available
4. A4 B6 C6 35 32 30 18 17 K6 K5 Table 2 Function Table INPUTS OUTPUTS EEN EE NR Lz JE Bypassed Z Z 1 8 V Nominal L L H L Lz E H L On i Y7 Active Y7 Active px ot L SN e ovna e x ee e e 9 mme x x 1 x w e fe uw 9 c x xo3c Due o mee d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 LD or OE Control and Test Logic The Logic Detect LD powers down the device when a logic low is applied to both CK and a wd TII pr a Figure 1 Logic Diagram Positive Logic d TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage range VppQ OF AVDD uexadducek eaae aie a een OR OR Ore es aea 0 5 V to 2 5 V Input voltage range Vj see Notes 1 and 21 0 5 V to Vppq 0 5 V Output voltage range Vo see Notes 1 and 2 0 5 V to Vppq 0 5 V Input clamp current le Vj amp 0O or Vi VppQ ssse RR III 50 mA Output clamp voltage lox Vo 0 or Vo VDDQ 650699 0 0 R eee RA 50 mA Continuous output current lo Vo OtO Vp 26 5 59 0 TAR 49 00 R TEA EE III 50 mA Continuous current through each See OF GND 244 vado
5. Vi VDD or GND 1 8 V 0 25 E Giaj Change in input current FBIN FBIN Vi Vpp or GND 1 8 V 025 P NOTES 1 Vopis the magnitude of the difference between the true and complimentary outputs See Figure 9 for a definition 2 Total IDD IppQ lADD 7 cK xCPD xX VDDQ solving for Cpp Ippo lapD ftc x VDDQ where fc is the input frequency VDDQ is the power supply and Cpp is the power dissipation capacitance timing requirements over recommended operating free air temperature range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fc Clock frequency operating see Notes 1 and 2 AVDD Vpp 1 8 V 0 1 V 10 400 MHz fCK Clock frequency application see Notes 1 and 3 AVDD Vpp 1 8 V 0 1 V 160 340 MHz tDC Duty cycle input clock AVDD Vpp 1 8 V 0 1 V 40 60 tL Stabilization time see Note 4 AVpp Vpp 1 8 V 0 1 V 12 us NOTES 1 The PLL must be able to handle spread spectrum induced skew 2 Operating clock frequency indicates a range over which the PLL must be able to lock but in which it is not required to meet the other timing parameters used for low speed system debug 3 Application clock frequency indicates a range over which the PLL must meet all timing parameters 4 Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up During normal operation the stabilization time is also
6. at 100 MHz d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to a ground plane or special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For information on the Quad Flatpack No Lead QFN package and its advantages refer to Application Report Quad Flatpack No Lead Packages Texas Instruments Literature No SCBA017 This document is available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration Bottom View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 13 K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 18 Feb 2005 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Di Type Drawing Qty CDCU877AGQLR ACTIVE VFBGA GQL
7. cates ho eC nei eR ena 100 mA Storage temperature range Deis ETH 65 C to 150 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 The input and output voltage ratings may be exceeded if the input and output clamp current ratings are observed 2 This value is limited to 2 5 V maximum recommended operating conditions MIN NOM MAX UNIT VDDQ Output supply voltage 1 7 1 8 1 9 V AVpp Supply voltage See Note 1 VDDQ VIL Low level input voltage see Note 2 OE OS 0 35 x VDDQ V Vu High level input voltage see Note 2 CK CK 0 65 x VppQ V loH High level output current see Figure 2 9 mA loL Low level output current see Figure 2 9 mA VIX Input differential pair cross voltage VppQo 2 0 15 VppQ 2 0 15 V VI Input voltage level 0 3 VDDQ 0 3 V VID Input differential voltage DC 0 3 VpDDQ 0 4 V see Note 2 and Figure 9 AC 0 6 VppQ 04 V TA Operating free air temperature 40 85 C NOTES 1 The PLL is turned off and bypassed for test purposes when AVpp is grounded During this test mode Vppq remains within the recommended operat
8. ns skew rates are shown as a recommended target Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application 6 Output differential pair cross voltage specified at the DRAM clock input or the test load 7 Vox of CDCU877A is on average 30 mV lower than that of CDCU877 for the same application 8 This parameter is assured by design and characterization d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 d GND C 10pF C 1pF Note V GND GND Figure 2 Output Load Test Circuit 1 Vop 2 C 10pF V 2 R 10Q Z 500Q R 10Q Z 500 Note V GND Vop 2 Figure 3 Output Load Test Circuit 2 Yx FBOUT Yx FBOUT t t cycle n cycle n 1 d W lade n Lee n 1 Figure 4 Cycle To Cycle Period Jitter d TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 L N N is a large number of samples N gt 1000 samples Figure 5 Static Phase Offset DX X X Yx l Yx FBOUT Yx FBOUT Figure 6 Output Skew d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUN
9. the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state enter the power down mode and later return to active operation CK and CK may be left floating after they have been driven low for one complete clock cycle d TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 switching characteristics over recommended operating free air temperature range unless otherwise noted see Note 1 AVpp Vpp 1 8 V 0 1 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ten Enable time OE to any Y Y See Figure 11 8 ns tdis Disable time OE to any Y Y See Figure 11 8 ns tiit cc f 0 40 Cycle to cycle period jitter see Note 8 160 MHz to 190 MHz see Figure 4 ps tjit cc 0 40 tiit cc ae 0 30 Cycle to cycle period jitter see Note 8 190 MHz to 340 MHz see Figure 4 ps tjit cc 0 30 tio Static phase offset time see Note 2 See Figure 5 50 50 ps Lutgen Dynamic phase offset time See Figure 10 15 15 ps isk o Output clock skew See Figure 6 35 ps Periodi ii 160 MHz to 190 MHz see Figure 7 30 30 ps Tipe Period jitter see Notes 9 and 6 190 MHz to 340 MHz see Figure 7 20 20 ps 160 MHz to 190 MHz see Figure 8 115 11
10. 5 ps S coinell N d 190 MHz to 250 MHz see Figure 8 70 70 ps Wiper Halt period jitter see Notes cS and 8 250 MHz to 300 MHz see Figure 8 40 40 ps 300 MHz to 340 MHz see Figure 8 60 60 ps Slew rate OE See Figure 3 and Figure 9 0 5 V ns SR Input clock skew rate See Figure 3 and Figure 9 1 2 5 4 Vins Output clock slew rate see Notes 4 and 5 See Figure 3 and Figure 9 1 5 2 5 3 Vins See Figure 2 CDCU877 VDDQ WER V Output differential pair cross voltage V OX see Note 6 See Figure 2 CDCU877A see Note 7 Vbpo 2 Vppq2 0 85 C 0 1 0 1 SSC modulation frequency 30 33 kHz SSC clock input frequency deviation 096 0 5 PLL loop bandwidth 2 MHz NOTES 1 There are two different terminations that are used with the following tests The load board in Figure 2 is used to measure the input and output differential pair cross voltage only The load board in Figure 3 is used to measure all other tests For consistency equal length cables must be used 2 Phase static offset time does not include jitter 3 Period jitter half period jitter specifications are separate specifications that must be met independently of each other 4 The output slew rate is determined from the IBIS model into the load shown in Figure 3 5 To eliminate the impact of input slew rates on static phase offset the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal The 2 5 V
11. E 2003 REVISED JANUARY 2004 Yx FBOUT Yx FBOUT Lien Yx FBOUT Yx FBOUT RE fo 1 L f pen jit per cyden fo fo average input frequency measured at CK CK Figure 7 Period Jitter Yx FBOUT Yx FBOUT f f half peroid n half peroid n 1 1 f z f m 5 L jit hper alf period n 2 T nsn inl ids f average input frequency measured at CK CK Figure 8 Half Period Jitter d TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 Clock Inputs 2076 and Outputs OE Vso V20 2 Vao V20 SIM jo SIT o Luet bilo Figure 9 Input and Output Slew Rates FBIN 50 VDD 50 VDD Figure 11 Time Delay Between OE and Clock Output Y Y Y d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 RECOMMENDED AVpp FILTERING CARD pn VIA AV Vopa GND C CARD AGND VIA See Notes 9 10 and 11 Figure 12 Recommended AVpp Filtering NOTES 9 Place the 2200 pF capacitor close to the PLL 10 Use a wide trace for the PLL analog power and ground Connect PLL and capacitors to AGND trace and connect trace to one GND via farthest from the PLL 11 Recommended bead Fair Rite PN 2506036017Y0 or equilvalent 0 8 Q dc maximum 600 Q
12. date Products conform to specifications per the terms of Texas Instruments L standard warranty Production processing does not necessarily include testing of all parameters EXAS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 Copyright 2004 Texas Instruments Incorporated CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 MicroStar Junior GQL Package TOP VIEW a a gt gt oF 6 gt gt gt Vi Y6 GND GND Yo Y7 GND GND Y2 Y7 VDDQ OS VDDQ VDDQ CK FBIN VDDQ VDDQ CK FBIN VDDQ OE AGND FBOUT VDDQ VDDQ VDDQ VDDQ AVDD FBOUT GND GND Y3 Y8 GND GND NC No Connection NB No Ball RTB PACKAGE TOP VIEW 40 pin HP VFQFP N 6 0 x 6 0 mm Body Size 0 5 mm Pitch M02220 Variation VJJD 2 E2 D2 2 9 mm 0 15 mm Package Pinouts d TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 Table 1 Terminal Functions Analog ground Clock input with a 10 kQ to 100 kQ pulldown resistor B2 B3 B4 B5 Ground C2 C5 H2 H5 J2 J3 J4 J5 D2 D3 D4 E2 1 6 9 15 20 E5 F2 G2 G3 23 28 31 36 G4 G5 Logic and output power Y 0 9 A2 A1 D1 J1 38 39 3 11 14 K3 A5 A6 D6 34 33 29 19 16 Clock outputs J6 K4 Y 0 9 A3 B1 C1 K1 37 40 2 12 13 Complementary clock outputs K2
13. ing conditions and no timing parameters are ensured 2 Vip is the magnitude of the difference between the input level on CK and the input level on CK see Figure 9 for definition The CK and CK Vip and Vu limits define the dc low and high levels for the logic detect state d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 CDCU877 CDCU877A 1 8 V PHASE LOCK LOOP CLOCK DRIVER SCAS688A JUNE 2003 REVISED JANUARY 2004 electrical characteristics over recommended operating free air temperature range PARAMETER TEST CONDITIONS ven MIN TYP MAX UNIT VIK Input cl inputs Is 18 mA 1 7V 1 2 V 1 7Vto Vi l lOH 100 pA iov 02 VOH High level output voltage V lod 9 mA 1 7V 1 1 beste lo 100 uA 0 1 v S tput volt OL ow level output voltage IOL IM 17V 0 6 lO DL Low level output current disabled VO DL 100 mV OE L 1 7V 100 uA VOD Differential output voltage see Note 1 1 7V 0 5 V CK CK 19V 250 ll Input current OE OS uA FBIN FBIN TOV 10 IDD LD Supply current static IDDQ lADD CK and CK L 19V 500 uA CK and CK 270 MHz All outputs are open 1 9V 135 Supply current dynamic IppQ lADD not connected to a PCB in DD see Note 2 for Cpp calculation All outputs are loaded with 2 pF and 19V 235 120 O termination resistor CK CK Vi Vpp or GND 1 8V 2 3 a deele FBIN FBIN Vj Vpp or GND 1 8V 2 al P CK CK
14. ls TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 MECHANICAL DATA GQL R PBGA N52 PLASTIC BALL GRID ARRAY coo 7X Via Hole Without Ball TE VK R O Missing Via Hole Indicates Pin A1 Quadrant e OOOO OC OC OO CO COT THO OOOO OOO CO OO EK DEO Bottom View 0 08 Seating Plane 4200583 2 1 07 04 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MO 225 variation BA D This package is tin lead SnPb Refer to the 52 ZQL package drawing 4204437 for lead free 35 TEXAS INSTRUMENTS www ti com MECHANICAL DATA RTB S PQFP N40 PLASTIC QUAD FLATPACK N em pm pm em bm em E pe E pe bm em bm E E bm pm em bm E Pin 1 Identifier LN Pucci 4 X Seating Plane C 0 20 Nominal 0 05 0 00 0 25 Min Exposed Thermal Pad A
15. please check http www ti com productcontent for the latest availability information and additional product content details None Not yet available Lead Pb Free Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Green RoHS amp no Sb Br TI defines Green to mean Pb Free and in addition uses package materials that do not contain halogens including bromine Br or antimony Sb above 0 1 of total product weight 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemica
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18. s previously described When OS and OE are both low OE has no affect on Y7 Y7 they are free running When AVpp is grounded the PLL is turned off and bypassed for test purposes When both clock inputs CK CK are logic low the device enters in a low power mode An input logic detection circuit on the differential inputs independent from input buffers detects the logic low level and performs in a low power state where all outputs the feedback and the PLL are off When the clock inputs transition from being logic low to being differential signals the PLL turns back on the inputs and the outputs are enabled and the PLL obtains phase lock between the feedback clock pair FBIN FBIN and the clock input pair CK CK within the specified stabilization time The CDCU877 is able to track spread spectrum clocking SSC for reduced EMI This device operates from 40 C to 85 C AVAILABLE OPTIONS 52 Ball BGA 40 Pin MLF S CDCU877ZQL 40 C to 85 C Pb Free CDCU877RTB CDCU877AZQL 40 C to 85 C Pb Free CDCU877ARTB 40 C to 85 C cocus77aqQL 40 C to 85 C CDCUB77AGQL Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet MicroStar Junior is a trademark of Texas Instruments PRODUCTION DATA information is current as of publication
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TEXAS INSTRUMENTS CDCU877 CDCU877A handbook