TEXAS INSTRUMENTS CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS handbook
Contents
1. 9 CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER DRIVER WITH 3 STATE OUTPUTS SCAS546B NOVEMBER 1995 REVISED MAY 1996 Provides System Clock Solution for DW PACKAGE Pentium 82430X 82430VX and TOP VIEW Pentium Pro 82440FX Chipsets Four Host Clock Outputs With Vcc L i REFO Programmable Frequency 50 MHz 60 MHz XtL ee Six PCI Clock Outputs at Half CPU OEMs 24 SBCLK Frequency HCLKO 6 23 GND One 48 MHz Universal Serial Bus USB HCLK1 7 221 PCLKO Clock Output Vcc 8 21 PCLK1 Three 14 318 MHz Reference Clock Outputs HCLK2 9 201 Voc All Output Clock Frequencies Derived From HCLK3 J10 4 19 PCLK2 a Single 14 31818 MHz Crystal Input GND 11 18 PCLK3 LVTTL Compatible Inputs and Outputs SEL1 12 171 GND SELO 13 16 PCLK4 Internal Loop Filters for Phase Locked 14 151 PCLK5 Loops Eliminate the Need for External Components 9 Operates at 3 3 Packaged in Plastic Small Outline Package description The CDC9842 is a high performance clock synthesizer driver that generates the system clocks necessary to support Pentium 82430X 82430VX and Pentium Pro 82440FX chipsets Four host clock outputs HCLKn are programmable to one of three frequencies 50 MHz 60 MHz or 66 MHz via the SELO and SEL 1 control inputs Six PCI clock outputs PCLKn are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns fro2. lt 2 5 ns C The outputs are measured one at a time with one transition per measurement Figure 1 Load Circuit and Voltage Waveforms CPU Clock HCLK CPU Clock HCLK HCLK to HCLK Skew PCI Clock PCI Clock PCLK to PCLK Skew 15 CPU Clock HCLK PCI Clock PCLK Offset Offset HCLK to PCLK Offset Figure 2 Waveforms for Calculation of tskew and Offset 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments its subsidiaries reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by go
3. BOX 655303 DALLAS TEXAS 75265 3 CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER DRIVER WITH 3 STATE OUTPUTS SCAS546B NOVEMBER 1995 REVISED MAY 1996 absolute maximum ratings over operating free air temperature range unless otherwise noted t Supply voltage range dese ee 0 5 V to 4 6 V Input voltage rarige V eere REP IA Re IE Ar eR RR eee EE 0 5 V to 4 6 V Voltage range applied to any output in the high impedance state or power off state Vo see Note 1 2202929 0 Ree Re Rede eh RR UE ERE 0 5 V to Vcc 0 5 V Current into any output in the low state lQ 16 mA Inputclamp current Ije Vs iuste reto imet te Rd eee nec t enden 18 mA Output clamp current lt 0 4 50 mA Maximum power dissipation at TA 55 C still air see Note 2 1 2W Storage temperature range Teig cede dined dein 65 C to 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated con
4. ditions for extended periods may affect device reliability NOTES 1 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed 2 The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils For more information referto the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book literature number SCBD002 recommended operating conditions see Note 3 High level input voltage E imis C High level output current Vi Ve V eur IOL Low level output current TA Operating free air temperature NOTE 3 Unused inputs must be held high or low to prevent them from floating electrical characteristics over recommended operating free air temperature range unless otherwise noted 25 25 TEST CONDITIONS UNIT MIN EN 21 t All typical values are at Vcc 3 3 V Device in normal operating mode with no load on outputs 4 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER DRIVER WITH 3 STATE OUTPUTS SCAS546B NOVEMBER 1995 REVISED MAY 1996 timing requirements over recommended ranges of supply voltage and operating free air temperature After SEL1 SELO Stabil
5. ization timet After OET After power up t Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal In order for phase lock to be obtained a fixed frequency fixed phase reference signal must be present at X1 Until phase lock is obtained the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable switching characteristics see Figures 1 and 2 Vcc 3 135 V FROM to 3 6 V PARAMETER INPUT OUTPUT Ta 0 C to 70 C HCLKn t skew PAK HCKLn Jittert HCLKn PCKLn HCKLn PCLKn T SELO L SEL1 C setts 5 t Specifications are applicable only after the PLL stabilization time has elapsed Rise and fall times are characterized using the load circuits shown in Figure 1 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER DRIVER WITH 3 STATE OUTPUTS SCAS546B NOVEMBER 1995 REVISED MAY 1996 PARAMETER MEASUREMENT INFORMATION CLOCK DRIVER CIRCUITS From Output _ tc Under Test Duty Cycle EM CL 20 pF 2 5002 see Note A LOAD CIRCUIT tf VOLTAGE WAVEFORMS NOTES A includes probe and jig capacitance B All input pulses are supplied by generators having the following characteristics PRR lt 10 MHz Zo 50 tr lt 2 5
6. m the rising edge of the CPU clock In addition a universal serial bus USB clock output at 48 MHz SBCLK and three 14 318 MHz reference clock outputs REFO REF1 REF2 are provided All output frequencies are generated from a 14 318 MHZ crystal input A reference clock can be provided at the X1 input instead of a crystal input Two phase locked loops PLLs are used to generate the host clock frequency and the 48 MHz clock frequency On chip loop filters and internal feedback eliminate the need for external components The PCI clock frequency is derived directly from the host clock frequency The PLL circuit can be bypassed in the TEST mode i e SELO SEL1 H to distribute a test clock provided at the X1 input The host and PCI clock outputs provide low skew low jitter clock signals for reliable clock operation All outputs are 3 state and are enabled via OE Because the CDC9842 is basedon PLL circuitry it requires a stabilization time to achieve phase lock of the PLL This stabilization time is required following power up and application of a fixed frequency fixed phase signal at the X1 input as well as following any changes to the OE or SELn inputs Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Pentium is a trademark of Intel Corporation PRODUCTION DATA i
7. nformation is current as of publication date Copyright 1996 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments processing does not necessarily include X TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER DRIVER WITH 3 STATE OUTPUTS SCAS546B NOVEMBER 1995 REVISED MAY 1996 FUNCTION TABLE SELO SELI HCLKn _ PCLKn REFn 14 318MHz Hi Z Hi Z 14 318 MHz 50 2 25MHz 14 318 MHz 14 318 MHz 60 MHz 30 MHz 14 318 MHz 14 318 MHz 66 MHz 33 MHz 14 318 MHz TCLKT TCLK 2 TCLK 4 TCLK t TCLK is a test clock input at the X1 input during test mode ki TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS TEXAS 75265 SBCLK Hi Z 48 MHz 48 MHz 48 MHz TCLK 4 CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER DRIVER WITH 3 STATE OUTPUTS SCAS546B NOVEMBER 1995 REVISED MAY 1996 functional block diagram x 3 gt 28 REFO osc 1 2 27 gt 1 eo gt 25 REFS B gt 24 SBCLK 0 4 gt 6 HCLKO 0 4 gt 7 HCLK1 3 2 6 1 10 HCLK3 gt gt 16 Pci KA e gt 18 PCLK3 gt 19 PcLK2 e gt 21 gt 22 PCLKO 35 TEXAS INSTRUMENTS POST OFFICE
8. vernment requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
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TEXAS INSTRUMENTS CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3 STATE OUTPUTS handbook