TEXAS INSTRUMENTS CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS handbook
Contents
1. 4040000 D 02 98 NOTES A All linear dimensions are in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JEDEC MS 013 gow kj TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMIC2. CDC33 7k hy A CDC337 CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS330B DECEMBER 1990 REVISED OCTOBER 1998 Low Output Skew Low Pulse Skew for DW PACKAGE Clock Distribution and Clock Generation TOP VIEW Applications TTL Compatible Inputs and CMOS Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same Frequency Outputs Four Half Frequency Outputs Distributed Vcc and Ground Pins Reduce Switching Noise High Drive Outputs 48 mA loH 48 mA loL State of the Art EP C IIB BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small Outline DW description The CDC337 is a high performance low skew clock driver It is specifically designed for applications requiring synchronized output signals at both the clock frequency and one half the clock frequency The four Y outputs switch in phase and at the same frequency as the clock CLK input The four Q outputs switch at one half the frequency of CLK When the output enable OE input is low and the clear CLR input is high the Y outputs follow CLK and the Q outputs toggle on low to high transitions at CLK Taking CLR low asynchronously resets the Q outputs to the low level When OE is high the outputs are in the high impedance state The CDC337 is characterized for operation from 40 C to 85 C FUNCTION TABLE INPUTS OUTPUTS OE CLR CLK Y1 Y4 ai a4 TThe level of the Q outputs
3. 0 5 V to Vcc 0 5 V Current into any output in the low state IQ 6 nnn nnn tenes 96 mA Input clamp current liq Vj lt 0 1 2 02 eee 18mA Maximum power dissipation at Ta 55 C in still air see Note 2 22 cece eee 1 6 W Storage temperature range Tstg 2 16 escent ee eee eee 65 C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed 2 The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils For more information refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book literature number SCBD002B ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC337 CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS330B DECEMBER 1990 REVISED OCTOBER 1998 recommended operating conditions see Note 3 OC A C ir IOL Low level output current fclock Input clock frequency 80 ME TA Operating free
4. air temperature NOTE 3 Unused pins input or I O must be held high or low to prevent them from floating electrical characteristics over recommended operating free air temperature range unless otherwise noted Voc 5 25 V Vj 2 7V Voc 5 25 V Vv 0 5V Vec 5 25 V Vi VocorGND l 0 mA t All typical values are at Vcc 5 V Ta 25 C timing requirements over recommended ranges of supply voltage and operating free air temperature unless otherwise noted fclock Clock frequency tw Pulse duration tsu Setup time CLR inactive before CLKT Clock duty cycle 40 60 vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 CDC337 CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS330B DECEMBER 1990 REVISED OCTOBER 1998 switching characteristics over recommended ranges of supply voltage and operating free air temperature C 50 pF unless otherwise noted See Note 4 and Figures 1 and 2 FROM TO PARAMETER INPUT OUTPUT MIN TYPT MAX UNIT t All typical values are at Voc 5 V Ta 25 C NOTE 4 All specifications are valid only for all outputs switching ki TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC337 CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS330B DECEMBER 1990 REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION 2xV o es TEST S1 From Output 500 Q O Open tpLH tPpHL Open Under Tes
5. before the indicated steady state input conditions were established Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet EPIC IIB is a trademark of Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments l standard warranty Production processing does not necessarily include testing of all parameters I EXAS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 Copyright 1998 Texas Instruments Incorporated CDC337 CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS330B DECEMBER 1990 REVISED OCTOBER 1998 logic symbolt logic diagram positive logic CLK t This symbol is in accordance with ANSI IEEE Std 91 1984 and OE 5 IEC Publication 617 12 eo 11 gt Q2 10 gt Q3 gt Q4 absolute maximum ratings over operating free air temperature range unless otherwise noted Supply Voltage range VOC certera tentantan oiingan p due date iia bine due anand D a 0 5Vto7V Input voltage range Vi see Note 1 0 ee eee 0 5Vto7V Voltage range applied to any output in the high state or power off state VOLSE NOLO A cusses siema sinesga deia l graces a ala D i oar ccmer VEE mecca
6. ONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
7. PLH2 tPLH10 eo NNN a Oo eee i Ne nr ce tPLH5 eo tPLH6 a rr ae lt tPLH7 ny ae i tPLH8 NOTES A Output skew tsk o from CLK to YT is calculated as the greater of the difference between the fastest and slowest of tPLHn n 1 2 3 4 or tPLHn N 9 10 11 12 B Output skew tgk g from CLKT to QT is calculated as the greater of the difference between the fastest and slowest of tPLHn n 5 6 7 8 C Output skew tsk 9 from CLKT to YT and QT is calculated as the greater of the difference between the fastest and slowest of tPLHn N 1 2 8 Figure 2 Waveforms for Calculation of tsk o ki TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC337 CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS330B DECEMBER 1990 REVISED OCTOBER 1998 MECHANICAL INFORMATION DW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 16 PIN SHOWN 0 050 1 27 0 020 0 51 0 014 0 35 16 9 0 010 0 25 0 0 419 10 65 0 400 10 15 7 59 0 010 0 25 NOM 7 45 A l Gage Plane 4 t 0 010 0 25 0 050 1 27 0 016 0 40 l TOO P 0 012 0 30 f 0 004 0 10 0 004 0 10 0 104 2 65 MAX PINS DIM A MAX A MIN
8. t GND pizitpzL 2x Voc tpHz tpZH Open see Note A g j i r tw gt LOAD CIRCUIT Input 1 5V 1 5V 3V ov Timing Input ov VOLTAGE WAVEFORMS 3V Data Input 1 5V 1 5V v ov Output 3 Control VOLTAGE WAVEFORMS low level enabling ov tPZzL gt W nut J N oy tpz K 1 5V 1 5 V l ov Output mea VCC PLH Waveform 1 50 Vcc Vo 0 3V 1 tPHL S1 at 2 x Vcc Lip a VOL oul Ai VoH see Note C tpHz le t Output 50 Vcc l Output Bem VOL Waveform 2 Vou 0 3 V TEN f S1 at Open 50 Voc OH 0 r gt i4 f gt id see Note C 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES A Cy includes probe and jig capacitance B All input pulses are supplied by generators having the following characteristics PRR lt 10 MHz Zo 50 Q tp lt 2 5 ns t lt 2 5 ns C Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control D The outputs are measured one at a time with one transition per measurement Figure 1 Load Circuit and Voltage Waveforms vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC337 CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS330B DECEMBER 1990 REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION eo NN t PLH1 PLH9 a i a a t
Download Pdf Manuals
Related Search
TEXAS INSTRUMENTS CDC337 CLOCK DRIVER WITH 3 STATE OUTPUTS handbook