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TEXAS INSTRUMENTS CDC2536 handbook

1. 10 11 15 across multiple devices under identical operating conditions Figure 3 Waveforms for Calculation of tsk o and tsk pr TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 MECHANICAL INFORMATION DB R PDSO G PLASTIC SMALL OUTLINE PACKAGE 28 PIN SHOWN 0 15 NOM A Gage Plane 4 t 2 00 MAX 0 05 MIN 4 0 10 PINS 4040065 C 10 95 NOTES A All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 150 gow ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are s
2. device outputs One device output must be externally wired to FBIN to complete the PLL The VCO operates such that the frequency of the output matches that of CLKIN In the case that a VCO 2 output is wired to FBIN the VCO must operate at twice the CLKIN frequency resulting in device outputs that operate at either the same or one half the CLKIN frequency If a VCO 4 output is wired to FBIN the device outputs operate at the same or twice the CLKIN frequency output configuration A Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to FBIN The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A Outputs configured as 1 2x outputs operate at half the CLKIN frequency while outputs configured as 1x outputs operate at the same frequency as CLKIN Table 1 Output Configuration A INPUT OUTPUTS SEL 1 2x FREQUENCY FEQ ENE L None All H 1Yn 2Yn NOTE n 1 2 3 output configuration B Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to FBIN The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B Outputs configured as 1x outputs operate at the CLKIN frequency while outputs configured as 2x outputs operate at double the frequency of CLKIN Table 2 Output Configuration B INPUT OUTPUTS SEL 1x 2x FREQUENCY FREQUENCY H 1Yn 2Yn L All None NOTE n
3. 1 2 3 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 functional block diagram OE 5 24 J gt gt ran 2 gt gt gt CLKIN 25 TEST vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 Terminal Functions TERMINAL 1 0 DESCRIPTION NAME NO Clock input CLKIN provides the clock signal to be distributed by the CDC2536 clock driver circuit CLKIN provides the reference signal to the integrated PLL that generates the clock output signals CLKIN must have CLKIN 3 a fixed frequency and fixed phase for the phase lock loop to obtain phase lock Once the circuit is powered up and a valid CLKIN signal is applied a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal CLR 24 E CLR is used for testing purposes only Feedback input FBIN provides the feedback signal to the internal PLL FBIN must be hardwired to one of the six clock outputs to provide frequency and phase lock The internal PLL adjusts the output clocks to obtain zero phase delay between the FBIN and differential CLKIN inputs Output enable OE is the outp
4. 4 The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed PARAMETER MEASUREMENT INFORMATION i et eer 3V Input 1 5 V 1 5 V 0 V tphase error gt From Output e Under Test VoH 500 2 O tp t af sv ON CL 15pF 0 a v Z7 j 0 8 V see Note A B VOL tr gt ti i 4 VOLTAGE WAVEFORMS LOAD CIRCUIT FOR OUTPUTS PROPAGATION DELAY TIMES NOTES A Cy includes probe and jig capacitance B Allinput pulses are supplied by generators having the following characteristics PRR lt 100 MHz Zo 50 Q tr lt 2 5 ns tf lt 2 5 ns C The outputs are measured one at a time with one transition per measurement Figure 1 Load Circuit and Voltage Waveforms TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION CLKIN S N f N gt j4 tphase error 1 Outputs Operating at 1 2 CLKIN Frequency tphase error 2 gt l tphase error 3 gt 4 tphase error 4 gt j4 tphase error 7 Outputs Operating at CLKIN Frequency gt tphase error 5 gt l4 tphase error 8 gt 4 tphase error 6 gt 4 tphase error 9 NOTES A Output skew tsk o is calculated as the greater of Th
5. CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 CDC2536 Av Fs Low Output Skew for Clock Disiribution DB PACKAGE and Clock Generation Applications TOP VIEW e Operates at 3 3 V Vcc e Distributes One Clock Input to Six Outputs e One Select Input Configures Three Outputs to Operate at One Half or Double the Input Frequency No External RC Network Required e On Chip Series Damping Resistors e External Feedback Pin FBIN Is Used to Synchronize the Outputs to the Clock Input e Application for Synchronous DRAM High Speed Microprocessor e TTL Compatible Inputs and Outputs e Outputs Drive 50 Q Parallel Terminated Transmission Lines e State of the Art EP C IIB BiCMOS Design Significantly Reduces Power Dissipation e Distributed Vcc and Ground Pins Reduce Switching Noise Packaged in Plastic 28 Pin Shrink Small Outline Package description The CDC2536 is a high performance low skew low jitter clock driver It uses a phase lock loop PLL to precisely align in both frequency and phase the clock output signals to the clock input CLKIN signal It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half frequency outputs The CDC2536 operates at 3 3 V Vcc and is designed to drive a 50 transmission line The CDC2536 also provides on c
6. IN The duty cycle of the Y output signals is nominally 50 independent of the duty cycle of the CLKIN signal Each output has an internal series resistor to dampen transmission line effects and improve the signal integrity at the load 2Y1 2Y3 22 19 16 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 absolute maximum ratings over operating free air temperature range unless otherwise noted t Supply voltage range VOC sas ersi curii haa an aa kaka aa na al n aa a ul k a l eee a a 0 5 V to 4 6 V Input voltage range V see Note 1 kk kk kk kk kk kk kk kk kK KEK KK KK KK kK kk KK kk kk kk kk ka 0 5 V to 7 V Voltage range applied to any output in the high state or power off state Vo see Note 1 0 5 V to 5 5 V Current into any output in the low state lO 3 xs a yl sl k Qal k kelk di mali nisu SETE k kn ad kn 24 mA Inputiclamp current hk Vj lt O 5 ys s ena na naske x we na gana y na Ana aa dek wets a a rn w e 20 mA Output clamp current loK V A sac n osazaklna sela xalan edna need a an a a SE E Ek EEE 50 mA Maximum power dissipation at Ta 55 C in still air see Note 2 KK 0 68 W Storage temperature range Tstg HHHH kk kk kk kK KK kK KK KK KK KK KK KK KK KK KK KK KK KK nba 65 C
7. e difference between the fastest and slowest of tphase error n N 1 2 6 The difference between the fastest and slowest of tohase error n n 7 8 9 B Process skew tsk pr is calculated as the greater of The difference between the maximum and minimum tphase error n N 1 2 6 across multiple devices under identical operating conditions The difference between the maximum and minimum tphase error n n 7 8 9 across multiple devices under identical operating conditions Figure 2 Waveforms for Calculations of tsk o and tsk pr vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION CLKIN f N S N Outputs Operating at CLKIN Frequency Outputs Operating at 2X CLKIN Frequency gt gt Bf NK tphase error 10 DLD J 4 tphase error 11 _ NK l tphase error 12 Zi DZ ZIZ 4 tphase error 13 ZAZA l tphase error 14 SA Sn SHY tphase error 15 NOTES A Output skew tsk o is calculated as the greater of The difference between the fastest and slowest of tphase error n n 10 11 15 B Process skew tsk pr is calculated as the greater of The difference between the maximum and minimum tphase error n N
8. hip series damping resistors eliminating the need for external termination components The feedback FBIN input is used to synchronize the output clocks in frequency and phase to the input clock CLKIN One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs The output used as the feedback pin is synchronized to the same frequency as CLKIN The Y outputs can be configured to switch in phase and at the same frequency as CLKIN The select SEL input configures three Y outputs to operate at one half or double the CLKIN frequency depending on which pin is fed back to FBIN see Tables 1 and 2 All output signal duty cycles are adjusted to 50 independent of the duty cycle at the input clock Output enable OE is provided for output control When OE is high the outputs are in the high impedance state When OE is low the outputs are active TEST is used for factory testing of the device and can be use to bypass the PLL TEST should be strapped to GND for normal operation Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet EPIC IIB is a trademark of Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date Copyright 1998 Texas Instruments Incorporated Products conform
9. ified under recommended operating conditions ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 timing requirements over recommended ranges of supply voltage and operating free air temperature When VCO is operating at four times the CLKIN frequency 25 50 fclock Clock frequency MHz When VCO is operating at double the CLKIN frequency 50 100 Duty cycle CLKIN 40 60 e ner SEL Stabilization timet us t Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal For phase lock to be obtained a fixed frequency fixed phase reference signal must be present at CLKIN Until phase lock is obtained the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable switching characteristics over recommended ranges of supply voltage and operating free air temperature C 15 pF see Note 4 and Figures 1 2 and 3 FROM TO PARAMETER INPUT OUTPUT MIN MAX UNIT A _______putyeyle PY 8H Pts ns Pte ts __L j jW UV eS r ___r _ ii U _I I I kji lkbi jk S S puf r The propagation delay tphase error S dependent on the feedback path from any output to FBIN The tphase error sk o and tsk pr Specfications are only valid for equal loading of all outputs NOTE
10. old subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI c
11. overing or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
12. to 150 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed 2 The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 75 mils For more information refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book literature number SCBDO02B recommended operating conditions see Note 3 Voc Supply voltage VIH High level input voltage VIL Low level input voltage VI Input voltage loH High level output current loL Low level output current TA Operating free air temperature NOTE 3 Unused inputs must be held high or low to prevent them from floating electrical characteristics over recommended operating free air temperature range unless otherwise noted PARAMETER TEST CONDITIONS VIK Voc MIN to MAX lOH 100 HA lon 12mA loL 100 pA lol 12 mA V 3 6 V Vi Vcc or GND ma For conditions shown as MIN or MAX use the appropriate value spec
13. to specifications per the terms of Texas Instruments e sei ofall aren Production processing does not necessarily include ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 CDC2536 3 3 V PHASE LOCK LOOP CLOCK DRIVER WITH 3 STATE OUTPUTS SCAS377D APRIL 1994 REVISED OCTOBER 1998 description continued Unlike many products containing PLLs the CDC2536 does not require external RC networks The loop filter for the PLL is included on chip minimizing component count board space and cost Because it is based on PLL circuitry the CDC2536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal This stabilization time is required following power up and application of a fixed frequency fixed phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals Such changes occur upon change of SEL enabling the PLL via TEST and upon enable of all outputs via OE The CDC2536 is characterized for operation from 0 C to 70 C detailed description of output configurations The voltage controlled oscillator VCO used in the CDC 2536 has a frequency range of 100 MHz to 200 MHz twice the operating frequency of the CDC2536 outputs The output of the VCO is divided by two and by four to provide reference frequencies with a 50 duty cycle of one half and one fourth the VCO frequency SEL determines which of the two signals is buffered to each bank of
14. ut enable for all outputs When OE is low all outputs are enabled When OE is high all outputs are in the high impedance state Since the feedback signal for the PLL is taken directly from an output placing the outputs in the high impedance state interrupts the feedback loop therefore when a high to low transition occurs at OE enabling the output buffers a stabilization time is required before the PLL obtains phase lock Output configuration select SEL selects the output configuration for each output bank e g 1x 1 2x or 2x see Tables 1 and 2 TEST is used to bypass the PLL circuitry for factory testing of the device When TEST is low all outputs operate using the PLL circuitry When TEST is high the outputs are placed in a test mode that bypasses the PLL circuitry TEST should be grounded for normal operation These outputs are configured by SEL to transmit one half or one fourth the frequency of the VCO The relationship between the CLKIN frequency and the output frequency is dependent on SEL The duty cycle of the Y output signals is nominally 50 independent of the duty cycle of the CLKIN signal Each output has an internal series resistor to dampen transmission line effects and improve the signal integrity at the load 1 1 1Y3 7 10 13 These outputs transmit one half the frequency of the VCO The relationship between the CLKIN frequency and the output frequency is dependent on the frequency of the output being fed back to FB

TEXAS INSTRUMENTS CDC2536 handbook

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