FAIRCHILD FAN5026 Manual
Contents
1. S ARE IN MILLIMETERS IS TO JEDEC REGISTRATION MO 153 VARIATION AB 6 DATED 7 93 IN MILLIMETERS E EXCLUSIVE OF BURRS MOLD FLASH t EXTRUSIONS AN ANCES PER ANSI Y14 5M 1982 MTC28REVA Figure 18 28 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http www fairchildsemi com packaging 2005 Fairchild Semiconductor Corporation www fairchildsemi com FAN5026 Rev 1 0 8 16 Wi FAIRCHILD SEMCOCONDUCTOY TRADEMARKS The Himig includes registered and unregistered trademarks and senice merks owned by Fairchild Serniconductor andor ts giobal absidiaies and is not ntended to be an exhaustive fst of al such trademarks AccuP oe Auto SPM AAA Buidit Now CorePLUS Core POWER CROSSYOLT CTL Currert Transfer Logc DEUXP2. T P MAK D MAX OJA Oja depends primarily on the amount of PCB area that can be devoted to heat sinking see Application Note AN 1029 Maximum Power Enhancement Techniques for SO 8 Power MOSFETs for SO 8 MOSFET thermal information T A MAX 33 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 15 Layout Considerations Switching converters even during normal operation produce short pulses of current that could cause substantial ringing and be a source of EMI if layout constraints are not observed There are two sets of critical components in a DC DC converter The switching power components process large amounts of energy at high rates and are noise generators The low power components responsible for bias and feedback functions are sensitive to noise A multi layer printed circuit board is recommended Dedicate one solid layer for a ground plane Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels Notice all the nodes that are subjected to high dV dt voltage swing such as SW HDRV and LDRV All surrounding circuitry tends to couple the signals from these nodes through stray capacitance Do not oversize copper traces connected to these nodes Do not place traces connected to the feedback components adjacent to these traces It is not recommended to use high density interconnect systems or micro vias on these signals The use o
3. bump or reduced phase shift The amount of phase shift reduction depends on the width of the region of flat gain and has a maximum value of 90 To further simplify the converter compensation the modulator gain is kept independent of the input voltage variation by providing feedforward of Vin to the oscillator ramp 600kHz 8 The zero frequency the amplifier high frequency gain and the modulator gain are chosen to satisfy most typical applications The crossover frequency appears at the point where the modulator attenuation equals the amplifier high frequency gain The system designer must specify the output filter capacitors to position the load main pole somewhere within a decade lower than the amplifier zero frequency With this type of compensation plenty of phase margin is achieved due to zero pole pair phase boost ng r or i g i o 1 i Ne f modul ator Boe i YE Figure 13 Compensation Conditional stability may occur only when the main load pole is positioned too much to the left on the freguency axis due to excessive output filter capacitance In this case an ESR zero placed within the 10kHz to 50kHz range gives some additional phase boost Fortunately there is an opposite trend in mobile applications to keep the output capacitor as small as possible 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 12 If a larger inductor value or low ESR v
4. Drive Equivalent Circuit 49 04 U0D WMd 3nding jeng Had iena 9Z0SNV 4 www fairchildsemi com Q Q G sw G SW ts l RER Voc Vsp R R 28 DRIVER GATE Most MOSFET vendors specify Qep and Qes Qesw can be determined as Qasw Qep Qes QtH 29 where Qr is the gate charge required to get the MOSFET to it s threshold VrH For the high side MOSFET Vps Vin which can be as high as 20V in a typical portable application Care should be taken to include the delivery of the MOSFET s gate power PGATE in calculating the power dissipation required for the FAN5026 P E Q ee Ai 30 GATE where Qe is the total gate charge to reach Vcc Low Side Losses Q2 however switches on or off with its parallel Schottky diode conducting therefore Vps 0 5V Since Psw is proportional to Vps Q2 s switching losses are negligible and Q2 is selected based on Rps on only Conduction losses for Q2 are given by 2 Rison 31 where Roson is the Rps on of the MOSFET at the highest operating junction temperature and P_ 1 D xl COND OUT 32 is the minimum duty cycle for the converter Since Dmn lt 20 for portable computers 1 D 1 produces a conservative result further simplifying the calculation The maximum power dissipation Powa is a function of the maximum allowable die temperature of the low side MOSFET the Oja and the maximum allowable ambient temperature rise
5. L x 4 4uH 15 Output Capacitor Selection The output capacitor serves two major functions in a switching power supply Along with the inductor it filters the sequence of pulses produced by the switcher and it supplies the load transient currents The requirements are usually dictated by ESR inductor ripple current Al and the allowable ripple voltage AV ESR lt av Al In addition the capacitors ESR must be low enough to allow the converter to stay in regulation during a load step The ripple voltage due to ESR for the converter in Figure 6 is 120mVpp Some additional ripple appears due to the capacitance value itself 16 7 Al Cout x 8 x fow AV 17 which is only about 1 5mV for the converter in Figure 6 and can be ignored The capacitor must also be rated to withstand the RMS current which is approximately 0 3 X Al or about 400mA for the converter in Figure 6 High frequency decoupling capacitors should be placed as close to the loads as physically possible Input Capacitor Selection The input capacitor should be selected by its ripple current rating 49 043U0D WMd 3nding jeng Had iena 9Z0SNV 4 www fairchildsemi com Two Stage Converter Case In DDR Mode Figure 5 the Vrr power input is powered by the Vppa output therefore all of the input capacitor ripple current is produced by the Vppa converter A conservative estimate of the output current required for the 2 5V regulator is
6. Parameter Conditions Power Supplies lvec Vcc Current LDRV HDRV Open Vsen Forced Above Regulation Point Shutdown EN 0 Isink Vin Current Sinking Vin 15V lsoURCE Vin Current Sourcing VIN 0V Isp Vin Current Shutdown Vuvio UVLO Threshold Rising Vcc Falling VuvLoH UVLO Hysteresis Oscillator fosc Frequency Ramp Amplitude Vin 16V Vin 5V Ramp Offset Ramp Vin Gain Vin lt 3V 1V lt Vin lt 3V 13 101 7U09 WMd Nnd no enq Yaa iena 9Z0SNV 4 Reference and Soft Start VREF Internal Reference Voltage Iss Soft Start Current At Startup Vss Soft Start Complete Threshold PWM Converters Load Regulation loutx from 0 to 5A Vin from 5 to 15V Isen Vsen Bias Current UVLOtsp Under Voltage Shutdown of Set Point 2us Noise Filter UVLO Over Voltage Threshold Yo of Set Point 2us Noise Filter Isns Over Current Threshold Rium 68 5KQ Figure 12 Minimum Duty Cycle Output Drivers HDRV Output Resistance Sourcing Sinking LDRV Output Resistance Sourcing Sinking Power Good Output and Control Pins Lower Threshold Yo of Set Point 2us Noise Filter Upper Threshold Yo of Set Point 2us Noise Filter PG Output Low IPG 4mA Lea
7. Any Schottky Diode 30V Fairchild Semiconductor BAT54 Inductor 6 4uH 6A 8 64mQ Panasonic ETQ P6F6R4HFA Inductor 0 8uH 6A 2 24mQ Panasonic ETQ P6FOR8LFA Dual MOSFET with Schottky Fairchild Semiconductor FDS6986AS DDR Controller N gt gt ININ gt N gt IN gt ININ gt NJ gt Fairchild Semiconductor FAN5026 Notes 1 C6 2 X 180pF in parallel 2 Suitable for typical notebook computer application of 4A continuous 6A peak for Vppa If continuous operation above 6A is required use single SO 8 packages For more information refer to the Power MOSFET Selection Section and use AN 6002 for design calculations 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 www fairchildsemi com Typical Applications Continued VIN 3 to 16V gt 2 5V 4A C6 4 04 U0D WMd 3nding jeng Yaa lend 9zOSNV4 Figure 6 Dual Regulator Application Table 2 Dual Regulator BOM Description Qty Ref Vendor Part Number Capacitor 68uf Tantalum 25V ESR 95mQ C1 AVX TPSV686 025 095 Capacitor 10nf Ceramic C2 C3 Any Capacitor 68uf Tantalum 6V ESR 1 80 C4 AVX TAJB686 006 Capacitor 150nF Ceramic C
8. U0D WMd 3nding jeng ad lend 9ZOSNV4 www fairchildsemi com Over Voltage Under Voltage Protection Should the Vsns voltage exceed 120 of Vrer 0 9V due to an upper MOSFET failure or for other reasons the over voltage protection comparator forces LDRV HIGH This action actively pulls down the output voltage and in the event of the upper MOSFET failure eventually blows the battery fuse As soon as the output voltage drops below the threshold the OVP comparator is disengaged This OVP scheme provides a soft crowbar function which accommodates severe load transients and does not invert the output voltage when activated a common problem for latched OVP schemes Similarly if an output short circuit or severe load transient causes the output to drop to less than 75 of the regulation set point the regulator shuts down Over Temperature Protection The chip incorporates an over temperature protection circuit that shuts the chip down if a die temperature of about 150 C is reached Normal operation is restored at die temperature below 125 C with internal power on reset asserted resulting in a full soft start cycle Design and Component Selection Guidelines As an initial step define the operating input voltage range output voltage and minimum and maximum load currents for the controller Setting the Output Voltage The internal reference voltage is 0 9V The output is divided down by a voltage divider to the
9. VSEN pin for example R5 and R6 in Figure 5 The output voltage therefore is 0 9V _ ee 0 9V 10 R6 R5 a To minimize noise pickup on this node keep the resistor to GND R6 below 2K for example R6 at 1 82KQ Then choose R5 1 82KQ Vv OUT 0 9 sii For DDR applications converting from 3 3V to 2 5V or other applications requiring high duty cycles the duty cycle clamp must be disabled by tying the converter s FPWM to GND When converters FPWM is at GND the converters maximum duty cycle is greater than 90 When using as a DDR converter with 3 3V input set up the converter for in phase synchronization by tying the VIN pin to 5V ros 3 24KQ Output Inductor Selection The minimum practical output inductor value keeps the inductor current just on the boundary of continuous conduction at some minimum load Industry standard practice is to choose the minimum current somewhere from 15 to 35 of the nominal current At light load the controller can automatically switch to Hysteretic Mode to sustain high efficiency The following equations select the proper value of the output filter inductor V OUT 12 A Al 2x1 MIN ESR where Al is the inductor ripple current and AVour is the maximum ripple allowed a Vin V out fo x Al 13 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 13 for this example use We 12 V our 2 5 Al 25 6A 1 5A tee 300KHz therefore
10. duty cycle to almost 100 for significant amount of time This could cause a large increase of the inductor current and lead to a long recovery from a transient over current condition or even to a failure at especially high input voltages To prevent this the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output TO PWM COMP Reference and Soft Start ILIM det Figure 12 Gate Driver Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification level shifting and shoot through protection Also it has functions that optimize the IC performance over a wide range of operating conditions Since MOSFET switching time can vary dramatically from type to type and with the input voltage the gate control logic provides adaptive dead time by monitoring the gate to source voltages of both upper and lower MOSFETs The lower MOSFET drive is not turned on until the gate to source voltage of the upper MOSFET has decreased to less than approximately 1V Similarly the upper MOSFET is not turned on until the gate to source voltage of the lower MOSFET has decreased to less than approximately 1V This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction or shoot through 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 11 voltage excursion
11. is detected limiting the maximum duty cycle to 5 This is designed to not interfere with normal PWM operation When FPWM is grounded the duty cycle clamp is disabled and the maximum duty cycle is 87 ILIM Ritm 4 ILIM 3 Current Limit Summing Circuits There must be a low resistance low inductance path between the driver pin and the MOSFET gate for the adaptive dead time circuit to function properly Any delay along that path subtracts from the delay generated by the adaptive dead time circuit and shoot through may occur Frequency Loop Compensation Due to the implemented current mode control the modulator has a single pole response with 1 slope at frequency determined by load 1 f gt Po 27RoCo 6 where Ro is load resistance Co is load capacitance 1 101 7U09 WMd Nd no enq Yaad Iena 9Z0SNV 4 www fairchildsemi com For this type of modulator a Type 2 compensation circuit is usually sufficient To reduce the number of external components and simplify the design the PWM controller has an internally compensated error amplifier Figure 13 shows a Type 2 amplifier and its response with the responses of a current mode modulator and the converter The Type 2 amplifier in addition to the pole at the origin has a zero pole pair that causes a flat gain region at frequencies between zero and the pole 1 __ 6kHz 27R C 7 1 27R C This region is also associated with phase
12. pee aoe 18 As an example if the average Ivona is 3A and average vit is 1A lvopa current is about 3 5A If average input voltage is 16V RMS input ripple current is D D 19 OUT MAX IO RMS where D is the duty cycle of the PWM1 converter and 20 Dual Converter 180 Phased In Dual Mode shown in Figure 5 both converters contribute to the capacitor input ripple current With each converter operating 180 out of phase the RMS currents add in the following fashion Bal 2 RMS 1 RMS 2 Ee or 22 Iams y1 D1 D17J l2 Dz Da 23 which for the dual 3A converters of Figure 6 calculates late 1 51A 24 Power MOSFET Selection Losses in a MOSFET are the sum of its switching Psw and conduction Pconp losses In typical applications the FAN5026 converter s output voltage is low with respect to its input voltage Therefore the lower MOSFET Q2 is conducting the full load current for most of the cycle Q2 should therefore be selected to minimize conduction losses thereby selecting a MOSFET with low Ropscon In contrast the high side MOSFET Q1 has a much shorter duty cycle and it s conduction loss has less impact Q1 however sees most of the switching losses the primary selection criteria should be gate charge High Side Losses Figure 16 shows a MOSFET s switching interval with the upper graph being the voltage and current on the drain to source and the lower graph de
13. 30 of the ramp amplitude at maximum load current and line voltage The following expression estimates the recommended value of Rsense as a function of the maximum load current lLoap max and the value of the MOSFET Roson TLoap MAX Rpscon 4 1K RseENsE gt a DRO 100 30 0 125 Vincmax 2a Rsense must however be kept higher than TLoap MAX Rps on w 1504A Rsense 100 2b The 1009 is the internal resistor in series with the ISNSx pins and has 15 typical variation Because Rsense is in series with the internal 1000 resistor the gain in the current feedback loop and the current limit accuracy is affected if Rsense is close to 1000 Setting the Current Limit A ratio of Isns is compared to the current established when a 0 9V internal reference drives the ILIM pin The threshold is determined as follows ISNS 4 a ui or ISNS 12 ILIM ii 3a 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 10 Since TLoap Rpscon 100 Roensg ISNS and at the ILIM 0 9V threshold 0 9 7 10 8 ISNS 12 um Rum therefore 10 8 100 RseNsE loa 5 Riv 3d Rpson Current limit ILimir Should be set high enough to allow inductor current to rise in response to an output load transient Typically a factor of 1 2 is sufficient In addition since lumt is a peak current cut off value multiply ILoap wax by the inductor ripple current e g 25
14. 5 C7 Any Capacitor 330uf Poscap 4V ESR 40mQ C6 C8 Sanyo 4TPB330ML Capacitor 0 1uF Ceramic c9 Any 56 2KQ 1 Resistor R1 R2 Any 10KQ 5 Resistor R3 Any 3 24KQ 1 Resistor R4 Any 1 82KQ 1 Resistor R5 R8 R9 Any 1 5KQ 1 Resistor R6 R7 Any Schottky Diode 30V D1 D2 Fairchild Semiconductor BAT54 Inductor 6 4uH 6A 8 64mQ L1 L2 Panasonic ETQ P6F6R4HFA Dual MOSFETs with Schottky Q1 Q2 Fairchild Semiconductor FDS6986AS DDR Controller U1 Fairchild Semiconductor FAN5026 Note 3 If currents above 4A continuous are required use single SO 8 packages For more information refer to the Power MOSFET Selection Section and AN 6002 for design calculations f ael MIMI IN j gt gt gt I INI ININJ AlN 2005 Fairchild Semiconductor Corporation www fairchildsemi com FAN5026 Rev 1 0 8 8 Circuit Description Overview The FAN5026 is a multi mode dual channel PWM controller intended for graphic chipset SDRAM DDR DRAM or other low voltage power applications in modern notebook desktop and sub notebook PCs The IC integrates control circuitry for two synchronous buck converters The output voltage of each controller can be set in the range of 0 9V to 5 5V by an external resistor divider The two synchronous buck converters can operate from an unregulated DC source such as a notebook battery with voltage ranging from 5 0V to 16V or from a r
15. EED Dual Cool EmGPARK Eficienta ESBO Fairchild Fairchild Semiconductor FACT Quet Senes FAC FAST FastvOore FETBench FlashVniter FPS F PFS FRFET Global Power Resource Green FPS Green FPS e Seres Grunx GTO Inte MAI ISOPLANART MegaBuck MICROCOUPLER Mido FETTY MicroPak MicroPaki MilerOnve MobonMax Moton SPrM rwvSever OptoHit OPTOLOGC OPTOPLANAR gt PDP SPM Power SPM PowerTrench Powerxs Programmable Active Droop OFET os Quiet Senes RapidConfigue oF Saving our word Ima a tine Signahice SmartMax SMART START SPH STEALTH SuperFET SuperSorm e3 SuperSOT SuperSOT 8 Supremos SyncFET Sync Lock gama Trademarks of System General Conporation used under icense by Fanchik Sermiconcuctor DISCLAIMER The Power Franchise The Right Technokeyy for Your Success Bwer TryBoost TryBuck TryCac TrryLogc TINYOPTO TryPorwer Tawa Tii ra ta Tifa Detect TRUECURRENT poerDes UHC Utes FRFET UriF ET vox VisualMax xs FARCHLD SEM CONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY UABILITY ARISING OUT OF THE APPLICATION OR LISE CF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DGES IT CONVEY ANY
16. Ea FAIRCHILD eS SEMICONDUCTOR FAN5026 Dual DDR Dual Output PWM Controller Features m Highly Flexible Dual Synchronous Switching PWM Controller that Includes Modes for DDR Mode with In phase Operation for Reduced Channel Interference 90 Phase shifted Two stage DDR Mode for Reduced Input Ripple Dual Independent Regulators 180 Phase Shifted Complete DDR Memory Power Solution Vit Tracks Vpodo2 Vppa2 Buffered Reference Output Lossless Current Sensing on Low Side MOSFET or Precision Over Current Using Sense Resistor Vcc Under Voltage Lockout Wide Input Range 3V to 16V Excellent Dynamic Response with Voltage Feedforward and Average Current Mode Control Power Good Signal Supports DDR II and HSTL 28 Lead Thin Shrink Small Outline Package Applications DDR Vppa and Vrr Voltage Generation PC Dual Power Supply Server DDR Power Desktop Computer Graphics Cards Ordering Information March 2011 Description The FAN5026 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range of 0 9V to 5 5V required to power I O chip sets and memory banks in high performance computers set top boxes and VGA cards Synchronous rectification and hysteretic operation at light loads contribute to high efficiency over a wide range of loads Efficiency is enhanced by using MOSFET Rosion as a current sense component Feedforward ramp modulation average current mode c
17. For example in Figure 6 the target for lumit lumit gt 1 2 x 1 25 x 1 6 x2A 5A 10 8 100 Ree Rizim gt p z limir Rpscon Since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the switching node side of Rsense is an accurate representation of the load current When using the MOSFET as the sensing element the variation of Rps on causes proportional variation in the Isns This value varies from device to device and has a typical junction temperature coefficient of about 0 4 C consult the MOSFET datasheet for actual values so the actual current limit set point decreases proportional to increasing MOSFET die temperature A factor of 1 6 in the current limit set point should compensate for MOSFET Roscon variations assuming the MOSFET heat sinking keeps its operating die temperature below 125 C qe E iow HA R pa SENE Figure 11 Improving Current Sensing Accuracy More accurate sensing can be achieved by using a resistor R1 instead of the Rps on of the FET as shown in Figure 11 This approach causes higher losses but yields greater accuracy in both Vproop and lumit R1 is a low value resistor e g 10mQ 4 04 3U0D WMd 3nding jeng Yaa iena 9Z0SNV 4 www fairchildsemi com Duty Cycle Clamp During severe load increase the error amplifier output can go to its upper limit pushing a
18. ISNS1 ISNS2 Current Sense Input Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback EN1 EN2 Enable Enables operation when pulled to logic HIGH Toggling EN resets the regulator after a latched fault condition These are CMOS inputs whose state is indeterminate if left open GND Ground VSEN1 VSEN2 Output Voltage Sense The feedback from the outputs used for regulation as well as PG under voltage and over voltage protection and monitoring 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 Continued on the following page 1 1017U09 WMd Nnd no enq Yaa Iena 9Z0SNV 4 www fairchildsemi com Pin Definitions Pin Name Description 11 ILIM1 Current Limit 1 A resistor from this pin to GND sets the current limit 12 SS1 17 SS2 Soft Start A capacitor from this pin to GND programs the slew rate of the converter during initialization During initialization this pin is charged with a 5mA current source 13 DDR DDR Mode Control HIGH DDR Mode LOW two separate regulators operating 180 degrees out of phase Input Voltage Normally connected to the battery providing voltage feedforward to set the amplitude of the internal oscillator ramp When using the IC for two step conversion from 5V input connect through 100KQ resistor to ground which sets the appr
19. LICENSE UNDER iTS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLD DE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN UFE SU EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury of the user ANTI COUNTERFEITING POLICY Fairchild Semiconductor Corporation s Ant Counterfeiting Policy Fairchild s Ant Counterfeiting Policy is also stated on our extemal website www fairchildseri com under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry All manufacturers of semiconductor products are expenencing counterfeiting of their parts Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation substandard performance failed applications and increased cost of production and manufacturing delays Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts Fairchi
20. Small Outline Package TSSOP Tape and Reel 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 4 04 U0D WMd Nd no enq Nad Iena 9ZOSNV4 www fairchildsemi com Block Diagrams 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 VIN BATTERY lt 3 to 16V Q VOUTI L owt 2 5V VOUT2 1 8V Figure 1 Dual Output Regulator VIN BATTERY lt 3 to 16V ILIM2 REF2 Figure 2 Typical Application 4 04 U0D WMd 3nding jeng Yaa lend 9zOSNV4 www fairchildsemi com Pin Configuration Pin Definitions 2 FAN5026 ILIM2 REF2 SS2 PG2 REF2OUT PG1 Figure 3 TSSOP 28 Pin Name Description AGND Analog Ground This is the signal ground reference for the IC All voltage levels are measured with respect to this pin LDRV1 LDRV2 Low Side Drive The low side lower MOSFET driver output Connect to gate of low side MOSFET PGND1 PGND2 Power Ground The return for the low side MOSFET driver Connect to source of low side MOSFET SWw1 SW2 Switching Node Return for the high side MOSFET driver and a current sense input Connect to source of high side MOSFET and low side MOSFET drain HDRV1 HDRV2 High Side Drive High side upper MOSFET driver output Connect to gate of high side MOSFET BOOT1 BOOT2 BOOT Positive supply for the upper MOSFET driver Connect as shown in Figure 4
21. all switching transitions in one converter take place far away from the decision points of the other converter me e NY Figure 10 Optimal 90 Phasing for DDR2 49 04 U0D WMd 3nding jeng Had iena 9Z0SNV 4 www fairchildsemi com Initialization and Soft Start Assuming EN is HIGH FAN5026 is initialized when Vcc exceeds the rising UVLO threshold Should Vcc drop below the UVLO threshold an internal power on reset function disables the chip The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin which is charged with a 5uA current source Once Css has charged to Vrer 0 9V the output voltage is in regulation The time it takes SS to reach 0 9V is 0 9xC gs 5 where tog is in seconds if Css is in pF 1 log When SS reaches 1 5V the power good outputs are enabled and Hysteretic Mode is allowed The converter is forced into PWM Mode during soft start Current Processing Section The following discussion refers to Figure 12 The current through the Rsense resistor Isns is sampled typically 400ns after Q2 is turned on as shown in Figure 12 That current is held and summed with the output of the error amplifier This effectively creates a current mode control loop The resistor connected to ISNSx pin Rsense sets the gain in the current feedback loop For stable operation the voltage induced by the current feedback at the PWM comparator input should be set to
22. alues are required by the application additional phase margin can be achieved by putting a zero at the LC crossover frequency This can be achieved with a capacitor across the feedback resistor e g R5 from Figure 6 as shown in Figure 14 Rae al Tres Figure 14 Improving Phase Margin The optimal value of C Z is P oy xC OUT Protections The converter output is monitored and protected against extreme overload short circuit over voltage and under voltage conditions A sustained overload on an output sets the PGx pin LOW and latches off the regulator on which the fault occurs Operation can be restored by cycling the Vcc voltage or by toggling the EN pin If Vout drops below the under voltage threshold the regulator shuts down immediately Over Current Sensing If the circuits current limit signal ILIM det in Figure 12 is HIGH at the beginning of a clock cycle a pulse skipping circuit is activated and HDRV is inhibited The circuit continues to pulse skip in this manner for the next eight clock cycles If at any time from the ninth to the sixteenth clock cycle the ILIM det is again reached the over current protection latch is set disabling the regulator If ILIM det does not occur between cycles nine and sixteen normal operation is restored and the over current circuit resets itself keh states CH1 5 0V CH3 2 0AQ Figure 15 CH2 100mV Over Current Protection Waveforms 4 04
23. e The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended In addition extended exposure to stresses above the recommended operating conditions may affect device reliability The absolute maximum ratings are stress ratings only Symbol Parameter Min Max Unit Vcc Vcc Supply Voltage 6 5 V Vin Vin Supply Voltage 18 BOOT SW ISNS HDRV 24 BOOTx to SWx 6 5 All Other Pins Junction Temperature Storage Temperature Lead Temperature Soldering 10 Seconds Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation Recommended 49 043U0D WMd 3nding jeng Had Iena 9Z0SNV 4 operating conditions are specified to ensure optimal performance to the datasheet specifications Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings Symbol Parameter Typ Max Unit Vcc Vcc Supply Voltage 5 25 Vin Vin Supply Voltage 16 Ta Ambient Temperature 85 Osa Thermal Resistance Junction to Ambient 90 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 www fairchildsemi com Electrical Characteristics Recommended operating conditions unless otherwise noted Symbol
24. egulated system rail of 3 3V to 5 0V In either mode the IC is biased from a 5V source The PWM modulators use an average current mode control with input voltage feedforward for simplified feedback loop compensation and improved line regulation Both PWM controllers have integrated feedback loop compensation that reduces the external components needed The FAN5026 can be configured to operate as a complete DDR solution When the DDR pin is set HIGH the second channel provides the capability to track the output voltage of the first channel The PWM2 converter is prevented from going into Hysteretic Mode if the DDR pin is HIGH In DDR Mode a buffered reference voltage buffered voltage of the REF2 pin required by DDR memory chips is provided by the PG2 pin Converter Modes and Synchronization Table 3 Converter Modes and Synchronization PWM 2 w r t PWM1 VIN DDR Mode Vin Pin Pin DDR1 Battery Vin HIGH IN PHASE R to DDR2 5V GND HIGH 90 DUAL ANY Vin LOW 180 When used as a dual converter as shown in Figure 6 out of phase operation with 180 degree phase shift reduces input current ripple For two step conversion where the Vrr is converted from Vppa as in Figure 5 used in DDR Mode the duty cycle of the second converter is nominally 50 and the optimal phasing depends on Vin The objective is to keep noise generated from the switching transition in one converter fro
25. f blind or buried vias should be limited to the low current signals only The use of normal thermal vias is at the discretion of the designer Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A Minimize the area within the gate source path to reduce stray inductance and eliminate parasitic ringing at the gate Locate small critical components like the soft start capacitor and current sense resistors as close as possible to the respective pins of the IC The FAN5026 utilizes advanced packaging technology with lead pitch of 0 6mm High performance analog semiconductors utilizing narrow lead spacing may require special considerations in design and manufacturing It is critical to maintain proper cleanliness of the area surrounding these devices 49 04 U0D WMd 3nding jeng Had Iena 9ZOSNV4 www fairchildsemi com Physical Dimensions 0 2 C BIA LEAD TIPS IDENT LAND PATTERN RECOMMENDATION SEE DETAIL A 4 04 U0D WMd 3nding jeng Yaad Iena 9Z0SNV 4
26. kage Current Veuttup 5V PG2 REF2OUT Voltage DDR 1 0 MA lt IrEF20uT lt 10MA DDR EN Inputs VINH Input High VINE Input Low 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 www fairchildsemi com Typical Application VIN 3 to 16V gt VIN VCC 1 25V 10mA PG2 REF Table 1 DDR Regulator BOM VDDQ 2 5V LDRV2 PGND2 ISNS2 VSEN2 ILIM2 REF2 Figure 5 DDR Regulator Application Tes 4 04 U0D WMd 3nding jeng Yaa lend 9zOSNV4 Description Qty Ref Vendor Part Number Capacitor 68uf Tantalum 25V ESR 150mQ C1 AVX TPSV686 025 0150 Capacitor 10nf Ceramic C2 C3 Any Capacitor 68uf Tantalum 6V ESR 1 80 C4 AVX TAJB686 006 Capacitor 150nF Ceramic C5 C7 Any Capacitor 180uf Specialty Polymer 4V ESR 15mQ C6A C6B Panasonic EEFUE0G181R Capacitor 1000uf Specialty Polymer 4V ESR 10mQ C8 Kemet T510E108 1 004AS4115 Capacitor 0 1uF Ceramic c9 Any 1 82KQ 1 Resistor R1 R2 R3 Any 56 2KQ 1 Resistor R3 Any 10KQ 5 Resistor R4 Any 3 24KQO 1 Resistor R5 Any 1 5KQ 1 Resistor
27. ld strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above Products custorrers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts have full traceability meet Fairchild s quality standards for handling and storage and provide access to Fairchild s full range of up to date technical and product information Fairchild and our Authonzed Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status p Formative Advance Information Preliminary First Production Definition Datasheet contains the design specifications for product development Specifications may change in any manner without notice Datasheet contains preliminary data supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design PPORT DEVICES OR SYSTEMS WITHOUT THE 2 A critical component in a
28. m influencing the decision to switch in the other converter When Vin is from the battery it s typically higher than 7 5V As shown in Figure 7 180 operation is undesirable because the turn on of the Vppa converter occurs very near the decision point of the Vrr converter 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 Figure 7 Noise Susceptible 180 Phasing for DDR1 In phase operation is optimal to reduce inter converter interference when Vin is higher than 5V when Vin is from a battery as shown in Figure 8 Because the duty cycle of PWM1 generating Vppq is short the switching point occurs far away from the decision point for the Vtt regulator whose duty cycle is nominally 50 Figure 8 Optimal In Phase Operation for DDR1 When Vin 5V 180 phase shifted operation can be rejected for the reasons demonstrated in Figure 7 In phase operation with Vin 5V is even worse since the switch point of either converter occurs near the switch point of the other converter as seen in Figure 9 In this case as Vin is a little higher than 5V it tends to cause early termination of the Vrr pulse width Conversely the Vtr switch point can cause early termination of the Vppa pulse width when Vin is slightly lower than 5V Figure 9 Noise Susceptible In Phase Operation for DDR2 These problems are solved by delaying the second converter s clock by 90 as shown in Figure 10 In this way
29. ny component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness No Identification Needed Obsolete Not In Production Full Production Datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor The datasheet is for reference information only Rev 153 4 04 U0D WMd Nnd no jenq Yaa lend 9ZOSNV4 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 17 www fairchildsemi com
30. ontrol and internal feedback compensation provide fast response to load transients Out of phase operation with 180 degree phase shift reduces input current ripple The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin In DDR Mode one of the channels tracks the output voltage of another channel and provides output current sink and source capability essential for proper powering of DDR chips The buffered reference voltage required by this type of memory is also provided The FAN5026 monitors these outputs and generates separate PGx power good signals when the soft start is completed and the output is within 10 of the set point Over voltage protection prevents the output voltage from exceeding 120 of the set point Normal operation is automatically restored when over voltage conditions cease Under voltage protection latches the chip off when output drops below 75 of the set value after the soft start sequence for this output is completed An adjustable over current function monitors the output current by sensing the voltage drop across the lower MOSFET If precision current sensing is required an external current sense resistor may be used Related Resources Application Note AN 6002 Component Calculations and Simulation Tools Operating Temperature Range Part Number Package Packing Method FANSO26MTCX 40 to 85 C 28 Lead Thin Shrink
31. opriate ramp gain and synchronizes the channels 90 out of phase Power Good Flag An open drain output that pulls LOW when Vsen is outside a 10 range of the 0 9V reference PG2 REF2OUT Power Good 2 When not in DDR Mode open drain output that pulls LOW when the Vouris out of regulation or in a fault condition Reference Out 2 When in DDR Mode provides a buffered output of REF2 Typically used as the Vppaq2 reference ILIM2 REF2 Current Limit 2 When not in DDR Mode a resistor from this pin to GND sets the current limit Reference for reg 2 when in DDR Mode Typically set to Voutiz VCC VCC This pin powers the chip as well as the LDRV buffers The IC starts to operate when voltage on this pin exceeds 4 6V UVLO rising and shuts down when it drops below 4 3V UVLO falling Block Diagram 2005 Fairchild Semiconductor Corporation POR UVLO ADAPTIVE GATE CONTROL LOGIC FANS026 Rev 1 0 8 ILIM det CURRENT PROCESSING OUT Reference and Soft Start lt DDR Figure 4 IC Block Diagram 4 04 U0D WMd 3nding jeng Yaad Iena 9Z0SNV 4 www fairchildsemi com Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the devic
32. tailing Ves vs time with a constant current charging the gate The X axis therefore is also representative of gate charge 2005 Fairchild Semiconductor Corporation FAN5026 Rev 1 0 8 14 Qe Ciss Cep Ces and it controls t1 t2 and t4 timing Cep receives the current from the gate driver during t3 as Vps is falling The gate charge Qe parameters on the lower graph are either specified in or can be derived from MOSFET datasheets Assuming switching losses are about the same for both the rising edge and falling edge Q1 s switching losses occur during the shaded time when the MOSFET has voltage across it and current through it These losses are given by Pupper Psw Poonp 25 26 V_ xl 08 Lx 2xty f 2 sw V OUT xl 27 P COND OUT VIN where Pupper is the upper MOSFET s total losses and Psw and Pconp are the switching and conduction losses for a given MOSFET Rpscon is at the maximum junction temperature Ty and ts is the switching period rise or fall time shown as t2 and t3 in Figure 16 The driver s impedance and Ciss determine t2 while t3 s period is controlled by the driver s impedance and Qep Since most of ts occurs when Ves Vsp use a constant current assumption for the driver to simplify the calculation of ts lt ISS a Co gt a Css V DS tt td Switching Losses and Qc Caf PHO O Rowe i Cog Sw Figure 16 Figure 17
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FAIRCHILD FAN5026 Manual