FAIRCHILD FAN5069 Manual
Contents
1. 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 15 www fairchildsemi com OQUIOD 19 0 1uO OUT PUE INAAd 690SNV4 FAN5069 has a high gain error amplifier around which For further information about Type 2 compensation the loop is closed Figure 24 shows a Type 3 compensa networks refer to tion network For Type 2 compensation R3 and C3 are not used Since the FAN5069 architecture employs sum ming current mode Type 2 compensation can be used for most applications m Venable H Dean The K factor A new mathematical tool for stability analysis and synthesis Proceedings of Powercon March 1983 Note For critical applications requiring wide loop bandwidth using very low ESR output capacitors use Type 3 compensation Type 3 Feedback Component Calculations Use the following steps to calculate feedback components Notation Co Net Output Filter capacitance G s Net Gain of Plant control to output transfer function L Inductor Value Rpsow ON state Drain to Source Resistance of Low side MOSFET Res Net ESR of the Output Filter Capacitors R Load Resistance T Switching Period Vin Input Voltage Foy Switching Frequency Equations Effective current sense resistance R 7 x Roson EQ 19 R Current modulator DC gain M F EQ 20 Viy 1 8 xT Effective ramp amplitude V 3 33 x 10x Ao ramp EQ 21 V Voltage modulator DC gain M go EQ 22 m2. Vcc uc 1 5V Vppo 1 5V and Vrr art 1 25V m Power Supply for FPGA DSP Embedded Controllers Graphic Card Processor and Communication Processors m Industrial Power Supplies m High Power DC to DC Converters Ordering Information Part Number Operating Temp Range Pb Free Package Packing Method Qty Reel FAN5069MTCX 10 C to 85 C Yes 16 Lead TSSOP Tape and Reel 2500 FAN5069EMTCX 40 C to 85 C Yes 16 Lead TSSOP Tape and Reel 2500 Note Contact Fairchild sales for availability of other package options 2005 Fairchild Semiconductor Corporation www fairchildsemi com FAN5069 Rev 1 1 5 oquio 1961107110023 OUT PUE INMd 690SNVJH Typical Application Rvcc 12V Wa 3 TO 24V X X VCC R8 A FAN5069 14 R RAMP AAA 4 5V 9 sa BOOT EN 11 C3 SS Cc C NEN L C4 C7 R4 AAA L 10 HDRV R5 I L1 PWM OUT R T 9 Sw e VY e I AGND Q2 2 A C6 PWM OUT 13 LDRV Ri I a 12 PGND Ga GLDO CLER e 16 6 e ULDO ca cij LDO OUT R7 FBLDO CONTROL COMP R3 T R2 1 R6 DoT men SEEN Figure 1 Typical Application Diagram 2005 Fairchild Semiconductor Corporation www fairchildsemi com FAN
3. ST FAIRCHILD ee SEMICONDUCTOR September 2006 PWM and LDO Controller Combo Features Description m General Purpose PWM Regulator and LDO Controller The FAN5069 combines a high efficiency Pulse Width m Input Voltage Range 3V to 24V Modulated PWM controller and an LDO Low DropOut m Output Voltage Range 0 8V to 15V linear regulator controller Synchronous rectification pro y vides high efficiency over a wide range of load currents _ ay Efficiency is further enhanced by using the low side MOSFET s Rpg on to sense current Shunt Regulator for 12V Operation Support for Ceramic Cap on PWM Output Both the linear and PWM regulator soft start are con trolled by a single external capacitor to limit in rush cur rent from the supply when the regulators are first enabled Current limit for PWM is also programmable Programmable Current Limit for PWM Output Programmable Switching Frequency 200KHz to 600KHz Ros on Current Sensing The PWM regulator employs a summing current mode control with external compensation to achieve fast load Internal Synchronous Boot Diode doe transient response and provide design optimization E m Soft Start for both PWM and LDO m Multi Fault Protection with Optional Auto restart FAN5069 is offered in both industrial temperature grade m 16 pin TSSOP Package 40 C to 85 C as well as commercial temperature grade 10 C to 85 C Applications m PC Server Motherboard Peripherals
4. The maximum voltage at the gate drive for the MOSFET can reach close to 0 5V below the Vcc of the controller For example for a 1 2V output the minimum enhance ment voltage required with 4 75V on Vcc is 3 05V 4 75V 0 5V 1 2V 3 05V The drop out voltage for the LDO is dependent on the load current and the MOSFET chosen It is recommended to use low enhancement voltage MOSFETs for the LDO In applications where LDO is not needed pull up the FBLDO pin Pin 1 higher than 1V to disable the LDO The soft start on the LDO output ramp is controlled by the capacitor on the SS pin to GND The LDO output is enabled only when the voltage on the SS pin reaches 2 2V Refer to Figure 9 for start up waveform Design Section General Design Guidelines Establishing the input voltage range and maximum cur rent loading on the converter before choosing the switch ing frequency and the inductor ripple current is highly recommended There are design trade offs in choosing an optimum switching frequency and the ripple current The input voltage range should accommodate the worst case input voltage with which the converter may ever operate This voltage needs to account for the cable drop encountered from the source to the converter Typically the converter efficiency tends to be higher at lower input voltage conditions When selecting maximum loading conditions consider the transient and steady state continuous loading sep arately The t
5. Unit Supply Current Iveco Vcc Current Quiescent HDRV LDRV Open 2 6 3 2 3 8 mA lvccisp Vcc Current Shutdown EN OV Voc 5 5V 200 400 LA lvcc opP Vcc Current Operating EN 5V Voc 5 0V 10 15 mA Qeet 20nC Fsw 200kHz VsHunT Vcc Voltage Sinking 1mA to 100mA at Vec 5 5 5 9 V Pin Under Voltage Lockout UVLO UVLO H Rising Vcc UVLO Threshold 4 00 4 25 4 50 V UVLO L Falling Vcc UVLO Threshold 3 60 3 75 4 00 V Vcc UVLO Threshold 0 50 V Hysteresis Soft Start las Current 10 LA Vi DOSTART LDO Start Threshold 2 2 V Vssok PWM Protection Enable 1 2 V Threshold Oscillator Fosc Frequency R T 56KQ 1 240 300 360 KHz R T Open 160 200 240 KHz Frequency Range 160 600 KHz AVnaup Ramp Amplitude R RAMP 330KQ 0 4 V Peak to Peak Minimum ON Time F 200kHz 200 ns Reference Vrer Reference Voltage TA 0 C to 70 C 790 800 810 mV Measured at FB Pin Ta 40 C to 85 C 788 800 812 mV Current Amplifier Reference 160 mV at SW node Error Amplifier DC Gain 80 dB GBWP Gain BW Product 25 MHz S R Slew Rate 10pF across COMP to GND 8 V uS Output Voltage Swing No Load 0 5 4 0 V IFB FB Pin Source Current 1 LA Gate Drive Ruup HDRV Pull up Resistor Sourcing 1 8 3 0 Q Rupn HDRV Pull down Resistor Sinking 1 8 3 0 Q Riup LDRV Pull up Resistor Sourcing 1 8 3 0 Q Rip LDRV Pull down Resistor Sinking e 1 2 2 0 Q 20
6. Plant DC gain M M IIM i bel EQ 23 an gain F 9 V M M Sampling gain natural frequency o EQ 24 S Sampling gain quality factor damping Q 2E EQ 25 T NS Mo M x Rj Effective inductance L ix L EQ 26 M 0 xQ M x Ri x RL M I 2005 Fairchild Semiconductor Corporation www fairchildsemi com FAN5069 Rev 1 1 5 16 oquio 7191107110023 OT PUE INMd 690SNVJH Poles and Zeros of Plant Transfer Function 1 Plant zero frequency f 2xaxG XH EQ 28 0 es Plant 15 pole frequency fous EQ 29 2xnx C_ xR Cs Rp gt nd 1 NP Plant 2 pole frequency foo uci CA TU EQ 30 0 L e rd on xL Plant 3 pole frequency fp3 SEZA EQ 31 p Plant gain magnitude response G f 20 x logMg 10 x log EQ 32 Plant phase response 1 f 1 f 1 f 1 f ASIR UM Aa ME EQ ZGp f tan G tan Gi tan a tan 5 EQ 33 Choose R1 Rgiag to set the output voltage using EQ 6 Choose the zero crossover frequency Feross of the overall loop Typically Feross should be less than fifth of Fgw Choose the desired phase margin typically between 60 to 90 Calculate plant gain at Fcrosg using EQ 34 by substituting Fcross in place of f The gain that the amplifier needs to pro vide to get the required crossover is given by 1 G EQ 34 AMP Du Feross The phase boost required is calculated as given in EQ 35 Phase Boost M Gp F oss 90 EQ
7. 200ys 2 5MS s Chi Ch3 20v Bw Ch4 500rnv Bw A Ch3 1 96Y Ch3 10v Figure 10 PWM LDO Power Down L FANSOBSB Auto Restart Vinz 12V Ydd 5Y lload 22A 4 i f are L La Lii Figure 11 Auto Restart S500mY iti Bw Ch2 2 04 Bw M 400ps 1 25NIS s 800ns pt Bw A Ch2 22V Figure 13 Enable OFF Ipww 5A 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 8 www fairchildsemi com oquio 19j 0 3u0 OUT Pue INMa 690SNVJ 1 54 PWM Line Regulation Voyr 1 5V 1 52 1 50 1 48 OUTPUT VOLTAGE V 1 46 1 210 1 205 1 200 8 10 Load Line Regulation Vour 1 203V 12 14 16 INPUT VOLTAGE V 18 Figure 14 PWM Line Regulation 20 OUTPUT VOLTAGE V 1 195 10 PWM Load Regulation Vour 1 50V 12 14 16 INPUT VOLTAGE V OUTPUT VOLTAGE V 18 Figure 15 LDO Line Regulation 20 4 6 LOAD CURRENT A Figure 16 PWM Load Regulation OUTPUT VOLTAGE V FREQUENCY kHz a Le eo Typical Performance Characteristics Continued 1 210 1 205 1 200 co a 1 190 700 EFFICIENCY LDO Load Regulation Vour 1 203V LOAD CURRENT A Figure 17 LDO Load Regulation Master Clock Frequency 100 200 Rr kQ Figure 18 Rz vs Frequency Efficiency vs Input Vo
8. 6 3e10 eFosc RRAMP EQ 4 where Fosc is in Hz For example for Fosc 300kHz and VIN 12V RRAMP 540KQ Gate Drive Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals and provides necessary amplification level shifting and shoot through protection It also has functions that help optimize the IC performance over a wide range of oper ating conditions Since the MOSFET switching time can vary dramatically from device to device and with the input voltage the gate control logic provides adaptive dead time by monitoring the gate to source voltages of both upper and lower MOSFETs The lower MOSFET drive is not turned on until the gate to source voltage of the upper MOSFET has decreased to less than approxi mately 1V Similarly the upper MOSFET is not turned on until the gate to source voltage of the lower MOSFET has decreased to less than approximately 1V This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction or shoot through A low impedance path between the driver pin and the MOSFET gate is recommended for the adaptive dead time circuit to work properly Any delay along this path reduces the delay generated by the adaptive dead time circuit thereby increasing the chances for shoot through Protection In the FAN5069 the converter is protected against extreme overload short circuit over voltage a
9. EQ 11 Pow 5 x 2x Few V OUT EQ 12 Pconp Vin x l ur x Ros on i where Pupper is the upper MOSFET s total losses and Psw and Pconp are the switching and conduction losses for a given MOSFET Rps onj is at the maximum junction temperature Ty and ts is the switching period rise or fall time and equals t2 t3 Figure 22 The driver s impedance and Ciss determine t2 while t3 s period is controlled by the driver s impedance and Qep Since most of tg occurs when Vas Vsp assume a con stant current for the driver to simplify the calculation of tg using the following equation i Qa sw Qa sw EQ 13 S a Ven s EQ 13 Driver CC SP Rpriver RGate Most MOSFET vendors specify Qgp and Qas Qasw can be determined as Qgsw Gan Qas QtH Where Qry is the gate charge required to reach the MOSFET threshold Vru Note that for the high side MOSFET Vpg equals Vin which can be as high as 20V in a typical portable appli cation Include the power delivered to the MOSFET s Paare in calculating the power dissipation required for the FAN5069 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 14 www fairchildsemi com OQUIOD 19 0 1uO OUT PUE INAAd 690SNV4 Paare is determined by the following equation V F EQ 14 Paate Qa x Voc x Fsw where Qeg is the total gate charge to reach Voc Low Side Losses Q2 switches on or off with its parallel schottky diode simul
10. TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only Rev 120 2005 Fairchild Semic
11. charged by a 10uA internal current source causing the voltage on the capacitor to rise When this voltage exceeds 1 2V all protection circuits are enabled When this voltage exceeds 2 2V the LDO output is enabled The input to the error amplifier at the non inverting pin is clamped by the voltage on the SS pin until it crosses the reference voltage The time it takes the PWM output to reach regulation TRise is calculated using the following equation Trise 8x10 x Cas Casis in uf EQ 2 Oscillator Clock Frequency PWM The clock frequency on the oscillator is set using an external resistor connected between R T pin and ground The frequency follows the graph as shown in Figure 18 The minimum clock frequency is 200KHz which is when R T pin is left open Select the value of R T as shown in the equation below This equation is valid for all Fosc 200kHz 5 x 10 Ree e O 7 Fasc 200 x 103 EQ 3 where Fosc is in Hz For example for Fosc 300kHz R T 50KQ Rramp Selection and Feed Forward Operation The FAN5069 provides for input voltage feed forward compensation through Rrawp The value of Rramp effec tively changes the slope of the internal ramp minimizing the variation of the PWM modulator gain when input volt age varies The Rramp also has an effect on the current limit as can be seen in the R jy equation EQ 5 The Rramp Value can be approximated using the following equation Vu 18
12. current switching frequency of the con verter and the input output voltages are established select the inductor using the following equation V OUT on eer IRipple 5 Fsw EQ 6 Luin EQ 7 where lRipple is the ripple current This number typically varies between 20 to 50 of the maximum steady state load on the converter When selecting an inductor from the vendors select the inductance value which is close to the value calculated at the rated current including half the ripple current Input Capacitor Selection PWM The input capacitors must have an adequate RMS cur rent rating to withstand the temperature rise caused by the internal power dissipation The combined RMS cur rent rating for the input capacitor should be greater than the value calculated using the following equation ea Sour bais Vin Vin cee Common capacitor types used for such application include aluminum ceramic POS CAP and OSCON Output Capacitor Selection PWM The output capacitors chosen must have low enough ESR to meet the output ripple and load transient require ments The ESR of the output capacitor should be lower than both of the values calculated below to satisfy both the transient loading and steady state ripple conditions as given by the following equation liNPUT RMS LOAD MAX X VstEP Ali GAD MAX and ESR lt Ripple EQ 9 Ripple ESR lt 2005 Fairchild Semiconductor Corpor
13. to the LDO can be from 1 5V to 5V respectively An internal shunt regulator at the VCC pin facilitates the controller operation from either a 5V or 12V power source Vcc Bias Supply FAN5069 can be configured to operate from 5V or 12V for Voc When 5V supply is used for Vcc no resistor is required to be connected between the supply and the Vcc When the 12V supply is used a resistor Rycc is connected between the 12V supply and the Vcc as shown in Figure 1 The internal shunt regulator at the VCC pin is capable of sinking 150mA of current to ensure that the controller s internal Voc is maintained at 5 6V maximum Choose a resistor such that m It is rated to handle the power dissipation m Current sunk within the controller is minimized to prevent IC temperature rise Rycc Selection IC The selection of Rycc is dependent on m Variation of the 12V supply m Gate charge of the top and bottom FETs Qrer m Switching frequency Fsw m Shunt regulator minimum current 1mA m Quiescent current of the IC la Calculate Rycc based on the minimum input voltage for the Vcc Vinyiy 5 6 EQ 1 la 1 10 Gret e Paw s 1 2 Rvcc For a typical example where Vinyin 11 5V lo 3mA Orgr 30nC Fsw 300KHz Rycc is calculated to be 398 650 PWM Section The FAN5069 s PWM controller combines the conven tional voltage mode control and current sensing through lower MOSFET Rpg ow to generate the PWM signals Th
14. 03 X7R 1 C16 Panasonic PCC332BNCT ND Connector Header 0 100 Vertical Tin 2 Pin 1 J1 Molex WM6436 ND Terminal Quickfit Male O52 Dia 187 Tab 6 J2 J7 Keystone 1212K ND Inductor 1 8uH 2096 26Amps Max 3 24mOhm 1 Li Inter Technical SC5018 1R8M MOSFET N CH 32 mO 20V 21A D PAK FSID FDD6530A 1 Q1 Fairchild Semiconductor FDD6530A MOSFET N CH 8 8 mO 30V 50A D PAK FSID FDD6296 1 Q2 Fairchild Semiconductor FDD6296 MOSFET N CH 6 mQ 30V 75A D PAK FSID FDD6606 2 Q3 Q4 Fairchild Semiconductor FDD6606 Resistor 5 11K 196 1 16W 1 R1 Panasonic P5 11KHCT ND Resistor 12 7K 196 1 16W 1 R2 Panasonic P12 7KHCT ND Resistor 8250 196 1 16W 1 R3 Panasonic P825HCT ND Resistor 49 9K 196 1 16W 1 R4 Panasonic P49 9KHCT ND Resistor 243K 1 1 16W 1 R5 Panasonic P243KHCT ND Resistor 453K 1 1 16W 1 R6 Panasonic P453KHCT ND Resistor 10K 1 1 16W 1 R7 Panasonic P10 0KHCT ND Resistor 4 99K 1 1 16W 1 R8 Panasonic P4 99KHCT ND Resistor 2209 196 1 4W 1 R9 Panasonic P200FCT ND Resistor 5 90K 1 1 16W 1 R10 Panasonic P5 90KHCT ND Resistor 2 20 1 1 4W 1 R11 Panasonic P2 2ECT ND Connector Header 0 100 Vertical Tin 1 Pin 3 TP1 TP2 Vcc Molex WM6436 ND IC System Regulator TSSOP16 FSID FAN5069 1 U1 Fairchild Semiconductor FAIRCHILD 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 19 www fairchildsemi com OquwoJ 49j 0 0uO07 OQ 1 DUS INMd 690SNVJ Typical Application Board Layout L
15. 05 Fairchild Semiconductor Corporation www fairchildsemi com FAN5069 Rev 1 1 5 5 OquwoJ 49jj0 11U0J OUT DUS INMd 690SNVJ Electrical Characteristics Continued Unless otherwise noted Vcc 5V Ta 25 C using circuit in Figure 1 The denotes that the specifications apply to the full ambient operating temperature range See Notes 4 and 5 Symbol Parameter Conditions Min Typ Max Unit Protection Disable IUM ILIMIT Source Current 9 10 11 LA Iswep ISW Pull down Current SW 1V EN 0V 2 mA Vuv Under Voltage Threshold As of set point 2uS noise fil 65 75 80 96 ter Voy Over Voltage Threshold As Yo of set point 2uS noise fil 110 115 120 96 ter TSD Thermal Shutdown 160 C Enable Threshold Voltage Enable Condition 2 0 V Enable Threshold Voltage Disable Condition 0 8 V Enable Source Current Vec BV 50 LA LDO Vi poner Reference Voltage mea T4 0 C to 70 C 775 800 825 mV sured at FBLDO pin T lt 40 C to 85 C e 770 800 830 mV Regulation OA lt li pap lt 5A 1 17 1 2 1 23 V Vipo po Drop out Voltage li oAp lt SA and Rps on lt 50mO 0 3 V External Gate Drive Voc 4 75V E 4 5 V Vec 5 6V 5 3 V Gate Drive Source Current 1 2 mA Gate Drive Sink Current 400 LA Notes 4 All limits at operating temperature extremes are guaranteed by design characterization and statistical quality control AC specificatio
16. 35 where M is the desired phase margin in degrees The feedback component values are calculated as given in equations below 2 K ran BS e EQ 36 1 C2 L 2xnx Feross Gawp x R1 EQ 37 C1 C2 x K 1 EQ 38 1 C3 _ EQ 39 2 qx Foross X J K x R3 R2 AK EQ 40 2 EL Feross X C1 R1 2005 Fairchild Semiconductor Corporation www fairchildsemi com FANS5069 Rev 1 1 5 17 oquio 7191107110023 OT PUE INMd 690SNVJH Design Tools Fairchild application note AN 6010 provides a PSPICE model and spreadsheet calculator for the PWM regula tor simplifying external component selections and verify ing loop stability The topics covered provide an understanding of the calculations in the spreadsheet The spreadsheet calculator which is part of AN 6010 can be used to calculate all external component values for designing around FAN5069 The spreadsheet pro vides optimized compensation components and gener ates a Bode Plot to ensure loop stability Based on the input values entered AN 6010 s PSPICE model can be used to simulate Bode Plots for loop sta bility as well as transient analysis to help customize the design for a wide range of applications Use Fairchild Application Note AN 6005 for prediction of the losses and die temperatures for the power semicon ductors used in the circuit AN 6010 and AN 6005 can be downloaded from www fairchildsemi com apnotes La
17. 5 7 Human Body Model and EIA JESD22C101 A Charge Device Model Thermal Information Symbol Parameter Min Typ Max Unit TsrG Storage Temperature 65 150 C TL Lead Soldering Temperature 10 Seconds 300 C Vapor Phase 60 Seconds 215 C Infrared 15 Seconds 220 C Pp Power Dissipation Ta 25 C 715 mW Oje Thermal Resistance Junction to Case 37 C W OJA Thermal Resistance Junction to Ambient 100 C W Notes 3 Junction to ambient thermal resistance 0 4 is a strong function of PCB material board thickness thickness and number of copper planes number of vias used diameter of vias used available copper surface and attached heat sink characteristics Recommended Operating Conditions Symbol Parameter Conditions Min Typ Max Unit Voc Supply Voltage Vcc to GND 4 5 5 0 5 5 V Commercial 10 85 C TA Ambient Temperature Industrial 40 85 C Ty Junction Temperature 125 C 2005 Fairchild Semiconductor Corporation www fairchildsemi com FAN5069 Rev 1 1 5 4 OquwoJ 49jj6 11U0J OUT PUE INMd 690SNVJ Electrical Characteristics Unless otherwise noted Vcc 5V Ta 25 C using circuit in Figure 1 The denotes that the specifications apply to the full ambient operating temperature range See Notes 4 and 5 Symbol Parameter Conditions Min Typ Max
18. All internal control voltages are referred to this pin Tie this pin to the ground island plane through the lowest impedance connection available 9 SW Switching Node Return for the high side MOSFET driver and a current sense input Connect to source of high side MOSFET and drain of low side MOSFET 10 HDRV _ High Side Gate Drive Output Connect to the gate of the high side power MOSFETs This pin is also monitored by the adaptive shoot through protection circuitry to determine when the high side MOSFET is turned off 11 BOOT _ Bootstrap Supply Input Provides a boosted voltage to the high side MOSFET driver Connect to bootstrap capacitor as shown in Figure 1 12 PGND Power Ground The return for the low side MOSFET driver Connect to the source of the low side MOSFET 13 LDRV Low Side Gate Drive Output Connect to the gate of the low side power MOSFETs This pin is also monitored by the adaptive shoot through protection circuitry to determine when the lower MOSFET is turned off 14 R RAMP Ramp Resistor A resistor from this pin to VIN sets the ramp amplitude and provides voltage feed forward 15 VCC VCC Provides bias power to the IC and the drive voltage for LDRV Bypass with a ceramic capacitor as close to this pin as possible This pin has a shunt regulator which draws current when the input voltage is above 5 6V 16 GLDO Gate Drive for the LDO Turned off low until SS is greater than 2 2V 2005 Fairchild Semico
19. S5069 Rev 1 1 5 2 OQUIOD 19 0 1uO OUT PUE INAAd 690SNV4 Pin Assignment FBLDO GLDO R T VCC ILIM R RAMP SS FAN5069 ED COMP PGND FB BOOT EN HDRV AGND SW Figure 2 Pin Assignment Pin Description Pin Name Description 1 FBLDO LDO Feedback This node is regulated to VREF 2 R T Oscillator Set Resistor This pin provides oscillator switching frequency adjustment By plac ing a resistor RT from this pin to GND the nominal 200kHz switching frequency is increased 3 ILIM Current Limit A resistor from this pin to GND sets the current limit 4 SS Soft Start A capacitor from this pin to GND programs the slew rate of the converter and the LDO during initialization It also sets the time by which the converter delays when restarting after a fault occurs SS has to reach 1 2V before fault shutdown feature is enabled The LDO is enabled when SS reaches 2 2V COMP COMP The output of the error amplifier drives this pin FB Feedback This pin is the inverting input of the internal error amplifier Use this pin in combi nation with the COMP pin to compensate the feedback loop of the converter 7 EN Enable Enables operation when pulled to logic high Toggling EN resets the regulator after a latched fault condition This is a CMOS input whose state is indeterminate if left open and needs to be properly biased at all times 8 AGND X Analog Ground The signal ground for IC
20. W node ringing frequency Fring with a low capacitance scope probe b Connect a capacitor Csnug from SW node to GND so that it reduces this ringing by half c Place a resistor Rgwup in series with this capacitor Rsnus is calculated using the following equation 2 EQ 17 TA Fring x Conus Rsnup d Calculate the power dissipated in the snubber resistor as shown in the following equation 2 PnisuuB Csnus Vincmaxy X Fsw EQ 18 where Vin max is the maximum input voltage and FSW is the converter switching frequency The snubber resistor chosen should be de rated to han dle the worst case power dissipation Do not use wire wound resistors for RsnuB Loop Compensation Typically the closed loop crossover frequency Fcross where the overall gain is unity should be selected to achieve optimal transient and steady state response to disturbances in line and load conditions It is recom mended to keep Feross below fifth of the switching fre quency of the converter Higher phase margin tends to have a more stable system with more sluggish response to load transients Optimum phase margin is about 60 a good compromise between steady state and transient responses A typical design should address variations over a wide range of load conditions and over a large sample of devices Reference Figure 24 Closed Loop System with Type 3 Network
21. ation FAN5069 Rev 1 1 5 13 www fairchildsemi com oquio 7191107110023 OT PUE INMd 690SNVJH In the case of aluminum and polymer based capacitors the output capacitance is typically higher than normally required to meet these requirements While selecting the ceramic capacitors for the output although lower ESR can be achieved easily higher capacitance values are required to meet the Youri restrictions during a load transient From the stability point of view the zero caused by the ESR of the output capacitor plays an important role in the stability of the converter Output Capacitor Selection LDO For stable operation the minimum capacitance of 100uF with ESR around 100mQ is recommended For other val ues contact the factory Power MOSFET Selection PWM The FAN5069 is capable of driving N Channel MOSFETs as circuit switch elements For better performance MOSFET selection must address these key parameters m The maximum Drain to Source Voltage Vps should be at least 25 higher than worst case input voltage m The MOSFETs should have low Qc Qep and Qes m The Rpg on Of the MOSFETs should be as low as possible In typical applications for a buck converter the duty cycles are lower than 20 To optimize the selection of MOSFETS for both the high side and low side follow dif ferent selection criteria Select the high side MOSFET to minimize the switching losses and the low side MOSFET to minimize the conduct
22. ication Board Schematic VIN 3to 24V Vour 1 5V at 20A 5V or 12V Vcc PWM OUT C7 A 022uF J7 LDO Out OF J6 560uF GND Bill of Materials FAN5069 R6 453K 3 24V mos CB 022uF L U C10 cj C6 Q2 QA4F 820uF 8204F PWM OUT L1 180H J4 e e FDD6606 FDD6606 Je 560yF 560uF 560uF O 1uF IE SW Out J5 LI GND 127k Figure 25 Application Board Schematic Part Description Quantity Designator Vendor Vendor Part Capacitor 1500pF 20 25V 0603 X7R 1 C1 Panasonic PCC1774CT ND Capacitor 220pF 5 50V 0603 NPO 1 C2 Panasonic PCC221ACVCT ND Capacitor 3300pF 1096 50V 0603 X7R 1 C3 Panasonic PCC1778CT ND Capacitor 0 1uF 10 25V 0603 X7R 4 C4 C5 C6 C15 Panasonic PCC2277CT ND Capacitor 0 22uF 20 25V 0603 X7R 2 C7 C8 Panasonic PCC1767CT ND Capacitor 0 01pF 1096 50V 0603 X7R 1 C9 Panasonic PCC1784CT ND Capacitor 820uF 20 10X20 25V 20mOhm 1 96A 2 C10 C11 Nippon Chemicon KZH25VB820MHJ20 Capacitor 820HF 20 8X8 2 5V 7mOhm 6 1A 1 C17 Nippon Chemicon PSC2 5VB820MH08 Capacitor 560uF 20 8X11 5 4V 7mOhm 5 58A 3 C12 C13 C14 Nippon Chemicon PSA4VB560MH11 Capacitor 3300pF 1096 50V 06
23. ion losses due to the channel and the body diode losses Note that the gate drive losses also affect the temperature rise on the controller For loss calculation refer to Fairchild s Application Note AN 6005 and the associated spreadsheet High Side Losses Losses in the MOSFET can be understood by following the switching interval of the MOSFET in Figure 22 MOS FET gate drive equivalent circuit is shown in Figure 23 a Ciss Ea Cap Cis V 1 DS Figure 22 Switching Losses and Qc VIN 5V Cool Ro HDRV Reate A VAVA al Ht Cos sw Figure 23 Drive Equivalent Circuit The upper graph in Figure 22 represents Drain to Source Voltage Vps and Drain Current Ip waveforms The lower graph details Gate to Source Voltage Vas vs time with a constant current charging the gate The x axis is representative of Gate Charge Qc Ciss Cap Cgs and it controls ti t2 and t4 timing Cap receives the current from the gate driver during t3 as Vpg is fall ing Obtain the gate charge Qg parameters shown on the lower graph from the MOSFET datasheets Assuming switching losses are about the same for both the rising edge and falling edge Q1 s switching losses occur during the shaded time when the MOSFET has voltage across it and current through it Losses are given by EQ 10 EQ 11 and EQ 12 Puppen Psw Pconp EQ 10 Vos gt li
24. ion of the inductor current Rps ow of the bottom FET and the gain of the current sense amplifier With the Rpg on method of current sensing the current limit can vary widely from unit to unit Rpg on not only varies from unit to unit but also has a typical junction temperature coefficient of about 0 4 C consult the MOSFET datasheet for actual values The set point of the actual current limit decreases in proportion to increase in MOSFET die tem perature A factor of 1 6 in the current limit set point typi cally compensates for all MOSFET Rpg oy variations assuming the MOSFET s heat sinking keeps its operat ing die temperature below 125 C For more accurate current limit setting use resistor sensing In a resistor sensing scheme an appropriate current sense resistor is connected between the source terminal of the bottom MOSFET and PGND Set the current limit by choosing Ri jy as follows 3 R 4934 E ax Roson 10 uiu aidh IM 1 43 Vin Fsw RRAMp EO 5 where Ry is in KO Imax is the maximum load current K1 is a constant to accommodate for the variation of With K1 1 6 Imax 20A Rps on 7MQ Vin 24V Vout 1 5V Fsw 300 KHz Rramp 400 KO Ry iy calculates to be 323 17KQ Auto Restart PWM The FAN5069 supports two modes of response when the internal fault latch is set The user can configure it to keep the power supply latched in the OFF state OR in the Auto Restart mode When the EN pin is tied
25. is method of current sensing is loss less and cost effective For more accurate current sense requirements an optional external resistor can be connected with the bottom MOSFET in series 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 10 www fairchildsemi com OQUIOD 19 0 1uO OUT PUE INAAd 690SNV4 PWM Operation Refer to Figure 20 for the PWM control mechanism The FAN5069 uses the summing mode method of control to generate the PWM pulses The amplified output of the current sense amplifier is summed with an internally generated ramp and the combined signal is amplified and compared with the output of the error amplifier to get the pulse width to drive the high side MOSFET The sensed current from the previous cycle is used to modu late the output of the summing block The output of the summing block is also compared against the voltage threshold set by the R jy resistor to limit the inductor cur rent on a cycle by cycle basis The controller facilitates external compensation for enhanced flexibility Initialization When the PWM is disabled the SW node is connected to GND through an internal 50000 MOSFET to slowly dis charge the output As long as the PWM controller is enabled this internal MOSFET remains OFF Soft Start PWM and LDO When Vcc exceeds the UVLO threshold and EN is high the circuit releases SS and enables the PWM regulator The capacitor connected to the SS pin and GND is
26. ltage 300 400 LOAD CURRENT A Figure 19 1 5V PWM Efficiency 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 www fairchildsemi com OQUIOD 19 0 1uO OU PUE INAAd 690SNV4 Block Diagram C im K Elo R U imil AAA ILIM 4 S Na i COMP FB I Amor S c4 HDRV 4 Vref tC eae Dine T Circuit Lo Vout osc SW 1 Co SS Current A LDRV A S Vin Reame Summing mpli L R RAMP Ampile POND Figure 20 Block Diagram Detailed Operation Description FAN5069 combines a high efficiency fixed frequency PWM controller designed for single phase synchronous buck Point Of Load converters with an integrated LDO controller to support GTL type loads This controller is ideally suited to deliver low voltage high current power supplies needed in desktop computers notebooks workstations and servers The controller comes with an integrated boot diode which helps reduce component cost and increase space savings With this controller the input to the power supply can be varied from 3V to 24V and the output voltage can be set to regulate at 0 8V to 15V on the switcher output The LDO output can be con figured to regulate between 0 8V to 3V and the input
27. m ee 1 e m Em m m va hh R so SSS Tr a pe FAIBCHILLU nana Fan 3B Figure 26 Assembly Diagram Figure 27 Top Layer Figure 28 Mid Layer 1 Figure 29 Mid Layer 2 Figure 30 Bottom Layer 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 20 www fairchildsemi com OquwoJ 49j 0 0u07 OQ 1 DUS INMd 690SNVJ Mechanical Dimensions Dimensions are in millimeters unless otherwise noted TSSOP 16 MP ee ven MINUI id Et 0 42 LL LAND PATTERN RECOMMENDATION GAGE PLANE Eus mm PLANE 0 8 0 6 0 1 IO 2ICTBIA DETAIL A ALL LEAD TIPS TYPICAL SCALE 40X PIN 1 IDENT SEE DETAIL A 0 90 e lap TIC ALL LEAD TIPS IR l Cf y 3 1 1 MAX TYP uA P T SN i L 0 10 0 05 TYP 0 09 0 20 TYP Figure 31 16 Lead TSSOP 2005 Fairchild Semiconductor Corporation www fairchildsemi com FAN5069 Rev 1 1 5 21 oquio 19j 0 3u0 OUT pUe INMd 690SNVJ TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks Programmable Active Droop DISCLAIMER LIFE SUPPORT POLICY As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life or c whose failure to perform when properly used in accordance
28. nd under voltage conditions All of these conditions generate an internal fault latch which shuts down the converter For all fault conditions both the high side and the low side drives are off except in the case of OVP where the low side MOSFET is turned on until the voltage on the FB pin goes below 0 4V The fault latch can be reset either by toggling the EN pin or recycling Vcc to the chip Over Current Limit PWM The PWM converter is protected against overloading through a cycle by cycle current limit set by selecting Rim resistor An internal 10A current source sets the threshold voltage for the output of the summing amplifier When the summing amplifier output exceeds this thresh old level the current limit comparator trips and the PWM starts skipping pulses If the current limit tripping occurs for 16 continuous clock cycles a fault latch is set and the controller shuts down the converter This shutdown fea 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 11 www fairchildsemi com oquio 7191107110023 OT PUE INMd 690SNVJH ture is disabled during the start up until the voltage on the SS capacitor crosses 1 2V To achieve current limit the FAN5069 monitors the inductor current during the OFF time by monitoring and holding the voltage across the lower MOSFET The volt age across the lower MOSFET is sensed between the PGND and the SW pins The output of the summing amplifier is a funct
29. nductor Corporation FANS5069 Rev 1 1 5 www fairchildsemi com oquio 1961107110023 OUT Pue INMd 690SNVJH Absolute Maximum Ratings The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings The Recommended Operating Conditions table defines the condi tions for actual device operation 1 Parameter Min Max Unit Vcc to PGND 6 0 V BOOT to PGND 33 0 V SW to PGND Continuous 0 5 33 0 V Transient t 50nS F 500kHz 3 0 33 0 V HDRV VBoor Vsw 6 0 V LDRV 0 5 6 0 V All Other Pins 0 3 Vcc 0 3 V Maximum Shunt Current for Voc 150 mA Electrostatic Discharge Protection ESD HBM 3 5 kV Level CDM 1 8 Notes 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Absolute maximum ratings apply individually only not in combination Unless otherwise specified all other voltages are referenced to AGND 2 Using Mil Std 883E method 301
30. ns guaranteed by design characterization not production tested For a case when Vcc is higher than the typical 5V Voc voltage observed at VCC pin when the internal shunt regulator is sinking current to keep voltage on VCC pin constant 7 Test Conditions Vipo IN 1 5V and Vi po our 1 2V 2005 Fairchild Semiconductor Corporation www fairchildsemi com FAN5069 Rev 1 1 5 6 Oqwo J 7191107110023 OT PUE INMd 690SNVJH Typical Performance Characteristics LOLLL BALL TT AD TTT T T TTTT T FANSOBSB Dead Time Raz Sas 32ns Cirici Piiii Li Liriitit M 200ns 2 5GS s A Ch4 9 6V ETE Figure 3 Dead Time Waveform rror rwT T T TT 44 rrr I FANSOG9B Transient Response V in 12 Vdd 5 lload 0 5A T T ry T T T T T T T T FANSO69B Transient Response V in 12 Ydd 5Y lload 0 154 Hoad piit n LA L M 200ys 2 5MSAS 400ns pt A Ch3 2 04 Ch1 50 0mv Bw Ch3 5 04 Q Bw Figure 6 PWM Load Transient 0 to 15A UR ERE UR EUER UR LU URL RR IRE AAA KANA REALES FA LEUR FANSOBSB Transient LDO Yin 42 dd SY lload 0 2A L ki iii Lu L 4 H Chi 50 0my Bw Ch3 2 04 Q Bw L LL Li L M 200us 25MS s 400nshpt A Ch3 204 Figure 4 PWM Load Transient 0 to 5A TT AA e FANSOG9B Transient Response Vin 12V Vdld 5V lload 0 104 Hoad lt tistittt La tiiritlittrstftt il H M200us2 5MS s 400nsipt A Ch3 2 0A Ch S50 0mY 4 B
31. onductor Corporation FAN5069 Rev 1 1 5 22 www fairchildsemi com oquio 49j 0 3u0 OUT Pue WMd 690SNVJ
32. ransient loading affects the selection of the inductor and the output capacitors Steady state loading affects the selection of MOSFETS input capacitors and other critical heat generating components The selection of switching frequency is challenging While higher switching frequency results in smaller com ponents it also results in lower efficiency Ideal selection of switching frequency takes into account the maximum operating voltage The MOSFET switching losses are directly proportional to Fsw and the square function of the input voltage When selecting the inductor consider the minimum and maximum load conditions Lower inductor values pro duce better transient response but result in higher ripple and lower efficiency due to high RMS currents Optimum minimum inductance value enables the converter to operate at the boundary of continuous and discontinuous conduction modes Setting the Output Voltage PWM The internal reference for the PWM controller is at 0 8V The output voltage of the PWM regulator can be set in the range of 0 8V to 90 of its power input by an exter nal resistor divider The output is divided down by an external voltage divider to the FB pin for example R1 and Rgias as in Figure 24 The output voltage is given by the following equation R1 Vour 08V x 14 S OUT Rpia To minimize noise pickup on this node keep the resistor to GND Rgias below 10KQ Inductor Selection PWM When the ripple
33. taneously conducting so the Vps 0 5V Since Psw is proportional to Vps Q2 s switching losses are negligible and Q2 is selected based on Rps on alone Conduction losses for Q2 are given by the equation Pgonp 1 D x lout x Rps ow EQ 15 where Rps oN is the RDs on of the MOSFET at the highest operating junction temperature and D VouT ViIN is the minimum duty cycle for the converter Since Dyn lt 20 for portable computers 1 D 1 pro duces a conservative result simplifying the calculation The maximum power dissipation Pp max is a function of the maximum allowable die temperature of the low side MOSFET the 0j4 and the maximum allowable ambient temperature rise Pp Max is calculated using the following equation T MA 7 Ta MAX OJA EQ 16 ja depends primarily on the amount of PCB area devoted to heat sinking Selection of MOSFET Snubber Circuit The Switch node SW ringing is caused by fast switch ing transitions due to the energy stored in the parasitic elements This ringing on the SW node couples to other circuits around the converter if they are not handled properly To dampen this ringing an R C snubber is con nected across the SW node and the source of the low side MOSFET PD MAX Current Sense Amplifier Ramp Generator Summing 2 Amplifier PWM amp DRIVER R C components for the snubber are selected as follows a Measure the S
34. to Voc the power supply is latched OFF When the EN pin is ter minated with a 100nF to GND the power supply is in Auto Restart mode The table below describes the rela tionship between PWM restart and setting on EN pin Do not leave the EN pin open without any capacitor EN Pin PWM Restart Pull to GND OFF Voc No restart after fault Cap to GND Restart after TDELAY Sec 0 85 x C where C is in uF The fault latch can also be reset by recycling the Vcc to the controller Under Voltage Protection PWM The PWM converter output is monitored constantly for under voltage at the FB pin If the voltage on the FB pin stays lower than 75 of internal Vref for 16 clock cycles the fault latch is set and the converter shuts down This shutdown feature is disabled during startup until the volt age on the SS capacitor reaches 1 2V Over Voltage Protection PWM The PWM converter output voltage is monitored con stantly at the FB pin for over voltage If the voltage on the FB pin stays higher than 115 of internal Vpep for two clock cycles the controller turns OFF the upper MOS FET and turns ON the lower MOSFET This crowbar action stops when the voltage on the FB pin reaches 0 4V to prevent the output voltage from becoming nega tive This over voltage protection OVP feature is active as soon as the voltage on the EN pin becomes high Turning ON the low side MOSFETs on an OVP condition pulls down the output res
35. ulting in a reverse current which starts to build up in the inductor If the output over voltage is due to failure of the high side MOSFET this crowbar action pulls down the input supply or blows its fuse protecting the system which is very critical During soft start if the output overshoots beyond 115 of Vper the output voltage is brought down by the low side MOSFET until the voltage on the FB pin goes below 0 4V The fault latch is NOT set until the voltage on the SS pin reaches 1 2V Once the fault latch is set the con verter shuts down 11596 Vref FB LS Drive Figure 21 Over Voltage Protection Thermal Fault Protection The FAN5069 features thermal protection where the IC temperature is monitored When the IC junction temper ature exceeds 160 C the controller shuts down and when the junction temperature gets down to 125 C the converter restarts 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 12 www fairchildsemi com OQUIOD 19 0 1uO OUT PUE INAAd 690SNV4 LDO Section The LDO controller is designed to provide ultra low volt ages as low as 0 8V for GTL type loads The regulating loop employs a very fast response feedback loop and small capacitors can be used to keep track of the chang ing output voltage during transients For stable opera tion the minimum capacitance on the output needs to be 100uF and the typical ESR needs to be around 100mQ
36. w Ch3 504 Q Bw Figure 5 PWM Load Transient 0 to 10A Cx bi Jp Py E Ti LT pp T Ch1 10 0m Bw M 200ys 2 5NIS s Ch3 104 Q Bw A Ch3 840m 400nsipt Figure 7 LDO Load Transient 0 to 2A TT Y rr morr FANSO69B Transient LDO Vin 12V vdd 5V lload 0 5A L LDOOUT E E T Li M 200ys 2 5MIS s 4D ns pt A Ch3 840mA Chi 10 0mY E Ch3 2 04 Q Bw Figure 8 LDO Load Transient 0 to 5A 2005 Fairchild Semiconductor Corporation FAN5069 Rev 1 1 5 www fairchildsemi com oquio 19j 0 3u0 OUT pUe WMd 690SNVJ Typical Performance Characteristics Continued aa a L aa LM A LALO BALL LS BALL MAL ML FANSOBSB Start Up vin 12Y vald SY lload 5A lldo 24 LDOOLIT SoftStart L La LL L L Lit rci E 3 3 Bh 1 La l ANY FANSOBSB Enable On vin 124 vod 5Y lload 5A do 2A LAA l rac ra daa aad aaaala iti Ch1 500mv Bw M 2 0ms 250kS s 4 0ps pt Ch1 500mY Ch3 2 04 Bw Chad 500mv Bw A Ch3 22V Ch3 500mv Figure 9 PWM LDO Power Up LvoUT FANSOBSB Shut Down Vinz12V vdd 5V lload 54 IIdo 24 VOUT Bw ch2 M400us 1 25MS s 800ns pt Bw A Ch2 22V Figure 12 Enable ON Ipwm 5A noon FANSOBSB Enable SoftStart Soft start 4 F s Lacy sl ea Fol TE et Fm Esca Ves Vk Pe TO et Te Ce L iti PTS TE et OT On Yen to T sil T lity icr D na Li LA 400nsipt Ch1 500mY Bw M
37. with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms ACEx FACT Quiet Series ocx SILENT SWITCHER UniFET ActiveArray GlobalOptoisolator OCXPro SMART START UltraFET Bottomless GTO OPTOLOGIC SPM VC X TN Build it Now HiSeC OPTOPLANAR Stealth Wire CoolFET cw PACMAN SuperFET CROSSVOLT i Lo POP SuperSOT 3 DOME ImpliedDisconnect Power247 SuperSOT 6 EcoSPARK IntelliMAX PowerEdge SuperSOT 8 E2cmos ISOPLANAR PowerSaver SyncFET EnSigna LittleFET PowerTrench TCM FACT MICROCOUPLER QFET TinyBoost FAST MicroFET QS TinyBuck FASTr MicroPak QT Optoelectronics TinyPWM FPS MICROWIRE Quiet Series TinyPower FRFET MSX RapidConfigure TinyLogic MSXPro RapidConnect TINYOPTO Across the board Around the world uSerDes TruTranslation The Power Franchise ScalarPump UHC FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE
38. yout Considerations The switching power converter layout needs careful attention and is critical to achieving low losses and clean and stable operation Below are specific recommenda tions for good board layout m Keep the high current traces and load connections as short as possible m Use thick copper boards whenever possible to achieve higher efficiency m Keep the loop area between the SW node low side MOSFET inductor and the output capacitor as small as possible m Route high dV dt signals such as SW node away from the error amplifier input output pins Keep com ponents connected to these pins close to the pins m Place ceramic de coupling capacitors very close to the VCC pin m All input signals are referenced with respect to AGND pin Dedicate one layer of the PCB for a GND plane Use at least four layers for the PCB m Minimize GND loops in the layout to avoid EMlI related issues m Use wide traces for the lower gate drive to keep the drive impedances low m Connect PGND directly to the lower MOSFET source pin m Use wide land areas with appropriate thermal vias to effectively remove heat from the MOSFETs m Use snubber circuits to minimize high frequency ring ing at the SW nodes m Place the output capacitor for the LDO close to the source of the LDO MOSFET 2005 Fairchild Semiconductor Corporation FANB5069 Rev 1 1 5 18 www fairchildsemi com OQUIOD 19 0 uO OU PUE INAAd 690SNV4 Appl
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FAIRCHILD FAN5069 Manual