FAIRCHILD FDMF6706B Manual
Contents
1. boot resistor RBoor may be required when operating Pin Vin X lin Vsv x Isv W 1 near the maximum rated Vin and is effective at Psw Vsw X lout W 2 controlling the high side MOSFET turn on slew rate and Pout Vour X lout W 3 VSHW overshoot Typical Rgoor values from 0 5 to p P Paw W 2 0VV are effective in reducing VSVVH overshoot Loss MoputE PIN Psw W 4 Doss soappchw Pour W 5 EFFuopute 100 x Psw Pin 70 6 EFFgoarp 100 x Pout Pin 7 V v A A Vu Isv RvciN Ke lin CVDRV CvcIN CViN VDRV VCIN A DISB DISB o PWM BOOT L AAA WE FDMF 706B CaooT ah ZCD_EN 77 m lour KIK A A Open PHASE Lour Ke Drain 7 SC V Output SS V Vsw Cour D S Bees 274 Figure 27 Block Diagram With Von Filter Va A T A Vin ee a lin CVDR CvIN VDRV VCIN VIN SE DISB DISB Resor PWM or Input mu FDMF6706B eR umasa d vSWH lout a BET wi Lee 7 uer Lour ka Drain Hu Output e a V Va Cour T per ZZ ZZ Figure 28 Power Loss Measurement 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 lnpol SOWA A u nb ld ubiH upuMOH d DIH lleu S e11X3 90Z94INGS VVVVVV fairchildsemi com PCB Layout Guidelines Figure 29 provides an example of a proper layout for the2. 2011 Fairchild Semiconductor Corporation www fairchildsemi com FDMF6706B Rev 1 0 1 19
3. Delay Vit_pwu to 90 GH t PWM HIGH Propagation PWM going HIGH to GH going HIGH 30 PD PHGHH Delay SMOD Held LOW ViH pwuto 10 GH SMOD LOW t Exiting 3 State Propagation PVVM From 3 State going HIGH to GH 30 de PD TSGHH 1 Delay going HIGH Vu pwu to 10 GH Lovv Side Driver aen er Output Impedance Sourcing Source Gureni T0mA B ri Ja Romca ouput medence Bing sene 0s fo SW going LOW to GL going HIGH HS to LS Deadband Time 2 2V SW to 10 GL 12 ns t PWM HIGH Propagation PWM going HIGH to GL going LOW 25 Ps Delay Vum Gay to 90 GL t Exiting 3 State Propagation PWM From 3 State going LOW to GL 20 PD TSOLH Delay going HIGH Vu pwu to 10 GL 9INPOW SOWA A u nb l ubiH upuMOH d DIH lleu S e11X3 90Z94INGS Boot Diode Vr Forward Votage Dop open Jul iv Va Breakcown Votage o lim sl lv O 2011 Fairchild Semiconductor Corporation VVVVVV fairchildsemi com FDMF6706B Rev 1 0 1 7 FDMF6706B Extra Small High Performance High Frequency DrMOS Module 5 o 2 e E ul vw e Fo f a Cc O l LO N l I EE N PPN m l Ge e l a U LU eg AS l sl EE S 32 Z m z zm sm G O CH n amp Q a UTU n i 5 O E D Figure 5 90 D DEADON M rd VVVVVV fairchildsemi com 2011 Fairchild Semiconductor Corporation FDMF6706B gt Rev 1 0
4. FDMF6706B and critical components All of the high current paths such as Vin VsvvH Vout and GND copper should be short and wide for low inductance and resistance This technique achieves a more stable and evenly distributed current flow along with enhanced heat radiation and system performance The following guidelines are recommendations for the PCB designer 1 Input ceramic bypass capacitors must be placed close to the VIN and PGND pins This helps reduce the high current power loop inductance and the input current ripple induced by the power MOSFET switching operation 2 The VswH copper trace serves two purposes In addition to being the high frequency current path from the DrMOS package to the output inductor it also serves as a heat sink for the low side MOSFET in the DrMOS package The trace should be short and wide enough to present a low impedance path for the high frequency high current flow between the DrMOS and inductor to minimize losses and temperature rise Note that the VSWH node is a high voltage and high frequency switching node with high noise potential Care should be taken to minimize coupling to adjacent traces Since this copper trace also acts as a heat sink for the lower FET balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission 3 An output inductor should be located close to the FDMF6706B to minimize the power loss due to the VSWH copper tra
5. Each part is capable of driving speeds up to 1MHz VCIN and Disable DISB The VCIN pin is monitored by an Under Voltage Lockout UVLO circuit When Von rises above 3 1V the driver is enabled When Voen falls below 2 7V the driver is disabled GH GL 0 The driver can also be disabled by pulling the DISB pin LOW DISB lt Vu piss which holds both GL and GH LOW regardless of the PWM input state The driver can be enabled by raising the DISB pin voltage HIGH DISB gt Vu DISB Table 1 UVLO and Disable Logic Three State PVVM input The FDMF6706B incorporates a three state 3 3V PWM input gate drive design The Three state gate drive has both logic H GH level and LOW level along with a 3 state shutdovvn vvindovv VVhen the PVVM input signal enters and remains within the three state window for a defined hold off time tp HoLp orF both GL and GH are pulled LOVV This feature enables the gate drive to shut down both high and low side MOSFETs to support features such as phase shedding a common feature on multi phase voltage regulators Exiting Three State Condition When exiting a valid three state condition the FDMF6706B design follows the PWM input command If the PWM input goes from three state to LOW the low side MOSFET is turned on If the PWM input goes from 3 state to HIGH the high side MOSFET is turned on as illustrated in Figure 25 The FDMF6 06B design allows for short propagation delays when exiting the
6. Mode This mode allovvs for gating on the lovv side FET VVhen the SMOD pin is pulled LOW the lovv side FET is gated off If the SMOD pin is connected to the PWM controller the controller can actively enable or disable SMOD when the controller detects light load condition from output current sensing This pin is active LOW See Figure 26 for timing delays SMOD Vu ww A VIL pww PVVM GH to VSVVH VSVVH GL e be rm zm pm rem em rm em rm rm pm rm rem pm Sachi oe ai et fae an Figure 26 O 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 I I I Sa 4 l I I I ti hel 207 pD PHGLL e nen ze b yt gt x b DEADON b DEADOFF Delay from SMOD going LOW to LS Ves LOW Table 2 SMOD Logic Note 4 The SMOD feature is intended to have low propagation delay between the SMOD signal and the low side FET Ves response time to control diode emulation on a cycle by cycle basis 9INPOW SOWA A u nb l ubiH upuMOH d DIH lleu S e11Xx3 4902941444 i EE gt e tpp SLGLL tPD_PHGHH top sHGLH Delay from SMOD going HIGH to LS Vgs HIGH HS turn on with SMOD LOW SMOD Timing Diagram VVVVVV fairchildsemi com Application information Suppiy Capacitor Selection For the supply inputs VDRV amp VCIN a local ceramic bypass capacitor is r
7. full traceability meet Fairchild s quality standards for handling and storage and provide access to Fairchilds full range of up to date technical and product information Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status fini 05 Datasheet contains the design specifications for product development Specifications may change Advance Information Formative In Design in any manner without notice Preliminary First Production Datasheet contains prelimin ary data supplementary data will be published ata later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design Ne identification Needed Full Production Datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor Obsolete Not In Production The datasheet is for reference information only Rev 161
8. lovv inductance Critical high frequency components such as Regoor CeBoor the RC snubber and bypass capacitors should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB If this is not feasible they should be connected from the backside through a network of low inductance vias 9INPOW SOWA A u nb l ubiH Sueuuloji q u BiH lleu S e1X3 4902941444 www fairchildsemi com m n Top Vievv O 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 Figure 29 PCB Layout Example Bottom View lnpoly SOWA A u nb l4 ubiH supuHMOH d DIH lieu S e11x3 g90Z94INGS VVVVVV fairchildsemi com Tl m g Physical Dimensions D b B PIN 1 9 gt 0 1 INDICATOR 2X CTA 5 80 m i A 4 50 g
9. three state window see Electrical Characteristics UVLO DISB Driver State 0 Disabled GH GL 0 1 A Disabled GH GL 0 Enabled See Table 2 Disabled GH GL 0 Low Side Driver The low side driver GL is designed to drive a ground Note 3 DISB internal pull down current source is 10HA Thermal Warning Flag THWN The FDMF6706B provides a thermal warning flag THWN to advise of over temperature conditions The thermal warning flag uses an open drain output that pulls to CGND when the activation temperature 150 C is reached The THWN output returns to high impedance state once the temperature falls to the reset temperature 135 C The THWN output requires a pull up resistor which can be connected to VCIN THWN does NOT disable the DrMOS module 135 C Reset 150 C referenced low Rpsiony N channel MOSFET The bias for GL is internally connected between VDRV and CGND When the driver is enabled the driver s output is 180 out of phase with the PWM input When the driver is disabled DISB OV GL is held LOW High Side Driver The high side driver is designed to drive a floating N channel MOSFET The bias voltage for the high side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor CBoor During startup Vswn is held at PGND allowing CBoor to charge to Vprv through the internal diode When the PWM input goes HIGH GH
10. 1 Typical Performance Characteristics Test Conditions Vin 12V Vour 1 0V Vcin 5V Vorv 5V Lovurz320nH Ta 25 C and natural convection cooling unless otherwise specified o ae Hu j N j A TL Vin 12V Vout 1 0V Opce 3 5 C W _ o Module Output current lour A Module Power Loss W o sch N oo A Wu c N co 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 PCB Temperature C Output Current lour A Figure 6 4 Safe Operating Area Figure 7 Module Povver Loss vs Output Current Normalized Module Povver Loss Normalized Module Povver Loss 200 300 400 500 600 700 800 900 1000 Module Switching Frequency fsw kHz 5 6 7 8 9 10 11 12 13 14 15 Module Input Voltage Vn V Figure 8 Power Loss vs Switching Frequency Figure 9 Power Loss vs Input Voltage inpol SOWA A u nb lzq ubiH Sueuuloji9q uBiH lleu S e11X3 4902941444 Normalized Module Power Loss Normalized Module Power Loss 4 50 4 75 5 00 5 25 5 50 0 5 1 0 1 5 2 0 2 5 3 0 3 5 Driver Supply Voltage Vpav and Ven V Output Voltage Vour V Figure 10 Power Loss vs Driver Supply Voltage Figure 11 Power Loss vs Output Voltage 2011 Fairchild Semiconductor Corporation www fairchildsemi com FDMF6706B Rev 1 0 1 9 Typical Performance Characteristics Continued Test Conditions Vin 12V Vout 1 0V Vcixz5V Vporv 5V Lour 320nH Ta 25 C and natural convection cooling unless oth
11. 20nH Ta 25 C and natural convection cooling unless otherwise specified SMOD Threshold Voltage V 4 50 4 75 5 00 5 25 5 50 Driver Supply Voltage Ven V Figure 18 SMOD Thresholds vs Driver Supply Voltage SMOD Pull up Current Ip y uA Driver IC Junction Temperature T C Figure 20 SMOD Pull Up Current vs Temperature Vu oss DISB Threshold Voltage V 4 50 4 75 5 00 5 25 5 50 Driver Supply Voltage Von V Figure 22 Disable Thresholds vs Temperature 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 11 ViL stop SMOD Threshold Voltage V Driver IC Junction Temperature C Figure 19 SMOD Thresholds vs Temperature m E a e ea ee ee eas Laer LI ll ves 1 8 1 DISB Threshold Voltage V Driver IC Junction Temperature T C lnpol SOWA Su nb 1igd uBiH Sueuuioji 9q uBiH lieu S e11X3g 4902941444 Figure 21 Disable Thresholds vs Driver Supply Voltage 12 0 11 5 11 0 P DISB Pull down Current Ip p UA 50 25 0 25 50 75 100 125 150 Driver IC Junction Temperature C Figure 23 Disable Pull Down Current vs Temperature www fairchildsemi com Functional Description The FDMF6706B is a driver plus FET module optimized for the synchronous buck converter topology A single PVVM input signal is all that is required to properly drive the high side and the lovv side MOSFE Ts
12. 40 os 6o v Vow ae ecg TPR nem ecoso os feo v Ee SES Reterencedtoceno os 250 v VGH High Gate Manufacturing Test Pin EE Ve PHASE Referencedtoco os so v Referenced to PGND CGND DC Onw 03 250 V _ ne Tag F h v ESCHER Referenced to VDRV 20 zl vv x Ra Output Current 27 Reference 7 5 55 source not found fsw 1MHz SES ESCH OV ME oms Juneionto POB Thermal Resisans 0 Las em T Ambient Temperature bag alle a GS LES ear sen pe ESD Etectostatc Discharge Protection Human Body Model JESD22 A114 2000 ESD Electrostatic Discharge Protection Charged Device Model JESD22 C101 1000 Note 1 l o av is rated using Fairchild s DrMOS evaluation board Ta 25 C natural convection cooling This rating is limited by the peak DrMOS temperature Ty 150 C and varies depending on operating conditions and PCB layout This rating can be changed with different application settings lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lo AV lt lnpoy soluq Su nb iqd uBiH 95u euuioji q uBiH lieuuS e1xd d90294WG4 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications Fairchild does not recommend exceeding them or designing t
13. E FAIRCHILD aS Sa SEMICONDUCTOR March 2012 FDMF6706B Extra Small High Performance High Frequency DrMOS Module Benefits Ultra Compact 6x6mm DOEN 72 Space Saving Compared to Conventional Discrete Solutions Fully Optimized System Efficiency m Clean Switching Waveforms with Minimal Ringing High Current Handling Features m Over 93 Peak Efficiency High Current Handling of 45A High Performance DOEN Copper Clip Package 3 State 3 3V PWM Input Driver Skip Mode SMOD Low Side Gate Turn Off Input m Thermal Warning Flag for Over Temperature Condition Driver Output Disable Function DISB Pin RH Internal Pull Up and Pull Down for SMOD and DISB Inputs Respectively m Fairchild PowerTrench Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing m FPairchild SyncFET Integrated Schottky Diode Technology in the Low Side MOSFET Integrated Bootstrap Schottky Diode Adaptive Gate Drive Timing for Shoot Through Protection Under Voltage Lockout UVLO RH Optimized for Switching Frequencies up to 1MHz Lovv Profile SMD Package Fairchild Green Packaging and ROHS Compliance Based on the Intel 4 0 DrMOS Standard Ordering Information Description The XS DrMOS family is Fairchild s next generation fully optimized ultra compact integrated MOSFET plus driver power stage solution for high current high frequency synchronous buck DC DC applicatio
14. ENT i STEALTH uSerDes MicroPak SuperF ET MicroPak2 P Fairchild Miller Drive SuperSOT 3 fies Fairchild Semiconductor MotionMax SuperSOT 6 UHC FACT Quiet Series Motion SPMT SuperSOT 8 Ultra FRFET EACT WS SupreMOS UniFET FAST cars SyncFET VC FastvCore m Sync Lock VisualMax FETBench he ee BAL VoltagePlus FlashWriter xs FPS a Trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN L FE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance
15. OH d UDIH Iews e1x3 4902944 Typical Application Circuit lnpoly SOWA A u nb ld ubiH upuMOH d DIH lieu S e11X3 4902941444 V V IN 3V 15V CVpRv Cyn VDRV VCIN VIN ee DISB DISB Reoor BOOT PWM Input PWM Ceoor 2 FDMF6706B ON SMODE VSVVH V e Vour L Open Drain Pawns Output C m OUT 7 CGND PGND e SE Figure 1 Typical Application Circuit DrMOS Block Diagram VDRV BOOT VIN EE oooO VCIN UVLO B d Q1 HS Povver a DBoot MOSFET 1 Gen DISBH GH OH 8277 207 H 30kQ SC Ven PHASE Rup_PwM Dead Time m Input Control R S o VSWH PVVM 3 State Logic RDN PWM E Vorv 5 zur b GL v ZV A E GL Logic THWN Get Von 30kQ Ce Fe T
16. OUT is longer than D DEADOFF I I I I I ua AERA TH KEE T ee WE lnpol SOWA A u nb ld ubiH upuMOH d DIH lleuuS e11X3 4902941444 Ii k i gt gt lt lt gt q y gt lt pp PHGLL tpo pen R e tr ei tpo rssuH b HOLD OFF pp rssuH Jess than p HoLD OFF tpp TSGLH zu i i u 2 b HOLD OFF gt ole gt lt T il 1 f il p DEADON b DEADOFF Enter Exit Enter Exit Enter Exit 3 State 3 State 3 State 3 State 3 State 3 State Example tpp pusu PWM going HIGH to LS Ves GL going LOW Example tp prapon LS Ves GL LOW to HS Ves GH HIGH Exiting 3 state pp TsGHH PWM 3 state to HIGH to HS Ves rise Vin_pwm to 10 HS Ves pp reen PWM 3 state to LOW to LS Ves rise Vi pwu to 10 LS Ves Dead Times p peapon LS Vas fall to HS Ves rise LS comp trip value 1 0V GL to 10 HS Ves p peaporr VSVVH fall to LS Ves rise SW comp trip value 2 2V VSWH to 10 LS Ves PWM and 3 StateTiming Diagram www fairchildsemi com 13 Skip Mode SMOD The SMOD function allovvs higher converter efficiency under light load conditions During SMOD the low side FET gate signal is disabled held LOVV preventing discharging of the output capacitors as the filter inductor current attempts reverse current flovv also knovvn as Diode Emulation Mode When the SMOD pin is pulled HIGH the synchronous buck converter vvill vvork in Synchronous
17. ance 1 e e Van PWM HighLevelVotage 1 zo z s iz v lnpol SOWA A u nb l ubiH upuMOH d DIH lleu S e11X3 4902941444 Vu PVVM PWM Low Level Voltage o o O TE 57 t Propadation Dela PWM GND Delay Between DISB from PD_DISBL pag y HIGH to LOW to GL from HIGH to LOW PWM GND Delay Between DISB from ko nenn Propagation Delay LOW to HIGH to GL from LOW to HIGH 25 ml i Provada Del PWM GND Delay Between SMOD from pag y HIGH to LOW to GL from HIGH to LOW l PWM GND Delay Between SMOD from Fp susi Propagation Delay LOW to HIGH to GL from LOW to HIGH 19 Continued on the following page On co On cO ns S n ns S n O 2011 Fairchild Semiconductor Corporation VVVVVV fairchildsemi com FDMF6706B Rev 1 0 1 6 Electrical Characteristics Typical values are Vin 12V Ven 5V Vorv V and TA 25 C unless otherwise noted Sinbo Parameter Condton os Tip max Unit Ter Activation Temperature 1 00 ll Ter ResetTempan 1 T i T C Fun Pul Dosn Resistance nama 00 Lal iq 250ns Timeout Circuit SW O0V Delay Between GH from HIGH to terme our HIMEOUL Delay LOW and GL from LOW to HIGH SE High Side Driver Ross Output impedance Seeerei Til la EES EES GL going LOW to GH going HIGH LS to HS Deadband Time 1V GL to 10 GH 10 ns t PWM LOW Propagation PWM going LOW to GH going LOW 16 30 PD PLOFL
18. ay pp pHcLL Once the GL pin is discharged below TV Q1 turns on after adaptive delay p DEADON Vin_pwm PWM less than D HOLD OFF T ie Notes pp xxx propagation delay from external signal PWM SMOD etc to IC generated signal p xx delay from IC generated signal to IC generated signal PWM tep pusu PWM rise to LS Vas fall Vi piyi to 90 LS Ves tpp pen PWM fall to HS Vas fall Vu pwu to 90 HS Vas tpp pucuy PWM rise to HS Vas rise Vik puvu to 10 HS Ves SMOD held LOW SMOD pp stet SMOD fall to LS Ves fall Vit_smop to 90 LS Ves pp enen SMOD rise to LS Ves rise Vum won to 1096 LS Ves Figure 25 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 tou OLD OFF T To prevent overlap during the HIGH to LOW transition Q1 off to Q2 on the adaptive circuitry monitors the voltage at the VSWH pin When the PWM signal goes LOW Q1 turns off after a propagation delay tPp_PLGHL Once the VSWH pin falls below 2 2V Q2 turns on after adaptive delay p peaporr Additionally Vesiq is monitored When Ves as is discharged below 1 2V a secondary adaptive delay is initiated that results in Q2 being driven on after tp timeout regardless of VSWH state This function ensures Cpoor is recharged each svvitching cycle in the event that the VSVVH voltage does not fall belovv the 2 2V adaptive threshold Secondary delay D TIME
19. begins to charge the gate of the high side W ature Activation MOSFET Q1 During this transition the charge is HIGH Temperature removed from Ceoor and delivered to the gate of Q1 As Q1 turns on Vswu rises to Vin forcing the BOOT TWN pin to Vin VBoor which provides sufficient Ves Logic Normal Thermal enhancement for Q1 To complete the switching cycle State Operation Warning Q1 is turned off by pulling GH to Vswu CBoor S then LOW TJ driver IC Figure 24 THVVN Operation 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 recharged to Vpopv when Vswu falls to PGND GH output is in phase with the PWM input The high side gate is held LOW when the driver is disabled or the PWM signal is held within the three state window for longer than the three state hold off time tp HOLD OFF 9INPOW SOWA A u nb l ubiH Sueuuloji q u BiH lleu S e1X3 4902941444 www fairchildsemi com Adaptive Gate Drive Circuit The driver IC design ensures minimum MOSFET dead time vvhile eliminating potential shoot through cross conduction currents t senses the state of the MOSFETs and adjusts the gate drive adaptively to prevent simultaneous conduction Figure 25 provides the relevant timing waveforms To prevent overlap during the LOW to HIGH switching transition Q2 off to Q1 on the adaptive circuitry monitors the voltage at the GL pin When the PWM signal goes HIGH Q2 turns off after a propagation del
20. ce Care should also be taken so the inductor dissipation does not heat the DrMOS 4 PowerTrench MOSFETs are used in the output stage The power MOSFETs are effective at minimizing ringing due to fast switching In most cases no VSWH snubber is required If a snubber is used it should be placed close to the VSWH and PGND pins The resistor and capacitor need to be of proper size for the power dissipation 5 VCIN VDRV and BOOT capacitors should be placed as close as possible to the VCIN to CGND VDRV to CGND and BOOT to PHASE pins to ensure clean and stable power Routing width and length should be considered 6 Include a trace from PHASE to VSWH to improve noise margin Keep the trace as short as possible 7 The layout should include a place holder to insert a small value series boot resistor RBoor between the 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 boot capacitor Cgoot and DrMOS BOOT pin The BOOT to VSWH loop size including RBoor and Caoor should be as small as possible The boot resistor may be required when operating near the maximum rated Vin The boot resistor is effective at controlling the high side MOSFET turn on slew rate and VSHW overshoot Rgoot can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSWH ringing However inserting a boot resistance lowers the DrMOS efficiency Efficiency vers
21. emp LS Power MOSFET Sense 10HA 6 50 CGND SMOD PGND Figure 2 DrMOS Block Diagram 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 www fairchildsemi com Pin Configuration PVVM Se 1401 r 9 DISB THWN B CGND re oL VSVVH VSVVH Lo VSWH Lo VSWH E VSVVH 7 o o gt gt PGND Qo a z Z o o D D PGND PGND Q z o a PGND Q z o a Figure 3 Bottom View Figure 4 Top View Pin emt Ten Description 7 SMOD HIGH the low side driver is the inverse of PWM input When SMOD LOW SMODt the low side driver is disabled This pin has a 10HA internal pull up current source Do not add a noise filter capacitor PE VCIN IC bias supply Minimum 1HF ceramic capacitor is recommended from this pin to CGND 3 VDRV Power for gate driver Minimum 1uF ceramic capacitor is recommended connected as close as possible from this pin to CGND 4 BOOT Bootstrap supply input Provides voltage supply to the high side MOSFET driver Connect a bootstrap capacitor from this pin to PHASE 5 37 41 CGND IC ground Ground return for driver IC 6 GH For manufacturing test only This pin must float must not be connected to any pin PHASE Switch node pin for bootstrap capacitor routing Electrically shorted to VSWH pin NC No connect The pin is not electrically connected internally but can be connected to VIN for convenience Switch node in
22. equired to reduce noise and to supply peak transient currents during gate drive switching action t is recommended to use a minimum capacitor value of 1uF X7R or X5R Keep this capacitor close to the VCIN and VDRV pins and connect it to the GND plane vvith vias Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor Cgoot as shown in Figure 28 A capacitance of 100nF X7R or X5R capacitor is typically adequate A series bootstrap resistor may be needed for specific applications to improve svvitching noise immunity The VCIN Filter The VDRV pin provides povver to the gate drive of the high side and lovv side power MOSFETs In most cases VDRV can be connected directly to VCIN which supplies power to the logic circuitry of the gate driver For additional noise immunity an RC filter can be inserted between VDRV and VCIN Recommended values of 100 Rvcin placed between VDRV and VCIN and 1HF Cycin from VCIN to CGND Figure 27 Power Loss and Efficiency Measurement and Calculation Refer to Figure 28 for power loss testing method Power loss calculations are
23. erwise specified Vin 12V lour 30A few 300kHz Vin 12V lour OA fey 300kHz o np Normalized Module Povver Loss mmh o mmh Driver Supply Current ypRv Ivcin mA 1 00 0 99 0 98 225 275 325 375 425 200 400 600 800 1000 Output Inductance Lour nH Module Switching Frequency fsw KHz Figure 12 Power Loss vs Output Inductance Figure 13 Driver Supply Current vs Frequency sch Wu Vin 12V lout 0A fow 300kHz A C 12 Driver Supply Current ypav Ivcin mA Normalized Driver Supply Current 11 4 50 4 75 5 00 5 25 5 50 Driver Supply Voltage Vpav amp Ven V Module Output Current La A Figure 14 Driver Supply Current vs Driver Figure 15 Driver Supply Current vs Output Current Supply Voltage lnpol SOWA A u nb lz ubiH upuMOH d DIH lleu S e11X3 4902941444 2 5 T gt uu P 2 0 VIRU HI S e gt 15 cm S KE PM KE o l ur sl 0 5 e z O ooo n 0 0 4 50 4 75 5 00 5 25 5 50 50 25 0 25 50 75 100 125 150 Driver Supply Voltage Ven V Driver IC Junction Temperature T C Figure 16 PWM Thresholds vs Driver Supply Voltage Figure 17 PWM Thresholds vs Temperature 2011 Fairchild Semiconductor Corporation www fairchildsemi com FDMF6706B Rev 1 0 1 10 Typical Performance Characteristics Continued Test Conditions Vin 12V Vout 1 0V Vein 5V Vporv 5V Lour 3
24. ns The FDMF6706B integrates a driver IC two power MOSFETs and a bootstrap Schottky diode into a thermally enhanced ultra compact 6x6mm DOEN package With an integrated approach the complete switching power stage is optimized for driver and MOSFET dynamic performance system inductance and power MOSFET Robson XS DrMOS uses Fairchild s high performance PowerTrench MOSFET technology which dramatically reduces switch ringing eliminating the snubber circuit in most buck converter applications A new driver IC with reduced dead times and propagation delays further enhances performance A thermal warning function warns of potential over temperature situations FDMF6 06B also incorporates features such as Skip Mode SMOD for improved light load efficiency along with a Three state 3 3V PWM input for compatibility with a wide range of PWM controllers Applications High Performance Gaming Motherboards Compact Blade Servers V Core and Non V Core DC DC Converters Desktop Computers V Core and Non V Core DC DC Converters Workstations m High Current DC DC Point of Load POL Converters Networking and Telecom Microprocessor Voltage Regulators m Small Form Factor Voltage Regulator Modules 45A 40 Lead Clipbond PQFN DrMOS 6 0mm x 6 0mm Package FDMF 7O6B 2011 Fairchild Semiconductor Corporation FDMF6706B Rev 1 0 1 VVVVVV fairchildsemi com lnpolW soluq A u nb l4 biH up uL
25. ns do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings htto www fairchildsemi con packaging 2011 Fairchild Semiconductor Corporation www fairchildsemi com FDMF6706B Rev 1 0 1 18 Ee FAIRCHILD SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such trademarks 2Cool F PFS PowerTrench The Power Franchise AccuPower FRFET PowerxS the AX CAP Global Power Resource Programmable Active Droop p Wer Bitsic GreenBridge QFET TinyBoost Build it Now Green FPS Qs TinyBuck CorePLUS Green FPS e Series Quiet Series TinvCale CorePOWER Gmax RapidConfigure TinyLogic TEL R o TINYOPTO ik j TM CTL f intelli Saving our world 1mVVA V KVV at a time T TinyPower Current Transfer Logic ISOPLANAR SignalWise TinyPWM DEUXPEED Making Small Speakers Sound Louder SmartMax TinyWire Dual Cool and Better fle SMART START TranSiC EcoSPARK MegaBuck Soluti ni ge utions for Your Success TriFault Detect EfficientMax MICROCOUPLER e Espi MicroFET SPM TRUECURR
26. o Absolute Maximum Ratings Control Circuit Supply Voltage Gate Drive Circuit Supply Voltage Vum Output Stage Supply Voltage l 15 0 Error Reference source not Note 2011 Fairchild Semiconductor Corporation www fairchildsemi com FDMF6706B Rev 1 0 1 4 2 Operating at high Vin can create excessive AC overshoots on the VSVVH to GND and BOOT to GND nodes during MOSFET switching transients For reliable DrMOS operation VSVVH to GND and BOOT to GND must remain at or below the Absolute Maximum Ratings shown in the table above Refer to the Application Information and PCB Layout Guldelines sections of this datasheet for additional information lnpoli SOWA A u nb l ubiH upuMOH d DIH lieu S e11X3 4902941444 O 2011 Fairchild Semiconductor Corporation VVVVVV fairchildsemi com FDMF6706B Rev 1 0 1 5 Electrical Characteristics Typical values are Vin 12V Ven 5V Vporv V and TA 25 C unless otherwise noted symbol Parameter Cono os Typ max Unit Mom Monsees 1 v iv PWM Input Von Vpnv 5V 1096 Bn PukUp m sin 1 TT m e Ben PukDownimpedance 1 v e Van PWM High LevelVotage ramilz s s v vun neier eg 1 rs 22 2 v Vino este Lower oyossil HB v Vics PWM Low Levei votas 10 oszlosluslv ioo State Shutorttime 1 Vml m rs Ven 3 Stato Open votage 1800 r l limiv bt PukUp impedance 10 J zl lm pen PukDownimped
27. put Provides return for high side bootstrapped driver and acts as a sense point 35 43 for the adaptive shoot through protection e a centers THWN Thermal warning flag open collector output When temperature exceeds the trip limit the output is pulled LOW THWN does not disable the module Output disable When LOW this pin disables the power MOSFET switching GH and GL are DISB held LOW This pin has a 10HA internal pull down current source Do not add a noise filter lnpol SOWA Su nb 1igd u BiH Sueuuioji9q uBiH lieuuS e11X3 90Z94INGS capacitor 40 PWM PWM signal input This pin accepts a Three state 3 3V PWM signal from the controller 2011 Fairchild Semiconductor Corporation www fairchildsemi com FDMF6706B Rev 1 0 1 3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended In addition extended exposure to stresses above the recommended operating conditions may affect device reliability The absolute maximum ratings are stress ratings only EE Ven Supply Votage N Reference 6640 ls v C Vow Drive Votage R feroncedto 6640 1 os so v Vases Output Disable o R ferncedto 6640 os so v Venu PWM Signaling Referencedtoceno os so v Vevos Skip Mode npt o R feroncedto 66
28. t Z C 30 21 m 31 20 6 00 3 2 50 Sex o 0 65 0 25 l 1 1 60 O Co js s F 14 5 40 Re SC 3 I 10 o TOP VIEVV Ve SEE 0 60 0 35 L DETAIL A 0 50 TYP 015 o 2 10 3 2 10 o i LAND PATTERN FRONT VIEW oun C A B RECOMMENDATION o 4 4040 10 0 05 C T 2 20 _ JEO 5 D p 21 300 20 40X L TU LU LUL L 31 Ti 0 50 205 D 0 70 E 0 20 z z 1 PIN INDICATOR s l E CH 1 5040 10 0 50 E TTT 030 OX lt 40 AED 0 40 10 1 I 2 00 0 10 201 O 0 20 H 0 50 dr 0 20 NOTES UNLESS OTHERVVISE SPECIFIED A DOES NOT FULLY CONFORM TO JEDEC C REGISTRATION MO 220 DATED c Ge MAY 2005 o B ALL DIMENSIONS ARE IN MILLIMETERS z C DIMENSIONS DO NOT INCLUDE BURRS 0 10 C OR MOLD FLASH MOLD FLASH OR BURRS DOES NOT EXCEED 0 10MM D DIMENSIONING AND TOLERANCING PER Z e ASME Y14 5M 1994 0 08 C 0 30 0 05 c E DRAWING FILE NAME PQFN40AREV2 SEATING DETAIL A PLANE SCALE 2 1 Figure 30 40 Lead Clipbond PQFN DrMOS 6 0x6 0mm Package Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specificatio
29. us noise trade offs must be considered Rgoort values from 0 5 to 2 09 are typically effective in reducing VSWH overshoot The VIN and PGND pins handle large current transients with frequency components gt 100MHZz If possible these pins should be connected directly to the VIN and board GND planes The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing GND pad and PGND pins should be connected to the GND plane copper with multiple vias for stable grounding Poor grounding can create a noise transient offset voltage level between CGND and PGND This could lead to faulty operation of the gate driver and MOSFETs Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor Do not add an additional BOOT to the PGND capacitor This may lead to excess current flow through the BOOT diode 10 The SMOD and DISB pins have weak internal 1 pull up and pull dovvn current sources respectively These pins should not have any noise filter capacitors Do not to float these pins unless absolutely necessary Use multiple vias on each copper area to interconnect top inner and bottom layers to help distribute current flovv and heat conduction Vias should be relatively large and of reasonably
30. with instructions for use provided in the labeling can be reasonably expected to result in a significant injury of the user 2 A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness inpoly SOWA A u nb l4 ubiH upuHMOH d UDIH lieu S e1x3 8902941444 ANTI COUNTERFEITING POLICY Fairchild Semiconductor Corporation s Anti Counterfeiting Policy Fairchild s Anti Counterfeiting Policy is also stated on our extemal website www fairchildsemi com under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry All manufacturers of semiconductor products are experiencing counterfeiting of their parts Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation substandard performance failed applications and increased cost of production and manufacturing delays Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts have
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FAIRCHILD FDMF6706B Manual