FAIRCHILD Applying Fairchild Power Switch (FPS ) FSBH-series to Standby Auxiliary Power Supply handbook
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1. Lu sw PK 49 0 295 0 78A Al Ibs Lepe EF Ip 3mo 2 za 3 0 49 0 295 STEP 5 Choose the Proper FPS Considering Input Power and Peak Drain Current With the resulting maximum peak drain current of the MOSFET Ips from Equation 8 choose the proper FPS for which the pulse by pulse current limit level lzm is higher than Ing Since FPS has 10 tolerance of Izm there should be some margin when choosing the proper FPS device The FSBH series lineup with power ratings is summarized in Table 2 2009 Fairchild Semiconductor Corporation Rev 1 0 1 9 18 09 APPLICATION NOTE Table 2 Lineup of FSBH Series with Power Ratings Maximum Output Power for luim Universal Input Range and Open Frame Design Example FSBH0370 is selected STEP 6 Determine the Minimum Primary Turns With a given core the minimum number of turns for the transformer primary side to avoid core saturation is given by Ne L Lulim 10 12 SAT A where A is the cross sectional area of the core in mm py is the pulse by pulse current limit level and Bs4r is the saturation flux density in Tesla The pulse by pulse current limit level is included in Equation 12 because the inductor current reaches the pulse by pulse current limit level during the load transient or overload condition Error Reference source not found shows the typical characteristics of ferrite core from TDK PC40 S2. where Izm is the pulse by pulse current limit and Vp 4 is the feedback saturation voltage which is typically 3 2V As described in step 4 it is typical to design the flyback converter to operate in CCM for heavy load condition For CCM operation the control to output transfer function of a flyback converter using current mode control is given by G KR Viy Np N U s a 1 s p 7 a Eo where R is the load resistance and the pole and zeros of Equation 21 are obtained as 1 R d D O gt 5 0 O f DL N IN i _d D R C RZ R Co Where D is the duty cycle of the FPS and Rc is the ESR of Co Notice that there is a right half plane RHP zero rz in the control to output transfer function of Equation 21 Because the RHP zero reduces the phase by 90 degrees the crossover frequency should be placed below the RHP zero 2009 Fairchild Semiconductor Corporation Rev 1 0 1 9 18 09 APPLICATION NOTE Figure 7 shows the variation of a CCM flyback converter control to output transfer function for different input voltages This figure shows the system poles and zeros together with the DC gain change for different input voltages The gain is highest at the high input voltage condition and the RHP zero is lowest at the low input voltage condition 40 dB Jne e 20 dB m High input voltage AA 20 dB E 4 a 40 dB 1 Hz 1 OHz 1O0Hz IkHz lOkHz 100kHz Figure 7 CC M F
3. Pin S F Wire Turns Winding Method Insulation Polyester Tape t 0 025mm 1 Layer Insulation Polyester Tape t 0 025mm 2 Layers Insulation Polyester Tape t 0 025mm 2 Layers Insulation Polyester Tape t 0 025mm 2 Layers Specifications Remark 2009 Fairchild Semiconductor Corporation www fairchildsemi com Rev 1 0 1 9 18 09 9 AN 8024 APPLICATION NOTE Related Datasheets FSBHOF70A FSBHO170 A FSBH0270 A FSBH0370 Green Mode Fairchild Power Switch FPS DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which 2 Accritical component is any component of a life support device a are intended for surgical implant into the body or b or system whose failure to perform can be reasonably support or sustain life or c whose failure to perform when expected to cause the failure of the life support devic
4. SS aa FAIRCHILD E SEMICONDUCTOR AN 8024 www fairchildsemi com Applying Fairchild Power Switch FPS FSBH series to Standby Auxiliary Power Supply 1 Introduction The highly integrated FSBH series consists of an integrated current mode Pulse Width Modulator PWM and an avalanche rugged 700V SenseFET It is specifically designed for high performance offline Switch Mode Power Supplies SMPS with minimal external components The integrated PWM controller features include a proprietary green mode function that provides off time modulation to linearly decrease the switching frequency at light load conditions to minimize standby power consumption The PWM controller is manufactured using the BICMOS process to further reduce power consumption The green and burst modes function with a low operating current 2 5mA in green mode to maximize the light load efficiency so that the power supply can meet stringent standby power regulations Reni Lo 4LLL LAA C o1 Coo The FSBH series has built in synchronized slope compensation to achieve stable peak current mode control The proprietary external line compensation ensures constant output power limit over a wide AC input voltage range from 90V ac to 264V ac and helps optimize the power stage Many protection functions such as open loop overload protection OLP over voltage protection OVP brownout protection and over temperature protection OTP are fully in
5. Vro _ 373 5 0 5 100 5 25 5V STEP 4 Determine the Transformer Primary Side Inductance Lm The transformer primary side inductance is determined for the minimum input voltage and nominal load condition With the Dmax from step 3 the primary side inductance Ly of the transformer is obtained as On Pre M 2P wd sw Kpr where fsw is the switching frequency and Kpr is the ripple factor at minimum input voltage and nominal load condition defined as shown in Figure 4 The ripple factor is closely related with the transformer size and the RMS value of the MOSFET current Even though the conduction loss in the MOSFET can be reduced by reducing the ripple factor too small a ripple factor forces an increase in 7 www fairchildsemi com AN 8024 transformer size From a practical point of view it is reasonable to set Kpr 0 3 0 6 for the universal input range and Kpr 0 4 0 8 for the European input range Once Ly is calculated by determining Kpr from Equation 7 the peak current and RMS current of the MOSFET for minimum input voltage and nominal load condition are obtained as Al a eee a 8 io RMS _ 3 I PO a gt Pex MAX 9 T where Te d 10 a Dax MIN and AI Vin Pax 11 Design Example Determining the ripple factor as 0 6 Vue Dux 13 0 477 M 2P x fey Kar 2 26 100x10 0 6 900 uH Po ___ 26 a nS 0 47 M Da _ 113 0 47 900 x 107 100x10 0 49A lene T AI 0 594
6. d be determined by a trade off between the voltage stresses of MOSFET and diode Especially for low output voltage application the rectifier diode forward voltage drop is a dominant factor determining the power supply efficiency Therefore the reflected output voltage should be determined such that rectifier diode forward voltage can be minimized Table 1 shows the forward voltage drops for Schottky diodes with different voltage ratings Because the actual drain voltage and diode voltage rise above the nominal voltage due to the leakage inductance of the transformer as shown in O it is typical to set Vro such that Vp and Vpo l are 60 70 of voltage ratings of MOSFET and diode respectively 2009 Fairchild Semiconductor Corporation Rev 1 0 1 9 18 09 APPLICATION NOTE Table 1 Diode Forward Voltage Drop for Different Voltage Ratings 3A Schottky Diode Design Example As can be seen in Table 1 it is necessary to use a rectifier diode with 40V voltage rating to maximize efficiency Assuming that the nominal voltages of MOSFET and diode are less than 68 of their voltage rating the reflected output voltage is given as V NOM eo Vo tyr ip Vo Vro 37 O een RO ieee 6 0 5 No 22 2 Ving V A V peo lt 0 68 700 476 gt Vro lt 476 373 lt 103V By determining Vpro as 100V to ___1 Bye 100 113 DD RO MAX MIN Vro Vin Vig V V9 373 100 473V Viger Vw Vo V n V
7. e or properly used in accordance with instructions for use provided system or to affect its safety or effectiveness in the labeling can be reasonably expected to result in significant injury to the user 2009 Fairchild Semiconductor Corporation www fairchildsemi com Rev 1 0 1 9 18 09 10
8. e with a diameter larger than 1mm to avoid severe eddy current losses as well as to make winding easier For high current output it is better to use parallel windings with multiple strands of thinner wire to minimize skin effect Design Example The RMS current of primary side i winding is obtained from step 4 as 0 36A The RMS current of secondary side winding is calculated as 1 D Re ai 5 MAX MAX 1 0 4 18 18 0 36 ai 6 9A 47 0 3mm 5A mm and 0 65mmx2 10A mm diameter _ wires are selected for primary and secondary windings _ respectively STEP 9 Choose the Rectifier Diode in the Secondary Side Based on the Voltage and Current Ratings The maximum reverse voltage and the RMS current of the rectifier diode are obtained as V MAX io oa rrr 16 n D n Pw 17 Dax www fairchildsSemi com AN 8024 The typical voltage and current margins for the rectifier diode are Ver gt L 3 V no 18 ae sid ke 19 where Vrry is the maximum reverse voltage and Ip is the current rating of the diode Design Example The diode voltage and current are calculated as Two 5A and 40V diodes in parallel are selected for the rectifier diode STEP 10 Feedback Circuit Configuration Since FSBH series employs current mode control the feedback loop can be implemented with a one pole and one zero compensation circuit The current control factor of FPS K is defined as z Lim lim 20 SAT
9. esulting Np is larger than Np obtained from Equation 12 The number of turns for the auxiliary winding for Vpp supply is determined as N Po N 14 Vogt ee where Vpp is the nominal value of the supply voltage and Vz is the forward voltage drop of Dpp as defined in Figure 6 Since Vpp increases as the output load increases it is proper to set Vpp at 3 5V higher than Vpp UVLO level 8V to avoid the over voltage protection condition during the peak load operation VF Do Ns Vo Figure 6 Simplified Transformer Diagram 2009 Fairchild Semiconductor Corporation Rev 1 0 1 9 18 09 APPLICATION NOTE Design Example Assuming the diode forward voltage drop is 0 5V the turn ratio is obtained as Np Vro _ 100 Ne Vo V 5 0 5 Then determine the proper integer for Ns such that the resulting Np is larger than Np as l N 8 Np n N 146 gt N Setting Poo as 15V the number of turns for the auxiliary winding is obtained as Vion V 15 1 2 Vat Vy oS 540 5 18 18 8 24 Ne STEP 8 Determine the Wire Diameter for Each Winding Based on the RMS Current of Winding The maximum RMS current of the secondary winding is obtained as lS Dux D RMS __ RMS sec n Ips 15 The current density is typically 3 5A mm when the wire is long gt 1m When the wire is short with a small number of turns a current density of 5 10A mm is also acceptable Avoid using wir
10. ince the saturation flux density Bs47 decreases as the temperature increases the high temperature characteristics should be considered If there is no reference data use Bway 0 3 T Magnetization Curves typical Material PC40 S00 400 300 200 Flux density B mT 100 0 S00 Magnetic field H A m Figure 5 Typical B H Characteristics of Ferrite Core TDK PC40 1600 www fairchildsemi com AN 8024 RSUEUEOUEUSODEGEUSEEGEODEEGEADEOESESEEOESESSEOEOESEOEGEEGEOEOEESEOESEESEOEOUESBSESUESOSOSSSUDEOESEEDEDESEEOEOESESGEOESESESESESOEOSSEEGEOROREGEODOEGBSRSG ESBS DESESBADES ESOS OESES SSUES ES OEOESESOESESESOEOSSSSOEORGESOEOEOSSOESEOOEOES EOS EOEEOES Design Example EEL 19 core is selected whose effective cross sectional area is 25mm Choosing the saturation flux density as 0 3 T the minimum number of turns for the primary side is obtained as Lu Lim x 10 B SAT A _ 900x10 1 2 0 3 25 STEP 7 Determine the Number of Turns for Each Winding ymn p 10 144 Figure 6 shows the simplified diagram of the transformer First calculate the turn ratio n between the primary side and the secondary side from the reflected output voltage determined in step 3 as n ep no 13 Ns V where Np and Ns are the number of turns for primary side and secondary side respectively Vo is the output voltage and Vpr is the diode Dg forward voltage drop Then determine the proper integer for Ns such that the r
11. lt Vorn Ves 7 arate as Lice 1x10 1x10 The minimum cathode current for KA431 is ImA lt Voro 1 2kQ a ixo 1kQ resistor is selected for Rgs The voltage divider resistors R and R for Vo sensing are selected as 20kQ and 20kQ STEP 11 Design Input Voltage Sensing Circuit Figure 10 shows a resistive voltage divider with low pass filter for line voltage detection of the VIN pin The Vj voltage is used for brownout protection which triggers when the V voltage drops below 0 6V A 500ms debounce time is introduced for brownout protection to prevent false triggering by the voltage ripple on the input capacitor FSBH series devices start up when the Vy voltage reaches 1 1V It is typical to use 100 1 voltage divider for Vzy level Voc FSBHOx70 Brown In Out Figure 10 Input Voltage Sensing www fairchildsSemi com AN 8024 Design Summary APPLICATION NOTE Figure 11 shows the final schematic of the 20W power supply of the design example BD1 2A 600V ZY ZZZ7 00 Rsni Csni S Cc gt gt C gt Cc OD C gt Cc OD C OD lt gt gt FR103 Dpp eO S ZZZZ 221 F n Cop Ri ey i 20k 10nF N IC3 KA431 20kl R3 Figure 11 Final Schematic of Design Example 2009 Fairchild Semiconductor Corporation Rev 1 0 1 9 18 09 www fairchildsemi com AN 8024 APPLICATION NOTE Figure 12 Transformer Specification Core EEL 19 Ae 25mm Bobbin EEL 19
12. lyback Converter Control to Output Trans fer Function Variation for Different Input Voltages Figure 8 shows the variation of a CCM flyback converter control to output transfer function for different loads This figure shows that the low frequency gain does not change for different loads and the RHP zero is lowest at the full load condition Light load Hz LOHz lOkKHz lOOHz IkHz 100KHz Figure 8 CCM Flyback Converter Control to Output Transfer Function Variation for Different Loads When the input voltage and the load current vary over a wide range it 1s not easy to determine the worst case for the feedback loop design The gain together with zeros and poles vary according to the operating conditions Moreover even though the converter is designed to operate in CCM or at the boundary of DCM and CCM in the minimum input voltage and full load condition the converter enters into DCM www fairchildsemi com AN 8024 changing the system transfer functions as the load current decreases and or input voltage increases One simple and practical way to address this problem is designing the feedback loop for low input voltage and full load condition with enough phase and gain margin When the converter operates in CCM the RHP zero is lowest in low input voltage and full load condition The gain increases only about 6dB as the operating condition is changed from the lowest input voltage to the highest input voltage condition u
13. maximize efficiency In this section a design procedure is presented using Figure 1 as a reference An offline SMPS with 20W 5V nominal output power has been selected as a design example STEP 1 Define the System Specifications When designing a power supply with peak load current profile the following specifications should be determined M Line voltage range Vie and Vine Line frequency f E Nominal output power Po E Estimated efficiencies for nominal load 7 The power conversion efficiency must be estimated to calculate the input powers for nominal load condition If no reference data is available set 7 0 7 0 75 for low voltage output applications and 7 0 8 0 85 for high voltage output applications With the estimated efficiency the input power for peak load condition is given by Design Example The specifications of the target system are Vime 90V ac and Vime 264VAC e Line frequency f 60Hz 90V ac and 50Hz 264V ac e Nominal output power Po 20W 5V 4A e Estimated efficiency 77 0 77 15 20 2009 Fairchild Semiconductor Corporation Rev 1 0 1 9 18 09 APPLICATION NOTE STEP 2 Determine the Input Capacitor Cm and the Input Voltage Range It is typical to select the input capacitor as 2 3uF per watt of peak input power for universal input range 85 265 V and luF per watt of peak input power for European input range 195V 265V ac With the input capacitor chosen the mi
14. nder universal input condition When the operating mode changes from CCM to DCM the RHP zero disappears making the system stable Therefore by designing the feedback loop with more than 45 degrees phase margin in low input voltage and full load condition the stability over all the operating ranges can be guaranteed Figure 9 is a typical feedback circuit mainly consisting of a shunt regulator and a photo coupler R and R form a voltage divider for output voltage regulation Rp and Cp are adjusted for control loop compensation The maximum source current of the FB pin is about ImA The phototransistor must be capable of sinking this current to pull the FB level down at no load The value of Rp is determined as fo Koero Tea CTR gt I 22 D where Vopp is the drop voltage of the photodiode about 1 2V Vga is the minimum cathode to anode voltage of KA431 2 5V and CTR is the current transfer rate of the opto coupler Figure 9 Feedback Circuit 2009 Fairchild Semiconductor Corporation Rev 1 0 1 9 18 09 APPLICATION NOTE The feedback compensation network transfer function of Figure 9 is obtained as Yep Or Lt sl Oe 23 V s l1 s 0c where O Rep Oro to and RR C CR PA JC 1 Op PC RoC rg and Rpg is the equivalent feedback bias resistor of FSBH series 5kQ and R Rp Rr Crand Crg are shown in Figure 10 Design Example Assuming CTR is 100 Vo Vor Va OTR gt 1x10 D R
15. nimum input capacitor voltage at nominal load condition is obtained as 2 Fy A Den C sdi Vo W 2 Vine 2 where Dcy is the input capacitor charging duty ratio defined as shown in Figure 2 which is typically about 0 2 The maximum input capacitor voltage is given as Lo i V2 re a 3 Minimum Input Capacitor Input Capacitor Voltage Den ty te 0 2 Figure 2 Input Capacitor Voltage Waveform Design Example By choosing 100uF capacitor for input capacitor the minimum input voltages for nominal load is obtained as P d D Va 2 Fa an i cH IN JE _ fy go 2E 00D 113V 100x10 60 The maximum input voltage is obtained as P a 2 264 373V STEP 3 Determine the Reflected Output Voltage Vro When the MOSFET is turned off the input voltage Vm together with the output voltage reflected to the primary Vro are imposed across the MOSFET as shown in 0 With a given Vpro the maximum duty cycle Dyy y and the maximum nominal MOSFET voltage Vos my are obtained as y Dux 4 MAX a i CL www fairchildsemi com AN 8024 E _ y Max V 5 MAX pa Vw AVENE y 6 Vro Figure 3 Output Voltage Reflected to the Primary As can be seen in Equation 5 the voltage stress across MOSFET can be reduced by reducing Vro This however increases the voltage stresses on the rectifier diodes in the secondary side as shown in Equation 6 Therefore Vro shoul
16. tegrated into FSBH series which improves the SMPS reliability without increasing the system cost This application note presents design consideration to apply FSBH series to a standby auxiliary power supply with single output It covers designing the transformer selecting the components feedback loop design and design tips to maximize efficiency For multi output applications refer to Fairchild application note AN 4137 Cony Dop Figure 1 Typical Application Circuit 2009 Fairchild Semiconductor Corporation Rev 1 0 1 9 18 09 www fairchildsSemi com AN 8024 2 Design Considerations Flyback converters have two kinds of operation modes Continuous Conduction Mode CCM and Discontinuous Conduction Mode DCM CCM and DCM each has advantages and disadvantages In general DCM provides better switching conditions for the rectifier diodes since the diodes are operating at zero current just before becoming reverse biased and the reverse recovery loss is minimized The transformer size can be reduced using DCM because the average energy storage is low compared to CCM However DCM inherently causes high RMS current which increases the conduction loss of the MOSFET severely for low line condition Thus especially for standby auxiliary power supply applications with low output voltage where Schottky diode without reverse recovery can be used it is typical to design the converter such that the converter operates in CCM to
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FAIRCHILD Applying Fairchild Power Switch (FPS ) FSBH series to Standby Auxiliary Power Supply handb