FAIRCHILD FSQ0565RS FSQ0565RQ Green-Mode Fairchild Power Switch (FPS ) for Quasi-Resonant Operation -Low EMI High Efficiency handbook
Contents
1. Figure 42 6 Lead TO 220 Package L Forming specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http www fairchildsemi com packaging 2 74 2 34 10 36 0 70 A 9 96 a 6 88 PC 1 E Jes 3 40 2 OO n i 3 08 d O O 16 08 15 68 17 83 O 21 01 Ll 1 13 pe ly i IL R1 00 1 30 dal 0 85 i 1 05 l 0 75 9PLCS 2 6 y 0 65 R1 00 6PLCS H H Ly aes Ltrs 1 6 l 13 Lo T 479 6PLCS 2 19 e 175 3 18 0 46 7310 05 C T2 10 200 AB 3 81 5 a pa 5 NOTES A NO PACKAGE STANDARD APPLIES B DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS i C DIMENSIONS ARE IN MILLIMETERS dh 4 80 D DRAWING FILENAME MKT T0220E06REV1 4 40 Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchi2. Sync Vstr Vcc Drain 5 6 3 1 AVS osc C gt i 5 es Viet dass l Vcc good H Voc Veet Bust En pr JLILTL 8V 12V ldetay Ire FB PWM 3R s Q 4 4 Soft LEB P gt Gats R T a2 driver Start 250ns RQ ton lt tosP y after SS e de xS Ly Vosp LPF e AOCP Ly 1 2 Vsp TSD S q Voce n Nu 1 1V sr OND Vec LPF RQ D gt VovP qa gt Vcc good 7 FSQ0565RS Rev 00 Figure 2 Internal Block Diagram of FSQ0565RS Sync Vstr Vcc Drain 5 6 3 1 E AVS osc gt x aei 0350 55 Mat Veo good Voc Ver Yew Ds JLIL TL 8V 12V laetay T FB di 3R PWM so 4 Si xe R Soft L Lg driver E Start 250ns 9 be ton lt tosp y after SS A e go Vosp LPF s A AOCP T Ly e2 Vsp TSD S Q Voce SEN 5 dvi V4 GND LPF R Q Vove pS i Vcc good pH FSQ0565RQ Rev 0
3. Ee FAIRCHILD AAA SEMICONDUCTOR FSQ0565RS RQ December 2009 Green Mode Fairchild Power Switch FPS for Quasi Resonant Operation Low EMI and High Efficiency Features m Optimized for Quasi Resonant Converters QRC m Low EMI through Variable Frequency Control and AVS Alternating Valley Switching m High Efficiency through Minimum Voltage Switching m Narrow Frequency Variation Range over Wide Load and Input Voltage Variation m Advanced Burst Mode Operation for Low Standby Power Consumption m Simple Scheme for Sync Voltage Detection m Pulse by Pulse Current Limit m Various Protection Functions Overload Protection OLP Over Voltage Protection OVP Internal Thermal Shutdown TSD with Hysteresis Output Short Protection OSP m Under Voltage Lockout UVLO with Hysteresis m Internal Startup Circuit m Internal High Voltage Sense FET 650V m Built in Soft Start 17 5ms Applications m Power Supply for LCD TV and Monitor VCR SVR STB and DVD amp DVD Recorder m Adapter Related Resources Visit http www fairchildsemi com apnotes for m AN 4134 Design Guidelines for Offline Forward Converters Using Fairchild Power Switch FPS m AN 4137 Design Guidelines for Offline Flyback Converters Using Fairchild Power Switch FPS m AN 4140 Transformer Design Consideration for Offline Flyback Converters Using Fairchild Power Switch FPS m AN 4141 Troubleshooting and Design Tips
4. R203 C205 18kQ 47nF m i 1301 VONT FOD817A R205 8kQ Figure 39 Demo Circuit of FSQ0565RS 2008 Fairchild Semiconductor Corporation www fairchildsemi com FSQO0565RS RQ Rev 1 0 3 18 uone4edo JUBUOSAY ISENH 104 w Sd YOUMS 19MOg pIIuoueJ epo y uea4e O3 SNS9500S3 2 Transformer FSQ0565RS EER3016 FSQ0565RS Rev 0 0 Rev 0 0 N Top 1 14V XXXXXXXXXXX gt A N N N N 2 2 _eeeee KXXXXXXXXXXXXXX TR KXXXXXXXXXXXXXX i CX XX XXXXXxxxxxxx2 _ 0000000000000000 Na 4 N 2 SR XXXXXXXXXXJ Dry Y YY PPP PPP ES Bottom Figure 40 Transformer Schematic Diagram of FSQ0565RS 3 Winding Specification Position No Pin sf Wire Turns Winding Method Top Insulation Polyester Tape t 0 025mm 4 Layers Np 2 2 gt 1 0 40 x 1 10 Center Solenoid Winding Insulation Polyester Tape t 0 025mm 2 Layers Na 455 0 150 x 1 7 Center Solenoid Winding Insulation Polyester Tape t 0 025mm 2 Layers Nsy 76 0 4 x 3 TIW 3 Solenoid Winding Insulation Polyester Tape t 0 025mm 2 Layers Nsy 8 gt 6 0 4 x 3 TIW 3 Solenoid Winding Insulation Polyester Tape t 0 025mm 2 Layers N44v 2 108 0 4 x 3 TIW 5 Solenoid Winding Insulation Polyester Tape t 0 025mm 2 Layers Bottom Np 2 3 gt 2 0 4 x 1 32 Two Layer Solenoid Winding 4 Electrical Characteristics Pin Specification Remarks Inductanc
5. To overcome these problems FSQ series employs a frequency limit function as shown in Figures 35 and 36 Once the SenseFET is turned on the next turn on is prohibited during the blanking time tg After the blanking time the controller finds the valley within the detection time window tyy and turns on the MOSFET as shown in Figures 35 and Figure 36 Cases A B and C If no valley is found during ty the internal SenseFET is forced to turn on at the end of ty Case D Therefore the devices have a minimum switching frequency of 48kHz and a maximum switching frequency of 67kHz 8 AVS Alternating Valley Switching Due to the quasi resonant operation with limited frequency the Switching frequency varies depending on input voltage load transition and so on At high input voltage the switching on time is relatively small compared to low input voltage The input voltage variance is small and the Switching frequency modulation width becomes small To improve the EMI performance AVS is enabled when input voltage is high and the switching on time is small Internally quasi resonant operation is divided into two categories one is first valley switching and the other is second valley switching after blanking time In AVS two successive occurrences of first valley switching and the other two successive occurrences of second valley switching is alternatively selected to maximize frequency modulation As depicted in Figure 36 the swit
6. 50ms delay time is typical for most applications FSQ0565 Rev 00 Ves Overload protection t27 Cn 6 0 2 5 laeiay Ta Ta GAA Figure 30 Overload Protection 4 2 Abnormal Over Current Protection AOCP When the secondary rectifier diodes or the transformer pins are shorted a steep current with extremely high di dt can flow through the SenseFET during the LEB time Even though the FSQ series has overload protection it is not enough to protect the FSQ series in that abnormal case since severe current stress is imposed on the SenseFET until OLP triggers The FSQ series has an internal AOCP circuit shown in Figure 31 When the gate turn on signal is applied to the power SenseFET the AOCP block is enabled and monitors the current through the sensing resistor The voltage across the resistor is compared with a preset AOCP level If the sensing resistor voltage is greater than the AOCP level the set signal is applied to the latch resulting in the shutdown of the SMPS i FSQ0765R Rev 00 Figure 31 Abnormal Over Current Protection 4 3 Output Short Protection OSP If the output is shorted steep current with extremely high di dt can flow through the SenseFET during the LEB time Such a steep current brings high voltage stress on the drain of SenseFET when turned off To protect the device from such an abnormal condition OSP is included in the FSQ series It is comprised of detecting Vrg and SenseFET t
7. instructions for use provided in the labeling can be reasonably safety or effectiveness expected to result in a significant injury of the user ANTI COUNTERFEITING POLICY Fairchild Semiconductor Corporation s Anti Counterfeiting Policy Fairchild s Anti Counterfeiting Policy is also stated on our external website www fairchildsemi com under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry All manufacturers of semiconductor products are experiencing counterfeiting of their parts Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation substandard performance failed applications and increased cost of production and manufacturing delays Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts have full traceability meet Fairchild s quality standards for handling and storage and provide access to Fairchild s full range of up to date technical and product information Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty iss
8. 0 Figure 3 Internal Block Diagram of FSQ0565RQ 2008 Fairchild Semiconductor Corporation www fairchildsemi com FSQO0565RS RQ Rev 1 0 3 3 uone1edo jueuosesrIseno 10 wi SdJ YOUMS 19MOG puse Y SPO A USIID OY SUS9SODSA Pin Definitions Pin Configuration 6 Vstr 5 Sync 4 FB 3 Vec 2 GND 1 Drain FSQ0565 Rev 00 Figure 4 Pin Configuration Top View Pin A Name Description 1 Drain SenseFET Drain High voltage power SenseFET drain connection 2 GND Ground This pin is the control ground and the SenseFET source 3 V Power Supply This pin is the positive supply input providing internal operating current for CC both startup and steady state operation Feedback This pin is internally connected to the inverting input of the PWM comparator The 4 FB collector of an opto coupler is typically tied to this pin For stable operation a capacitor should be placed between this pin and GND If the voltage of this pin reaches 6V the overload protection triggers which shuts down the FPS 5 Se Sync This pin is internally connected to the sync detect comparator for quasi resonant switch y ing In normal quasi resonant operation the threshold of the sync comparator is 1 2V 1 0V Startup This pin is connected directly or through a resistor to the high voltage DC link At 6 V startup the internal high voltage current source supplies internal bias and charges the exter st nal capacitor connected to th
9. 0 M MEME DE ES O E UNCLE RS 0 0 fi fi fi fi i fi 25 0 25 50 75 100 125 25 0 25 50 75 100 125 Temperature C Temperature C Figure 13 Shutdown Delay Current Ipe Ay vs TA Figure 14 Burst Mode High Threshold Voltage Vburn vs TA o 12 T r T T 1 2 T T T 3 EU E E L o us 9 8L Re amo rl L Le L 06 oo ppp 06 odo N TRUM ONU FRUI DUE UNS NN T NM 0 4 y OA ru sd op DEE E ERES PS RE E ES ES 0 2 o2L cesset d ee leo i clio a 0 0 9 0 0 lo L u d 25 0 25 50 75 100 125 25 0 25 50 75 100 125 Temperature C Temperature C Figure 15 Burst Mode Low Threshold Voltage Figure 16 Peak Current Limit lj jy vs Ta Vburi VS TA 2008 Fairchild Semiconductor Corporation www fairchildsemi com FSQO0565RS RQ Rev 1 0 3 10 uoneaedo 3ueuosesr Isenp 104 wi Sd YOUMS JAMO piIu2ue A epojy uea15 OY SUS9SOOSS Typical Performance Characteristics Continued These characteristic graphs are normalized at TA 25 C o 12r r mm 1 2 i pee D 3 N F D i ll A z 1 0 D E L L E O gie iuo Lo e selbe ll z Ol o ooo eo oo S ae 2 06 e d S OG AEE EEN E EEU ef ION 04L gaa e o lo 0 PEE ene Geet OE EEN EEN EEE A Ce PE 133 E ep oe E a E E 0 0 pee e o fe e A 0 0 pap eo ij eo
10. 1000yF 10V Low ESR Electrolytic Capacitor Samwha EER3016 Ae 109 7mm 2008 Fairchild Semiconductor Corporation FSQO0565RS RQ Rev 1 0 3 20 www fairchildsemi com uone1edo jueuosesrIseno 10 wi Sd YOUMS 19MOd PI Yde4 epojy uea46 OY SUNS9SOOSA Package Dimensions e NOTES UNLESS OTHERWISE SPECIFIED 5 5 A THIS PACKAGE DOES NOT COMPLY TO ANY CURRENT PACKAGING STANDARD B ALL DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D LEADFORM OPTION A E DFAWING FILENAME TO220A06REV3 Figure 41 6 Lead TO 220 Package Forming Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http www fairchildsemi com packaging 2008 Fairchild Semiconductor Corporation www fairchildsemi com FSQO565RS RQ Rev 1 0 3 21 uoneaedo 3ueuosesr Isenp 104 wi Sd YOUMS JAMO piIu2ue Y epojy uea15 OY SUS9SOOSS Package Dimensions Continued
11. NN NN Q 4 LLL LLL O e VERN E INP ENERO QI PUE EE SES A IESS ES Qa eee peel ee do 0 2 EE ERE RET DEM RUN SEEN VEN IS GNI D NE 0 0 o sito de po qp opo 0 0 pues Rl py xp sdlicet qoc 3 25 0 25 50 75 100 125 Temperature C Figure 9 Initial Switching Frequency fs vs TA Figure 10 Maximum On Time ton max VS TA 2008 Fairchild Semiconductor Corporation FSQO0565RS RQ Rev 1 0 3 www fairchildsemi com uone1edo jueuosesrIseno 10 wi Sd YOUMS 19MOd piluoue Y epo y ueao46 OY SUS9SOOSA Typical Performance Characteristics Continued These characteristic graphs are normalized at TA 25 C 5 1 2 r D o N D r EN E O O A O eene E z L o O PEA O O ka AEE EEN EES PA PE PR SO RE PARAS PA EESE E o EI LO IA PS O E A AA Da s SR dec O SS E ER Donc PR RES EEN BEN ERE PR TOPE Q2 o a EE DESE O 0 0 S E ESE HS tf p 0 0 p Apr qe Piles or pe Ale e cnp 9 25 0 25 50 75 100 125 25 0 25 50 75 100 125 Temperature C Temperature C Figure 11 Blanking Time tg vs TA Figure 12 Feedback Source Current Ig vs TA vo 12 r r 1 2 T T r T T T D o N o j m A A ei S a E O De a O O z L e 5 BEEN RN NN RUN UN dot PNE NE Q 6L O 0 4 L es ccr pecu O A MR 0 2 i E coe ED EA ARO O A DR Da Noo DM E E M PE E 0
12. S employs a leading edge blanking LEB circuit This gt circuit inhibits the PWM comparator for a short time Xx VREF t gg after the SenseFET is turned on 8V 12V gt Vec good Internal 3 Synchronization The FSQ series employs a quasi Bias resonant switching technique to minimize the switching noise and loss The basic waveforms of the quasi Figure 23 Startup Circuit resonant converter are shown in Figure 25 To minimize the MOSFET s switching loss the MOSFET should be turned on when the drain voltage reaches its minimum value which is indirectly detected by monitoring the Vec FSQ0565 Rev 00 2 Feedback Control FPS employs current mode control as shown in Figure 24 An opto coupler such as ES aT the FOD817A and shunt regulator such as the KA431 Winding voltage as shown in Figure 25 are typically used to implement the feedback network i i i Comparing the feedback voltage with the voltage across the Rsense resistor makes it possible to control the switching duty cycle When the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2 5V the opto coupler LED current increases pulling down the feedback voltage and reducing the duty cycle This typically happens when the input voltage is Veyne increased or the output load is decreased Vcc Vrer i lao ls 0 Le V
13. T Quiet Series Motion SPM SuperSOT 6 s FACT OPTOLOGIC pod UHC o OPTOPLANAR SuperSOTa 8 Maree FAST El e SupreMOS tra FETA iy SyncFET pete encha Sync Lock a PDP SPM VisualMax XS Trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are 2 A critical component in any component of a life support device or intended for surgical implant into the body or b support or sustain life system whose failure to perform can be reasonably expected to and c whose failure to perform when properly used in accordance cause the failure of the life support device or system or to affect its with
14. ching frequency hops when the input voltage is high The internal timing diagram of AVS is described in Figure 37 19us AVS trigger point Constant Variable frequency within limited range frequency i CC M DCM i AVS region D c FSQ0565 Rev 00 Figure 36 Switching Frequency Range 2008 Fairchild Semiconductor Corporation FSQ0565RS RQ Rev 1 0 3 www fairchildsemi com uoneaedo 3ueuosesr Isenp 104 wi Sd YOUMS JAMO piIuoue Y epojy uea15 OY SUS9SOOSS Vaate continued 2 pulse eziuoJuouAS azIluoJyou s o a IJ Tt Avs triggering i 1 1 1 1 1 1 F 1 1 GateX2 Counting Vgate every 2 pulses independent on other signals FSQ0565 Rev 00 PCB Layout Guide Due to the combined scheme FPS shows better noise immunity than conventional PWM controller and MOSFET discrete solutions Furthermore internal drain current sense eliminates noise generation caused by a sensing resistor There are some recommendations for PCB layout to enhance noise immunity and suppress the noise inevitable in power handling components There are typically two grounds in the conventional SMPS power ground and signal ground The power ground is the ground for primary input voltage and power while the signal ground is ground for PWM controller In FPS those two grounds share the same pin GND Nor
15. ction voltage voltage 2008 Fairchild Semiconductor Corporation FSQO0565RS RQ Rev 1 0 3 www fairchildsemi com uone1edo jueuosesr seno 10 wi Sd YOUMS 19MOd P IYILIE Y epo y uea46 OY SUS9SODSA Typical Performance Characteristics These characteristic graphs are normalized at TA 25 C 25 0 25 50 75 100 125 Temperature C O D N N 1 T ec as eet E 9 Q8p M 9 068p ee 0 6 pe 0 6 Q 4 iL LLL 9 4 LLL LLL LLL LL LLL 0 2 a e II O A 0 2 EAER PE o e E E 0 0 i 1 ipe EE 1 0 0 i b l Ld 4 25 0 25 50 75 100 125 25 0 25 50 75 100 125 Temperature C Temperature C Figure 5 Operating Supply Current lop vs TA Figure 6 UVLO Start Threshold Voltage Vstart VS TA UO 1 2 i EEE eS or 1 2 T T T T T T T D D N F D r A O A E L os o pate qp E L Z L Kage ES ae E S NEE SEN polo o o nl O16 a eso N SEE EGO PS ESE eer Q 4 LL OA SE Dolcd a E coil co E 0 2L 0 0 i Lb a loo lot y 0 0 pose tp opp e AA 25 0 25 50 75 100 125 25 0 25 50 75 100 125 Temperature C Temperature C Figure 7 UVLO Stop Threshold Voltage Figure 8 Startup Charging Current Icy vs TA Vsrop VS TA o 12 r r r 1 2 r T r T T r D o N o E E So E Dad AS eui eit L Z L OG a S C RR e az E ESE S EN Pu AS RES MUI C
16. e 1 3 600UH 10 67kHz 1V Leakage 1 3 15u4H Maximum Short all other pins 5 Core amp Bobbin m Core EER3016 Ae 109 7mm2 m Bobbin EER3016 O 2008 Fairchild Semiconductor Corporation www fairchildsemi com FSQO0565RS RQ Rev 1 0 3 19 uone1edo JUBUOSAY ISENH 10 wi Sdd YOUMS 19MOd P IYILIE Y POW U3919 OY SUS9SOOSA 6 Demo Board Part List 47nF 50V Film Sehwa 1W 4 7nF 1kV Y cap Samwha 1 2W Inductor 1W 5uH 5A Rating jumper 5uH 5A Rating optional 1 4W 1 4W 1 IN4007 VISHAY 1 AW 1 UF4004 VISHAY 1 4W 1N4745A 1W 16V Zener Diode optional 1 4W 1 4W 1 MBRF10H100 MBRF1060 10A 100V Schottky Rectifier 10A 60V Schottky Rectifier 8kQ 1 4W 1 1 4W 1 IC FSQ0565RS FPS Capacitor KA431 TL431 Voltage Reference 150nF 275Vac Box Capacitor PILKOR FOD817A Opto Coupler 150nF 275Vac Box Capacitor PILKOR Fuse 100uUF 400V Electrolytic Samwha 2A 250V 3 3nF 630V Film Sehwa NTC 33nF 50V Film Sehwa 5D 9 100nF 50V Mono PILKOR Bridge Diode 47yF 50V Electrolytic Samyoung 2KBP06M Bridge Diode 1000yF 25V Low ESR Electrolytic Capacitor Samwha Line Filter 1000yF 25V Low ESR Electrolytic Capacitor Samwha 30mH 2200yF 10V Low ESR Electrolytic Capacitor Samwha Transformer
17. e Vcc pin Once Vcc reaches 12V the internal current source is disabled It is not recommended to connect Va and Drain together 2008 Fairchild Semiconductor Corporation FSQO0565RS RQ Rev 1 0 3 www fairchildsemi com uonejedo jueuosesrIseno 10 wi Sd YOUMS 19MOd puse 3 POW U3919 OY SUS9SODSA Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device The device may not function or be opera ble above the recommended operating conditions and stressing the parts to these levels is not recommended In addi tion extended exposure to stresses above the recommended operating conditions may affect device reliability The absolute maximum ratings are stress ratings only Ta 25 C unless otherwise specified 8 Free standing with no heat sink under natural convection 9 Infinite cooling condition refer to the SEMI G30 88 Symbol Parameter Min Max Unit Vatr Vet Pin Voltage 500 V Vos Drain Pin Voltage 650 V Vcc Supply Voltage 20 V VEB Feedback Voltage Range 0 3 13 0 V Vsync Sync Pin Voltage 0 3 13 0 V lpm Drain Current Pulsed 11 A f Tc 25 C 2 8 Ip Continuous Drain Current A Tc 100 C 1 7 Eas Single Pulsed Avalanche Energy 190 mJ Pp Total Power Dissipation Tc 25 C 45 W Tj Operating Junction Temperature Internally limited C TA Operating Ambient Tem
18. endent on standby current load This causes the feedback voltage to rise Once it passes Veury 550mV switching resumes The feedback voltage then falls and the process repeats Burst mode operation alternately enables and disables switching of the power SenseFET thereby reducing switching loss in standby mode Vo Vos FSQ0565 Rev 00 Switching Switching disabled i2 i3 disabled t4 Figure 34 Waveforms of Burst Operation 2008 Fairchild Semiconductor Corporation FSQ0565RS RQ Rev 1 0 3 www fairchildsemi com uoneaedo 3ueuosesr Isenp 104 wi Sd YOUMS JAMO piIu2ue Y epojy uea15 OY SUS9SOOSS 7 Switching Frequency Limit To minimize switching loss and Electromagnetic Interference EMI the MOSFET turns on when the drain voltage reaches its minimum value in quasi resonant operation However this causes switching frequency to increases at light load conditions As the load decreases or input voltage increases the peak drain current diminishes and the switching frequency increases This results in severe switching losses at light load condition as well as intermittent switching and audible noise These problems create limitations for the quasi resonant converter topology in a wide range of applications max ts 21us 179 218 FSQ0565 Rev 00 Figure 35 QRC Operation with Limited Frequency
19. for Fairchild Power Switch FPS Flyback Applications m AN 4145 Electromagnetic Compatibility for Power Converters m AN 4147 Design Guidelines for RCD Snubber of Flyback Converters m AN 4148 Audible Noise Reduction Techniques for Fairchild Power Switch FPS Ej Applications m AN 4150 Design Guidelines for Flyback Converters Using FSQ Series Fairchild Power Switch FPS Description A Quasi Resonant Converter QRC generally shows lower EMI and higher power conversion efficiency than a conventional hard switched converter with a fixed switching frequency The FSQ series is an integrated Pulse Width Modulation PWM controller and SenseFET specifically designed for quasi resonant operation and Alternating Valley Switching AVS The PWM controller includes an integrated fixed frequency oscillator Under Voltage Lockout UVLO Leading Edge Blanking LEB optimized gate driver internal soft start temperature compensated precise current sources for a loop compensation and self protection circuitry Compared with a discrete MOSFET and PWM controller solution the FSQ series can reduce total cost component count size and weight while simultaneously increasing efficiency productivity and system reliability This device provides a basic platform for cost effective designs of quasi resonant switching flyback converters 2008 Fairchild Semiconductor Corporation FSQO565RS RQ Rev 1 0 3 www fairchildsemi com uo
20. g Blanking Time Ty 25 C Vsync 5V 13 5 15 0 16 5 us tw Detection Time Window Ty 25 C Vsync OV 6 0 Hs fs Initial Switching Frequency 59 6 66 7 75 8 kHz Afs Switching Frequency Variation 1 25 C lt Tj 85 C 5 10 tavs AVS Triggering On Time at Vin 240Vpc Lm 360uH 4 0 us VS Threshold 11 Feedback a HE a when Vays gt spec Ja V Voltage and tays spec tw Switching Time Variance by AVS 11 Me M x eid 13 5 20 5 us le Feedback Source Current Vrg OV 700 900 1100 pA Duin Minimum Duty Cycle Vep OV 0 VsTART_ UVLO Threshold Voltage IAE ASS a Vstop After turn on 7 8 9 V ts s Internal Soft Start Time With free running frequency 17 5 ms Vovp Over Voltage Protection FSQ0565RS 18 19 20 V Vove Over Voltage Protection eg Yom TPVNEE TAY A 7h FSQ0565RQ Blanking 1 0 1 7 24 ifs Time BURST MODE SECTION VBURH 0 45 055 0 65 V VeurL Burst Mode Voltages Ty 25 C tpp 200ns 1 0 25 0 35 045 V Hysteresis 200 mV Continued on the following page 2008 Fairchild Semiconductor Corporation FSQ0565RS RQ Rev 1 0 3 www fairchildsemi com uone1edo jueuosesrIseno 10 wi Sd YOUMS 19MOG piluoue Y POW U3919 OY SUS9SODSA Electrical Characteristics Continued Ta 25 C unless otherwise specified mbo aramete
21. hown at Vcc winding coil Figure 33 OVP Triggering of FSQ0565RQ 4 5 Thermal Shutdown with Hysteresis TSD The SenseFET and the control IC are built in one package This enables the control IC to detect the abnormally high temperature of the SenseFET If the temperature exceeds approximately 140 C the thermal shutdown triggers IC shutdown The IC resumes operation when the junction temperature decreases 60 C from TSD temperature and Vcc reaches startup voltage Vstart 5 Soft Start The FPS has an internal soft start circuit that increases PWM comparator inverting input voltage with the SenseFET current slowly after it starts The typical soft start time is 17 5ms The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers inductors and capacitors The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage This mode helps prevent transformer saturation and reduces stress on the secondary diode during startup 6 Burst Operation To minimize power dissipation in standby mode the FPS enters burst mode operation As the load decreases the feedback voltage decreases As shown in Figure 34 the device automatically enters burst mode when the feedback voltage drops below VeurL 350MV At this point switching stops and the output voltages start to drop at a rate dep
22. irchildsemi com FSQO0565RS RQ Rev 1 0 3 7 uone1edo jueuosesr Iseno 10 wi Sd YOUMS 19MOd piluoue Y SPO A USIID OY SUS9SODSA EMI Reduction Operation Method Constant Frequency PWM Frequency Modulation Quasi Resonant Operation Reduced EMI Noise Comparison Between FSDMOx65RNB and FSQ Series Function FSDMOx65RE FSQ Series FSQ Series Advantages m improved efficiency by valley switching m Reduced EMI noise m Reduced components to detect valley point m Valley Switching m Inherent Frequency Modulation m Alternate Valley Switching Hybrid Control CCM or AVS Based on Load and Input Condition m improves efficiency by introducing hybrid control Burst Mode Operation Burst Mode Operation Advanced Burst Mode Operation m improved standby power by advanced burst mode Strong Protections OLP OVP OLP OVP OSP m improved reliability through precise OSP TSD 145 C without Hysteresis 140 C with 60 C Hysteresis m Stable and reliable TSD operation m Converter temperature range Differences Between FSQ0565RS and FSQ0565RQ Function FsaosesRs Fsaosesra Remark W Lower current peak is suitable to reduce conduc tion loss IM Son on m Higher current peak is suitable for handling higher power Over Voltage Vec OVP Sync OVP m Sync OVP is suitable when Vcc voltage is pre reg triggered by Vcc triggered by Sync ulated Prote
23. irectly monitoring the output voltage If Vcc exceeds 19V an OVP circuit is activated resulting in the termination of the switching operation To avoid undesired activation of OVP during normal operation Vcc should be designed below 19V 4 4 2 Sync Over Voltage Protection OVP of FSQ0565RQ If the secondary side feedback circuit malfunctions or a solder defect causes an opening in the feedback path the current through the opto coupler transistor becomes almost zero Veg climbs up in a similar manner to the overload situation forcing the preset maximum current to be supplied to the SMPS until the overload protection triggers Because more energy than required is provided to the output the output voltage may exceed the rated voltage before the overload protection triggers resulting in the breakdown of the devices in the secondary side To prevent this situation an OVP circuit is employed In general the peak voltage of the sync signal is proportional to the output voltage and the FSQ series uses a sync signal instead of directly monitoring the output voltage If the sync signal exceeds 8V an OVP is triggered shutting down the SMPS To avoid undesired triggering of OVP during normal operation two points are considered as depicted in Figure 33 The peak voltage of the sync signal should be designed below 6V and the spike of the SYNC pin must be as low as possible to avoid getting longer than toyp by decreasing the leakage inductance s
24. ld Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions 2008 Fairchild Semiconductor Corporation FSQO565RS RQ Rev 1 0 3 22 www fairchildsemi com uoneaedo 3ueuosesr Isenp 104 wi Sd YOUMS JAMO piIu2ue Y epojy uea15 OY SUS9SOOSS pS FAIRCHILD SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such trademarks AccuPower FlashWriter Power SPM SYSTEM Auto SPM FPS PowerTrench GENERAL rad Build it Now F PFS PowerxS The Power branch CorePLUS FRFET Programmable Active Droop p wer CorePOWER Global Power Resource QFET franchise CROSSVOLT Green FPS Qs TinyBoost CTL Green FPS e Series Quiet Series TinyBuck Current Transfer Logic Gmax RapidConfigure TinyCalea DEUXPEED GTO E TinyLogic EcoSPARK IntelliMAX e TINYOPTOA EfficientMax ISOPLANARS Saving our world 1mW W kW at a time TinyPower EZSWITCH MegaBuck EOM Ser TinyPWMA e martMax et ee EZ MICROCOUPLER SMART STARTA TinyWire e MicroFET SsPM TriFault Detect MicroPak TRUECURRENT Fairchild MillerDrive ene nSerDesa Fairchild Semiconductor MotionMax superSOTa 3 FAC
25. m uonejedo jueuoses Iseno 104 Wi Sd YOM 19MOg piluoue 3 epojy ueaJo OY SUSISOOSS Typical Application Circuit Input Voltage Range Output Voltage Maximum Current 5 0V 2 0A 14V 2 8A Rated Output Power Application FPS Device LCD Monitor Power Supply FSQ0565RS 85 265Vac 50W Features m Average efficiency of 25 50 75 and 100 load conditions is higher than 80 at universal input m Low standby mode power consumption lt 1W at 230VAc input and 0 5W load m Reduce EMI noise through valley switching operation m Enhanced system reliability through various protection functions m Internal soft start 17 5ms Key Design Notes m The delay time for overload protection is designed to be about 23ms with C105 of 33nF If faster slower triggering of OLP is required C105 can be changed to a smaller larger value e g 100nF for 70ms m The input voltage of Vsync must be between 4 7V and 8V just after MOSFET turn off to guarantee hybrid control and to avoid OVP triggering during normal operation m The SMD type 100nF capacitor must be placed as close as possible to Vcc pin to avoid malfunction by abrupt pulsating noises and to improve surge immunity 1 Schematic FSQO0565RS Rev 00 n D201 rud EER3016 MBRF10H100 A BD101 2KBP06M R1057G106 C107 1000 100nF 47uF 0 5W MD 50 D202 L202 MBRF1060 SuH 5V 2A i zptot 11N4745A
26. mally the separate grounds do not share the same trace and meet only at one point the GND pin More wider patterns for both grounds are good for large currents by decreasing resistance Capacitors at the Vcc and FB pins should be as close as possible to the corresponding pins to avoid noise from the switching device Sometimes Mylar amp or ceramic capacitors with electrolytic for Vcc is better for smooth operation The ground of these capacitors needs to connect to the signal ground not power ground The cathode of the snubber diode should be close to the Drain pin to minimize stray inductance The Y capacitor between primary and secondary should be directly connected to the power ground of DC link to maximize surge immunity Because the voltage range of feedback and sync line is small it is affected by the noise of the drain pin Those traces should not draw across or close to the drain line When the heat sink is connected to the ground it should be connected to the power ground If possible avoid using jumper wires for power ground and drain Figure 37 Alternating Valley Switching AVS 1st valley 2nd valley frequency modulation Modulation frequency is approximately 17kHz n B102 ciot Gordan Sorg 3 T Figure 38 Recommended PCB Layout Mylar is a registered trademark of DuPont Teijin Films 2008 Fairchild Semiconductor Corporation FSQ0565RS RQ Rev 1 0 3 www fairchildsemi co
27. n 2 1 Pulse by Pulse Current Limit Because current mode control is employed the peak current through the SenseFET is limited by the inverting input of PWM comparator Veg as shown in Figure 24 Assuming 1 Startup At startup an internal high voltage current source supplies the internal bias and charges the external capacitor C4 connected to the Vcc pin as illustrated in Figure 23 When Vee reaches 12V the that the 0 9mA current source flows only through the i 1 d DNUS ES internal resistor 3R R 2 8k the cathode voltage of FPS begins switching and the internal high voltage diode D2 is about 2 5V Since D1 is blocked when the current source is disabled The FPS continues its feedback voltage Veg exceeds 2 5V the maximum normal switching operation and tne power isjSupplieo voltage of the cathode of D2 is clamped at this voltage from the auxiliary transformer winding unless Vcc goes de clamping Vrg Therefore the peak value of the current below hs stop voltage of through the SenseFET is limited 2 2 Leading Edge Blanking LEB At the instant the internal SenseFET is turned on a high current spike usually occurs through the SenseFET caused by primary side capacitance and secondary side rectifier reverse recovery Excessive voltage across the Rgense fes atl A O LI 61 Vs resistor would lead to incorrect feedback operation in the pcm current mode PWM control To counter this effect the pr SO c FP
28. nejedo jueuosesrIseno 10 wi Sd YOUMS 19MOG piluoue Y POW U3919 OY SUS9SODSA Ordering Information Maximum Output Power Product pKG 5 Operating Current Roson 230VAct15 2 85 265VAc Replaces Number Temp Limit Max e Open g Open Devices Adapter Frame 4 Adapter Framel FSQ0565RSWDTU TO 220F 2 25A FSCM0565R 25 to 85 C 2 22 70W 80W 41W 60W FSQ0565ROWDTU 6L 3 0A FSDMOS565RE FSQO565RSLDTU TO 220F 2 25A 6L 25 to 85 C 2 20 70W 80W 41W 60W ESCM FSQ0565RQLDTU 1 Forming 3 0A FSDMOS65RE C For Fairchild s definition of Eco Status please visit http www fairchildsemi com company green rohs green html Notes 1 The junction temperature can limit the maximum output power 2 230V ac or 100 115V ac with doubler 3 Typical continuous power in a non ventilated enclosed adapter measured at 50 C ambient temperature 4 Maximum practical continuous power in an open frame design at 50 C ambient 5 Eco Status RoHS Application Diagram FSQO565RS Rev 00 Figure 1 Typical Flyback Application 2008 Fairchild Semiconductor Corporation www fairchildsemi com FSQO565RS RQ Rev 1 0 3 2 uone1edo jueuosesrIseno 10 wi SdJ YOUMS 19MOG piluoue Y POW U3919 OY SUS9SOOSA Block Diagrams
29. o i Vee 7 RA SenseFET H11A817A f Di o f d Ca 3R 230ns Delay y BEANE i i 1 X H gt i MOSFET Gate i Gate ls H i VeeS R driver H i H LA 177 H i i d La OLP Reense a FSQ0565 Rev 00 i Vso LD i H i FERRAN beee Figure 25 Quasi Resonant Switching Waveforms Figure 24 Pulse Width Modulation PWM Circuit 2008 Fairchild Semiconductor Corporation www fairchildsemi com FSQ0565RS RQ Rev 1 0 3 12 uoneaedo 3ueuosesr Isenp 104 w Sd YOUMS JAMO piIu2ue A epojy uea15 OY SUS9SOOSS The switching frequency is the combination of blank time tg and detection time window ty In case of a heavy load the sync voltage remains flat after tg and waits for valley detection during tw This leads to a low switching frequency not suitable for heavy loads To correct this drawback additional timing is used The timing conditions are described in Figures 26 27 and 28 When the Vsync remains flat higher than 4 4V at the end of tg which is instant tx the next switching cycle starts after internal delay time from ty In the second case the next switching occurs on the valley when the Vsync goes below 4 4V within tg Once Vsync detects the first valley in tg the other switching cycle follows classical QRC operation tg 15us tx te 15 t i ii FSQ0565 Rev 00 S x i f E i d sl internal delay Figure 28 After V
30. perature 25 85 C TsrG Storage Temperature 55 150 C ESD Electrostatic Discharge Capability Human Body Model 2 0 m Electrostatic Discharge Capability Charged Device Model 2 0 Notes 6 Repetitive rating pulse width limited by maximum junction temperature 7 L 14mH starting Tj 25 C Thermal Impedance TA 25 C unless otherwise specified Symbol Parameter Package Value Unit OA Junction to Ambient Thermal Resistance 50 C W Bye Junction to Case Thermal Resistance 102 m 2 8 C W Notes 2008 Fairchild Semiconductor Corporation FSQO0565RS RQ Rev 1 0 3 5 www fairchildsemi com uone1edo jueuosesrIseno 10 wi Sd YOUMS 19MOG P YI1IE Y epojy uea46 OY SUS9SODSA Electrical Characteristics Ta 25 C unless otherwise specified Symbol Parameter Condition Min Typ Max Unit SENSEFET SECTION BVpss Drain Source Breakdown Voltage Vcc OV lp 100A 650 V Ipss Zero Gate Voltage Drain Current Vps 560V 300 pA Rps on Drain Source On State Resistance Ty 25 C Ip 0 5A 1 76 2 20 Q Coss Output Capacitance Ves OV Vos 25V f 1MHz 78 pF ta on Turn On Delay Time Vpp 350V Ip 25mA 22 ns tr Rise Time Vpp 350V Ip 25mA 52 ns la off Turn Off Delay Time Vpp 350V Ip 25mA 95 ns tr Fall Time Vpp 350V Ip 25mA 50 ns CONTROL SECTION ton max Maximum On Time Ty 25 C 8 8 10 0 11 2 us t
31. r ondition in p Max Uni Symbol P t Conditi Mi Typ M Unit PROTECTION SECTION lui MIT Peak Current FSQ0565RS Ty 25 C di dt 370mA us 2 00 2 25 2 50 A limit Limit FSQ0565RQ Ty 25 C di dt 370mA us 264 3 0 3 36 A Vsp Shutdown Feedback Voltage Vec 15V 5 5 6 0 6 5 V IpELay Shutdown Delay Current Vep 5V 4 5 6 yA ti Ep Leading Edge Blanking Time 250 ns tosp Threshold Time Tj 25 C 12 14 us V Output Short Threshold Feedback OSP triggered when ton lt tosp 48 20 V OSP Protection Voltage Veg gt Vosp and lasts longer than tosp_FB Feedback Blanking Time losP FB 2 0 25 3 0 us Tsp Thermal Shutdown Temperature 125 140 155 C Hys Shutdown Hysteresis 60 SYNC SECTION VsH1 10 12 14 Sync Threshold Voltage 1 Vec 15V Veg 2V V Vsi4 0 8 1 0 12 tsync Sync Delay Time 12 230 ns Vsu2 433 E4728 I oM Sync Threshold Voltage 2 Vcc 15V Vgg 2V V VsL2 40 44 48 VeLamp Low Clamp Voltage SYNC Max A 0 0 04 08 V SYNC_MIN H TOTAL DEVICE SECTION lop Operating Supply Current Vec 13V 1 3 5 mA Vcc 10V Istart Start Current before Vec reaches Vstarr 350 450 550 pA lc Startup Charging Current Vece OV Vstr minimum 50V 0 65 0 85 1 00 mA VsTR Minimum Vsrg Supply Voltage 26 V Notes 10 Propagation delay in the control IC 11 Guaranteed by design not tested in production 12 Includes gate turn on time 2008 Fairchild Semiconductor Corporation www fa
32. rchildsemi com FSQO0565RS RQ Rev 1 0 3 13 uoneJedo JUBUOSAY ISEND 104 wi Sd u21 s 19MOG pIIuoue Y epoW uIeI15 OY SUS9SODS4 4 1 Overload Protection OLP Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event In this situation the protection circuit should trigger to protect the SMPS However even when the SMPS is in the normal operation the overload protection circuit can be triggered during the load transition To avoid this undesired operation the overload protection circuit is designed to trigger only after a specified time to determine whether it is a transient situation or a true overload situation Because of the pulse by pulse current limit capability the maximum peak current through the SenseFET is limited and therefore the maximum input power is restricted with a given input voltage If the output consumes more than this maximum power the output voltage Vo decreases below the set voltage This reduces the current through the opto coupler LED which also reduces the opto coupler transistor current thus increasing the feedback voltage VEB If Veg exceeds 2 5V D1 is blocked and the 5pA current source starts to charge Cg slowly up to Vcc In this condition Veg continues increasing until it reaches 6V when the switching operation is terminated as shown in Figure 30 The delay time for shutdown is the time required to charge Crp from 2 5V to 6V with 5pA A 20
33. s sir te ne Cf silo 25 0 25 50 75 100 125 25 0 25 50 75 100 125 Temperature C Temperature C Figure 17 Sync High Threshold Voltage 1 Figure 18 Sync Low Threshold Voltage 1 Vsu1 vs Ta VsL1 vs TA o 12 r r r 1 2 T r r T r r D o N f D r E 10 e e a e 5 O O A O O O O ee us T i O QB aaa ens ee lA ell T EE eee BEES SP A UN D DINI TN Sad 2 o s edo a A BAR sevens ASAS ea A E REE EEE PIN DEN NEN oo dee 0371 RNC DENDUM DD ADR EUREN S HE PH M QAL CEE EEE EPE ole D do moss pa dong uu d Qo cu UE e ca e 0 0 OE IN E E PS A ING TUN 0 0 1 f L I i f i f 25 0 25 50 75 100 125 25 0 25 50 75 100 125 Temperature C Temperature C Figure 19 Shutdown Feedback Voltage Vsp vs TA Figure 20 Over Voltage Protection Voy vs TA vo 12 r r r r r 1 2 N 9 F E ee A 1 0 F E F 9 osp C E PN Re eee eee M PR RN L Z L 0 6 E 0 6 LL i i dr een ae ee le es ea SU O O EUN NE is E 0 2 esp eet al sli dm leo ido rini 0 2 S RE E LEE alto de EN M 0 0 EU O e dd ient O 1 0 0 1 i fi f i 1 fi 25 0 25 50 75 100 125 25 0 25 50 75 100 125 Temperature C Temperature C Figure 21 Sync High Threshold Voltage 2 Figure 22 Sync Low Threshold Voltage 2 Vsu2 vs Ta VsL2 vs Ta O 2008 Fairchild Semiconductor Corporation www fairchildsemi com FSQO0565RS RQ Rev 1 0 3 11 uoneaedo 3ueuosesr Isenp 104 wi Sd YOUMS JAMO pIIu2ue Y epojy uea15 OY SUS9SOOSS Functional Descriptio
34. sync Finds First Valley gt 4 Protection Circuits The FSQ series has several self protective functions such as Overload Protection OLP Over Voltage Protection OVP and Thermal Shutdown TSD All the protections are implemented as gt auto restart mode Once the fault condition is detected switching is terminated and the SenseFET remains off This causes Vcc to fall When Vcc falls down to the Under Voltage Lockout UVLO stop voltage of 8V the protection is reset and the startup circuit charges the BIA Red Vcc capacitor When the Vcc reaches the start voltage internal delay oe of 12V normal operation resumes If the fault condition is Figure 26 Vsync gt 4 4V at tx not removed the SenseFET remains off and Vcc drops to stop voltage again In this manner the auto restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated i tx te is gt Because these protection circuits are fully integrated into the IC without external components reliability is improved without increasing cost Fault occurs Fault removed gt H ii FSQ0565 Rev 00 internal delay gt gt E FSQ0565 Rev 00 Normal Fault Normal Figure 27 Vsync lt 4 4V at tx operation situation operation Figure 29 Auto Restart Protection Waveforms 2008 Fairchild Semiconductor Corporation www fai
35. ues that may arise Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors PRODUCT STATUS DEFINITIONS Definition of Terms Semiconductor reserves the right to make changes at any time without notice to improve design Datasheet Identification Product Status Definition Advance Information Formative In Design Datasheet contains the design specifications for product development Specifications may change in any manner without notice Preliminary First Production Datasheet contains preliminary data supplementary data will be published at a later date Fairchild Datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes NN aed Full Producton at any time without notice to improve the design Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor Obsolete Not In Production The datasheet is for reference information only Rev 144 2008 Fairchild Semiconductor Corporation 2008 Fairchild Semiconductor Corporation FSQO565RS RQ Rev 1 0 3 23 www fairchildsemi com www fairchildsemi com uoneaedo 3ueuosesr Isenp 104 w Sd YOUMS JAMO piIu2ue A epojy uea15 OY SUS9SOOSS
36. urn on time When the Veg is higher than 2V and the SenseFET turn on time is lower than 1 2us the FPS recognizes this condition as an abnormal error and shuts down PWM switching until Vcc reaches Vstart again An abnormal condition output short is shown in Figure 32 Rectifier Turn off delay Diode Current MOSFET Drain Current 1 2us output short occurs 0 A lo FSQ0565 Rev 00 Figure 32 Output Short Waveforms 4 4 14 Vcc Over Voltage Protection OVP of FSQ0565RS If the secondary side feedback circuit malfunctions or a solder defect causes an opening in the feedback path the current through the opto coupler transistor becomes almost zero In this case Vg climbs up in a similar manner to the overload situation forcing the preset maximum current to be supplied to the SMPS until overload protection is activated Because more energy than required is provided to the output the output voltage may exceed the rated voltage before overload protection is activated resulting in the breakdown of the devices in the secondary side To prevent this situation an over voltage protection OVP circuit is employed In general Vcc is proportional to the output voltage and the 2008 Fairchild Semiconductor Corporation FSQO565RS RQ Rev 1 0 3 www fairchildsemi com uoneaedo 3ueuosesr Isenp 104 w Sd YOUMS JAMO piIu2ue Y epojy uea15 OY SUS9SOOSS FSQ series uses Vcc instead of d
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