FAIRCHILD AN-4153 Designing Asymmetric PWM Half-Bridge Converters with a Current Doubler Synchronous Rectifier using FSFA-Series Fairchild Power Switches (FPS ) handbook
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1. Drossits x py fy Dioss215 x I po A NY 2 O e eee b m Dossi Ts xU pi Lp2 2 27 Design Example When the voltage ripple on the capacitor is 30 V the DC blocking capacitance is calculated using Equation 27 as Drossit s X Lpi Doss21s X Lpa l 2 2 2AV e102 1 D Doss Ls x Upi Lp 2 0 039 x1l0ux2 1 7 0 06 x10 u x3 47 AE 2 2 2x30 J 0 397 0 039 x10 u x 2 1 3 47 2 Cio 190nF Therefore 220 nF is selected as the DC blocking capacitor STEP 8 Sensing Resistor The pulse by pulse current limit of the FSFA series switches can be adjusted by changing R in Figure 11 It is determined by the peak of the primary current obtained using Equation 21 when the input voltage is maximized Due to the ripple current of the magnetizing inductance the maximum peak of the primary current happens when the input voltage is maximized Design Example Continuing with the example calculate the duty cycle at the maximum input voltage and full load conditions using Equation 14 www fairchildsemi com AN 4153 ta Hied nVo Vsr loby Dea arov 100 5 6 5 12 0 3 30x 20u 4 G00 6 5x 410x10 5x x i Yong 410 u g 2 0 338 Then the peak of the primary current is obtained combining Equations 7 9 10 and 21 as is Spey ea n 2 lioni a _ pla n n n pr AEE 2 nd DW L L 1 gt d a a 6 5 6 5 6 5 0338x104 30x20u pease 6 5 1 0 338 410 600u 20u 3 72A Si2. 20 1 2x6 5 400u 20u 6 5 12 0 uH The required leakage inductance is 12 0 uH which is too small to control in a mass production If the obtained value is larger than the assumed value the obtained value is used and the SMPS designer must repeat Step 2 to check if the turns ratio is still valid However in this design example the designer chooses the initial value for productivity and there is no iteration needed Figure 12 Primary Current Waveform www fairchildSemi com AN 4153 The magnetizing inductance can be determined using Equation 12 as DI 2x 2C ass 1 DYV mo O tar Ly n 0 305 1 0 305 410 10y Oy eo sues 20u btb 6384H Therefore L is selected as 600 uH STEP 4 Transformer Using Equations 9 and 10 the peak magnetizing current is obtained as i eae 5 lro2 _ p401 2 n n 2 Lm Li 15 DT ees x The maximum value of the peak magnetizing current occurs when each output inductor carries half the load current for the worst case and the duty cycle is zero during startup or transient instant Therefore the maximum i 1s max lo LL O 2n 16 The minimum number of turns for the transformer primary side 1s given as 17 where A is the effective cross sectional area of the used core in mm and Bmax is the maximum flux density in Tesla Bmax 9 2 0 25 T is recommended if there is no reference data The number of turns for the transformer secondar
3. Dioss2Ts i i i i Vgate SR1 Vin Vow h n Vo ne os Vorne i a t Same shape as vroz except for ng Vgate_SR2 Vew n Vo ng Vo Ng S to ti t2 t3 t4 b Figure 10 Gate Signals for Synchronous Rectifier a Transformer Coupled b Output Inductor Coupled 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 APPLICATION NOTE 3 Design Procedure and Example In this chapter a design procedure is shown using the design reference illustrated in Figure 11 The target system for this example is a game console power supply unit with 12 V of output voltage and 30 A of output load current To handle the large output load current the current doubler with the synchronous rectifier discussed in the previous chapter is used Since the input comes from a power factor correction PFC circuit the input voltage range is not wide STEP 1 System Specifications The first step in designing is to define the system specifications Generally a PFC circuit is used for medium or high power applications such as LCD PDP TV systems game console power supplies and beam projectors to meet international harmonic regulations Thus the input voltage range for the main power stage i e the output voltage of PFC stage is almost fixed e g 370 410 Vac However the input voltage range may be widened to meet special requirements In this chapter the target specificat
4. body diode of S turns on after the S output capacitance is wholly discharged and that of S is entirely charged Since both SRs turn on iro and ig are free wheeling with the slope of Vo Lo and Vod Le respectively and vy and vy are zero Vc 1s applied only on the leakage inductance causing the primary current s polarity to change rapidly When S turns on after the S body diode conducts the S ZVS condition is achieved The duration of this mode is obtained as I O Lig ye en 6 n DV xTs 6 loss2 7 Mode 4 another powering mode starts with the end of commutation between SRs The applied voltage on the primary side of the transformer is Vcp so that the magnetizing current decreases with the slope of V L and loss1 Ty k D oss2 Ty 1 D T d Mode 4 t t di tdi dizsi di Lo2 Lol e Key waveforms Figure 7 Mode Analysis and Waveforms for Asymmetric PWM Half Bridge Converter with the Current Doubler 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 www fairchildsemi com AN 4153 the slope of iz9o2 is Vq n Vo Lo2 The other inductor current is free wheeling through SR As can be seen in Figure 7 the large ripple on each output inductor is cancelled because of the out of phase Therefore two smaller inductors can be used in the current doubler configurations compared with the center tapped or bridge rectifying configurations Whe
5. magnetizing inductance with the leakage inductance In Equation 11 ignoring the second term in the denominator e Key waveforms Figure 8 Detailed Mode Analysis During Mode 1 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 www fairchildsSemi com AN 4153 rearrangement for L yields D 1 D Vin xT S DI 2 x 2Coss 1 DVV O tar Lig n Lp Lg lt 12 To obtain appropriate L and Ly using Equations 11 and 12 iterations are necessary An example of this is given in the next section b Mode 3_2 tt Cb d Mode 3_4 tet APPLICATION NOTE 2 3 Synchronous Rectifier It is more profitable that the conduction losses on the secondary rectifying stage are composed of ohmic losses instead of diode losses when the output current is high Since most of load current flow through the channel conduction losses can be reduced dramatically if synchronous MOSFETs with very low Rason less than several mQ turn on and off appropriately In buck derived topologies such as forward half bridge and full bridge converters the gate signal for SR is easily obtained from the Diosso T5 e Key waveforms Figure 9 Detailed Mode Analysis During Mode 3 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 www fairchildsSemi com AN 4153 main transformer as shown in Figure 6 a Unlike flyback or LLC converters there is no need to add any other speci
6. P 5 Output Inductance The output inductor current ripple is given as Vo V sp ya ROF Diosst Fs _ 24 Ol M Vo Vsr XD Dioss2 Ts 25 Loz In general the current ripple on the output inductor is set to 10 20 of the rated output load current Design Example In the design example the ripple on each output inductor is selected to be less than 20 of the rated output load current The inductances are calculated as V k Vopr X1 zo Dros Ls ee Aizo _ 12 0 3 1 0 397 0 039 x10 _ 13 2uH 6 z Vo Vsr XD Dioser Ts Aizo2 _ 12 oa 0 060 x 10m _ 9 4 uH To increase productivity both output inductors are selected as the same value 15H STEP 6 Operating frequency In Figure 11 the operating frequency fs is obtained by using the following equation when FSFA series is used 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 APPLICATION NOTE 2 pa aig el 26 Rios Design Example For the design example the frequency setting resistor R05 1S selected as 27 kQ for 100 kHz operation STEP 7 DC Blocking Capacitance It has been assumed that the DC blocking capacitor is large enough to neglect the voltage ripple on it However too large a DC blocking capacitor leads to slow dynamic response Therefore it is recommended to make the voltage ripple on the DC blocking capacitor around 10 of the input voltage The voltage ripple on the DC blocking capacitor is obtained as
7. Ses FAIRCHILD Saeed SEMICONDUCTOR AN 4153 www fairchildsemi com Designing Asymmetric PWM Half Bridge Converters with a Current Doubler and Synchronous Rectifier using FSFA Series Fairchild Power Switches FPS Introduction In general high frequency operation allows the use of small sized passive components in switch mode power supplies SMPS though it causes the switching losses to increase in a hard switching mode To reduce switching losses at high switching frequencies many soft switching techniques have been developed including load resonant and zero voltage transition techniques Load resonant techniques use a resonant feature of capacitors and inductors during the entire switching period to vary the switching frequency depending on the input voltage and load current The change of the switching frequency 1 e pulse frequency modulation PFM makes it difficult to design an SMPS including input filters Since there is no output inductor for filtering the clamped voltage across output rectifying diodes allows designers to select low voltage rating diodes However the absence of the output inductor burdens the output capacitors when the load current increases making load resonant techniques unsuitable for applications with high output current and low output voltage On the other hand zero voltage transition techniques use a resonant feature between parasitic components during turn on and or turn off trans
8. THER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life or c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 16 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com
9. al functions except for the driving circuit Ease of construction of the SR driver is another reason to use the half bridge topology for high output load current applications Moreover when using a current doubler it is more efficient to get the gate signal from the output inductors than from the main transformer as shown in Figure 6 b Figure 10 illustrates the SR gate signal waveforms from the main transformer and the output inductors It is difficult to tune up the turns ratio n and n where n n n and n n n2 to make the sufficient gate voltage as shown in Figure 10 a This is because both positive and negative parts are dependent not only on the turns ratios n and n but also on Vc Additionally the power loss by the negative part of the gate signal is determined by the turns ratio Vcs and Vin On the other hand the power loss by the negative part of the gate signal does not depend on the load condition as shown in Figure 10 b where n n3 n and ng n n2 In addition during the duty loss part Dioss iTs and Dyoss2Ts the gate signals change their polarity to a negative value so that the SRs turn off rapidly and definitely This helps to reduce the turn off loss of the synchronous MOSFETs a Dioss Ts Vin Vow n Vin Vew n Na Vegate SRI Vo n Np Vegate SR2 Vin Vcp n p a Same shape as vy 0 except for n EES Dioss Ts b gt
10. condary winding could be used with the same core and the same gauge of wire Third the winding itself is easier than the center tapped configuration This is notable especially for multi output applications because of the limitation of the pin number of the bobbin of the transformer Fourth the gate signals for SR are obtained easily and effectively from the output inductors as shown in Figure 6 b An appropriate gate voltage e g between 10 V and 20 V could be easily obtained from the output inductors due to an enough number of turns while the secondary side number of turns of the transformer is only a few Additionally the separated output inductors reduce the burden of the cost of the bigger core These advantages make the current doubler one of the most popular topologies for high output current applications 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 APPLICATION NOTE 2 1 Operational Principles Figure 7 shows the mode analysis for the asymmetric PWM half bridge converter with the current doubler and corresponding key waveforms Assume ZVS is achieved sufficiently with very short duration The ZVS modes can be ignored in the mode analysis The ZVS operation is discussed in detail in the next section Other assumptions are 1 The DC blocking capacitor C is large enough to neglect the voltage ripple on it and 2 All elements in the circuit are ideal Figure 5 Asymmetric PWM Half Bridge Conver
11. ctance of the transformer is applied the following is obtained www fairchildSemi com AN 4153 Figure 1 Conventional Asymmetric PWM Half Bridge Converter with a Center Tapped Transformer Vin Voy x D Vey x A D l gt Vey DVin The volt sec balance for the output inductor yields V Vy V V9 xD 9 H D 2 n n where n is the turns ratio of the transformer Combining Equations 1 and 2 the output voltage is obtained as yo 2y 3 in n As can be seen in Figure 2 the gain curve according to the duty cycle using Equation 3 ignoring turns ratio n the gain is proportional to the duty cycle up to 50 and inversely proportional to it above 50 Because of this symmetry the maximum duty cycle should be restricted up to 50 to regulate the output voltage The loss parts of the duty cycle by the leakage inductance are not considered in Equation 3 Figure 3 shows the key waveforms of the conventional asymmetric PWM half bridge converter illustrated in Figure 1 Since both secondary rectifying diodes conduct the voltage across the primary side of the transformer becomes zero during Djs Ts and Dossz2Ts AS a result the output voltage is not as high as in Equation 3 which is obtained by averaging rectifying 0 50 100 Duty Figure 2 Normalized Gain Curve 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 APPLICATION NOTE Lf m L V
12. d MOSFETs specifically designed for asymmetric controlled topologies with minimal external components Compared with discrete PWM controller and MOSFETs solutions FSFA series switches can reduce total cost bill of materials BOM list size and weight while simultaneously increasing efficiency productivity and system reliability This application note describes design considerations of an asymmetric PWM half bridge converter with current doubler and synchronous rectifier employing FSFA series switches It includes a step by step design procedure as well as the general features and operational principles of the proposed topology 1 Operational Principles of a Conventional Asymmetric PWM Half Bridge Converter Figure 1 shows a conventional asymmetric PWM half bridge converter with a center tapped transformer While the switch S operates with a duty D depending on the input voltage and load current the switch S operates with D During DTs Vin Vc is applied on the primary side of the transformer and the secondary diode D turns on The primary current i increases since the magnetizing current i of the transformer not illustrated and the output inductor current iz increase together During D Ts Vc is applied on the transformer and D turns on The capacitor C is not only a voltage source during D Ts but also a DC blocking capacitor to prevent transformer saturation When the volt sec balance for the magnetizing indu
13. d time and the reason mentioned in 2 With respect to both energy 1 and 1 and timing 2 amp 3 and 2 amp 3 the ZVS condition of S is more difficult to achieve than that of S Therefore the ZVS condition should be considered with S only In general the condition for timing is easily satisfied if the condition for energy is www fairchildsemi com AN 4153 satisfied Therefore the required leakage inductance for the ZVS of both switches at special load condition can be calculated as 2Coss 1 DW F 11 b gt _2assl D Fa DA DW x Ts Lotar Ln Plo tar where Coss 1s the output capacitance of the switch and Jo ja is the target load condition where a designer wants the system to operate in ZVS condition with the leakage inductance d Mode 1_4 t t APPLICATION NOTE An easy way to achieve ZVS for both switches even at light load conditions is to increase L However the increased Li increases duty loss parts by reducing the slope of the primary current in Modes 1 and 3 This results in the increase of conduction loss for the reduced effective duty cycle Therefore it is not recommended as a method to increase L for ZVS at very light load According to Equation 9 as the load current decreases the DC component of the magnetizing current decreases as well If the DC component of i is less than half the ripple component of i the ZVS operation is performed by the
14. eneninad a ZVS fail begins Vos s 20V div Vis s 200V div OUNO NEAN A b Figure 18 ZVS Verification a at 40 Load b at 30 Load 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 Nee Ta te een APPLICATION NOTE 96 95 F 94 93 p 92 p Efficiency 91 F 90 F 89 p 88 40 50 60 Load Figure 19 Measured Efficiency of the Designed Converter 6 References 1 Hong Mao Songquan Deng Yangyang wen and Issa Batarseh Unified Steady State Model and DC Analysis of Half Bridge DC DC Converters with Current Doubler Rectifier APEC 04 Nineteenth Annual IEEE Vol 2 2004 pp 786 791 2 Yu Chieh Hung Fu San Shyu Chih Jung Lin and Yen Shin Lai Design and Implementation of Symmetrical Half Bridge DC DC Converter The Fifth International Conference on PEDS 2003 Vol 1 Nov 2003 pp 338 342 3 Panov Y and Jovanovic M M Design and Performance Evaluation of Low Voltage High Current DC DC On board Modules IEEE Transactions on Power Electronics Vol 16 Issue 1 Jan 2001 pp 26 33 www fairchildsSemi com AN 4153 DISCLAIMER APPLICATION NOTE FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEI
15. er waveforms the SRs are turned off more rapidly and definitely than in the transformer coupling case In Figure 17 the smaller negative parts in the inductor coupling case are shown compared to the transformer coupling case The smaller negative parts allow the power losses on the gate driver circuit for SRs to be reduced The ZVS operations at various load conditions are shown in Figure 18 The drain voltage and the gate signal of the lower side switch are displayed As designed in the previous chapter the converter shows ZVS operation downs to 30 load condition The efficiency of the converter is shown in Figure 19 The measured efficiencies are 93 7 94 6 and 93 1 at 20 50 and 100 of the rated load condition respectively It shows a marginal performance so that the 85 PLUS program can be achieved with well designed PFC and DC DC stages ito1 5A div itoo 5A div sr 10A div isr2 10A div EF 2us div AEE ee Figure 16 Waveforms for the Secondary Side 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 www fairchildSemi com AN 4153 Vn2 10V div sae aaoo anne 7 o Var 10V div Vn2 10V div Vat 10V div i oF 10 wit Figure 17 Gate Signals for SR Upper Waveforms Use Output Inductors Lower Waveforms Use the Transformer ri Vos s 20 V div GUSAN en Vis s 200V div puneunaanibanenemspeseesaneninunietannnneetiasenn
16. erally i has a DC offset so the core saturation has to be taken into account when the transformer is designed 2 Operational Principles of an Asymmetric PWM Half Bridge Converter with Current Doubler and Synchronous Rectifier For low output voltage and high output current applications the current doubler is widely used Figure 5 illustrates the asymmetric PWM half bridge converter with the current doubler on the secondary side The secondary winding is a single ended configuration while the output inductors are divided into two smaller inductors To increase the total efficiency a synchronous rectifier SR comprised of MOSFETs with low Rason is used The current doubler has several advantages compared to the conventional center tapped configuration First the DC component of the magnetizing current is lower than or equal to that of the center tapped configuration which makes it possible to use the smaller core for the transformer The amount of the magnetizing current is the same as that of the center tapped configuration when each output inductor carries half the load current The amount of the magnetizing current is reduced when the output inductors carry the load current unevenly Second the root mean square rms value of the secondary winding current is smaller than that of the center tapped configuration since almost half of the load current flows through each output inductor As a result the low current density for the se
17. ers inductors and capacitors The voltage on the output capacitors is progressively increased to smoothly establish the required output voltage For the FSFA series the soft start time is internally implemented for 15ms when the operating frequency is set to 100 kHz In addition to help the soft start operation a capacitor and a resistor are connected on the Ry pin externally as shown in Figure 11 Before the power supply is powered on the capacitor C07 remains fully discharged After power on Cj97 becomes charged gradually by the current through the Rr pin which determines the operating frequency The current through the Ry pin is inversely proportional to the total impedance of the connected resistors The total impedance during startup is lower than that of the normal operation because Rj97 is added on Rj 5 in parallel which means the operating frequency decreases continuously from higher to nominal Eventually Cjo7 is fully charged to the Ry pin voltage and the operating frequency is determined by R o5 only During C797 charging time the operating frequency is higher than during normal operation In asymmetric PWM half bridge converters a switching period contains powering and commutation periods The energy cannot be transferred to the output side during the commutation period Since the DC www fairchildsemi com AN 4153 APPLICATION NOTE link voltage applied to the Vp pin and the leakage inductance of the main transfor
18. from Vey to Vin 2 The instant t must be earlier than when the primary current changes its polarity Otherwise the drain voltages of S and S are again charged and discharged respectively 3 The gate signal of S must be applied before the primary current changes its polarity Figure 9 shows the detailed modes in Mode 3 While the detailed mode analysis is similar to the case of Figure 8 three conditions for the ZVS operation of S are different from those of Figure 8 1 Since the polarity of the transformer terminals changes when vpsz reaches Vc the portion of discharging S by the load current t t is much larger than t t in Figure 8 Therefore the remaining portion of discharging S by the energy in the leakage inductance only is shortened the ZVS of S is easier to achieve compared with the ZVS of S Therefore the energy in the leakage inductance should be sufficient to discharge S from Vc to zero and charge S from Vin Vcp to Vin 2 The commutation between SRs begins with the change of polarity of the transformer terminals so that it takes longer from to the instant when the currents in SRs are equal In addition the commutation slope is more sluggish than the case in Figure 8 since the applied voltage on the leakage inductance is reduced to Vc from V V cy 3 The gate signal of S must be applied before the primary current changes its polarity if Condition 3 is satisfied due to the same dea
19. in SS Ss 2n 2 6 5 The given core is EER4042 4 158 mm The minimum turns number for the transformer primary side is calculated as 2 31A ee L max 5 1 yin En _ 6004 2331 _ mn 38 14 158u 0 23 A B e max When Np is selected as 39 the secondary turns number is obtained as 6 Use Equations 19 23 to get the rms value of the transformer primary side current Assume each output inductor carries the output load current evenly at the nominal condition D 0 397 6 5 2 l l 6 5 15 1 357 _ 6 5 2 Paa aane e ET 6 5 2 www fairchildsemi com AN 4153 Therefore the rms value of the transformer primary side current is obtained by Equation 19 as 2 1 2 1 3 46 3 467 FMS 3 7 1 15 1 15 2 51 2 51 3 0 397 1 0 397 2 29 A The rms value of the transformer secondary side current 1s half the load current so is 15 A Since the diameter of the wire becomes too thin it is not easy to wind 39 turns for the primary side of the transformer in two layers Choose the biggest wire that can be wound 13 turns in one layer of the bobbin for EER4042 Due to consideration of the skin effect Litz wire of 100 strands with AWG38 American wire gauge is selected as the primary wire In this case the current density is around 2 9 A mm For the secondary side 250 strand Litz wire with AWG36 is chosen where the current density is around 4 7 A mm STE
20. in Vow L nf L m L i ie Vo F D1 D2 t t 4 t t t Figure 3 Key Waveforms of the Conventional Asymmetric PWM Half Bridge Converter and scaling down v7 by n In addition the applied voltage on the primary side of the transformer during powering modes t t and t3 t is slightly less than V Vc or V ce due to the leakage inductance L as shown in Figure 3 Therefore the output voltage equation could be obtained as L 2D 1 DW AloL Vo m in _ 9 lk _ V 4 where Jo is the output load current and V is the forward voltage drop of the secondary side rectifying diodes To design the transformer the magnetizing current must be known Assume that the magnetizing inductance and the output inductance are high enough for the current ripple on them to be ignored and the leakage inductance is low enough for the duty loss parts to be neglected Then the current waveforms are simplified as shown in Figure 4 To meet the current sec balance for C the positive part of the primary current i 1s equivalent to the negative part such p that the magnetizing current is obtained as lpri same area Figure 4 Simplified Current Waveforms in the Primarv Side www fairchildSemi com AN 4153 1 10 D 1 40 lt a D n n o 1 2p 42 n 5 where J is the DC component of im As can be seen in Equation 5 could be zero when the duty cycle is 50 Gen
21. ions are Nominal input voltage 390 Vac Input voltage range 370 410 Vac Output voltage 12 V Output current 30 A Switching frequency 100 kHz STEP 2 Turns Ratio and Duty Cycle The output voltage equation Equation 8 is used to determine turns ratio n However the output voltage equation contains the leakage and magnetizing inductance which are not yet determined Therefore a designer should make assumptions for the following Vsr considering Rason of used MOSFETs as an SR a the ratio between L and Lp L The leakage inductance that will be changed later by iterations of Equations 11 and 12 The nominal duty cycle at the nominal input voltage According to Equation 8 the turns ratio is obtained as D Dp Winn Dn 0 Diy Winn 4V o V sp lol o l p13 2 Vo Vsr a n where Vinn and D are the nominal input voltage and the nominal duty cycle at Vinn respectively For turns ratio n the duty cycle at an input voltage and a load current is calculated as 1 1 4 nVo Vsr aV nV D ___ Se 14 www fairchildsemi com AN 4153 C102 FUSE1 oN R105 R107 Vin o PFC output Clink 242 APPLICATION NOTE Vo 12V 30A N N Rsn2 Cout1 Q102 Csn2 L201 No QOOU Figure 11 Reference Design Schematic Design Example For the example the following values are assumed E V sp 0 3V qis 0 95 The initial
22. itions of the switching period One of the advantages of these techniques is to use the parasitic components such as the leakage inductance of the main transformer and the output capacitances of the switches so there is no need to add more external components to achieve soft switching In addition these techniques take pulse width modulation PWM up with fixed switching frequency Therefore these are easier to understand analyze and design than load resonant techniques Due to its simple configuration and zero voltage switching ZVS characteristic an asymmetric PWM half bridge converter is one of the most popular topologies using the zero voltage transition technique In addition the ripple component of the output current due to an output inductor becomes small enough to be handled by an appropriate output capacitor Being easy to analyze and design and having an output inductor it is generally used for applications with high output current and low output voltage 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 e g game console power supplies To handle the large output current using a synchronous rectifier in the secondary side is popular to obtain the conduction losses as ohmic losses instead of diode losses In addition a current doubler increases the utilization of the main transformer when the output current is high Fairchild s FSFA series of green power switches FPS integrates a PWM controller an
23. leakage inductance is 20 uH This may be increased after checking the ZVS condition Taking the core size for 360W into account if L is less than this value the productivity is not good The nominal duty cycle at 390 V4 1s 0 4 Using these values the turns ratio is obtained by Equation 13 as 0 4 0 6 390 0 4 0 6 390 4 12 0 3 oe 0 95 10u 2 12 0 3 0 95 n 6 52 yielding a turns ratio is 6 5 The nominal duty cycle at the nominal input voltage is recalculated by Equation 14 as 1 h 4a65 02 0 3 _ 30 204 0 95 390 6 5 390 10 D lt 0 397 2 STEP 3 Magnetizing and Leakage Inductance Using the turns ratio obtained in Step 2 the ZVS condition could be checked with Equations 11 and 12 Design Example This example is designed to achieve the ZVS operation from full to 30 load condition using the leakage inductance and the magnetizing inductance The duty cycle at 30 load condition and the maximum input voltage is obtained by Equation 14 as 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 1 h4 6 5 02 0 3 9 20u 0 95 410 6 5 410 10u Do3 2 0 305 Since Coss of the FSFA2100 MOSFETs is 150 pF the required leakage inductance is obtained with D so0 305 as 2Coss 1 DW F 5 2 DiI D V x T ux 1 Lin y DI 6 sar 2 L Lg 2n Le F E n 2 150p 1 0 305 410 230s oS ome 9 t 4004 ras 2 400 u
24. lectrical Characteristics Magnetizing Inductance Lm 600 uH typical Remark 100 kHz 1 V All other pins open Spec 600 H 5 20 uH 10 Leakage Inductance Ly W N 5 Experimental Results Figures 15 and 16 show the experimental waveforms of the converter designed in the previous chapter at the nominal input and the full load condition The gate signal of S the primary and secondary side voltages across the main transformer and the primary current are shown in Figure 15 These waveforms are consistent with the theoretical analysis including the ZVS operation The output inductor currents and the SRs currents are shown in Figure 16 The output inductor currents are unbalanced due to the duty cycle and the parasitic components which means the averaged magnetizing current is smaller than that of the center tapped configuration Figure 17 shows the winding voltages for the gate driver circuits of SRs at the full load condition The upper waveforms are for the inductor coupling illustrated in Figure 6 b while the lower ones are for the transformer coupling Yen st Wav AA vn 100V div i r Vro 20V div en a d i n 2us div pri 2A div J ee a a ScEnE hea aae Figure 15 Experimental Waveforms 100 kHz 1 V All other pins shorted illustrated in Figure 6 a As can be seen in Figure 17 since the winding voltage decreases to the negative at the turn off transition in the upp
25. mer are fixed the powering period over the switching period is shorter in high switching frequencies As C797 is charged the switching frequency decreases so that the powering period over the switching period increases It is helpful to start SMPS with the internal soft start time together Design Example In the design example 2 2 uF and 12 KQ are selected as C307 and R97 respectively R105 R107 27k 12k Vin Clink 330uF ZZZZ PFC output 450V 3 mm 4 Design Summary Figures 13 and 14 show the full schematic of the reference design and its transformer configuration Table 1 shows the detailed wire information of the transformer The electrical features of the transformer are described in Table 2 No N4 1 1 EER4042 Rsni L202 15uH Csn1 Cout2 1000uF 2 2nF 2 50R Cout1 1000uF L201 ea Csn2 15uH 2 2nF gt V 3mm 25 J 25 X24 X23 X22 X21 X20 19 K 18 Y 17 Xie 15 X14 V Y ai air a Ci ma a a ai a a OA ay Oe 1 EO Figure 14 Transformer Construction of the Reference Design www fairchildsSemi com 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 AN 4153 APPLICATION NOTE Table 1 Transformer Winding Specifications Pin start Winding end Wire Winding Method Insulation Tape 25 um IT Insulation Tape 25 um IT NOTE 1 Insulation tape 25 um 1T each should be inserted between the layers Table 2 Transformer E
26. n S turns off Mode 1 starts as another regenerating mode The operating principle of Mode is almost the same as Mode 3 except for a ZVS condition In Mode 1 vy becomes zero at the instant when the output capacitance voltage of S is equivalent to V Vc Before this instant the load current on the output inductor Loz is reflected to the primary side of the transformer and helps to meet the ZVS condition of the switches The energy stored in the leakage inductance only has to discharge and charge the output capacitance of the switches after this instant Therefore the ZVS condition for S is harder than S since V Vc is higher than Vc in general In all other respects Mode 1 can be analyzed in the same way as Mode 3 The duration of Mode 1 is obtained as I L Dass n 7 n d DW in x Is The detailed output voltage is calculated with Equations 6 and 7 as m __ L DQ DY r LAL Say k ra 8 n n Ts where Vspr is the voltage across the MOSFET as an SR during powering modes It is similar to Equation 4 except for the turns ratio which is half that of the conventional converter By modifying Equation 5 the DC and ripple components of i are obtained as Ly 1 py 22 p40 9 n n 10 LL Oe Nin E DT W X where J 9 and J q7 are the DC components of the output inductor currents 2 2 ZVS Conditions In the previous section the duration for ZVS operation was omitted to simplify mode anal
27. nce the internal threshold voltage for the pulse by pulse current limit is 0 58 V 0 1 Q is selected as the sensing resistor R701 STEP 9 Synchronous Rectifier The voltage stresses on the SRs are calculated as DV Vsr z VS 29 For windings to drive the gate of the SRs during powering modes the voltages across the output inductors are Voi N 30 n DV in O Vo 31 n Design Example Considering the worst case for each SR the voltage stresses on them are DV 0 5x410 Vip e nn 82 di 6 5 A DW 1 0 x410 ou aaa Ta 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 APPLICATION NOTE An N channel power MOSFET with 8mQ of Rason and 100V of the voltage rating HUF75652G3 is selected for both SRs with consideration of the voltage ringing and overshoot The voltages across the output inductors during powering modes are in De sz70v 100 370 7 Viz O n z Q 0 458 370 1 _ 19 6 5 max 1 0 410 410 Vr201 oy Ca ek V 12 51 n 6 5 min 0 in V2 3 Vo zE ax _ Pasmo 100 X370 _ E 0 458 x 370 a L202 7 O 65 12 14 To protect the SRs the gate signal has to be restricted 20 V The turns ratios between the output inductors and the windings for the gate drivers are N ae 3 Nj N a N3 STEP 10 External Soft Start At startup the duty cycle starts increasing slowly to establish the correct working conditions for transform
28. ter with the Current Doubler b Figure 6 Methods for Producing the Gate Driver Signal Using a the Transformer b the Output Inductor www fairchildsSemi com AN 4153 Let s start with Mode 2 a powering mode When S turns on V Vcp 18 applied on the primary side of the transformer The magnetizing current i increases with the slope of Vin Vcp Lm The slope of the current of Lo is determined by subtracting the output voltage from V Vcp n because SR turns off On the other hand the current of Loz decreases with the slope of Vo Loz2 which is free wheeling through SR While two output inductors share the load current SR carries the whole load current The secondary winding of the transformer handles only izo so that izo n is the reflected current to the primary side of the transformer and it is superimposed on the magnetizing current which constitutes the primary current i In fact vm is slightly lower than the value illustrated in Figure 7 due to leakage inductance see Chapter 1 It is ignored in this section to simplify analysis When S turns off Mode 3 begins As the output capacitance of S is discharged vr decreases It becomes zero when the output capacitance voltage of S equals Vc At this time the Lo1 APPLICATION NOTE body diode of SR turns on since its reverse biased voltage is eliminated Subsequently both SRs turn on together during this mode The
29. y side is obtained as 18 where Np is larger than Np in Equation 17 The diameter of the wire is selected based on the current density whose range is generally 4 10 A mm It is recommended to select the current density as low as possible to reduce conduction losses on the wire However try to reduce the winding layers at the same time The more winding layers the more circulating current caused by the proximity effect Sometimes trying to reduce conduction losses by increasing the wire diameter makes conduction losses increase by increasing the circulating current In 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 APPLICATION NOTE addition it is better to choose a wire with multi strands of thinner wire such as Litz wire to minimize the skin effect When the output inductor current ripple is ignored Figure 12 shows the primary current waveform The rms value of this waveform is given as 2 2 2 2 i Cu tine hi p Hes eintiid 19 io lro I 2n 20 I oI I Abn 21 n 2 Ip u L n 22 Ip 202 4g 2n 23 where and 4i are defined in Equations 9 and 10 For the secondary side winding half the load current is the rms value when it is assumed that each output inductor carries the load current evenly and the ripple on the output inductor is small enough to be ignored Design Example When the duty cycle is zero the maximum i is obtained as Io 30 L
30. ysis More detailed analysis for ZVS operation is given in this section to discover an exact ZVS condition for each switch Figure 8 shows the detailed modes for Mode 1 From fj the primary current starts to charge and discharge the output capacitance of the switches Before the drain voltage of S vps reaches to V Vc the dotted terminal of the transformer is negative so that SR is still reverse biased 2008 Fairchild Semiconductor Corporation Rev 1 0 0 12 9 08 APPLICATION NOTE Therefore not only the energy in the leakage inductance but also the energy of the load current helps S be discharged from V to V Vc After vps is reduced more than V V cp the dotted terminal of the transformer changes its polarity which allows the body diode of SR to turn on Therefore the magnetizing inductance is short circuited so that the switches are charged and discharged by the energy in the leakage inductance only from t Finally vps is fully discharged at so the primary current flows through the body diode of S as can be seen in Figure 8 c After te the primary current flows through both the channel and the body diode since the gate signal of S is applied Mode 2 begins with the end of the commutation between SRs from ft For the ZVS operation of S there are three conditions in Figure 8 as follows 1 The energy in the leakage inductance should be sufficient to discharge S from V Vc to zero and charge S
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