FAIRCHILD HUF75332G3 HUF75332P3 HUF75332S3S Manual
Contents
1. 10 1000 259 FOR TEMPERATURES n ABOVE 25 C DERATE PEAK a v CURRENT AS FOLLOWS gt EI Tc P E iw 150 2 o x i Ves 10V n 100 Bs TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 105 10 4 103 10 109 10 t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY 500 MRO TTT 500 T MAX RATED 1 22 tav L Ias 1 3 RATED BVpss Vpp kom m m mum n n o Tc 25 C IfR 0 lt cz E tav L R In las R 1 3 RATED BVpss Vpp 1 ae S 100 Y E 2 X x MES Fe Es 100 4 in E STARTING Ty 25 C T gt z hA E 10 gt 1 lt z OPERATION IN THIS _ 4509 E AREA MAY BE N 3 STARTING Ty 150 C L LIMITED BY rps oN 10ms E VDSS MAX 55V T 1 0 001 0 1 1 1 10 100 200 tay TIME IN AVALANCHE ms Vps DRAIN TO SOURCE VOLTAGE V NOTE Refer to Fairchild Application Notes AN9321 and AN9322 FIGURE 5 FORWARD BIAS SAFE OPERATING AREA FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 150 T T T PULSE DURATION 80us 25 C DUTY CYCLE 0 5 MAX 2 4 120 E E 2 90 p 3 3 2 2 5 60 z 60 5 5 5 30 PULSE DURATION 80us 30 DUTY CYCLE 0 5 MAX 25 C 15V 0 1 0 1 5 3 0 45 6 0 7 5 0 1 5 3 0 4 5 6 0 7 5 Vps DRAIN TO SOURCE VOLTAGE2. FAIRCHILD SEMICONDUCTOR Data Sheet HUF75332G3 HUF 75332P3 HUF75332S3S 60A 55V 0 019 Ohm N Channel UltraFET Power MOSFETs a These N Channel power MOSFETs T are manufactured using the r innovative UltraFET process This advanced process technology achieves the lowest possible on resistance per silicon area resulting in outstanding performance This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge It was designed for use in applications where power efficiency is important such as switching regulators switching converters motor drivers relay drivers low voltage bus switches and power management in portable and battery operated products January 2005 Features 60A 55V Simulation Models Temperature Compensated PSPICE and SABER Models SPICE and SABER Thermal Impedance Models Available on the WEB at www fairchildsemi com Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334 Guidelines for Soldering Surface Mount Components to PC Boards Symbol Formerly developmental type TA75332 D Ordering Information PART NUMBER PACKAGE BRAND G HUF75332G3 TO 247 75332G HUF75332P3 TO 220AB 75332P S HUF75332S3S TO 263AB 75332S NOTE When ordering use the entire part number Add the suffix T to obtain
3. WAVEFORMS IN DESCENDING ORDER lp 60A Vas GATE TO SOURCE VOLTAGE V Ip 45A 4 Ip 30A 1 15 0 10 20 Qg GATE CHARGE nC 40 50 60 NOTE Refer to Fairchild Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 75332535 Rev B1 HUF75332G3 HUF75332P3 HUF75332S3S Test Circuits and Waveforms Vps VARY tp TO OBTAIN REQUIRED PEAK lAs Vas ov FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT Vps RL Vas DUT IG REF FIGURE 16 GATE CHARGE TEST CIRCUIT Vps RL V Gs DUT FIGURE 18 SWITCHING TIME TEST CIRCUIT BVpss tp Vps las B ed VDD FIGURE 15 UNCLAMPED ENERGY WAVEFORMS VoD lg REF 0 FIGURE 17 GATE CHARGE WAVEFORM 90 Ves 50 PULSE WIDTH FIGURE 19 RESISTIVE SWITCHING WAVEFORMS 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 75332535 Rev B1 HUF75332G3 HUF75332P3 HUF75332S3S PSPICE Electrical Model SUBCKT HUF75332 213 rev 17 February 1999 12 8 1 8e 9 CB 15 14 1 73e 9 LDRAIN CIN 6 8 1 19e 9 DPLCAP 5 Sm DRAIN 02 10 DBODY 7 5 DBODYMOD RSLC1 BEDBAIM DBREAK 5 11 DBREAKMOD DBREAK DPLCAP 10 5 DPLCAPMOD RSLC2 ESLC
4. 9 ns Rise Time tr 90 ns Turn Off Delay Time td OFF 50 ns Fall Time tf E 45 ns Turn Off Time 125 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Qg ror Vas 0Vto20V Vpp 30V 70 85 nC Gate Charge at 10V agao Vas OV to 10V oe aa 40 50 nC Threshold Gate Charge Qg TH Vas OV to 2V lg REF 1 0mA 2 5 3 0 nC Gate to Source Gate Charge Qgs Figure 13 6 nC Reverse Transfer Capacitance 15 nC 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 HUF75332S3S Rev B1 HUF75332G3 HUF75332P3 HUF75332S3S Electrical Specifications 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Vas OV s 1300 E pF Output Capacitance Coss fbi 480 pF Reverse Transfer Capacitance Crss 115 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Reverse Recovery Time trr Isp 60A dlsp dt 100A us 75 ns Reverse Recovered Charge QRR Isp 60A dlsp dt 100A us 140 nC Typical Performance Curves 12 80 J 10 E 60 E E 08 2 5 0 6 5 40 E 2 a z 2 04 29 8 0 2 a 0 0 25 50 75 100 125 150 175 25 50 75 1
5. MODEL MWEAKMOD NMOS VTO 2 703 KP 0 008 IS 1 30 N 10 TOX 1 L 1u W 1u RG 13 MODEL RBREAKMOD RES TC1 1 05e 3 TC2 4 5e 7 MODEL RDRAINMOD RES TC1 1 16e 2 TC2 1 7e 5 MODEL RSLCMOD RES TC1 3 96e 3 TC2 2 7e 6 MODEL RSOURCEMOD RES TC1 1 3 TC2 1 5 MODEL RVTHRESMOD RES TC1 2 8e 3 TC2 1 0e 5 MODEL RVTEMPMOD RES TC1 2 75e 3 TC2 5 0e 7 MODEL S1AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 8 VOFF 3 MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 3 VOFF 8 MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 VOFF 0 5 MODEL S2BMOD VSWITCH RON 1 5 ROFF 0 1 VON 0 5 VOFF 0 ENDS NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 HUF75332S3S Rev B1 HUF75332G3 HUF75332P3 HUF75332S3S SABER Electrical Model REV 17 February 1999 template huf75332 n2 n1 n3 electrical n2 n1 n3 var i d model dbodymod is 1 3e 12 xti 6 cjo 1 7e 9 tt 4 0e 8 m 0 45 vj 0 75 d model dbreakmod LDRAIN d model dplcapmod 1 8e 9 is 1e 30 m 0 9 vj 1 45 DPLCAP 5 DRAIN m model mmedmod type n vto 3 183 kp 2 is 1e 30 tox 1 10 2 m m
6. SABER Thermal Model SABER thermal model HUF75332 template thermal_model th tl thermal_c th tl ctherm ctherm1 th 6 4 00e 3 ATER ctherm ctherm2 6 5 7 00e 3 ctherm ctherm3 5 4 7 50e 3 ctherm ctherm4 4 3 8 00e 3 ctherm ctherm5 2 1 85e 2 ctherm ctherm6 2 tl 12 55 CTHERM4 RTHERM5 5 rtherm rtherm1 th 6 7 09e 3 rtherm rtherm2 6 5 1 77e 2 rtherm rtherm3 5 4 4 97e 2 rtherm rtherm4 4 3 2 79e 1 rtherm rtherm5 3 2 4 21e 1 rtherm rtherm6 2 tl 5 58e 2 RTHERM6 CTHERM6 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 HUF75332S3S Rev B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx FAST IntelliMAX POP SPM ActiveArray FASTr ISOPLANAR Power247 Stealth Bottomless FPS LittleFET PowerEdge SuperFET CoolFET FRFET MICROCOUPLER PowerSaver SuperSOT 3 CROSSVOLT GlobalOptoisolator MicroFET PowerTrench SuperSOT 6 DOME GTO MicroPak QFET SuperSOT 8 EcoSPARK MICROWIRE QS SyncFET 5 MSX QT Optoelectronics TinyLogic EnSigna i Lo MSXPro Quiet Series TINYOPTO ImpliedDisconnect RapidConfigure TruTranslation FACT Quiet Series OCXPro RapidConnect
7. V FIGURE 7 SATURATION CHARACTERISTICS Vas GATE TO SOURCE VOLTAGE V FIGURE 8 TRANSFER CHARACTERISTICS 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 75332535 Rev B1 HUF75332G3 HUF75332P3 HUF75332S3S Typical Performance Curves Continued 2 5 r PULSE DURATION 80us DUTY CYCLE 0 5 MAX Ves 10V Ip 60A NORMALIZED DRAIN SOURCE ON RESISTANCE amp 0 5 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1 2 Ip 250uA E o NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 9 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 1 2 Ves Vps lp 2504 o NORMALIZED GATE THRESHOLD VOLTAGE 0 6 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2000 Ves OV f 1MHz Ciss Cos Cnss T 1500 Coss Cps Cap4 E 2 Ciss 1000 8 amp oO 500 999 CRss 0 0 10 20 30 40 50 60 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10
8. contains the design specifications for In Design product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only Rev 115
9. the TO 263AB variant in tape and reel e g HUF75332S3ST Packaging JEDEC STYLE TO 247 JEDEC TO 220AB SOURCE SOURCE DRAIN DRAIN GATE GATE DRAIN FLANGE DRAIN TAB JEDEC TO 263AB DRAIN GATE FLANGE SOURCE Product reliability information can be found at http www fairchildsemi com products discrete reliability index html For severe environments see our Automotive HUFA series All Fairchild semiconductor products are manufactured assembled and tested under ISO9000 and 059000 quality systems certification 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 HUF75332S3S Rev B1 HUF75332G3 HUF75332P3 HUF75332S3S Absolute Maximum Ratings 25 C Unless Otherwise Specified UNITS Drain to Source Voltage Note 1 Vpss 55 V Drain to Gate Voltage Ras 20kO Note 1 VpGR 55 V Gate to Source Voltage Vas 320 V Drain Current Continuous Figure 2 Ip 60 A Pulsed Drain Figure 4 Pulsed Avalanche 0 EAS Figure 6 Power Dissipation iam Rn E rre Pp 145 6 2500 i tute edo esce xa Dae DN 0 97 W C Operating and Storage Ty 55 to 175 C Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case
10. 00 125 150 175 CASE TEMPERATURE 9 Tc CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE 2 DUTY CYCLE DESCENDING ORDER 10 5 0 2 0 05 i 1 5 0 02 w 4001 1 s 2 DM 9 d 01 J Sz r ty 1 NT t 2 NOTES 1 DUTY FACTOR D 1 42 1 SINGLE PULSE PEAK Ty X Zouc X Tc 0 01 pot pitiit 105 10 4 103 10 1071 100 101 t RECTANGULAR PULSE DURATION s FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 HUF75332S3S Rev B1 HUF75332G3 HUF75332P3 HUF75332S3S Typical Performance Curves Continued
11. 105 TL 300 Me Package Body for 10s See Techbrief 334 Tpkg 260 oc CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE 1 Ty 25 C to 150 C Electrical Specifications Tc 25 C Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250uA Vas OV Figure 11 55 V Zero Gate Voltage Drain Current Ipss Vps 50V Ves OV 1 uA Vps 45V Vas 150 C 250 Gate to Source Leakage Current lass Vas 320V 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas rTH Vas Vps lp 250uA Figure 10 2 4 V Drain to Source On Resistance lp 60A Vag 10V Figure 9 0 016 0 019 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case ReJc Figure 3 1 03 Thermal Resistance Junction to Ambient RaJA TO 247 e 5 30 C W TO 220 TO 263 62 C W SWITCHING SPECIFICATIONS Ves 10V Turn On Time ton Vpp 30V Ip 60A E 130 ns Turn On Delay Time ld ON idm nn
12. 11 EBREAK 11 7 17 18 58 85 50 EDS 14 8 5 81 EGS 13 8 6 81 RDRAIN e DBODY ESG 6 106 8 1 ESG O EBREAK EVTHRES 6 21 198 1 EVTHRES Ia 7 EVTEMP 20 6 18 22 1 a 4 MWEAK LGATE EVTEMP GATE RGATE 6 LDRAIN 2 5 16 9 LSOURCE LGATE 1 9 1 9 CIN OURCE LSOURCE 3 7 1 9 SE 33 K1 LSOURCE LGATE 0 0085 RSOURCE RLSOURCE IT 8 17 1 MMED 16 6 8 8 MMEDMOD sia 9 sna MSTRO 16 6 8 8 MSTROMOD 12 i RBREAK MWEAK 16 21 8 8 MWEAKMOD 13 14 17 18 RBREAK 17 18 RBREAKMOD 1 SIBo 9528 RVTEMP RDRAIN 50 16 RDRAINMOD 4 5e 3 13 eH M RGATE 9 20 1 3 CA IT 4 RLDRAIN 2 5 10 A RLGATE 1910 EGS EDS NBAT RLSOURCE 37 10 t RSLC1 5 51 RSLCMOD 1e 6 RSLC2 5 50 1e3 22 RSOURCE 8 7 RSOURCEMOD 5 95e 3 RVTHRES RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 180 4 6 MODEL DBODYMOD D IS 1 3e 12 RS 3 0e 3 IKF 20 6 TRS1 2 7e 3 TRS2 7 0e 7 1 7e 9 TT 4 0 8 M 0 45 vj 0 75 MODEL DBREAKMOD D RS 1 71e 2 IKF 1 0e 5 TRS1 4 0e 4 TRS2 1 55e 5 MODEL DPLCAPMOD D CJO 1 8e 9 IS 1e 30 N 1M 2 0 9 vj 1 45 MODEL MMEDMOD NMOS VTO 3 183 KP 2 IS 1 30 N 10 TOX 1L 1u W tu RG 1 3 MODEL MSTROMOD NMOS 3 66 KP 51 5 IS 1 30 N 10 1L 1u W 1
13. UHC Across the board Around the world OPTOLOGIC uSerDes UltraFET The Power Franchise OPTOPLANAR J SILENTSWITCHER UniFET Programmable Active Droop PACMAN SMART START VOX DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TOANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into support device or system whose failure to perform can the body or b support or sustain life or c whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can be effectiveness reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms Advance Information Formative or This datasheet
14. drain n2 n5 10 res rlgate n1 n9 10 res rlsource n3 n7 10 51 1 n5 n51 1 6 3 96e 3 tc2 2 7e 6 res rsic2 n5 n50 1e3 res rsource n8 n7 5 95 3 1e 3 tc2 1e 5 res rvtemp n18 n19 1 tcl 2 75e 3 tc2 5 0e 7 res rvthres n22 n8 1 tc1 2 8e 3 tc2 1 0e 5 Spe ebreak n11 n7 n17 n18 58 85 Spe eds n14 n8 n5 n8 1 spe egs n13 n8 n8 1 spe esg n6 n10 n6 n8 1 spe evtemp n20 n6 n18 n22 1 spe evthres n6 n21 n19 n8 1 vcsp s a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod vcsp s2a n6 n15 n14 n13 model s2amod vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 166 180 4 6 1 SOURCE pun RSOURCE RLSOURCE RBREAK 17 18 RVTEMP 19 4 1 VBAT 22 RVTHRES 2005 Fairchild Semiconductor Corporation HUF75332G3 HUF75332P3 HUF75332S3S Rev B1 HUF75332G3 HUF75332P3 HUF75332S3S SPICE Thermal Model th JUNCTION REV 11 1999 HUF75332 CTHERM th 6 4 00 3 RTHERM1 CTHERM1 CTHERM2 6 5 7 00e 3 CTHERMS 5 4 7 50e 3 CTHERMA 4 3 8 00e 3 CTHERM5 3 2 1 85e 2 CTHERM6 2 tl 12 55 RTHERM2 2 RTHERM1 th 6 7 09e 3 2 6 5 1 77e 2 RTHERMS 5 4 4 97 2 RTHERM4 4 3 2 79e 1 RTHERMS 3 2 4 21e 1 RTHERM6 2 tl 5 58e 2 RTHERM3 CTHERM3
15. odel mstrongmod type n vto 3 66 kp 51 5 is 1e 30 tox 1 RLDRAIN m model mweakmod type n vto 2 703 kp 8 0e 3 is 1e 30 tox 1 RSLC1 Sw vcsp model 1 ron 16 5 roff 0 1 von 8 voff 3 51 RDBREAK sw vcsp model s1bmod 16 5 0 1 von 3 voff 8 RSLC2 2 Sw vcsp model s2amod ron 16 5 roff 0 1 von 0 voff 0 5 ISCL RDBODY vcsp model s2bmod ron 16 5 roff 0 1 von 0 5 voff 0 50 DBREAK c ca n12 n8 1 8e 9 RDRAIN 71 c cb n15 n14 1 73e 9 ESG o 11 c cin n6 n8 1 19e 9 EVTHRES 21 16 d dbody n7 71 model dbodymod LGATE EVTEMP O MWEAK DBODY d dbreak n72 n11 model dbreakmod GATE RGATE Ig d dplcap n10 n5 model dplcapmod 10 DET e MED RLGATE 4 5 i it n8 n17 1 CIN LSOURCE 8 I Idrain n2 n5 1 0 9 l lgate n1 n9 1 0e 9 5 n7 1 0e 9 k Kl i I lgate i I lsource I l Igate I I lsource 0 0085 S1A 9 952 12 13 14 13 S1B o m mmed n16 n6 n8 n8 model mmedmod 1u w 1u m mstrong n16 n6 n8 n8 model mstrongmod 1u w 1u m mweak n16 n21 n8 n8 model mweakmod 1u w 1u CA res rbreak n17 n18 1 tc1 1 05e 3 tc2 4 5e 7 res rdbody n71 n5 3 0e 3 tc1 2 7 3 tc2 7 0e 7 res rdbreak n72 n5 1 71e 2 tc1 4 0e 4 tc2 1 55e 5 res rdrain 50 n16 4 5e 3 1 16e 2 tc2 1 7e 5 res rgate n9 n20 1 3 res rl
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