Cherry Semiconductor CS5111 handbook
Contents
1. internally fused leads Thermal Data 24 Lead SO Wide Rejc typ 9 C W Roy A typ 55 C W Surface Mount Wide Body DW 300 mil wide 7 60 299 7 40 291 ii 291 0 51 2 aaa ais 3 gt 1 27 050 BSC 2 49 098 ra 24 088 niles 050 0 32 oi 0 40 016 0 23 009 REF JEDEC MS 013 lt _ D Mercer 10 65 419 10 00 394 394 2 65 104 2 35 093 L 0 30 012 0 10 004 a Ordering Information Part Number Description CS5111YDWF24 24 Lead SO Wide internally fused leads CS5111YDWFR24 24 Lead SO Wide internally fused leads tape amp reel Rev 12 28 98 Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice Please contact Cherry Semiconductor Corporation for the latest available information 1999 Cherry Semiconductor Corporation2. 6 25ms In practice the tolerance of The 5V linear regulator circuitry is shown in Figure 2 Cpelay and Rpy s must be taken into account when calculat When an unregulated voltage greater than 6 6V is applied ing the minimum watchdog time twp to the Vegc input a 5V regulated DC voltage will be pre sent at Vin For proper operation of the 5V linear regula tor the Igras lead must have a 64 9kQ pull down resistor to ground A 100uF or larger capacitor with an ESR lt 8Q must be connected between V y and ground To operate the 5V linear regulator as an independent regulator i e separate from the switching supply the input voltage must be tied to the Vpgg lead As the voltage at the Vgc input is increased Q is turned on Q4 provides base drive for Q which in turn provides base current for Q3 As Q is turned on the output voltage Vin begins to rise as Q3 s output current charges the out put capacitor Cour Once Vi yn rises to a certain level the error amplifier becomes biased and provides the appropri ate amount of base current to Q4 The error amplifier mon itors the scaled output voltage via an internal voltage divider R through Rs and compares it to the bandgap voltage reference The error amplifier output or error sig nal is an output current equal to the error amplifier s input 50 Duty differential voltage times the transconductance of the gt Cycle amplifier Theref
3. SO Wide Internally Fused Leads Vin EJ ENABLE NC C VREG NC Vun Vsw C IBias Gnd Gnd Gnd _ Gnd Gnd Gnd Gnd M Gnd VEB RESET VFB2 M Cpelay SELECT WDI COMP Cosc Cherry Semiconductor Corporation 2000 South County Trail East Greenwich RI 02818 Tel 401 885 3600 Fax 401 885 5786 Email info cherry semi com Web Site www cherry semi com AG HERRY Company TIISSD CS5111 Absolute Maximum Ratings Logic Inputs Outputs ENABLE SELECT WDI RESET o csceeecsssesesssssesessesscseestesesesseescseeneescseeaeescseeaeeneaeas 0 3V to Vin N AES T hence SO ee E tesa cd beaten aes aarc ah na tasdessad 0 3V to 10V Vin VREG BDC Input Voltages iia wait aea aE AE AE eE a E A N A EE EE EN 0 3V to 26V Peak Transient Voltage 40V Load Dump 14V Viy ses sssssssssssssssssissssrssssstisssrsenssnrsnsnntenssnienssnrsesnnneennnrnessnn 0 3V to 54V Vow Peak Transient Volo gpe coiere iea Ea A NO AE MRT R AEE cea AEA 54V Cosc CbDelay COMP Vrp1 VeEp2 essseesesessascesssesaasoesesessaccessecesaocessesasasoesesesssosesesesesosesesesesososseesseceescosssscesssoereseeesscenaseseesos 0 3V to VLN Power DISSIPAtlOMssss cvs seed rrari niig a EA Ea E AEE A TE A Internally Limited Vin Output Current assinar eli anid a aE CN Dapa i KE E ini AE RENNE RaR Internally Limited Vaw Output Current oe yea oriori anr ETETE EEEE E EAEAN EEA NOESEN EEEE EEA E EE Internally Limited RESET Output Sinki Wiron neeesa ioar e ETE
4. transferred to the load when the output transistor is turned off The output transistor is turned back on at the next rising edge of the oscillator On a cycle by cycle basis the current mode controller in a discontinu ous mode of operation charges the inductor to the appro priate amount of energy based on the energy demand of the load Figure 7 shows the typical current and voltage waveforms for a boost supply operating in the discontinu ous mode NOTES 1 Refer to Figure 1d to determine oscillator frequency 2 The switching regulator can be disabled by providing a logic high at the ENABLE input 3 The boost output voltage can be controlled dynamically by the feedback select input If select is open Vzpo is selected If select is low then Vp is selected Protection Circuitry If the input voltage at Vgc is increased above the over voltage threshold the drive to the linear and switcher out put transistors is shut off Therefore Vin is disabled and Vsw can not be pulled low The current out of Viy is sensed in order to limit exces sive power dissipation in the linear output transistor over the output range of OV to regulation Also the current into Vow is sensed in order to provide the current limit func tion in the switcher output transistor If the die temperature is increased above 160 C either due to excessive ambient temperature or excessive power dis sipation the drive to the linear output transistor is red
5. well as the Power On Reset delay are set by one external RC network The current mode PWM switching regu lator is comprised of an error amplifier with selectable feedback inputs a cur rent sense amplifier an adjustable oscil lator and a 1 4A output power switch with anti saturation control The switch ing regulator can be configured in a variety of topologies The CS5111 is load dump capable and has protection circuitry which includes overvoltage shutdown current limit on the linear and switcher outputs and an overtemperature limiter 2 Vsw Logic m IBIAS Current Sense Amplifier 24 gt Ly Cosc Oscillator Gnd E pl gt Switcher Shutdown VREG I Over Voltage Linear Error Amplifier 1 25V Bandgap Reference VLIN Current Limit 2 Over gt Temperature CDELAY RESET amp WDI Watchdog Timer RESET X Cherry Rev 12 28 98 Semiconductor Linear Regulator 5V 2 100mA Switching Regulator 1 4A Peak Internal Switch 120kHz Maximum Switching Frequency 5V to 26V Operating Supply Range Smart Functions Watchdog RESET ENABLE Protection Overvoltage Overtemperature Current Limit 54V Peak Transient Capability Package Option 24 Lead
6. 0 0 Css oo NIN CS5111 1 4A Switching Regulator with 5V 100mA Linear Regulator with Watchdog RESET and ENABLE The CS5111 is a dual output power sup ply integrated circuit It contains a 5V 2 100mA linear regulator a watchdog timer a linear output voltage monitor to provide a Power On Reset POR and a 1 4A current mode PWM switching reg ulator The 5V linear regulator is comprised of an error amplifier reference and super visory functions It has low internal sup ply current consumption and provides 1 2V typical dropout voltage at maxi mum load current The watchdog timer circuitry monitors an input signal WDI from the micro processor It responds to the falling edge of this watchdog signal If a correct watchdog signal is not received within the externally programmable time a reset signal is issued The externally programmable active reset circuit operates correctly for an out put voltage Vim as low as 1V During power up or if the output voltage shifts Block Diagram Switcher ee Error Amplifier FB2 SELECT 6 is a COMP below the regulation limit RESET tog gles low and remains low for the duration of the delay after proper output voltage regulation is restored Additionally a reset pulse is issued if the correct watchdog is not received within the programmed time Reset pulses continue until the cor rect watchdog signal is received The reset pulse width and frequency as
7. 3A 7 Error Amp DC Gain 67 dB Error Amp Transconductance 2700 uA V E ENABLE Input VIL 0 8 1 24 V VIH 1 30 2 0 V Hysteresis 60 mV Input Impedance 10 20 40 KQ E Select Input VIL Selects Vpg1 4 9 lt Vin lt 5 1 0 8 1 25 V VIH Selects Vpp2 4 9 lt Vin lt 5 1 1 25 2 0 V SELECT Pull Up SELECT 0V 10 24 50 kQ Floating Input Voltage 29 4 5 V Note 1 Guaranteed by Design not 100 tested in production TIISSD CS5111 Package Lead Description PACKAGE LEAD LEAD SYMBOL FUNCTION 24 Lead SO Wide 1 Vin Supply Voltage DS NC No connection 4 Vsw Collector of NPN power switch for switching regulator section 5 6 7 8 17 18 19 20 Gnd Connected to the heat removing leads 9 Vepi Feedback input voltage 1 referenced to 1 25V 10 Veo Feedback input voltage 2 referenced to 1 25V 11 SELECT Logic level input that selects either Vrs or Vpg2 An open selects Verp2 Connect to Gnd to select Vpg1 12 COMP Output of the transconductance error amplifier 13 Cosc A capacitor connected to Gnd sets the switching frequency Refer to Figure 1d 14 WDI Watchdog input Active on falling edge 15 CbDelay A capacitor connected to Gnd sets the Power On Reset and Watchdog time 16 RESET RESET output Active low if Vim is below the regulation limit If watchdog timeout is reached a reset pulse train is issued 21 Ibias A resistor connected to Gnd sets i
8. Determine the minimum output capacitance and maxi mum ESR based on the allowable output voltage ripple I sa ie 7a Coutmin 8fAV ripple AV ESR nin a P In practice it is normally necessary to use a larger capaci tance value to obtain a low ESR By placing capacitors in parallel the equivalent ESR can be reduced Step 8 Compensate the feedback loop to guarantee stability under all operating conditions To do this we calculate the modulator gain and the feedback resistor network attenu ation and set the gain of the error amplifier so that the overall loop gain is 0dB at the crossover frequency fco In addition the gain slope should be 20dB decade at the crossover frequency The low frequency gain of the modulator i e error ampli fier output to output voltage is AVout Ryoad Lf Ipk max i 8a AVEA VEA max 2 where Veatmax Gesa__ 2 4V 7 Tpkmax Rs 150mQ 2 3A The Vour Vra transfer function has a pole at fp 1 MRioadCour 8b and a zero due to the output capacitor s ESR at f 1 2nESR Cour 8c Since the error amplifier reference voltage is 1 25V the output voltage must be divided down or attenuated before being applied to the input of the error amplifier The feedback resistor divider attenuation is 1 25V _ Vout The error amplifier in the CS5111 is an operational transcon ductance amplifier OTA with a gain given by Gora 8MZout 8d wh
9. E EI NETE TEONE 5mA ESD Susceptibility Human Body Model ccccsccscessessesssessssessessessssesssssssesssssssesssssesesssssssesnssnescsesnsassseessssesesssseasaneseansens 2kV ESD Susceptibility Machine Model siic cissscscssssssssonssovstscssvssescssaiseiavassscsundansdassnsansaitonnadeasesotaoeverstevssiervavascsabassuntdensdhashattests 200V Storage Temperate a e aE AT aN A RETARA EEEE eles 65 to 150 C Lead Temperature Soldering Reflow SMD styles only s ssssssssssssssssisssriesssrissssee 60 sec max above 183 C 230 C peak Electrical Characteristics 5V lt V lt 26V and 40 C lt Tj lt 150 C Cour 1004F ESR lt 8Q Cbpelay 0 1uF Regras 64 9kQ Cosc 390 pF Ccomp 0 1uF unless otherwise specified PARAMETER TEST CONDITIONS UNIT E General In Off Current 6 6V lt Vin lt 26V Isw 0A 2 0 mA Im On Current 6 6V lt Vin lt 26V Isw 1 4A 30 70 mA Irec Current Iun 100mA 6 6V lt Vreg lt 26V 6 mA Thermal Limit Guaranteed by design 160 210 A E 5V Regulator Section Vin Output Voltage 6 6V lt Vreg lt 26V 1mA lt Liy lt 100mA 4 9 5 0 5 1 V Dropout Voltage Vrec Vim Iun 100mA 1 2 1 5 V Overvoltage Shutdown 30 34 38 V Line Regulation 6 6V lt Vrsc lt 26V IL 5MA 5 25 mV Load Regulation Vreg 19V 1mA lt l lt 100mA 5 25 mV Current Limit 6 6V lt Vreg lt 26V 120 mA DC Ripple Rejection 14V lt Vreg lt 24V 60 75 dB E RESET Section Low Threshold Ver Vin Decreas
10. ere Alour 8e AVIN For the CS5111 gm 27004A V typical One possible error amplifier compensation scheme is shown in Figure 9 This gives the error amplifier a gain plot as shown in Figure 10 For the error amplifier gain shown in Figure 10 a low fre quency pole is generated by the error amplifier output impedance and C4 This is shown by the line AB with a 20dB decade slope in Figure 12 The slope changes to zero at point B due to the zero at f 1 2nR4C 8f Error Amplifier R4 v SELECT Figure 9 RC network used to compensate the error amplifier OTA Application Notes continued Pole due to error amplifier PA output impedance and C1 fz 1 2nR4C1 fp 1 nR4C2 a 20dB dec error amplifier gain fp 1 t RLoadCouT D modulator gain feedback resistor divider attenuation fz 1 2n ESR Cout Z Figure 10 Bode plot of error amplifier OTA gain and modulator gain added to the feedback resistor divider attenuation A pole at point C fp 1 nRyCo 8g offsets the zero set by the ESR of the output capacitors An alternative scheme uses a single capacitor as shown in Figure 11 to roll the gain off at a relatively low frequency Vout 18V Select gt 2V Vout 16V Select lt 0 8V L 33uH f ENABLE Hi VREG Ven O IBIAS Gnd Gnd Gnd Gnd MICROPROCESSOR VFB1 RESET VFB2 CbDelay SELECT WDI COMP 100uF ESR lt 8Q R
11. gias 64 9kQ Cosc Figure 11 A typical application diagram with external components con figured in a boost topology Step 9 Finally the watchdog timer period and Power on Reset time is determined by Delay 1 353 x CpelayReras 9 Linear Regulator Output Current vs Input Voltage 100 i a Te eee aaa OJA 55 C W Vin 14V Max Total Power 1 18W ILIN mA 0 5 10 15 20 25 30 VREG V OJA 35 C W Vin 14V Max Total Power 1 86W ILIN mA 0 5 10 15 20 25 30 VREG V Figure 12 The shaded area shows the safe operating area of the CS5111 as a function of Irn Vreg and Oza Refer to the table below for typical loads and voltages Worst Case Switcher Worst Case Switcher Linear Power Power Available Power Available VREG Vin lun Dissipation Oja 55 C W Oja 35 C W V V mA W W W 20 14 25 0 44 0 74 1 42 20 14 50 0 83 0 35 1 03 20 14 75 1 22 i 0 64 20 14 100 1 60 7 0 26 25 14 25 0 60 0 58 1 26 25 14 50 1 11 0 07 0 75 25 14 75 1 62 0 24 25 14 100 2 14 z a Subjecting the CS5111 to these conditions will exceed the maximum total power that the part can handle thereby forcing it into thermal limit TIISSO CS5111 Package Specification PACKAGE DIMENSIONS IN mm INCHES PACKAGE THERMAL DATA D Lead Count Metric English Max Min Max Min 24 Lead SO Wide 15 60 15 20 614 598
12. ing 4 05 4 25 4 45 V High Threshold Vp Vn Increasing 4 20 4 45 4 70 V Hysteresis Vertu VRTL 140 190 240 mV Active High VLN gt VRTE Ireser 25UA Vim 0 5 V Active Low Vun 1V 10kQ pullup from RESET to Vin 0 4 V Vim 4V Ireser IMA 0 7 V Delay Invalid WDI 6 25 8 78 11 0 ms Power On Delay Vin crossing Very 6 25 ms Electrical Characteristics 5V lt Vy lt 26V and 40 C lt T lt 150 C Coyy 100uF ESR lt 8Q Cbpelay 0 1UF Rgras 64 9k PARAMETER TEST CONDITIONS UNIT E Watchdog Input WDI Cosc 390 pF Ccomp 0 1uF unless otherwise specified VIH Peak WDI needed to activate RESET 2 0 V VIL 0 8 V Hysteresis Note 1 25 50 mV Pull Up Resistor WDI 0V 20 50 100 KQ Low Threshold 6 25 8 78 11 0 ms Floating Input Voltage 3p V WDI Pulse Width 5 us E Switcher Section Minimum Operating 5 0 V Input Voltage Switching Frequency Refer to Figure 1d 80 95 110 kHz Switch Saturation Voltage Isw 1 4A 0 7 1 1 1 6 V Output Current Limit 1 4 2 5 A Max Switching Frequency Vsw 7 5V with 50Q load 120 kHz Refer to Figure 1d Vepi Regulation Voltage 1 206 1 25 1 294 V Vep2 Regulation Voltage 1 206 1 25 1 294 V Vrey Vep2 Input Current VrB1 Vep2 5V 1 uA Oscillator Charge Current Cosc 0V 35 40 45 uA Oscillator Discharge Current Cosc 4V 270 320 370 uA Cpelay Charge Current Cpelay OV 35 40 45 uA Switcher Max Duty Cycle Vsw 5V with 50Q load 72 85 95 Vrei Vre2 1V Current Sense Amp Gain lsw 2
13. n rises above 4 45V typical Figure 5b RESET signal is issued whenever Viy falls below 4 25V typical Current Mode PWM Switching Circuitry The current mode PWM switching voltage regulator con tains an error amplifier with selectable feedback inputs a current sense amplifier an adjustable oscillator and a 1 4A output power switch with antisaturation control The switching regulator and external components connected in a boost configuration are shown in Figure 6 The switching regulator begins operation when Vreg and Vin are raised above 5 volts Vggg is required since the switching supply s control circuitry is powered through Vin Vin Supplies the base drive to the switcher output transistor The output transistor turns on when the oscillator starts to charge the capacitor on Cogc The output current will develop a voltage drop across the internal sense resistor Rs This voltage drop produces a proportional voltage at the output of the current sense amplifier which is com pared to the output of the error amplifier The error ampli fier generates an output voltage which is proportional to the difference between the scaled down output boost volt age Vppi or Vrp and the internal bandgap voltage refer ence Once the current sense amplifier output exceeds the error amplifier s output voltage the output transistor is turned off The energy stored in the inductor during the output tran sistor on time is
14. nternal bias currents as well as the Cosc and Cpelay charge currents 22 Vin Regulated 5V output from the linear regulator section 23 VREG Input voltage to the linear regulator and the internal supply cir cuitry 24 ENABLE Logic level input to shut down the switching regulator Typical Performance Characteristics 4 5mA r 7 7 7 0A z i O W a 30mA H i 40mA 3 5mA OA 20mA 40mA 60mA 80mA 100mA OA 0 5A 1 0A 1 5A 2 0A ILIN Isw Figure 1a 5V Regulator Bias Current vs Load Current Figure 1b Supply Current vs Switch Current 1 4V 180 i 160 T 2V fecsesecesteeecelenetcectnetttidietcttnetntnt ett ennnen 140 l 120 ii 100 P CEVRE ae ee 2 sol gt D A e E a A 2 eol 20 oov i O 500 1000 1500 2000 2500 3000 OA 0 5A 1 0A 1 5A 2 0A ISW Cosc pF Figure 1c Switch Saturation Voltage Figure 1d Oscillator Frequency kHz vs Cosc pF assuming Rgras 64 9kQ Circuit Description Linear Over Voltage Error Amplifier ESR lt 8Q O io Court 1004F a 1 25V Bandgap Over Reference Temperature RESET amp O RESET Watchdog Timer Figure 2 Block diagram of 5V linear regulator portion of the CS5111 a a _ ing from 6 25ms to 11ms assuming ideal components Based The 5V linear regulator consists of an error amplifier on this the software must be written so that the watchdog bandgap voltage reference and a composite pass transistor arrives at least every
15. ore the error amplifier varies the base current to Q4 which provides bias to Q and Q3 based on the difference between the reference voltage and the scaled V n output voltage Control Functions The watchdog timer circuitry monitors an input signal WDI from the microprocessor It responds to the falling edge of this watchdog signal which it expects to see within an externally programmable time see Figure 3 A Watchdog waiting for B RESET stays low for jow going transition on twp time The watchdog time is given by two 1 353 x Cpelay Reis Figure 4 Timing diagram when WDI fails to appear within the preset time interval twpr TIISSO CS5111 Circuit Description continued If a correct watchdog signal is not received within the specified time a reset pulse train is issued until the correct watchdog signal is received The nominal reset signal in this case is a 5 volt square wave with a 50 duty cycle as shown in Figure 4 The RESET signal frequency is given by 1 2 twor The Power On Reset POR and low voltage RESET use the same circuitry and issue a reset when the linear output voltage is below the regulation limit After Viy rises above the minimum specified value RESET remains low for a fixed period tpog as shown in Figure 5 The POR delay tpor is given by fi RESET 7 tpor 1 353 x Cpetay Rgras Figure 5a The power on reset time interval tpor begins when Vi
16. te Ry where R Vr2 _ Versi Vep2 3c Tro Vrpi Re Then find R3 where Roko R 3d TIISSO CS5111 Application Notes continued Step 4 Determine the maximum on time at the minimum oscilla tor frequency and Vw For discontinuous operation all of the stored energy in the inductor is transferred to the load prior to the next cycle Since the current through the inductor cannot change instantaneously and the induc tance is constant a volt second balance exists between the on time and off time The voltage across the inductor dur ing the on cycle is Vj and the voltage across the inductor during the off cycle is Vour Vin Therefore Vinton Vout Vin tort 4a where the maximum on time is V F 1 ton max 1 IN nin 4b Voutimax fswomin Step 5 Calculate the maximum inductance allowed for discontin uous operation fswomin VIN min ton Giad 5 2 Pour n Lomax where y efficiency Usually n 0 75 is a good starting point The IC s power dissipation should be calculated after the peak current has been determined in Step 6 If the efficiency is less than originally assumed decrease the efficiency and recalculate the maximum inductance and peak current Step 6 Determine the peak inductor current at the minimum inductance minimum V j and maximum on time to make sure the inductor current doesn t exceed 1 4A Vincmin t Ipk IN min ton max 6 Limin Step 7
17. uced proportionally with increasing die temperature Therefore Viy will decrease with increasing die tempera ture above 160 C Since the switcher control circuitry is powered through Vn the switcher performance includ ing current limit will be affected by the decrease in Vi Nn Circuit Description continued Oscillator ENABLE O Switcher Shutdown O Switcher Error L 1 25V Bandgap Reference Figure 6 Block diagram of the 1 4A current mode control switching regulator portion of the CS5111 in a boost configuration Application Notes Design Procedure for Boost Topo This section outlines a procedure for designing a boost switch ing power supply operating in the discontinuous mode Step 1 Determine the output power required by the load Pour lourVour 1 Step 2 Choose Cosc based on the target oscillator frequency with an external resistor value Rgras 64 9kQ See Figure 1d Figure 7 Voltage and current waveforms for boost topology in CS5111 Step 3 Next select the output voltage feedback sense resistor divider as follows Figure 8 For Vppi active choose a value for R4 and then solve for Rego where Ry Vour 4 Versi For Vrp active find Reg 3a Vigi za Vout _ Rig 3b Ri Reo Figure 8 Feedback sense resistor divider connected between Vour and ground and then calcula
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Cherry Semiconductor CS5111 handbook