FAIRCHILD FDS4410 Manual
Contents
1. 2000 tae aA ur Ciss g _ 1000 n LL fe amp m 9 o Z 500 2 E 3 E Coss Iz F4 p 200 8 gt Crss 100 w 0 5 10 15 20 25 0 1 05 1 2 5 10 30 Qg GATE CHARGE nC V ps DRAIN TO SOURCE VOLTAGE V Figure 7 Gate Charge Characteristics Figure 8 Capacitance Characteristics 100 30 WE 7 ih ES ds 25 SINGLE PULSE 4 49 eet ng RoJA 125 C W E 7 m Ta 25 C J wi 3F Ns amp 700 c 5 s ui 15 o 7s 8 Z 05 E os 40 a F Vas 10V C 2 SINGLE PULSE E E Ry 125 0 W F Ta 25 C 0 01 e EN Sa 0 005 01 02 05 1 2 5 10 2030 50 0 01 01 05 1 10 50 100 300 Vps DRAIN SOURCE VOLTAGE V SINGLE PULSE TIME SEC Figure 9 Maximum Safe Op2. ESE FAIRCHILD ee SEMICONDUCTOR m FDS4410 April 1998 Single N Channel Logic Level PWM Optimized PowerTrench MOSFET General Description This N Channel Logic Level MOSFET has been designed specifically to improve the overall efficiency of DC DC converters using either synchronous or conventional switching PWM controllers The MOSFET features faster switching and lower gate charge than other MOSFETs with comparable Roysow specifications The result is a MOSFET that is easy and safer to drive even at very high frequencies and DC DC power supply designs with higher overall efficiency tig a a SOT 23 SuperSOT 6 SuperSOT 8 Features m 10A 30V Pasion 0 0135 Q Vg 10 V Roson 0 0200 Vs 4 5 V m Optimized for use in switching DC DC converters with PWM controllers Very fast switching Low gate charge typical 22 nC me ma SO 8 SOT 223 SOIC 16 5 mr r 4 D 6e 0 A 3 X gt E 7 4 WQ 4 2 8 L1 Absolute Maximum Ratings T 25 C unless other wise noted Symbol Parameter FDS4410 Units Voss Drain Source Voltage 30 V Voss Gate Source Voltage 20 V l5 Drain Current Continuous Note 1a 10 A Pulsed 50 Py Power Dissipation for Single Operation Note 1a 2 5 W Note 1b 1 2 Note 1c 1 Ty T stg Operating and Storage Temperature Range 5
3. 0 w DE az T X08 a 0 6 50 25 0 25 50 75 100 125 Tj JUNCTION TEMPERATURE C Figure 3 On Resistance Variation with Temperature 50 TA 550 V4 z IA ib d 25 C lt 40 125 C B Zz c T 30 o A 20 a a a 10 0 2 3 4 5 Vas GATE TO SOURCE VOLTAGE V Figure 5 Transfer Characteristics 3 Ww S Vgg 3 5V q 25 N o ZR 4 0V 22 5 9 ui 4 5V 15 5 0V E a t na me 7 0V cr oz 1 10V a a 0 5 0 10 20 30 40 50 Ip DRAIN CURRENT A Figure 2 On Resistance Variation with Drain Current and Gate Voltage 0 05 Ip 5A 004 Q W 2 Z 0 03 E o 0 02 TA 125 C FA 9 0 01 Ta 25 C N Q a 0 2 4 6 8 10 Vas GATE TO SOURCE VOLTAGE V Figure 4 On Resistance Variation with Gate to Source Voltage 50 T Ves 0V Z w z Im cc c 1 3 s TA 125 amp m on 25 C Q w 55 C 2 0 01 W gt Im C 0 001 D 0 0001 0 2 0 4 0 6 0 8 12 14 Vsp BODY DIODE FORWARD VOLTAGE V Figure 6 Body Diode Forward Voltage Variation with Source Current and Temperature FDS4410 Rev B1 Typical Electrical And Thermal Characteristics
4. 5 to 150 C THERMAL CHARACTERISTICS Rya Thermal Resistance Junction to Ambient Note 1a 50 C W Ryc Thermal Resistance Junction to Case Note 1 25 C W 1998 Fairchild Semiconductor Corporation FDS4410 Rev B1 Electrical Characteristics T 25 C unless otherwise noted Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVpss Drain Source Breakdown Voltage Veg 20V 152 250 pA 30 V ABV AT Breakdown Voltage Temp Coefficient l 250 pA Referenced to 25 C 21 mV 7C logs Zero Gate Voltage Drain Current Vos 2 24 V Veg 0 V 1 pA T 55 C 10 pA lesse Gate Body Leakage Forward Veg 20V Vj OV 100 nA lessr Gate Body Leakage Reverse Vos 20 V Vog OV 100 nA ON CHARACTERISTICS Note 2 Vasin Gate Threshold Voltage Vhs Ves Ip 250 pA 1 2 3 V AVesm AT Gate Threshold Voltage Temp Coefficient l 250 pA Referenced to 25 C 4 5 mV PC Roson Static Drain Source On Resistance Ves 10V 15210A 0 011 0 0135 Q T 125 C 0 018 0 023 Vas 2 45V 1 9A 0 017 0 02 bon On State Drain Current Veg 10 V Vos 5V 50 A Ors Forward Transconductance Vpg 10V 152 10A 27 S DYNAMIC CHARACTERISTICS C Input Capacitance Vos 15V Veg 20V 1340 pF Coss Output Capacitance POMA 340 pF Css Reverse Transfer Capacitance 125 pF SWITCHING CHARACTERISTI
5. CS Note 2 toron Turn On Delay Time Vog 15V lp 1A 12 22 ns t Turn On Rise Time V 2 10 V Ren 260 13 24 ns toon Turn Off Delay Time 38 60 ns t Turn Off Fall Time 10 18 ns Q Total Gate Charge Vps 15V 15 210A 22 31 nC Qs Gate Source Charge Veg 10V 5 nC Quy Gate Drain Charge nC DRAIN SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS ls Maximum Continuous Drain Source Diode Forward Current 2 1 A Vsp Drain Source Diode Forward Voltage Vas 20V l52 2 1 A Note 2 0 73 12 V Notes 1 Rya is the sum of the junction to case and case to ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins Rsc is guaranteed by design while R is determined by the user s board design Ter a 50 C W on a 1 in pad of 20z copper Scale 1 1 on letter size paper 2 Pulse Test Pulse Width lt 300us Duty Cycle lt 2 0 b 105 C W on a 0 04 in pad of 20z copper c 125 C W on a 0 006 in pad of 20z copper FDS4410 Rev B1 Typical Electrical Characteristics 50 f Vgg 10V ee 5 0V 40 Meer p 8 5 V Ip DRAIN SOURCE CURRENT A 0 0 5 1 1 5 2 2 5 3 Vos DRAIN SOURCE VOLTAGE V Figure 1 On Region Characteristics 1 8 Ip 10A amp 18 Vos 10V Q o N 14 a x T Grau e
6. IFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into support device or system whose failure to perform can the body or b support or sustain life or c whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can be effectiveness reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms Advance Information Formative or This datasheet contains the design specifications for In Design product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obso
7. erating Area Figure 10 Single Pulse Maximum Power Dissipation i AT z 0 5 25 o 0 2 LE o9 03 Reya t r t Ro gJa Euro Ed Raja 125 0 W z 0 05 zl at 0 05 H a i Hm 0 02 LHH P pk Jg 0 02 CEHRT t E 00 0 01 d Lg a S fi ii Single Pulse rita Z G 0 005 a ez Ty Ta P R gal 0 002 Duty Cycle D t b 0 00 Jttit L Jot pt tiit 0 0001 0 001 0 01 0 1 1 10 100 300 t TIME sec Figure 11 Transient Thermal Response Curve Thermal characterization performed using the conditions described in Note 1c Transient thermal response will change depending on the circuit board design FDS4410 Rev B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx ISOPLANAR TinyLogic CoolFET MICROWIRE UHC CROSSVOLT POP VCX E CMOS M PowerTrench FACT QFET FACT Quiet Series Qs FAST Quiet Series FASTr SuperSOT 3 GTO SuperSOT 6 HiSeC SuperSOT 8 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS L
8. lete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only
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