FAIRCHILD FDMS3622S Manual
Contents
1. 1000 PTEE SINGLE PULSE Roya 125 C W 100 10 1 0 5 10 10 10 10 1 10 100 1000 t PULSE WIDTH sec Figure12 Single Pulse Maximum Power Dissipation www fairchildsemi com 2M81S 1 MOd gu 9ueJ 10MOd SZc9ESINQA Typical Characteristics Q1 N Channel 1 25 c unless otherwise noted j DUTY CYCLE DESCENDING ORDER D 0 5 d E a 3 T 005 Y ZA Di 002 Pom O 9 s 0 01 SA NE du m 3 zz 0 01 SINGLE PULSE t2 9 Raya 125 C W ee 9JA DUTY FACTOR D t t Note 1b PEAK Ty Pow X Zoua X Roja TA 0 001 e mr ig 1 10 100 t RECTANGULAR PULSE DURATION sec Figure 13 Junction to Ambient Transient Thermal Response Curve 2011 Fairchild Semiconductor Corporation FDMS3622S Rev C2 1000 www fairchildsemi com 2M81S 19MOd gu 9ueJ 10MOd SZc9ESINQA Typical Characteristics Q2 N Channel T 25 c unless o2. e mrt Is REVERSE DRAIN CURRENT A e e e mrt 0 0 0 2 0 4 0 6 0 8 1 0 Vsp BODY DIODE FORWARD VOLTAGE V Figure 19 Source to Drain Diode Forward Voltage vs Source Current www fairchildsemi com 2M81S 19MOd U9UALIIMOY SZZ9ESINGS Typical Characteristics Q2 N Channel T 25 c unless otherwise noted
3. 10 10000 gt DPR eum LL Ciss E S LL zd amp Coss gt LU gs 2 rs q 1000 S 4 lt S e Ciss et 2 L f 1 MHz 3 Ves 0V o A ix i 3 p is ag i Vps DRAIN i0 SOURCE VOLTAGE A b Qg GATE CHARGE nC pa v Figure 20 Gate Charge Characteristics Figure 21 Capacitance vs Drain to Source Voltage 100 180 150 S E a Ty 25 C 6 120 tc tc 3 5 e 10 Ty 100 C o 90 Ty 125 C N z tc a 60 gt D 30 o E 1 0 0 001 0 01 0 1 1 10 100 1000 25 50 75 100 125 150 tay TIME IN AVALANCHE ms Tc CASE TEMPERATURE C Figure 22 Unclamped Inductive Figure 23 Maximum Continuous Drain Switching Capability Current vs Case Temperature 200 3000 CO 100 x N 100 us gt E E 4000 SINGLE PULSE SR S D e o T i e S4 i D A Roya 120 C W L 10 ce ted IS 5 E a x x D d Es A SS A 1 ms 100 oc RIMS IMAN z 3 4 L THIS AREAIS NU SS EN s N 10 ms z LIMITED BY Z z DSton SoS SF 100 ms q DE SINGLE PULSE SUN Sas gt 10 6 0 1 Ty MAX Pau Ma S 408 L q Ta 25 C d E 4 0 01 NECS T MN a 0 5 Vps DRAIN to SOURCE VOLTAGE V t PULSE WIDTH sec Figure 24 Forward Bias Safe Figure 25 Single Pulse Maximum Power Operating Area Dissipation 2011 Fairchild Semiconductor Corporation 8 www fairchildsemi com FDMS3622S Rev C2 2M81S 19MOd gu 9ueJ L1 MOd SZZ9ESINGS Typical Characteristics Q2 N Channel 1 25 c unless othe
4. 5 10 s 00 5 10 C ch 0 10 C 4 90 PA S e 2X E B Tum O j 1 27 TYP 8 5 e vg Y m 0 65 TYP i 7 6 ills i qe bs 2 52 2 15 EE L OS KOC 0 00 07 PIN 1 Ja 1 4 16 KK XXX LX IDENT MAY MPO AN o e NIA KEEP APPEARAS 4 0 10 6 J1 2 133 RS 231 OUT nh hate TOP VIEW So ssl 3 4 3 15 AREA SEE o 0 59 DETAIL A ET RECOMMENDED LAND PATTERN SIDE VIEW T 0 1000 C A B 0 8 _ 300 _070 ES ke 2 80 0 50 0 051 6 0 35 1112 3 4 _132 dd D mn 11 12 0 71 0 61 3 NOTES UNLESS OTHERWISE SPECIFIED 2 25 D i 9 2 05 A DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO 240 c mim mer ISSUE B DATED 10 2009 0 58 8 7 6 5 082 B ALL DIMENSIONS ARE IN 0 38 d L K MILLIMETERS 0 44 C DIMENSIONS DO NOT INCLUDE po Eel BURRS OR MOLD FLASH MOLD BOTTOM VIEW FLASH OR BURRS DOES NOT EXCEED 0 10MM DP D DIMENSIONING AND TOLERANCING 7T 38l6 0 31 PER ASME Y14 5M 1994 i E IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA SS i E F DRAWING FILE NAME RM ses y C G PLANE DETAIL A SCALE 2X 2011 Fairchild Semiconductor Corporation 11 www fairchildsemi com FDMS3622S Rev C2 iS SSeS FAIRCHILD A SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such tra
5. A e O al N QU 0O O N e di dt 300 A us sch al CURRENT A 10 0 40 80 120 160 200 240 280 320 360 TIME ns Figure 27 FDMS3622S SyncFET body diode reverse recovery characteristic 2011 Fairchild Semiconductor Corporation FDMS3622S Rev C2 10 Schottky barrier diodes exhibit significant leakage at high tem perature and high reverse voltage This will increase the power in the device Loes REVERSE LEAKAGE CURRENT A mb N sch e e 2M81S 1o9MOd gu 9ueJ 10MOd SZc9ESINQA sch e A mb e eo A T N al o O sch e 0 5 10 15 20 25 Vps REVERSE VOLTAGE V Figure 28 SyncFET body diode reverse leakage versus drain source voltage www fairchildsemi com Dimensional Outline and Pad Layout 2M81S 19MOd gu 9ueJ 10MOd SZZ9ESINGS
6. C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Drain Source Diode Characteristics Vas 0V lg 17 5A Note 2 Ql 0 8 1 2 Vsp Source to Drain Diode Forward Voltage Vos 0V lox 34A Note 2 Q2 08 12 V l Q1 Q1 23 ly Reverse Recovery Time le 17 5 A di dt 100 A us Q2 35 ns Q R R Ch E C T everse Recovery Charge lc 34 A di dt 300 A us Q2 43 n Notes 1 RgjA is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1 5 x 1 5 in board of FR 4 material Rec is guaranteed by design while Reca is determined by the user s board design b 50 C W when mounted on a 57 C W when mounted on a 1 in pad of 2 oz copper a 1 in pad of 2 0z copper c 125 C W when mounted on a d 120 C W when mounted on a minimum pad of 2 oz copper minimum pad of 2 oz copper 0000 X sso 2 Pulse Test Pulse Width 300 us Duty cycle 2 096 3 Q1 Eas of 29 mJ is based on starting Ty 25 C N ch L 1 2 mH las 7 A Vpp 23 V Vas 10 V 100 test at L 0 1 mH lag 16 A Q2 Ens of 145 mJ is based on starting Ty 25 C N ch L 0 9 mH las 18 A Vpp 23 V Vas 10 V 100 test at L 0 1 mH Ing 39 A 4 As an N ch device the negative Vgs rating is for low duty cycle pulse occurrence only No continuous rating is implied 2011 Fairchild Semiconductor Corporation 3 www fairchildsemi com F
7. O Ty 100 C O q Ty 125 C q gt lt E 1 0 001 0 01 0 1 1 10 50 tav TIME IN AVALANCHE ms Figure9 UnclampedInductive Switching Capability 100 TM na la ETA 100 ps SZ 10 ESI E x bi S LY hi gt N b Lu gt N tc gt sa gt 1 oc Uv US x ms 2 1 NS NL a O THIS AREA IS A ome Z LIMITED BY Fos on ANES cc Ss 100 ms a SINGLE PULSE TNS S i amp 0 1 T MAX RATED Ze xt IS a F o 5 10s Roya 125 C W e Ta 25 SE 0 01 l p pep qu ri 0 01 0 1 1 10 100200 Vps DRAIN to SOURCE VOLTAGE V Figure 11 Forward Bias Safe Operating Area 2011 Fairchild Semiconductor Corporation FDMS3622S Rev C2 2000 1000 CR T E LLI Coss o E 5 100 lt D st O Crss f21MHz Vas 0V 10 z 0 1 1 10 30 Vps DRAIN TO SOURCE VOLTAGE V Figure8 Capacitancevs Drain to Source Voltage 80 GER E elen 5 SE TSK Ves 10 V t 50 e e tc 2 O Z lt tc a A gt 20 Limited by Package 10 Bac 3 0 C W P px PEAK TRANSIENT POWER W 0 25 50 75 100 125 150 Te CASE TEMPERATURE C Figure 10 Maximum Continuous Drain Current vs Case Temperature
8. IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used here in 1 Life support devices or systems are devices or systems which a are 2 intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury of the user A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness ANTI COUNTERFEITING POLICY Fairchild Semiconductor Corporation s Anti Counterfeiting Policy Fairchild s Anti Counterfeiting Policy is also stated on our external website www Fairchildsemi com under Sales Support Counterfeiting of semiconductor parts is a growin
9. 1 100 nA lass Gate to Source Leakage Current Vas 12 V 8 V Vps 0 V Q2 100 nA On Characteristics Vas Vos lp 250 uA Q1 0 8 1 2 2 0 Noen Gate to Source Threshold Voltage Mice Nie Ine nA Q2 11 WH 22 V AV sith Gate to Source Threshold Voltage Ip 250 uA referenced to 25 C Q1 4 mV C AT Temperature Coefficient Ip 10 mA referenced to 25 C Q2 4 Vas 10 V Ip 17 5A 3 8 5 0 Vas 4 5 V Ip 16A Q1 4 4 5 7 r Drain to Source On Resistance a A e e pe des mo i i SEN i Vas 10 V Ip 34A EE 14 Vas 4 5 V lp 32 A Q2 1 3 1 6 Vas 10 V lp 234 A Ty 2125 C 1 5 2 0 Vps 5 V Ip 17 5A Q1 100 Ors Forward Transconductance Vosa 5V AMA Q2 272 S Dynamic Characteristics l Q1 1570 Ci Input Capacitance Q1 F ss GE Vps 13V Vas 0V f 1MHZ Q2 5565 j e Q1 448 Goce Output Capacitance Q2 Q2 1405 pF Vps 13 V Ves 0 V f 1 MHZ Gres Reverse Transfer Capacitance i SS e e pF Hg Gate Resistance a E Q Switching Characteristics Joan Turn On Delay Time e 3 ns a EHE Q1 2 t Rise Time Vpp 13 V Ip 17 5 A Reen 6 Q Q2 7 ns ta off Turn Off Delay Time Q2 ES ns Vpp 13 V Ip 34 A Reen 6 Q i Q1 2 lr Fall Time Q2 6 ns Q1 26 Qy Total Gate Charge Ves 0 Vto10V Q Q2 86 nC MODS v Q1 12 Qy Total Gate Charge Vas 0 Vto4 5V 17 5A Q2 40 nC Qgs Gate to Source Gate Charge Q2 e A nC Vpp 13 V Qaod Gate to Drain Miller Charge Ip 2 34A e n nC 2M81S 1o9MOd gu 9ueJ L1 MOd SZZ9ESINGS Electrical Characteristics Tj 25
10. AAA SSA FAIRCHILD AE SEMICONDUCTOR FDMS36225 PowerTrench Power Stage 25V Asymmetric Dual N Channel MOSFET Features Q1 N Channel B Max rps on 5 0 MQ at Veg 10 V Ip 17 5 A B Max rps on 9 7 MQ at Ves 4 5 V lp 16A Q2 N Channel December 2011 General Description This device includes two specialized N Channel MOSFETs in a dual PQFN package The switch node has been internally connected to enable easy placement and routing of synchronous buck converters The control MOSFET Q1 and synchronous m Max eum 1 4 MQ at Vas 10 V Ip 34 A SyncFET Q2 have been designed to provide optimal power 2M81S 1o9MOd UU 10MOd SZc9ESINQA efficiency B Max DS on 1 6 mQ at Ves 4 5 V Ip 32A B Low inductance packaging shortens rise fall times resulting in Applications lower switching losses B Computing B MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing m Communications B General Purpose Point of Load B Notebook VCORE B RoHS Compliant Pin 1 Bottom Top Power 56 MOSFET Maximum Ratings T 25 c unless otherwise noted Symbol Parameter Q1 Q2 Units Vps Drain to Source Voltage 25 25 V Vas Gate to Source Voltage Note 4 12 12 V Drain Current Continuous Package limited Teo 25 C 30 70 lo Continuous Ta 25 C 17 512 3416 A Pul
11. DMS3622S Rev C2 oDe1S 19MOd gu 9U94 19MOd SZZ9ESINGS Typical Characteristics Q1 N Channel 1 25 c unless otherwise noted NORMALIZED DRAIN TO SOURCE ON RESISTANCE 70 Vas 10 V 60 Vas 4 5 V 50 Ves 3 5 V 40 Vas 23V 30 Ves 2 5 V 20 Ip DRAIN CURRENT A 10 PULSE DURATION 80 us DUTY CYCLE 0 5 MAX 0 0 0 3 0 6 0 9 1 2 1 5 Vic DRAIN TO SOURCE VOLTAGE V DS Figure 1 On Region Characteristics 1 8 I Ip 17 5 A 1 4 1 2 1 0 0 8 0 6 75 50 25 0 25 50 75 100 125 150 Ty JUNCTION TEMPERATURE C Figure3 Normalized On Resistance vs Junction Temperature 70 PULSE DURATION 80 us 60 DUTY CYCLE 0 5 MAX a Vpsz5V 50 z e 40 5 Ty 150 C 30 q Ty 25 oC C 20 E Tj 55 C 10 0 0 5 1 0 1 5 2 0 2 5 3 0 Ves GATE TO SOURCE VOLTAGE V Figure 5 Transfer Characteristics 2011 Fairchild Semiconductor Corporation FDMS3622S Rev C2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE FDS on DRAIN TO SOURCE ON RESISTANCE mo 3 0 T l l PULSE DURATION 80 us DUTY CYCLE 0 5 MAX 2 5 Ves 2 5 V 2 0 16 mE e 1 0 Veg 23 5 V Veg 4 5V Vgg 10V 0 5 0 10 20 30 40 50 60 70 Ip DRAIN CURRENT A Figure 2 Normalized On Resistance vs Drain Current and Gate Volta
12. demarks The Power Franchise 2Cool FPS AccuPower F PFS the d Auto SPM FRFET PowerTrench p wer AX CAP Global Power Resource M PowerXSTM dE Bitsic GreenBridge Programmable Active Droop Hy icai Build it Now Green FPS QFET CM CorePLUS Green FPS e Series QSIM SUR AR S CorePOWER Gmax Quiet Series EVO Om CROSSVOLT GTO RapidConfigure T CTL IntelliMAX AU TOME Current Transfer Logic ISOPLANAR 72 Wee DEUXPEED Marking Small Speakers Sound Louder Saving our world 1mW W kW at a time neice Dual Cool and Better SignalWise TriFault Detect EcoSPARK MegaBuck SmartMax TRUECURRENT EfficentMaxTM MICROCOUPLER SMART START SerDes ESBC MicroFET Solutions for Your Success ee E MicroPak SPM Me LC MicroPak2 STEALTH ues Fairchild MillerDrive M SuperFET UHC Fairchild Semiconductor MotionMax SuperSOT 3 e tee FACT Quiet Series Motion SPM SuperSOT 6 UniFET FACT mWSaver M SuperSOT M 8 VOX FAST OptoHiT SupreMOS VisualMax FastvCordiM OPTOLOGIC SyncFET VoltagePlus FETBench OPTOPLANAR Sync Lock XS Flash Writer SYSTEM Y GENERAL Trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER 2M81S 1oMOd gu 9U94 10MOd SZZ9ESINGS FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
13. g problem in the industry All manufactures of semiconductor products are experiencing counterfeiting of their parts Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation substandard performance failed application and increased cost of production and manufacturing delays Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts have full traceability meet Fairchild s quality standards for handing and storage and provide access to Fairchild s full range of up to date technical and product information Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Datasheet con
14. ge N e Ipz 17 5 A PULSE DURATION 80 us DUTY CYCLE 0 5 MAX sch O sch N Tj 125 C 2 3 4 5 6 7 8 9 10 Ves GATE TO SOURCE VOLTAGE V Figure 4 On Resistance vs Gate to Source Voltage N e sch e Is REVERSE DRAIN CURRENT A e e as 0 0 0 2 0 4 0 6 0 8 1 0 1 2 Vsp BODY DIODE FORWARD VOLTAGE V Figure6 Source to Drain Diode Forward Voltage vs Source Current www fairchildsemi com 2M81S 19MOd gu 9ueJ 10MOd SZc9ESINQA Typical Characteristics Q1 N Channel 1 25 c unless otherwise noted sch e lp 17 Vas GATE TO SOURCE VOLTAGE V 0 4 8 12 16 20 24 28 Qy GATE CHARGE nC Figure 7 Gate Charge Characteristics 50 lt E i Ty 25 C 5 10
15. rwise noted 2 T T T Le a T T T Tas ns DE nS 1 DUTY CYCLE DESCENDING ORDER Dz0 5 lt lt 0 1 0 2 ii N 0 1 E ul 0 05 ag 7 002 NX 0017 0 01 zu SINGLE PULSE 9 1902 NOTES 0 001 Ai DUTY FACTOR D t to Note 1b PEAK Ty Pom X Zoua X Roja TA 0 0001 10 10 10 10 1 10 100 t RECTANGULAR PULSE DURATION sec Figure 26 Junction to Ambient Transient Thermal Response Curve 2011 Fairchild Semiconductor Corporation FDMS3622S Rev C2 1000 www fairchildsemi com 2M81S 19MOd gu 9ueJ 10MOd SZc9ESINQA Typical Characteristics continued SyncFET Schottky body diode Characteristics Fairchild s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET Figure 27 shows the reverse recovery characteristic of the FDMS3622S
16. sed 70 140 Eas Single Pulse Avalanche Energy Note 3 29 145 mJ B Power Dissipation for Single Operation Ta 25 C 22 8 2 516 2 Power Dissipation for Single Operation Ta 25 C 1 0 1 019 Ty TsTG Operating and Storage Junction Temperature Range 55 to 150 C Thermal Characteristics Rosa Thermal Resistance Junction to Ambient 5713 501 Raja Thermal Resistance Junction to Ambient 125 12019 C W Hui Thermal Resistance Junction to Case 3 0 1 9 Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity ese FDMS36228 Power 56 13 12 mm 3000 units 090D 2011 Fairchild Semiconductor Corporation 1 www fairchildsemi com FDMS3622S Rev C2 Electrical Characteristics T 25 c unless otherwise noted 2011 Fairchild Semiconductor Corporation FDMS3622S Rev C2 www fairchildsemi com Symbol Parameter Test Conditions Type Min Typ Max Units Off Characteristics Ip 250 uA Vas 0 V Q1 25 BVpss Drain to Source Breakdown Voltage lp 1 mA Vas 0 V Q2 25 V ABVpss Breakdown Voltage Temperature Ip 250 uA referenced to 25 C Q1 12 mV C Al Coefficient Ip 10 mA referenced to 25 C Q2 24 l Q1 1 uA loss Zero Gate Voltage Drain Current Vos 20 V Vas 0V Q2 500 iA Q
17. tains the design specifications for product development Specifications Advance Information Formative In Design may change in any manner without notice Datasheet contains preliminary data supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design TM Datasheet contains final specifications Fairchild Semiconductor reserves the right to No Identification Needed Full Production make changes at any time without notice to improve the design Datasheet contains specifications on a product that is discontinued by Fairchild Obsolete OLIN FTOOUGHOR Semiconductor The datasheet is for reference information only Rev 160 www fairchildsemi com First Production 2011 Fairchild Semiconductor Corporation 12 FDMS3622S Rev C2
18. therwise noted Ip DRAIN CURRENT A PULSE DURATION 80 us DUTY CYCLE 0 5 MAX 0 0 0 3 0 6 0 9 1 2 1 5 Vic DRAIN TO SOURCE VOLTAGE V DS Figure 14 On Region Characteristics 1 6 Ip 234A Ves 10 V 1 4 1 2 1 0 0 8 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 0 6 75 50 25 0 25 50 75 100 125 150 Ty JUNCTION TEMPERATURE C Figure 16 Normalized On Resistance vs Junction Temperature 140 PULSE DURATION 80 us 120 DUTY CYCLE 0 5 MAX TN Vos 5V X 100 T cc 80 tc 60 lt Ty 125 C Ty 25 C C 40 a Ty 55 C 20 0 1 0 1 5 2 0 2 5 3 0 Vas GATE TO SOURCE VOLTAGE V Figure 18 Transfer Characteristics 2011 Fairchild Semiconductor Corporation FDMS3622S Rev C2 PULSE DURATION 80 us Veg 2 5V DUTY CYCLE 0 5 MAX 0S SSS NORMALIZED DRAIN TO SOURCE ON RESISTANCE N 0 20 40 60 80 100 120 140 Ip DRAIN CURRENT A Figure 15 Normalized on Resistance vs Drain Current and Gate Voltage PULSE DURATION 80 us DUTY CYCLE 0 5 MAX Ip 34 A FDS on DRAIN TO SOURCE ON RESISTANCE mo Tj 25 C 2 4 6 8 10 Ves GATE TO SOURCE VOLTAGE V Figure 17 On Resistance vs Gate to Source Voltage 200 100
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FAIRCHILD FDMS3622S Manual