FAIRCHILD FDMS3600S Manual
Contents
1. 10 2000 FJ r Ir WU 1000 Ciss 2 8 lt ir T O Q u 6 ui Coss E O z t lt 2 O 100 n 4 O Q Ww gt Crss lt 2 o f 1 MHz o Vas 20V gt 0 10 0 5 10 15 20 0 1 1 10 25 Qg GATE CHARGE nC Vps DRAIN TO SOURCE VOLTAGE V Figure 7 Gate Charge Characteristics Figure8 Capacitancevs Drain to Source Voltage 20 80 Rouc 3 5 C W lt za E 10 E r Ty 259C m tc tc 2 tc O 2 Lu T 100 C o 5 z z x lt a 4 Ty 125 C gt lt Limited by Package Es 1 0 0 01 0 1 1 10 100 25 50 75 100 125 150 tay TIME IN AVALANCHE ms Tc CASE TEMPERATURE C Figure9 Unclamped Inductive Figure 10 Maximum Continuous Drain Switching Capability Current vs Case Temperature 100 1000 d 100 us SINGLE PULSE R SKIN ec Roja 125 C W X 10 p P ES Wi T 25 C E s R rt 1 ms O 100 PN D Lu NON E cc NLIS Z B 1 NOS Tale 10 ms H O THIS AREA IS gt CH z LIMITED BY rps on Es s Ka EE X 40 L JA E SINGLE PULSE Zen RE x 6 0 1 ts MAX RATED s J 10s i Raya 125 C W DC E F x TA225 C m 4 0 01 nao 0 5 e 0 01 0 1 1 10 100 200 10 10 10 10 1 10 100 1000 Vps DRAIN to SOURCE VOLTAGE V Figure 11 Forward Bias Safe Operating Area 2011 Fairchild Semiconducto2. XS TM FETBench SYSTEM GENERAL Trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used here in 1 Life support devices or systems are devices or systems which a are 2 intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury of the user A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness ANTI COUNTERFE
3. 80 60 tc tc 3 gt 40 lt z 20 PULSE DURATION 80 us DUTY CYCLE 0 5 MAX 0 0 0 0 2 0 6 0 8 1 0 Vps DRAIN TO SOURCE VOLTAGE V Figure 14 On Region Characteristics 1 D W Ip 20 A Ves 10 V o 1 4 o Lu ac N iu 1 2 O tc O 2 20 o o 1 0 E lt lt tc 2 0 8 75 50 25 25 50 100 125 150 Ty JUNCTION TEMPERATURE C Figure 16 Normalized On Resistance vs Junction Temperature 100 PULSE DURATION 80 us DUTY CYCLE 0 5 MAX _ 80 lt Vos z DV R Ty 1259C 60 tc tc 2 o z 40 lt tc a _ 20 Ty 55 C 0 1 0 1 5 2 0 2 5 3 0 Vgs GATE TO SOURCE VOLTAGE V Figure 18 Transfer Characteristics 2011 Fairchild Semiconductor Corporation FDMS3600S Rev C3 Veg 3 5 V PULSE DURATION 80 us DUTY CYCLE 0 5 MAX 0 20 40 60 80 100 Ip DRAIN CURRENT A NORMALIZED DRAIN TO SOURCE ON RESISTANCE N Figure 15 Normalized on Resistance vs Drain Current and Gate Voltage PULSE DURATION 80 us DUTY CYCLE 0 5 MAX Ip 30A Ty 125 C DS on DRAIN TO SOURCE ON RESISTANCE mo A T 259C 2 4 6 8 10 Vas GATE TO SOURCE VOLTAGE V Figure 17 On Resistance vs Gate to Source Voltage 200 100 Ves 0V E Lu tc tc 3 z
4. 10 V 100 test at L 0 3 mH Ing 30 A 2011 Fairchild Semiconductor Corporation 3 www fairchildsemi com FDMS36005 Rev C3 2M81S 19MOd gu 9U91 10MOd SOOIESINGS Typical Characteristics Q1 N Channel r 25 c unless otherwise noted 40 6 _ u PULSE DURATION 80 us Ver I E DUTY CYCLE 0 5 MAX E Ves 4 5 V 5 gt Vas 4V 5 GS a t t Vos 3 5 V N cC 20 lt H 2 SO O zc z o2 E 2 A 10 o Vgg 3V PULSE DURATION 80 ps z DUTY CYCLE 0 5 MAX oc 0 0 0 0 0 2 0 4 0 6 0 8 1 0 0 10 20 30 40 Vps DRAIN TO SOURCE VOLTAGE V Ip DRAIN CURRENT A Figure 1 On Region Characteristics Figure2 Normalized On Resistance vs Drain Current and Gate Voltage 1 6 25 W Ip 215A SS PULSE DURATION 80 us z Ves 10 V Q DUTY CYCLE 0 5 MAX E 1 4 E 20 o Lu n o S Ip 15A A lt uz12 ZF 15 NO et Y l cw gS z 10 03 a O 0 E w O E 08 S 5 9 T 25 C 0 6 0 75 50 25 0 25 50 75 100 125 150 2 4 6 8 10 Tu JUNCTION TEMPERATURE C Vas GATE TO SOURCE VOLTAGE V Figure3 Normalized On Resistance Figure4 On Resistance vs Gateto vs Junction Temperature Source Voltage 40
5. 40 PULSE DURATION 80 us Veg 0V DUTY CYCLE 0 5 MAX E 10 Lu lt 30 oc Soe 3 Vps 5V 5 o UE Tj 259C O Cc Ty 150 C z 5 20 oc O A o T y 55 lt E a 10 e 0 01 Ty 55 C P 0 0 001 1 2 3 4 0 0 0 2 0 4 0 6 0 8 1 0 1 2 Vas GATE TO SOURCE VOLTAGE V Vsp BODY DIODE FORWARD VOLTAGE V Figure 5 Transfer Characteristics Figure6 Sourceto Drain Diode Forward Voltage vs Source Current 2011 Fairchild Semiconductor Corporation 4 www fairchildsemi com FDMS3600S Rev C3 2M81S J MOd gu 9U91 10MOd SOOIESINGS Typical Characteristics Q1 N Channel T 25 c unless otherwise noted
6. 10 st tc a d Ty 259C tc LL 1 gt t E Ty 55 C 0 1 0 0 0 2 0 4 0 6 0 8 1 0 1 2 Vsp BODY DIODE FORWARD VOLTAGE V Figure 19 Source to Drain Diode Forward Voltage vs Source Current www fairchildsemi com 281S 19MOd gu 9U94 10MOd SOOIESINGS Typical Characteristics Q2 N Channel 1 25 c unless otherwise noted 10 Vas GATE TO SOURCE VOLTAGE V 10 30 40 Qg GATE CHARGE nC 50 60 Figure 20 Gate Charge Characteristics 40 3 E Ty 25 C Lu e 10 gt O Tj 100 C L L o Z lt f Ty 125 C lt A 1 0 01 0 1 1 10 100 300 tay TIME IN AVALANCHE ms Figure 22 Unclamped Inductive Switching Capability 200 100 SEN s SCH et a e N Del AN 1 ms E 10 HU T ls ia 10 ms gt THIS AREA IS TR SKI IA Z 1 LIMITED BY reen MIR 100 ms lt F NI 1s SINGLE PULSE N
7. B Power Dissipation for Single Operation Ta 25 C 22 SEN Power Dissipation for Single Operation Ta 25 C 1 0 1 019 Ty TerG Operating and Storage Junction Temperature Range 55 to 150 C Thermal Characteristics Rosa Thermal Resistance Junction to Ambient 5718 5015 Roja Thermal Resistance Junction to Ambient 12510 1201 C W Rojc Thermal Resistance Junction to Case 9 5 2 Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity SE FDMS3600S Power 56 13 12 mm 3000 units 2011 Fairchild Semiconductor Corporation FDMS3600S Rev C3 www fairchildsemi com 2M81S 19MOd GUUS L10MOd SOOSESINGS Electrical Characteristics T 25 c unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Off Characteristics Ip 250 uA Vas 20 V Q1 25 BVpss Drain to Source Breakdown Voltage Ip 1 mA Vas 0 V Q2 25 V ABVpss Breakdown Voltage Temperature Ip 250 uA referenced to 25 C Q1 20 mV C AT Coefficient Ip 10 mA referenced to 25 C Q2 18 Q1 1 uA loss Zero Gate Voltage Drain Current Vos 20 V Vas 0V Q2 500 LA Gate to Source Leakage Current R M Q1 100 nA lass Forward MGs ED NEDEN Q2 100 nA On Characteristics Vas Vos ID 25
8. 0 uA Q1 1 1 1 8 2 7 Noen Gate to Source Threshold Voltage Ves Vhs Ine nA Q2 1 15 3 V AVas th Gate to Source Threshold Voltage Ip 250 uA referenced to 25 C Q1 6 wiist AT Temperature Coefficient Ip 10 mA referenced to 25 C Q2 5 Vas 10V lp 215A 4 3 5 6 Vas 4 5 V Ip 14A Q1 6 2 8 1 Vas 10V lp 15A Tj 2 125 C 5 9 8 7 D On Resist mQ DS on rain to Source On Resistance Ves 10 V Ip 30 A 13 16 Vas 4 5 V lp225A Q2 1 7 2 4 Vas 10 V Ip 2 30A Tj 2 125 C 1 8 21 Vps 2 5V lp 15A Q1 67 JFS Forward Transconductance Vose 5V p 30 A Q2 171 S Dynamic Characteristics Q1 1264 1680 Ci Input Capacitance Q1 F ze GEN Vps 13V Veg 0V f 1MHZ Q2 4042 5375 P Q1 340 450 Goce Output Capacitance Q2 Q2 1207 1605 pF Vos 13V Veg 0 V f 1 MHZ Q1 58 90 Lues Reverse Transfer Capacitance Q2 148 220 pF Q1 0 2 0 6 2 Rg Gate Resistance Q2 0 2 0 9 3 Q Switching Characteristics ta on Turn On Delay Time e d S ns Q1 ere Q1 2 10 t Rise Time Vpp 13 V lp 15 A Regu 6 Q Q2 53 11 ns ta off Turn Off Delay Time Q2 ES Ee Ss ns Vpp 13 V lp 30 A Regen 6 Q Q1 1 8 10 lr Fall Time 02 39 10 ns Q Total Gate Charge Ves 0 Vto10 o ES e EE Q1 9 13 Qg Total Gate Charge Ves 0 Vto4 5V Ip 2 15A Q2 27 38 nC Qgs Gate to Source Gate Charge Q2 e E nC Vpp 13 V QA gd Gate to Drain Miller Charge Ip 30A e BA nC 2011 Fairchild Semiconductor Corporation FDMS3600S Rev C3 www fai
9. E FAIRCHILD AE SEMICONDUCTOR FDMS36005 PowerTrench Power Stage 25 V Asymmetric Dual N Channel MOSFET Features Q1 N Channel B Max rps on 5 6 MQ at Vas 10 V Ip 15A B Max rps on 8 1 mQ at Ves 4 5 V lp 14A Q2 N Channel W Max rps on 1 6 MQ at Vas 10 V Ip 30 A B Max rps on 2 4 mQ at Veg 4 5 V Ip 25A B Low inductance packaging shortens rise fall times resulting in lower switching losses B MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing B RoHS Compliant August 2011 General Description This device includes two specialized N Channel MOSFETS in a dual PQFN package The switch node has been internally connected to enable easy placement and routing of synchronous buck converters The control MOSFET Q1 and synchronous SyncFET Q2 have been designed to provide optimal power efficiency Applications B Computing B Communications B General Purpose Point of Load B Notebook VCORE B Server MOSFET Maximum Ratings T 25 c unless otherwise noted Symbol Parameter Q1 Q2 Units Vps Drain to Source Voltage 25 25 V Vas Gate to Source Voltage Note 3 20 20 V Drain Current Continuous Package limited Tc 25 C 30 40 Continuous Silicon limited Tc 25 C 65 155 A Continuous TA 25 C 1518 3010 Pulsed 40 100 Eas Single Pulse Avalanche Energy 504 200 mJ
10. ITING POLICY Fairchild Semiconductor Corporation s Anti Counterfeiting Policy Fairchild s Anti Counterfeiting Policy is also stated on our external website www Fairchildsemi com under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry All manufactures of semiconductor products are experiencing counterfeiting of their parts Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation substandard performance failed application and increased cost of production and manufacturing delays Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts have full traceability meet Fairchild s quality standards for handing and storage and provide access to Fairchild s full range of up to date technical and product information Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources Fairchild is committed to combat th
11. amp 0 1 Us MAX RATED Tht 10s Roya 120 C W DC T 25 C 0 01 EE 0 01 0 1 1 10 100200 Vps DRAIN to SOURCE VOLTAGE V Figure 24 Forward Bias Safe Operating Area 2011 Fairchild Semiconductor Corporation FDMS3600S Rev C3 Ip DRAIN CURRENT A P pk PEAK TRANSIENT POWER W CAPACITANCE pF 10000 1000 100 10 Crss f 1MHz Ves 0V 0 1 200 1 10 25 Vps DRAIN TO SOURCE VOLTAGE V Figure 21 Capacitance vs Drain to Source Voltage 150 100 Limited by Package 25 50 Tc 75 100 125 CASE TEMPERATURE C 150 Figure 23 Maximun Continuous Drain Current vs Case Temperature 10000 1000 100 10 SINGLE PULSE Roya 120 C W Ta 25 C 100 1000 10 10 1 10 t PULSE WIDTH sec Figure 25 Single Pulse Maximum Power Dissipation www fairchildsemi co
12. and wider PHASE trace to the inductor reduces the conduction loss Preferably the Power Stage should be directly in line as shown in figure 31 with the inductor for space savings and compactness 4 The PowerTrench Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing It allows the part to operate well within the breakdown voltage limits This eliminates the need to have an external snubber circuit in most cases If the designer chooses to use an RC snubber it should be placed close to the part between the PHASE pad and S2 pins to dampen the high frequency ringing 5 The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible At higher frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance This will result in slower rise and fall times and additional switching losses Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board This provides a very compact path for the drive signals and improves efficiency of the part 6 S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding Poor grounding ca
13. is global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors PRODUCT STATUS DEFINITIONS Definition of Terms Definition Datasheet Identification Product ProductStatus Datasheet contains the design specifications for product development Specifications Advance Information Formative In Design may change in any manner without notice Datasheet contains preliminary data supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design First Production Preliminary TM Datasheet contains final specifications Fairchild Semiconductor reserves the right to No Identification Needed Full Production make changes at any time without notice to improve the design Datasheet contains specifications on a product that is discontinued by Fairchild Obsolete Nota riroduenon Semiconductor The datasheet is for reference information only airchild Semiconductor Corporation 15 FDMS36008 Rev C3 Rev 155 www fairchildsemi com
14. istics to a discrete external Schottky diode in parallel with a MOSFET Figure 27 shows the reverse recovery characteristic of the FDMS36005 oO o wW o N al N e didt 300 A us 10 CURRENT A a 0 50 100 150 200 250 300 TIME ns Figure 27 FDMS3600S SyncFET body diode reverse recovery characteristic 2011 Fairchild Semiconductor Corporation FDMS3600S Rev C3 Schottky barrier diodes exhibit significant leakage at high tem perature and high reverse voltage This will increase the power in the device 10 Joe REVERSE LEAKAGE CURRENT A mb e N Ty 1259C T 100 C l a b e A 10 Ty 25 C 10 0 5 10 15 20 25 Vos REVERSE VOLTAGE V Figure 28 SyncFET body diode reverse leakage versus drain source voltage www fairchildsemi com 2M81S 19MOd gu 9U91 10MOd SOOIESINGS Application Information 1 Switch Node Ringing Suppression Fairchild s Power Stage products incorporate a proprietary design that minimizes the peak overshoot ringing voltage on the switch node PHASE without the need of any external snubbing components in a buck converter As shown in the figure 29 the Power Stage solution rings significantly less than competitor solutions under the sa
15. m 2M81S 19MOd gu 9U91 10MOd SOOIESINGS Typical Characteristics Q2 N Channel T 25 c unless otherwise noted 2 T T T T Kaabes T T T ER ET E RTI 4 DUTY CYCLE DESCENDING ORDER E D 0 5 lt Y lt 0 1 0 2 Eg 01 e ce ESI Ww N Pom I ui 0 05 m O 0 02 N 001 0 01 ty a A D g Q t2 zz SINGLE PUE NOTES 2 0 001 Roja 2120 C W DUTY FACTOR D t4 to Note 1d PEAK Ty Pom X Zoya X Roja TA 0 0001 10 10 10 10 1 10 100 t RECTANGULAR PULSE DURATION sec Figure26 Junction to Ambient Transient Thermal Response Curve 2011 Fairchild Semiconductor Corporation FDMS3600S Rev C3 1000 www fairchildsemi com 2M81S J MOd gu 9U91 10MOd SOOIESINGS Typical Characteristics continued SyncFET Schottky body diode Characteristics Fairchild s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET This diode exhibits similar character
16. me set of test conditions Fie Edi Vertical Horz Acq Tr Deplay Cursors Measure Math Utiles Fie Edt Vertical Hepi cn Trig Delay Cursors Measure Math Utiles Tek Stopped 425 AGG 28 Sep 10 09 31 29 Tek Stopped 11280 Ac qs 27 Sep 10 15 48 23 Ka li A ad rdg PES a T E E et A on p ah i x m CA AAA He L4 I e WW hl 50 OG M 20 0 5 065 ITS8 pst CHI 2 Uy M M 0 On 5 0658 M8 Opel A Ch 50Y A CT 50 Power Stage Device Competitors solution Figure 29 Power Stage phase node rising edge High Side Turn on Patent Pending 2011 Fairchild Semiconductor Corporation 11 FDMS3600S Rev C3 www fairchildsemi com 2M81S J MOd 420491 10MOd SOOIESINGS D1 C1 Eto Power Stage 1 eel vul Ja FET H L s1 V in PHASE e D2 A Figure 30 Shows the Power Stage in a buck converter topology 2 Recommended PCB Layout Guidelines As a PCB designer it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train Power Stage is a high power density solution and all high current flow paths such as VIN D1 PHASE S1 D2 and GND S2 should be short and wide for better and stable current flow heat radiation and system performance A recommended layout proce dure is discussed below to maximize the electrical and thermal performance of the part Top Layer Bottom Layer Figure 31 Recommended PCB Layout 2011 Fairchild Semico
17. n create a noise transient offset voltage level between S2 and driver ground This could lead to faulty operation of the gate driver and MOSFET 7 Use multiple vias on each copper area to interconnect top inner and bottom layers to help smooth current flow and heat conduction Vias should be relatively large around 8 mils to 10 mils and of reasonable inductance Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB If not feasible they should be connected from the backside via a network of low inductance vias 2011 Fairchild Semiconductor Corporation 13 www fairchildsemi com FDMS3600S Rev C3 PEIS 19MOd gu 9U91 10MOd SOOIESINGS Dimensional Outline and Pad Layout 4 00 E e T 1 27 TYP 0 65 TYP WS 2 52 PKG AA SCH 1 60 t Der Kee ll D I E RAI PIN 1 121 IDENT MAY 7 APPEAR AS 1 2 31 3 15 OPTIONAL TOP VIEW 0 1002 C A B 0 05 M NOTES UNLESS OTHERWISE SPECIFIED A DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO 240 ISSUE B DATED 10 2009 B ALL DIMENSIONS ARE IN MILLIMETERS 1 27 C DIMENSIONS DO NOT INCLUDE 3 81 BURRS OR MOLD FLASH MOLD BOTTOM VIEW FLASH OR BURRS DOES NOT EXCEED 0 10MM 0 51 D DIMENSIONING AND TOLERANCING PER ASME Y 14 5M 1984 L SEATING 0 90 DETAIL A run SCALE 2X 2011 Fairchild Semiconductor Corporation 14 www fairchildsemi com FDMS3600S Re
18. nductor Corporation 12 www fairchildsemi com FDMS3600S Rev C3 281S 19MOd g 994 L4 MOd SOO9ESINGS Following is a guideline not a reguirement which the PCB designer should consider 1 Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation C1 and C2 show the bypass capacitors placed close to the part between D1 and S2 Input capacitors should be connected in parallel close to the part Multiple input caps can be connected depending upon the application 2 The PHASE copper trace serves two purposes In addition to being the current path from the Power Stage package to the output inductor L it also serves as heat sink for the lower FET in the Power Stage package The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor This is done to minimize conduction losses and limit temperature rise Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential Care should be taken to minimize coupling to adjacent traces The reference layout in figure 31 shows a good balance between the thermal and electrical performance of Power Stage 3 Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance A shorter
19. r Corporation FDMS3600S Rev C3 t PULSE WIDTH sec Figure 12 Single Pulse Maximum Power Dissipation www fairchildsemi com 2M81S J MOd gu 9U91 10MOd SOOIESINGS Typical Characteristics Q1 N Channel T 25 c unless otherwise noted 2 1 DUTY CYCLE DESCENDING ORDER a D 0 5 Y E 2 0 2 TT Ic 0 31 oi Pom a O L 0 05 uz 002 sl T z 0 01 t E 0 01 SINGLE PULSE O o NOTES z Roya 125 C W DUTY FACTOR D t4 to Note 1c PEAK Ty Pom X Zoya X Roja TA 0 001 10 10 10 10 1 10 100 t RECTANGULAR PULSE DURATION sec Figure 13 Junction to Ambient Transient Thermal Response Curve 2011 Fairchild Semiconductor Corporation FDMS3600S Rev C3 1000 www fairchildsemi com abels J MOd gu 9U91 10MOd SOOIESINGS Typical Characteristics Q2 N Channel T 25 c unlenss otherwise noted 100
20. rchildsemi com 2M81S J MOd ouUe1LI9MOd SOOIESINGS Electrical Characteristics T 25 c unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Drain Source Diode Characteristics Vas 0 V Ig 15A Note 2 Q1 0 8 1 2 Vsp Source to Drain Diode Forward Voltage Vos 0 V Is 30 A Note 2 Q2 0 8 12 V Q1 Q1 21 34 t Reverse Recovery Time ns i i SR I 15 A di dt 100 A us Q2 32 51 Q2 Q1 6 6 13 Qy Reverse Recovery Charge l 30 A di dt 300 A us Q2 36 58 nC Notes 1 Roja is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1 5 x 1 5 in board of FR 4 material Rojc is guaranteed by design while Reca is determined by the user s board design b 50 C W when mounted on a 57 C W when mounted on a 1 in pad of 2 oz copper a 1 in pad of 2 oz copper c 125 C W when mounted on a d 120 C W when mounted on a minimum pad of 2 oz copper minimum pad of 2 oz copper o o 00000 00000 2 Pulse Test Pulse Width lt 300 us Duty cycle lt 2 0 3 As an N ch device the negative Vgs rating is for low duty cycle pulse ocurrence only No continuous rating is implied 4 Ens of 50 mJ is based on starting Ty 25 C N ch L 1 mH las 10 A Vpp 23 V Vas 10 V 100 test at L 0 3 mH las 15 A 5 Ens of 200 mJ is based on starting Tj 25 C N ch L 1 mH las 20 A Vpp 23 V Vas
21. v C3 2M81S J MOd 420491 10MOd SOOIESINGS AAA FAIRCHILD EH SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such trademarks 2M81S 19MOd gu 9U81J L10MOd S009 SIAQA 2Cool FlashWriter PDP SPM The Power Franchise AccuPower FPS Power SPM The Right Technology for Your Success Auto SPM F PFS PowerTrench AX CAP FRFET PowerxS wer Bitsic Global Power Resource Programmable Active Droop Ti franchise ya Build it Now Green FPSTM QFET Ae CorePLUSTM Green FPS e Series QS mc CorePOWER Gmax Quiet Series TRE 0 CROSSVOLT GTO RapidConfigure ERU O CTL IntelliMAXTM TM TinyP CR Current EE Logic ISOPLANAR 7 T DU DEUXPEED MegaBuck Saving our world 1mW W kW at a time se Dual Cool MICROCOUPLER SignalWise Troes EcoSPARK MicroFET SmartMax TriFault Detect EfficentMax MicroPak SMART START Or ESBC MicroPak2 SPM kao i e MillerDrive STEALTH We IC MotionMax SuperFET WA Fairchild Motion SPM SuperSOT 3 apes Fairchild Semiconductor mWSaver SuperSOT 6 SIS FACT Quiet Series OptiHi TTV UPI eds caer riget FACTO OPTOLOGIC SupreMOs UniFET FAST OPTOPLANAR SyncFET VOX FastvCore Sync Lock VisualMax
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FAIRCHILD FDMS3600S Manual