MOTOROLA Semiconductor MMSF10N02Z handbook(1)
Contents
1. MAXIMUM RATINGS T 25 C unless otherwise noted Symbol Value Drain to Source Voltage Vpss 20 Drain to Gate Voltage Rs 1 0 MQ VDGR 20 Gate to Source Voltage Continuous GS Drain Current Continuous TA 25 C Ip Continuous TA 70 C ID Single Pulse tp lt 10 us IDM Total Power Dissipation TA 25 C 1 Maximum Temperature for Soldering 1 When mounted on 1 inch square FR 4 or G 10 board VGs 4 5 V 10 Seconds DEVICE MARKING ORDERING INFORMATION MMSF10N02ZR2 12 mm embossed tape 2500 units Designer s Data for Worst Case Conditions The Designer s Data Sheet permits the design of most circuits entirely from the information presented SOA Limit curves representing boundaries on device characteristics are given to facilitate worst case design Preferred devices are Motorola recommended choices for future use and best overall value Designer s HDTMOS and EZFET are trademarks of Motorola Inc TMOS is a registered trademark of Motorola Inc Thermal Clad is a trade mark of the Bergquist Company REV2 M MOTOROLA Motorola Inc 1997 MMSF10NO2Z ELECTRICAL CHARACTERISTICS Ta 25 C unless otherwise noted OOOO o ooo O Smha T we we we ww OFF CHARACTERISTICS Drain to Source Breakdown Voltage V BR DSS Vdc Vas 0 Vdc Ip 0 25 mAdc 20 Temperature Coefficient Positive 17 mV C Zero Gate Voltage Drain Current Ipss uAdc Vps 202. MOTORODA D 0 0 SEMICONDUCTOR TECHNICAL DATA Designers Data Sheet Medium Power Surface Mount Products TMOS Single N Channel with Monolithic Zener ESD Protected Gate EZFETs are an advanced series of power MOSFETs which utilize Motorola s High Cell Density HDTMOS process and contain Order this document by MMSF10N02Z D MMSF10NO2Z Motorola Preferred Device SINGLE TMOS POWER MOSFET 10 AMPERES 20 VOLTS monolithic back to back zener diodes These zener diodes RDS on 0 015 OHM provide protection against ESD and unexpected transients These miniature surface mount MOSFETs feature low RDS on and true logic level performance They are capable of withstanding high energy in the avalanche and commutation modes and the drain to source diode has a very low reverse recovery time CAS EZFET devices are designed for use in low voltage high speed 5 switching applications where power efficiency is important Zener Protected Gates Provide Electrostatic Discharge Protection Low RDS on Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO 8 Surface Mount Package Saves Board Space Diode Exhibits High Speed With Soft Recovery S IDSs Specified at Elevated Temperature Mounting Information for SO 8 Package Provided CASE 751 05 Style 12 G SO 8 Source Source Source Gate
3. ZONES2 amp 5 ZONES3 amp 6 ZONES 4 amp 7 RAMP RAMP SOAK SPIKE 205 TO 219 C 200 C 170 C PEAK AT DESIRED CURVE FOR HIGH SOLDER JOINT MASS ASSEMBLIES 150 C 150 C 100 C MASS ASSEMBLIES 50 C 160 C 140 C DESIRED CURVE FOR LOW SOLDER IS LIQUID FOR 40 TO 80 SECONDS DEPENDING ON MASS OF ASSEMBLY TIME 3 TO 7 MINUTES TOTAL gt TMAX Figure 15 Typical Solder Heating Profile Motorola TMOS Power MOSFET Transistor Device Data MMSF10NO2Z PACKAGE DIMENSIONS NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 DIMENSIONS ARE IN MILLIMETERS DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION MAXIMUM MOLD PROTRUSION 0 15 PER SIDE DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION MILLIMETERS DIM MIN MAX 1 35 1 75 0 10 0 25 0 35 0 49 0 18 0 25 4 80 5 00 3 80 4 00 1 27 BSC 5 80 6 20 0 25 0 50 0 40 1 25 09 19 A SEATING J PLANE O 0 10 e amp r x e m o o v Z AQ STYLE 12 PIN 1 SOURCE 2 SOURCE SOURCE GATE CASE 751 05 DRAIN DRAIN SO 8 DRAIN ISSUE S DRAIN Motorola reserves the right to make changes without furt
4. power electronic loads are inductive the data in the figure is taken with a resistive load which approximates an optimally snubbed inductive load Power MOSFETs may be safely op erated into an inductive load however snubbing reduces switching losses C CAPACITANCE pF 500 0 2 4 6 8 Vps DRAIN TO SOURCE VOLTAGE VOLTS 12 14 16 18 20 Figure 7 Capacitance Variation Motorola TMOS Power MOSFET Transistor Device Data z 16 Vps o 14 g 12 6 lt 3 m QT 2 e 4 VG 8 1 2 Q i Q2 Hb i y Lu E gi Q3 Ips 10A 44 5 TJ 25 C A 2 6 gt 0 0 0 5 10 15 20 25 Qg TOTAL GATE CHARGE nC Figure 8 Gate To Source and Drain To Source Voltage versus Total Charge Vps DRAIN TO SOURCE VOLTAGE VOLTS MMSF10N02Z t TIME ns 1 10 100 RG GATE RESISTANCE OHMS Figure 9 Resistive Switching Time Variation versus Gate Resistance DRAIN TO SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode Of particular interest are the reverse re covery characteristics which play a major role in determining switching losses radiated no
5. profiles from one operating session to the next Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board This profile will vary among soldering systems but it is a good starting point Factors that can affect the profile include the type of soldering system in use density and types of components on the board type of solder used and the type of board or substrate material being used This profile shows temperature versus time The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint The two profiles are based on a high density and a low density board The Vitronics SMD310 convection in frared reflow soldering system was used to generate this profile The type of solder used was 62 36 2 Tin Lead Silver with a melting point between 177 189 C When this type of furnace is used for solder reflow work the circuit boards and solder joints tend to heat first The components on the board are then heated by conduction The circuit board because it has a large surface area absorbs the thermal energy more efficiently then distributes this energy to the components Because of this effect the main body of a component may be up to 30 degrees cooler than the adjacent solder joints STEP 1 STEP2 STEP3 STEP 4 STEP 5 STEP 6 STEP 7 PREHEAT VENT HEATING HEATING HEATING VENT COOLING ZONE 1 SOAK
6. 0 1 0 01 2 5 5 7 5 10 12 5 15 17 5 20 Vps DRAIN TO SOURCE VOLTAGE VOLTS Figure 6 Drain to Source Leakage Current versus Voltage MMSF10NO2Z POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled The lengths of various switching intervals At are deter mined by how fast the FET input capacitance can be charged by current from the generator The published capacitance data is difficult to use for calculat ing rise and fall because drain gate capacitance varies greatly with applied voltage Accordingly gate charge data is used In most cases a satisfactory estimate of average input current IG Av can be made from a rudimentary analysis of the drive circuit so that t Q IG AV During the rise and fall time interval when switching a resis tive load Vas remains virtually constant at a level known as the plateau voltage Vsqp Therefore rise and fall times may be approximated by the following tr Q2 x RG VGG VasP tt Qo x RG VGSP where VGG the gate drive voltage which varies from zero to VGG RG the gate drive resistance and Qo and VGsP are read from the gate charge curve During the turn on and turn off delay times gate current is not constant The simplest calculation uses appropriate val ues from the capacitance curves in a standard equation for voltage change in an RC network The equations ar
7. C 0 0 02 04 06 08 1 12 14 16 18 2 Vps DRAIN TO SOURCE VOLTAGE VOLTS Figure 1 On Region Characteristics 0 03 e c n2 c e c n5 e ce c e e e c 2 c Vps gt 10V Ty 25 C p DRAIN CURRENT AMPS oco 0 0 5 1 1 5 2 2 5 VGs GATE TO SOURCE VOLTAGE VOLTS Figure 2 Transfer Characteristics Ty 25 C on DRAIN TO SOURCE RESISTANCE OHMS ce Rps PO 3 4 5 6 7 8 9 10 1d 12 Vas GATE TO SOURCE VOLTAGE VOLTS Figure 3 On Resistance versus Gate to Source Voltage 50 25 0 25 50 75 100 125 150 TJ JUNCTION TEMPERATURE C RDS on DRAIN TO SOURCE RESISTANCE NORMALIZED Figure 5 On Resistance Variation with Temperature Motorola TMOS Power MOSFET Transistor Device Data RDS on DRAIN TO SOURCE RESISTANCE OHMS 1 3 5 7 9 11 13 15 Ip DRAIN CURRENT AMPS Figure 4 On Resistance versus Drain Current and Gate Voltage 10000 Vas 0V Ty 125 C 1000 100 C 100 m o S 10 a Oo 25 C o 1
8. MOSFET Transistor Device Data MMSF10NO2Z TYPICAL ELECTRICAL CHARACTERISTICS 0 1 0 01 Rthja t EFFECTIVE TRANSIENT THERMAL RESISTANCE SINGLE PULSE 0 001 1 0E 05 1 0E 04 1 0E 03 1 0E 02 1 0E 01 1 0E 00 1 0E 01 1 0E 02 1 0E 03 t TIME s Figure 13 Thermal Response TIME Figure 14 Diode Reverse Recovery Waveform Motorola TMOS Power MOSFET Transistor Device Data 7 MMSF10NO2Z INFORMATION FOR USING THE SO 8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package With the correct pad geometry the packages will self align when subjected to a solder reflow process 0 041 1 04 z 0 015 l l p 0 0256 0 38 0 65 inches mm SO 8 POWER DISSIPATION The power dissipation of the SO 8 is a function of the input pad size This can vary from the minimum pad size for soldering to the pad size given for maximum power dissip
9. Vdc Vas 0 Vdc 10 Vps 20 Vdc VGs 0 Vdc Ty 125 C 100 Gate Body Leakage Current Vas 12 Vdc Vps 0 Vdc lass 06 15 pi ON CHARACTERISTICS 1 Gate Threshold Voltage Vps Vas Ip 0 25 mAdc Threshold Temperature Coefficient Negative Static Drain to Source On Resistance Vas 4 5 Vdc Ip 10 Adc Vas 2 7 Vdo Ip 5 0 Adc DYNAMIC CHARACTERISTICS Input Capacitance Vps 10 Vdc Vas 0 Vdc Output Capacitance f 1 0 MHz Transfer Capacitance SWITCHING CHARACTERISTICS 2 Turn On Delay Time VDD 10 Vdc Ip 5 0 Ado Turn Off Delay Time Vas 4 0 Vdc RG 10 Q Fall Time Gate Charge Vps 16 Vdc Ip 10 Adc Vas 4 0 Vdc SOURCE DRAIN DIODE CHARACTERISTICS Forward On Voltage Ig 10 Adc Vas 0 Vdc Is 10 Adc Vas 0 Vdc Ty 125 C Reverse Recovery Time Ig 10 Adc Vas 0 Vdc dis dt 100 A us Reverse Recovery Storage Charge 1 Pulse Test Pulse Width x 300 us Duty Cycle x 2 2 Switching characteristics are independent of operating junction temperature 3 Reflects typical values Max limit Typ pk 3x SIGMA 2 Motorola TMOS Power MOSFET Transistor Device Data MMSF10N02Z TYPICAL ELECTRICAL CHARACTERISTICS 20 r r Vag 12V 27V 18 P 45N D 16 19V 14 E i 12 T gt 10 17V e Zz 8 16V O 6 i a 15V 4 2 TJ 25
10. ated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Mfax is a trademark of Motorola Inc How to reach us USA EUROPE Locations Not Listed Motorola Literature Distribution JAPAN Nippon Motorola Ltd SPD Strategic Planning Office 4 32 1 P O Box 5405 Denver Colorado 80217 303 675 2140 or 1 800 441 2447 Nishi Gotanda Shinagawa ku Tokyo 141 Japan 81 3 5487 8488 Mfax RMFAX0 email sps mot com TOUCHTONE 602 244 6609 ASIA PACIFIC Motorola Semiconductors H K Ltd 8B Tai Ping Industrial Park US amp Canada ONLY 1 800 774 1848 51 Ting Kok Road Tai Po N T Hong Kong 852 26629298 INTERNET http motorola com sps Mj MOTOROLA MMSF10NO2Z D
11. ation Power dissipation for a surface mount device is determined by TJ max the maximum rated junction temperature of the die RgJA the thermal resistance from the device junction to ambient and the operating temperature TA Using the values provided on the data sheet for the SO 8 package Pp can be calculated as follows Pp TJ max TA ReJA The values for the equation are found in the maximum ratings table on the data sheet Substituting these values into the equation for an ambient temperature Ta of 25 C one can calculate the power dissipation of the device which in this case is 2 5 Watts Pp 190 C 25 C 2 5 Watts 50 C W The 50 C W for the SO 8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2 5 Watts using the footprint shown Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad Using board material such as Thermal Clad the power dissipation can be doubled using the same footprint SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device When the entire device is heated to a high temperature failure to complete soldering within a short time could result in device failure Therefore the following items should always be observed in order to minimize the thermal stress to which the devices are subjected e Always preheat the device e Th
12. e td on RG Ciss In VGG Vaa VasP l td off RG Ciss In VaG VGsP The capacitance Ciss is read from the capacitance curve at a voltage corresponding to the off state condition when cal culating td on and is read at a voltage corresponding to the on state when calculating tq off At high switching speeds parasitic circuit elements com plicate the analysis The inductance of the MOSFET source lead inside the package and in the circuit wiring which is common to both the drain and gate current paths produces a voltage at the source which reduces the gate drive current The voltage is determined by Ldi dt but since di dt is a func tion of drain current the mathematical solution is complex The MOSFET output capacitance also complicates the mathematics And finally MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source but the internal resistance is difficult to mea sure and consequently is not specified The resistive switching time variation versus gate resis tance Figure 9 shows how typical switching performance is affected by the parasitic circuit elements If the parasitics were not present the slope of the curves would maintain a value of unity regardless of the switching speed The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components Most
13. e delta temperature between the preheat and soldering should be 100 C or less e When preheating and soldering the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet When using infrared heating with the reflow soldering method the difference shall be a maximum of 10 C e The soldering temperature and time shall not exceed 260 C for more than 10 seconds e When shifting from preheating to soldering the maximum temperature gradient shall be 5 C or less e After soldering has been completed the device should be allowed to cool naturally for at least three minutes Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress e Mechanical stress or shock should not be applied during cooling Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device Motorola TMOS Power MOSFET Transistor Device Data MMSF10N02Z TYPICAL SOLDER HEATING PROFILE For any given circuit board there will be a group of control settings that will give the desired heat pattern The operator must set temperatures for several heating zones and a figure for belt speed Taken together these control settings make up a heating profile for that particular circuit board On machines controlled by a computer the computer remembers these
14. her notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary overtime All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associ
15. ise EMI and RFI System switching losses are largely due to the nature of the body diode itself The body diode is a minority carrier de vice therefore it has a finite reverse recovery time trr due to the storage of minority carrier charge QRR as shown in the typical reverse recovery wave form of Figure 11 It is this stored charge that when cleared from the diode passes through a potential and defines an energy loss Obviously repeatedly forcing the diode through reverse recovery further increases switching losses Therefore one would like a diode with short trr and low QRR specifications to minimize these losses The abruptness of diode reverse recovery effects the amount of radiated noise voltage spikes and current ring ing The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di dts The diode s negative di dt during t is directly con trolled by the device clearing the stored charge However the positive di dt during tp is an uncontrollable diode charac teristic and is usually the culprit that induces current ringing Therefore when comparing diodes the ratio of tp ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated A ratio of 1 is considered ideal and values less than 0 5 are considered snappy Compared to Motorola standard cell density low voltage MOSFETs high cell density MOSFET diodes are fa
16. nsient Thermal Resistance General Data and Its Use Switching between the off state and the on state may traverse any load line provided neither rated peak current IDM nor rated voltage Vpss is exceeded and that the transition time tr tf does not exceed 10 us In addition the total power averaged over a complete switching cycle must not exceed TJ MAX TC ReJC A power MOSFET designated E FET can be safely used in switching circuits with unclamped inductive loads For reliable operation the stored energy from cir cuit inductance dissipated in the transistor while in ava lanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified Although industry practice is to rate in terms of energy avalanche energy capability is not a constant The energy rating decreases non linearly with an in crease of peak current in avalanche and peak junction temperature 100 r4 Vas 11V FEE E SINGLE PULSE ims SG Tc 25C 4 ATT 10 A Zz zZ Llu TN ra dc jam Oo Zz lt L a 1 c B Rpg on LIMIT THERMAL LIMIT PACKAGE LIMIT 0 1 0 1 10 100 Vps DRAIN TO SOURCE VOLTAGE VOLTS Figure 12 Maximum Rated Forward Biased Safe Operating Area Motorola TMOS Power
17. ster shorter trr have less stored charge and a softer reverse re covery characteristic The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di dt than a standard cell MOSFET diode without increasing the current ringing or the noise gen erated In addition power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses Ves 0V Ty 25 C Ig SOURCE CURRENT AMPS a 0 01 02 03 Vsp SOURCE TO DRAIN VOLTAGE 0 4 05 06 0 7 VOLTS 08 0 9 Figure 10 Diode Forward Voltage versus Current Motorola TMOS Power MOSFET Transistor Device Data MMSF10NO2Z di dt 300 A us Standard Cell Density trr High Cell Density Is SOURCE CURRENT t TIME Figure 11 Reverse Recovery Time trr SAFE OPERATING AREA The Forward Biased Safe Operating Area curves de fine the maximum simultaneous drain to source voltage and drain current that a transistor can handle safely when it is forward biased Curves are based upon maximum peak junction temperature and a case temperature TC of 25 C Peak repetitive pulsed power limits are deter mined by using the thermal response data in conjunction with the procedures discussed in AN569 Tra
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MOTOROLA Semiconductor MMSF10N02Z handbook(1)