FAIRCHILD FDG6318PZ Dual P-Channel Digital FET handbook
Contents
1. 10 3 PULSE DURATION 80us DUTY CYCLE 0 5 MAX lt T Vpp 10V hva 100 5 T 5 2 Ty 150 C w w 4 R s g g 1 X H T 25 C o at o z X E n ims z E OPERATION IN THIS h R Hs E a F REA MAY BE a A 1 Ty 55 C 4 LIMITED BY rps on 10ms a I SINGLE PULSE 0 1 Tj MAX RATED F Ta 25 C 0 05 L 1 1 0 1 10 30 0 1 2 3 4 Vps DRAIN TO SOURCE VOLTAGE V Vas GATE TO SOURCE VOLTAGE V Figure 5 Forward Bias Safe Operating Area Figure 6 Transfer Characteristics 3 1 0 PULSE DURATION 80us PULSE DURATION 80us DUTY CYCLE 0 5 MAX Vas 4 5V DUTY CYCLE 0 5 MAX 1 w 0 9 T TA 25 C e E d 2 u 7s o 9 08 5 z o z 5 z fn E S B oz g eter ai 2 o i e 0 6 0 0 5 0 0 5 1 0 1 5 2 0 2 5 3 0 2 3 4 5 6 Vps DRAIN TO SOURCE VOLTAGE V Vgs GATE TO SOURCE VOLTAGE V Figure 7 Saturation Characteristics Figure 8 Drain to Source On Resistance vs Gate Voltage and Drain Current 1 50 2 w PULSE DURATION 80us Ves Vps lp 2504A DUTY CYCLE 0 5 MAX gt o w H Ow Bo x 1 e 2 1 25 5 5 1 0 z a n Es E H ao lt 0 ac NZ F 3 O 1 00 9 t 0 8 4 L P g o z Veg 4 5V Ip 0 5A 0 75 0 6 80 40 0 40 80 120 160 80 40 0 40 80 120 160 Ty JUNCTION TEMPERATURE C Ty JUNCTION TEMPERATURE C2. Typical Characteristic T 25 C unless otherwise noted 1 2 0 6 o 1 0 w gt z Ej 0 8 E 04 2 x x gt O 06 o br z Q lt Vas 2 5V 2 04 A 0 2 a E 02 z 0 n 0 0 0 25 50 75 100 125 150 25 50 75 100 125 150 Ta AMBIENT TEMPERATURE C Ta CASE TEMPERATURE C Figure 1 Normalized Power Dissipation vs Figure 2 Maximum Continuous Drain Current vs Ambient Temperature Case Temperature 71 1 ay CYCLE DESCENDING ORDER E 0 2 w E 0 1 ag L 0 05 K E L 0 02 0 01 w ave 9 3 04 Pom N I t F gt ty NOTES DUTY FACTOR D t1 t2 PEAK Ty Ppy X Zoua X Roua TA 0 01 L LILI IIIN 105 104 10 10 10 109 10 10 10 t RECTANGULAR PULSE DURATION s Figure 3 Normalized Maximum Transient Thermal Impedance 20 UE TA 25 C 10 Sy TRANSCONDUCTANCE A lt A MAY LIMIT CURRENT FOR TEMPERATURES IN THIS REGION ABOVE 25 C DERATE PEAK E hi CURRENT AS FOLLOWS Lu E TES 150 TA o 125 l wW n 2 Toad Ves 4 5V l Ves 2 5V 0 4 105 104 103 10 107 10 101 10 108 t PULSE WIDTH s Figure 4 Peak Current Capability 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev B Zd8lLE9DdS Typical Characteristic Continued TA 25 C unless otherwise noted
3. rtherm rtherm1 th c2 11 2 rtherm rtherm2 c2 c3 11 5 rtherm rtherm3 c3 c4 12 5 rtherm rtherm4 c4 c5 27 rtherm rtherm5 c5 c6 81 rtherm rtherm6 c6 c7 88 rtherm rtherm7 c7 c8 92 rtherm rtherm8 c8 tl 93 RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERM5 RTHERM6 RTHERM7 RTHERM8 th JUNCTION CTHERM1 CTHERM2 CTHERM3 CTHERM4 CTHERMS5 CTHERM6 CTHERM7 CTHERM8 tl AMBIENT 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev B Zd8lLE9DdS TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use andis not intended to be an exhaustive list of all such trademarks ACExTM FACT ImpliedDisconnect PACMAN SPM ActiveArray FACT Quiet Series ISOPLANAR POP Stealth Bottomless FAST LittleFET Power247 SuperSOT 3 CoolFET FASTr MicroFET PowerTrench SuperSOT 6 CROSSVOLT FRFET MicroPak QFET SuperSOT 8 DOME GlobalOptoisolator MICROWIRE Qs SyncFET EcoSPARK GTO MSX QT Optoelectronics TinyLogic E CMOSTM HiSeC MSXPro Quiet Series TruTranslation EnSigna ZC TM OCXTM RapidConfigure UHC Across the board Around the world M OCXPro RapidConnect UltraFET The Power Franchise OPTOLOGIC SILENT SWITCHER VCX Programmable Active Droop OPTOPLANAR SMART START DISCLAIMER FAIRCHILD SEMICONDUCT
4. Figure 9 Normalized Drain to Source On Figure 10 Normalized Gate Threshold Voltage vs Resistance vs Junction Temperature Junction Temperature 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev B Zd8lLE9DdS Typical Characteristic Continued TA 25 C unless otherwise noted 1 10 Ip 250uA 200 Ciss Cos Cap 100 Lee NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE C CAPACITANCE pF 10 Vas OV f 1MHz 40 0 40 80 Ty JUNCTION TEMPERATURE C 120 Figure 11 Normalized Drain to Source Breakdown Voltage vs Junction Temperature Voltage 160 0 1 1 10 20 Vps DRAIN TO SOURCE VOLTAGE V Figure 12 Capacitance vs Drain to Source Vpp 10V WAVEFORMS IN Vgs GATE TO SOURCE VOLTAGE V DESCENDING ORDER 1 Figure 13 Gate Charge Waveforms for Constant Gate Currents lp 0 5A Ip 0 1A 0 5 1 0 1 5 2 0 Qg GATE CHARGE nC 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev B Zd8lLE9DdS PSPICE Electrical Model SUBCKT FDG6318PZ 213 rev January 2003 CA 12 80 6e 10 CB 15 14 1 1e 10 ESG CIN 6 8 0 75e 10 LDRAIN n 5 an DBODY 5 7 DBODYMOD E DBREAK 7 11 DBREAKMOD RLDRAIN DPLCAP 10 6 DPLCAPMOD RSLC1 RSLC2 51 A EBREAK 5 11 17 18 23 3 E ES
5. a ee FAIRCHILD os e SEMICONDUCTOR FDG6318PZ Dual P Channel Digital FET General Description These dual P Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductor s especially tailored to minimize on state resistance This device has been designed especially for bipolar digital transistors and small signal MOSFETS Applications Battery management Pint 7 s G SC70 6 January 2003 Features 0 5A 20V DS ON 780mQ Max Ves 4 5 V FDS ON 1200mQ Max Ves 2 5V Very low level gate drive requirements allowing direct operation in 3V circuits Vgs tH lt 1 5V Gate Source Zener for ESD ruggedness 1 4kV Human Body Model Compact industry standard SC 70 6 surface mount package The pinouts are symmetrical pin1 and pin 4 are interchangeable MOSFET Maximum Ratings 1 25 c unless otherwise noted Symbol Parameter Voss Drain to Source Voltage Ratings 20 Gate to Source Voltage 2 Drain Current Continuous Tg 25 C Veg 4 5V Continuous Tc 100 C Vas 2 5V Pulsed 0 5 0 3 Figure 4 Power dissipation 0 3 Derate above 25 C 2 4 Operating and Storage Temperature 55 to 150 Electrostatic Discharge Rating MIL STD 883D Human Body Model 100pF 15002 Characteristics Thermal Resistance Junction to Ambient Note 1 Thermal Rosa 1 4 Package Ma
6. 2 1e 7 MODEL RDRAINMOD RES TC1 2 8e 3 TC2 4 9e 6 MODEL RSLCMOD RES TC1 3 7e 3 TC2 7 8e 6 MODEL RSOURCEMOD RES TC1 3e 3 TC2 5 2e 6 MODEL RVTHRESMOD RES TC1 9e 4 TC2 3e 7 MODEL RVTEMPMOD RES TC1 5 5e 4 TC2 1e 9 MODEL S1AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 5 VOFF 0 2 MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 2 VOFF 0 5 MODEL S2AMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 4 VOFF 0 1 MODEL S2BMOD VSWITCH RON 1e 5 ROFF 2 0 1 VON 0 1 VOFF 0 4 ENDS Note For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev B Zd8L 99q4 SABER Electrical Model REV January 2003 template fdg6318pz n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod isl 7 7e 11 nl 1 277 rs 1e 3 trs1 2 8e 1 trs2 3e 4 xti 0 cjo 3 9e 11 ikf 0 5 tt 33e 9 m 0 50 dp model dbreakmod rs 5 3e 1 trs1 5 5e 3 trs2 9 0e 5 dp model dplcapmod cjo 0 5e 10 isl 10e 30 nl 10 m 0 55 m model mmedmod type p vto 1 17 kp 0 6 is 1e 30 tox 1 m model mstrongmod type _p vto 1 45 kp 1 5 is 1e 30 tox 1 m model mweakmod type _p vto 0 99 kp 0 05 is 1e 30 to
7. C EDS 14 8 5 81 EBREAK Ge EGS 13 8 6 81 56 4 ESG 510861 EVTHRES 6 21198 1 DPLCAP RDRAIN DBODY EVTEMP 6 20 18 22 1 egies 1 IT 8 17 1 GATE EVTEMP HAN MWEAK m E ree ae O LDRAIN251e 9 10 E y 6 T LGATE 1 9 0 47e 9 m LSOURCE 3 70 47e 9 RLGATE DBREAK LSOURCE MMED 16 6 8 8 MMEDMOD 8 RSOURCE P SOURCE MSTRO 16 6 8 8 MSTROMOD 7 MWEAK 16 21 8 8 MWEAKMOD RLSOURCE RBREAK 17 18 RBREAKMOD 1 SIAO S2A RBREAK RDRAIN 50 16 RDRAINMOD 280e 3 12 13 14 15 17 18 RGATE 9 2012 4 8 13 RLDRAIN 2 5 10 SIB9 9 S2B RVTENP RLGATE 1 9 4 7 13 CB RLSOURCE 3 7 4 7 CA RSLC1 5 51 RSLCMOD 1e 6 dF RSLC2 5 50 1e3 EGS EDS VERE RSOURCE 8 7 RSOURCEMOD 190e 3 RVTHRES 22 8 RVTHRESMOD 1 8 RVTEMP 18 19 RVTEMPMOD 1 RVTHRES S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 20 2 5 MODEL DBODYMOD D IS 7 7e 11 N 1 277 RS 1e 3 TRS1 2 8e 1 TRS2 3e 4 XTI 0 IKF 0 5 CJO 3 9e 11 TT 33e 9 M 0 50 MODEL DBREAKMOD D RS 5 3e 1 TRS1 5 5e 3 TRS2 9e 5 MODEL DPLCAPMOD D CJO 0 5e 10 IS 1e 30 N 10 M 0 55 MODEL MMEDMOD PMOS VTO 1 17 KP 2 0 6 IS 1e 30 N 10 TOX 2 1L 2 1u W tu RG 12 4 MODEL MSTROMOD PMOS VTO 1 45 KP 21 5 IS 1e 30 N 10 TOX 2 1L 1u W 1u MODEL MWEAKMOD PMOS VTO 0 99 KP 0 05 IS 1e 30 N 10 TOX 1 L 1u W 1u RG 124 RS 0 1 MODEL RBREAKMOD RES TC1 5 5e 4 TC
8. Ip 0 5A 13 ns taorr _ Turn Off Delay Time Ves 4 5V Reg 1202 40 ns tr Fall Time 24 z ns torr Turn Off Time 96 ns Drain Source Diode Characteristics Vsp Source to Drain Diode Voltage Isp 0 5A 2 0 9 21 2 V tj Reverse Recovery Time Isp 0 5A digp dt 100A us E 22 ns QRR Reverse Recovered Charge Isp 0 5A digp dt 100A us a 16 nC Notes 1 Roja is the sum of the junction to case and case to ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the center drain pad Reyc is guaranteed by design while Roc is determined by user s board design Roya 415 C W when mounted on a 1inch copper pad 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev B Zd8I 95q04
9. OR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life or c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development Specifications may change in any manner without notice Preliminary First Production This dat
10. VTHRES res rvthres n22 n8 1 tc1 9e 4 tc2 3e 7 Spe ebreak n5 n11 n17 n18 23 3 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 Spe esg n5 n10 n6 n8 1 spe evtemp n20 n6 n18 n22 1 Spe evthres n6 n21 n19 n8 1 Sw vcsp s a n6 n12 n13 n8 model s1amod sw_vesp s1b n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod sw_vesp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 gt n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 20 2 5 H 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev B Zd8lLE9DdS SPICE Thermal Model REV January 2003 FDG6318PZ_JA Junction Ambient Copper Area 1sq in CTHERM1 Junction c2 0 17e 4 CTHERM2 c2 c3 2 7e 4 CTHERMG c3 c4 5 5e 4 CTHERM4 c4 c5 1 4e 3 CTHERMSB c5 c6 2 2e 3 CTHERM6 c6 c7 2 6e 3 CTHERQM7 c7 c8 6 6e 3 CTHERMB c8 Ambient 0 29 RTHERM Junction c2 11 2 RTHERM c2 c3 11 5 RTHERMS c3 c4 12 5 RTHERMA c4 c5 27 RTHERM5 c5 c6 81 RTHERM6 c6 c7 88 RTHERWM7 c7 c8 92 RTHERM8 c8 Ambient 93 SABER Thermal Model SABER thermal model FDG6318PZ Copper Area 1sq in template thermal_model th tl thermal_c th tl ctherm ctherm1 th c2 0 17e 4 ctherm ctherm2 c2 c3 2 7e 4 ctherm ctherm3 c3 c4 5 5e 4 ctherm ctherm4 c4 c5 1 4e 3 ctherm ctherm5 c5 c6 2 2e 3 ctherm ctherm6 c6 c7 2 6e 3 ctherm ctherm7 c7 c8 6 6e 3 ctherm ctherm8 c8 tl 0 29
11. asheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only Rev 12
12. rking and Ordering Information Device Marking Tape Width Quantity FDG6318PZ C706 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev B Zd81 95q04 Electrical Characteristics T 25 C unless otherwise noted Switching Characteristics Vgs 4 5V Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics Bypss Drain to Source Breakdown Voltage Ip 250uA Veg OV 20 V Ipss Zero Gate Voltage Drain Current Ves 2d6V Vas 0V a E 3 HA lass Gate to Source Leakage Current Ves 12V Vas OV 2 10 HA On Characteristics Vas tH Gate to Source Threshold Voltage Ves Vps lp 2504A 0 65 0 9 1 5 V Ip 0 5A Veg 4 5V 580 780 FDS ON Drain to Source On Resistance D 2 98 mQ i i Ip 0 4A Vas 2 5V 910 1200 Dynamic Characteristics Ciss Input Capacitance 85 4 pF Coss Output Capacitance Me in Vas OV 24 9 pF Onss Reverse Transfer Capacitance J 8 83 pF Qaror Total Gate Charge at 4 5V Ves OV to 4 5V 1 08 1 62 nC Qg 2 5 _ Total Gate Charge at 2 5V Vas 0V to 2 5V Mus udi 067 10 nC Qgs Gate to Source Gate Charge P _ 1 mn 0 21 nC Qoa Gate to Drain Miller Charge 9 0 33 nC ton Turn On Time 35 ns la ON Turn On Delay Time 10 ns tr Rise Time Vpp 10V
13. x 1 rs 0 1 Sw vcsp model s1amod ron 1e 5 roff 0 1 von 0 5 voff 0 2 Sw vcsp model sibmod ron 1e 5 roff 0 1 von 0 2 voff 0 5 Sw vcsp model s2amod ron 1e 5 roff 0 1 von 0 4 voff 0 1 Sw vcsp model s2bmod ron 1e 5 roff 0 1 von 0 1 voff 0 4 ESG LDRAIN DRAIN c ca n12 n8 0 6e 10 5 c cb n15 n14 1 1e 10 1 miei c cin n6 n8 0 75e 10 RLDRAIN RSLC1 dp dbody n5 n7 model dbodymod RSLC2 5 dp dbreak n7 n11 model dbreakmod scc EBREAK cm dp dplcap n10 n6 model dplcapmod 30 P tit n8 n17 1 DPLCAP HERUM DBODY EVTHRES Lidrain n2 n5 1e 9 Cente EVTEMP 2 P MWEAK I lgate n1 n9 0 47e 9 GATE RGATE _ ess 59 l source n3 n7 0 47e 9 10 rr MAE 8 MMED I BREAK RLGATE MSTROJ m mmed n16 n6 n8 n8 model mmedmod l 1u w 1u LSOURCE m mstrong n16 n6 n8 n8 model mstrongmod l 1u w 1u en 8 RSOURCE ET SOURCE m mweak n16 n21 n8 n8 model mweakmod l 1u w 1u RLSOURCE res rbreak n17 n18 1 tcl 5 5e 4 tc2 1e 7 S1A 0 S2A res rdrain n50 n16 280e 3 tc1 2 8e 3 tc2 4 9e 6 12 13 14 s MEAN 18 res rgate n9 n20 12 4 1 res rldrain n2 n5 10 SIET al S RVTEMP CB CA res rlgate n1 n9 4 7 14 4 IT res rlsource n3 n7 4 7 BE res rsic1 n5 n51 16 6 tc1 3 7e 3 tc2 7 8e 6 EGS 2 evs 2 VBAT res rsic2 n5 n50 1e3 gt res rsource n8 n7 190e 3 tc1 3e 3 tc2 5 2e 6 8 22 res rvtemp n18 n19 1 tcl 5 5e 4 tc2 1e 9 R
Download Pdf Manuals
Related Search
FAIRCHILD FDG6318PZ Dual P Channel Digital FET handbook