Home

FAIRCHILD FDD2582 N-Channel PowerTrench MOSFET 150V 21A 66mOhm handbook

1. Typical Characteristics To 25 unless otherwise noted 100 C IfRz0 LE tay L Iag 1 3 RATED BVpss Vpp T 0 oe L R In las R 1 3 RATED BVpss Vpp 1 a 2 4 7 tc S 175 N zy c 10 gt t z V 10 STARTING 25 85110 5 o OPERATION IN THIS shims 9 t N ST 5 LIMITED BY SaL TDS ON lt 5 SINGLE PULSE 5 Ty MAX RATED Te 25 C 0 1 1 Log piiit 1 1 10 100 300 0 001 0 01 0 1 1 10 Vps DRAIN TO SOURCE VOLTAGE V tay TIME IN AVALANCHE ms Figure 5 Forward Bias Safe Operating Area NOTE Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6 Unclamped Inductive Switching Capability 50 50 PULSE DURATION 8005 Ves 10V DUTY CYCLE 0 5 MAX 40 Vppz 15V 40 PULSE DURATION 80us Ves 7V 4 amp DUTY CYCLE 0 5 To 25 C c 30 30 E Ty 175 C x o o z lt 20 lt 20 tc za oc a A T 25 55 2 4 10 10 0 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 7 0 0 1 2 3 4 5 Ves GATE TO SOURCE VOLTAGE V Vps DRAIN TO SOURCE VOLTAGE V Figure 7 Transfer Characteristics Figure
2. FAIRCHILD September 2002 Ea SEMICONDUCTOR FDD2582 N Channel PowerTrench MOSFET 150V 21A 66 Features Applications DS ON 58mQ Typ Ves 10V lp 7A DC DC converters and Off Line UPS Qg tot 19nC Vas 10V Distributed Power Architectures and VRMs Low Miller Charge Low Qrr Body Diode UIS Capability Single Pulse and Repetitive Pulse Qualified to AEC 0101 Direct Injection Diesel Injection System Primary Switch for 24V and 48V Systems High Voltage Synchronous Rectifier Formerly developmental type 82855 42V Automotive Load Control Electronic Valve Train System DRAIN FLANGE GATE SOUR CE 252 FDD SERIES MOSFET Maximum Ratings 1 25 unless otherwise noted Symbol Parameter Ratings Voss Drain to Source Voltage 150 Gate to Source Voltage 320 Continuous Tc 25 Veg 10V 21 Continuous 100 C Veg 10V 15 Continuous 25 C Veg 10V Roya 529C W 3 7 Pulsed Figure 4 Single Pulse Avalanche Energy Note 1 59 Power dissipation 95 Derate above 25 C 0 63 Ty Tstg Operating and Storage Temperature 55 to 175 Thermal Characteristics ReJc Thermal Resistance Junction to Case TO 252 C W Rosa Thermal Resistance Junction to Ambient TO 252 C W Rosa Thermal Resistance Junction to Ambient TO 252 1in copper pad area 52 C W This product has been designed to m
3. odd Vas 0V pF Cnss Reverse Transfer Capacitance 5 pF QgtoT Total Gate Charge at 10V Ves OV to 10V 25 nC Qg TH Threshold Gate Charge Vas 0V to2V v 75V 3 2 nC Qgs Gate to Source Gate Charge lp 7 nC Gate Charge Threshold to Plateau lg 1 0mA nC Gate to Drain Miller Charge nC Resistive Switching Characteristics Vas 10 ton Turn On Time 41 ns la oN Turn On Delay Time ns n Rise Time Vpp 75V lp 7A E ns ta OFF Turn Off Delay Time Ves 10V Res 160 ns ty Fall Time ns torr Turn Off Time 77 ns Drain Source Diode Characteristics V Source to Drain Diode Voltage isp 7 1 1 5 9 Isp 4A 1 0 V tr Reverse Recovery Time Isp 7A digp dt 100A us 67 ns QRR Reverse Recovered Charge Isp 7A digp dt 100A us 134 nC 2002 Fairchild Semiconductor Corporation FDD2582 Rev B cgscadd Typical Charact
4. In using surface mount devices such as the TO 252 package the environment in which it is applied will have a significant influence on the part s current and maximum power dissipation ratings Precise determination of Ppp is complex and influenced by many factors 1 Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board 2 The number of copper layers and the thickness of the board The use of external heat sinks The use of thermal vias Air flow and board orientation A For non steady state applications the pulse width the duty cycle and the transient thermal response of the part the board and the environment they are in Fairchild provides thermal information to assist the designer s preliminary application evaluation Figure 21 defines the for the device as a function of the top copper component side area This is for a horizontally positioned FR 4 board with 102 copper after 1000 seconds of steady state power with no air flow This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation
5. Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 37e 3 8 22 Rgate 9 20 1 8 RVTHRES RSLC1 5 51 RSLCMOD 1 0e 6 RSLC2 5 50 1 0e3 Rsource 8 7 RsourceMOD 11 9 3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 6 12 13 8 S1TAMOD Sib 13 12 13 8 S1TBMOD 52 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 42 2 5 MODEL DbodyMOD D IS 2 3E 12 RS 5 3e 3 TRS1 2 2e 3 TRS2 4 5e 7 CJO 8 8e 10 M 0 64 TT 3 8e 8 4 2 MODEL DbreakMOD D RS 0 4 TRS1 1 4e 3 TRS2 5e 5 MODEL DplcapMOD D CJO 2 75e 10 IS 1 0e 30 N 10 M 0 67 MODEL MmedMOD NMOS 3 76 2 7 5 1 30 N 10 TOX 1 L 1u W 1u RG 1 64 MODEL MstroMOD NMOS VTO 4 25 30 IS 1e 30 10 TOX 1 L 1u W 1u MODEL MweakMOD NMOS VTO 3 2 KP 0 068 IS 1e 30 N 10 TOX 1 L 1u W 1u RG 16 4 RS 0 1 MODEL RbreakMOD RES 1 1 1 3 2 1 1 8 MODEL RdrainMOD RES 1 1 0 2 2 2 5 MODEL RSLCMOD RES 1 2 7 3 2 2 0 6 MODEL RsourceMOD RES 1 1 0 3 2 1 0 6 MODEL RvthresMOD RES TC1 3 9e 3 2 1 7 5 MODEL RvtempMOD RES TC1 3 7e 3 TC2 1 9e 6 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH ENDS Wheatley RON 1e 5 ROFF 0 1 VON 5 0 VOFF 2 0 RON 1e 5 ROFF 0 1 VON 2 0 VOFF 5 0 RON 1e 5 ROFF 0 1 VON 0 4 VOFF 0 3 RON 1e 5 ROFF 0 1 VON 0 3 VOFF 0
6. 2 or 3 Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square The area in square inches or square centimeters is the top copper area including the gate and source pads 23 84 Area in Inches Squared 154 Rota 33 32 1 73 Area EQ 3 Area in Centimeters Squared 125 Roua 33 324 23 84 0 268 A e Resa 33 32 154 1 73 Area EQ 3 2 Rosa C W N 50 25 0 01 0 0645 Figure 21 Thermal Resistance vs Mounting 0 1 1 0 645 6 45 AREA TOP COPPER AREA ir cm Pad Area 10 64 5 2002 Fairchild Semiconductor Corporation FDD2582 Rev B c8Scadd PSPICE Electrical Model SUBCKT FDD2582 213 rev July 2002 Ca 12 8 4e 10 Cb 15 14 4 6e 10 Cin 6 8 1 24e 9 DPLCAP 5 LDRAIN DES Dbody 7 5 DbodyMOD 10 AMYN Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 1 DBREAK 5 RSLC2 d Ebreak 11 7 17 18 160 4 ESLC 11 Eds 148581 50 Egs 138681 Esg 6 10681 E Evthres 6 21 198 1 Evtemp 20 6 18 22 1 DBODY It 8 17 1 I Lgate 1 9 4 88e 9 REGATE Ldrain 2 5 1 0e 9 CIN Lsource 3 7 2 24e 9 LSOURCE 8 Eo SOURCE RSOURCE RLgate 1 9 48 8 RLSOURCE RLdrain 2 5 10 12 RBREAK RLsource 3 7 22 4 4 17 18 Mmed 16 6 8 8 MmedMOD Mstro 16 6 88 MstroMOD CA
7. 4 Note For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank 2002 Fairchild Semiconductor Corporation FDD2582 Rev B cgscadd SABER Electrical Model REV July 2002 ttemplate FDD2582 n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod dp model dbreakmod rs 0 4 trs1 1 4e 3 trs2 5 0e 5 dp model dplcapmod cjo 2 75e 10 isl 10 0e 30 nl 10 m 0 67 m model mmedmod type _n vto 3 76 kp 2 7 is 1e 30 tox 1 m model mstrongmod type _n vto 4 25 kp 30 is 1e 30 tox 1 m model mweakmod type _n vto 3 2 kp 0 068 is 1 e 30 tox 1 rs 0 1 Sw vcsp model s1amod ron 1e 5 roff 0 1 von 5 0 voff 2 0 sw vcsp model 1 ron 1e 5 roff 0 1 von 2 0 voff 5 0 5 Sw vcsp model s2amod ron 1e 5 roff 0 1 von 0 4 voff 0 3 sw_vcsp model s2bmod ron 1e 5 roff 0 1 von 0 3 voff 0 4 10 c ca n12 n8 4e 10 RSLC1 c cb n15 n14 4 6e 10 51 c cin n6 n8 1 24e 9 RSLC2 dp dbody n7 n5 model dbodymod dp dbreak n5 n11 model dbreakmod p dp dplcap n10 n5 model dplcapmod 50 EVTHRES OT I 3MSTRO Spe ebreak n11 n7 n17 n18 160 4 Spe eds n14 n8 n5 n8 1 Spe egs n13 n8 n6 n8 1 Spe esg n6 n10 n6 n8 1 Spe evthres n6 n21 n19 n8 1 spe evtemp 20 n6 n18 22 1 LGATE GAT
8. 8 Saturation Characteristics 9 3 0 E PULSE DURATION 8035 PULSE DURATION 8015 DUTY CYCLE 0 5 MAX DUTY CYCLE 0 5 Z 80 5 95 E B wy E Pg tr Vos 6V 2520 in 5 u T5 8 E 60 Vgs 10V d tc z oO 10 5 2 Vas 10V Ip 21 50 0 5 0 5 10 15 20 25 80 40 0 40 80 120 160 200 Ip DRAIN CURRENT Ty JUNCTION TEMPERATURE C Figure 9 Drain to Source On Resistance vs Drain Figure 10 Normalized Drain to Source On Current Resistance vs Junction Temperature 2002 Fairchild Semiconductor Corporation FDD2582 Rev B c8Scadd Typical Characteristics To 25 unless otherwise noted Ty JUNCTION TEMPERATURE C Figure 11 Normalized Gate Threshold Voltage vs Junction Temperature 1 2 1 2 Vas Vps lp 250A w Ip 2504A 5 1 0 9 9 lt E oh e x 14 9 25 ul 42 da 08 az ao a9 Eo 58 Na g 1 0 T to F 0 6 gm z 0 4 0 9 80 40 0 40 80 120 160 200 80 40 0 40 80 120 Ty JUNCTION TEMPERATURE C Figure 12 Normalized Drain to Source Breakdown Voltage vs Junction Temperature 160 200 Voltage Gate Currents 2000 10 Vpp 75V 1000 Ciss Co
9. 82 CTHERM TH 6 1 6e 3 CTHERMe 6 5 4 5e 3 CTHERMS 5 4 5 0e 3 CTHERM4 4 3 8 0e 3 CTHERMS 3 2 8 2e 3 CTHERM6 2 TL 4 7e 2 RTHERM 1 6 3 3e 2 RTHERM2 6 5 7 9e 2 RTHERMS 5 4 9 5e 2 RTHERMA 4 3 1 4 1 RTHERMS 3 2 2 9e 1 RTHERM6 2 TL 6 7 1 SABER Thermal Model SABER thermal model FDD2582 template thermal model th tl thermal c th tl ctherm ctherm1 th 6 1 6 3 ctherm ctherm2 6 5 4 5 3 ctherm ctherm3 5 4 5 0e 3 ctherm ctherm4 4 3 8 0 3 ctherm ctherm5 3 2 8 2e 3 ctherm ctherm6 2 tl 24 7e 2 rrtherm rtherm1 th 6 3 3e 2 rtherm rtherm2 6 5 7 9e 2 rtherm rtherm3 5 4 9 5e 2 rtherm rtherm4 4 3 1 4e 1 rtherm rtherm5 3 2 2 9e 1 rtherm rtherm6 2 tl 6 7e 1 RTHERM1 RTHERM2 RTHERM3 RTHERM4 5 RTHERM6 th JUNCTION CTHERM1 CTHERM2 CTHERM3 CTHERM4 5 CTHERM6 2002 Fairchild Semiconductor Corporation FDD2582 Rev B c8Scadd TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx FACT ImpliedDisconnect PACMAN SPM ActiveArray FACT Quiet Series ISOPLANAR POP Stealth Bottomless FAST LittleFET Power247 SuperSOT 3 CoolFET FASTr MicroFET PowerTrench SuperSOT 6 CROSSVOLT FRFET MicroPak QFET SuperSOT 8 DOME GlobalOptoisolator MICRO
10. E PE RLGATE i it n8 n17 1 l gate n1 n9 4 88e 9 I Idrain n2 n5 1 0e 9 l source n3 n7 2 24e 9 res rlgate n1 n9 48 8 res rldrain n2 n5 10 res rlsource n3 n7 22 4 CA m mmed n16 n6 n8 n8 model mmedmod l 1u w 1u m mstrong n16 n6 n8 n8 model mstrongmod 1 w 1u m mweak n16 n21 n8 n8 model mweakmod 1 1 w 1u res rbreak n17 n18 1 1 1 3 2 1 1 8 res rdrain n50 n16 37e 3 tc1 1 0e 2 tc2 2 6e 5 res rgate n9 n20 1 8 res rsic1 n5 n51 1 0e 6 tc1 2 7e 3 tc2 2 0e 6 res rsic2 n5 n50 1 0e3 res rsource n8 n7 11 9e 3 tc1 1 0e 3 tc2 1 0e 6 res rvthres n22 n8 1 tc1 3 9e 3 tc2 1 7e 5 res rvtemp n18 n19 1 1 3 7 3 1 2 1 9 6 sw vcsp s a n6 n12 n13 n8 model stamod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 2n50 iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 42 2 5 isl 2 3e 12 rs 5 3e 3 trs 1 2 2e 3 trs2 4 5e 7 cjo 8 8e 10 m 0 64 tt 3 8e 8 xti 4 2 Y DBREAK RDRAIN 11 MWEAK MMED EBREAK qz RSOURCE RBREAK 17 RVTHRES LDRAIN DRAIN SLE RLDRAIN DBODY LSOURCE SOURCE Ett RLSOURCE 18 RVTEMP 19 22 2002 Fairchild Semiconductor Corporation FDD2582 Rev B c8Scadad SPICE Thermal Model REV 19 July 2002 FDD25
11. WIRE Qs SyncFET EcoSPARK GTO MSX QT Optoelectronics TinyLogic E CMOS MSXPro Quiet Series TruTranslation EnSigna OCX RapidConfigure UHC Across the board Around the world OCXPro RapidConnect UltraFET The Power Franchise V OPTOLOGIC SILENT SWITCHER VCX Programmable Active Droop OPTOPLANAR SMART START DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTENAPPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into support device or system whose failure to perform can the body or b support or sustain life or c whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling
12. can be effectiveness reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms Advance Information Formative or This datasheet contains the design specifications for In Design product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only
13. eet the extreme test conditions and environment demanded by the automotive industry Fora copy of the requirements see AEC Q101 at http www aecouncil com Reliability data can be found at http www fairchildsemi com products discrete reliability index html All Fairchild Semiconductor products are manufactured assembled and tested under ISO9000 and QS9000 quality systems certification 2002 Fairchild Semiconductor Corporation FDD2582 Rev B c8Scadd Package Marking and Ordering Information Notes 1 Starting Ty 25 C L 1 17 mH las 10A Device Marking Tape Width Quantity FDD2582 FDD2582 TO 252AA 2500 units Electrical Characteristics 1 25 unless otherwise noted Symbol Parameter Test Conditions Max Units Off Characteristics Bypss Drain to Source Breakdown Voltage Ip 250A Vas OV x V Zero Gate Voltage Drain Current soe DSS Ves OV Tc 150 C 250 less Gate to Source Leakage Current Vas 220V 100 nA On Characteristics Gate to Source Threshold Voltage Vas lp 250 4 V lp 7A Veg 10V 0 066 DS ON Drain to Source On Resistance Ip 4 Ves 0999 d Ip 7A Veg 10V 0 172 Tc 175 C Dynamic Characteristics Ciss Input Capacitance pF Coss Output Capacitance
14. eristics To 25 unless otherwise noted 12 25 Ves 10V 1 0 ui 20 2 a 08 gt 15 z 5 5 10 o 04 E a 0 2 5 5 0 0 0 25 50 05 100 125 150 75 25 50 75 100 125 150 175 Tc CASE TEMPERATURE Tc CASE TEMPERATURE C Figure 1 Normalized Power Dissipation vs Figure 2 Maximum Continuous Drain Current vs Ambient Temperature Case Temperature 2 T DUTY CYCLE DESCENDING ORDER 1 0 5 0 2 0 1 0 05 82 0 02 5a 0 01 2 04 s 9 t gt n SINGLE PULSE DUTY FACTOR D t4 t PEAK T Ppy X Zouc X Rouc Tc 0 01 1 1 1 LJIJIILII 1 1 RE 80 86 20 105 104 103 102 107 109 10 t RECTANGULAR PULSE DURATION s Figure 3 Normalized Maximum Transient Thermal Impedance i ve III d TRANSCONDUCTANCE 2536 MAY LIMIT CURRENT FOR TEMPERATURES Ly T IN THIS REGION ABOVE 25 C DERATE PEAK CURRENT AS FOLLOWS z N 121 175 100 25 150 a Ves 10V x lt 20 105 104 103 102 1071 100 10 t PULSE WIDTH s Figure 4 Peak Current Capability 2002 Fairchild Semiconductor Corporation FDD2582 Rev B c8Scadd
15. s Cap 5 E H Cps Cap e o Mog z 5 5 Crss 9 9 __ Cnss amp 100 O 4 lt 5 o WAVEFORMS IN 2 DESCENDING ORDER 7 gt Ip 21A Vas OV f 1 2 lp 7A 10 0 1 1 10 150 0 10 15 20 Vps DRAIN TO SOURCE VOLTAGE V Qy GATE CHARGE nC Figure 13 Capacitance vs Drain to Source Figure 14 Gate Charge Waveforms for Constant 2002 Fairchild Semiconductor Corporation FDD2582 Rev B cgscadd Test Circuits Waveforms VARY tp TO OBTAIN REQUIRED PEAK las Ves ov lg REF Ves Figure 19 Switching Time Test Circuit BVpss lg REF 0 Figure 18 Gate Charge Waveforms ton torr ta orF Ves 50 46 PULSE WIDTH Figure 20 Switching Time Waveforms 2002 Fairchild Semiconductor Corporation FDD2582 Rev B c8Scadad Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation in an application Therefore the application s ambient temperature C and thermal resistance Rey C W must be reviewed to ensure that T jy is never exceeded Equation 1 mathematically represents the relationship and Serves as the basis for establishing the rating of the part T ju Pp 1

FAIRCHILD FDD2582 N-Channel PowerTrench MOSFET 150V 21A 66mOhm handbook

Contents

Download Pdf Manuals

Related Search

Related Contents