FAIRCHILD FDD3672 Manual
Contents
1. t PULSE WIDTH s Figure 4 Peak Current Capability 2 en Soe ILL DUTY CYCLE DESCENDING ORDER 1 0 2 0 1 0 05 0 02 LU ao 0 01 E y du Ia z 04 23 sE El ti lt E NOTES SINGLE PULSE DUTY FACTOR D tte PEAK Ty Ppm X Zouc X Rouc To 0 01 i LILLLI LL UII 105 104 10 107 10 10 10 t RECTANGULAR PULSE DURATION s Figure 3 Normalized Maximum Transient Thermal Impedance 500 TITTI TT LI TRANSCONDUCTANCE To 25 C sl L MAY LIMIT CURRENT FOR TEMPERATURES Pertti IN THIS REGION ABOVE 25 C DERATE PEAK NI CURRENT AS FOLLOWS T S 175 T E Vas 10V Webs jee z GS 150 D 5 100 x lt q UI a 30 105 107 10 107 107 100 10 2010 Fairchild Semiconductor Corporation FDD3672 Rev A2 CL9 004 300 o o las AVALANCHE CURRENT A o WAZOO i ni tav L Iag 1 3 RATED BVoss Von TTT TTT R 0 tav L R In las R 1 3 RATED BVpss Vpp 1 HHHH HHHH STARTING T 25 C 0 001 0 01 0 1 1 10 tav TIME IN AVALANCHE ms NOTE Refer to Fairchild Application Notes AN7514 and AN7515 Figure2. 2010 Fairchild Semiconductor Corporation FDD3672 Rev A2 cL9 004 SABER Electrical Model REV May 2002 template FDD3672 n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod dp model dbreakmod rs 15 trs1 4 0e 3 trs2 5 0e 6 dp model dplcapmod cjo 3 8e 10 isl 10 0e 30 nl 10 m 0 60 m model mmedmod type _n vto 3 6 kp 3 is 1e 40 tox 1 m model mstrongmod type _n vto 4 3 kp 59 is 1e 30 tox 1 m model mweakmod type _n vto 3 09 kp 0 05 is 1e 30 tox 1 S BA cap sw_vcsp model stamod ron 1e 5 roff 0 1 von 5 0 voff 3 5 5 sw_vesp model stbmod ron 1e 5 roff 0 1 von 3 5 voff 5 0 10 sw_vcsp model s2amod ron 1e 5 roff 0 1 von 0 5 voff 0 3 SW vesp model s2bmod ron 1e 5 roff 0 1 von 0 3 voff 0 5 51 c ca n12 n8 5 8e 10 RSLC2 c cb n15 n14 6 8e 10 c cin n6 n8 1 6e 9 50 EVTHRES a 5 10 dp dbody n7 n5 model dbodymod dp dbreak n5 n11 model dbreakmod dp dplcap n10 n5 model dplcapmod LGATE Geng spe ebreak n11 n7 n17 n18 105 GATE We 18 spe eds n14 n8 n5 n8 1 i ne 9 20 spe egs n13 n8 n6 n8 1 RLGATE i spe esg n6 n10 n6 n8 1 CIN spe evthres n6 n21 n19 n8 1 8 spe evtemp n20 n6 n18 n22 1 MSTRO iitn8n17 1 ligate n1 n9 95 6e 9 8 I ldrain n2 n5 1 0e 9 l lsource n3 n7 4 45e 9 13 CA res rlgate n1 n9 9 56 res rldrain n2 n5 10 res rlsource n3 n7 44 5 S m mmed n16 n6 n8 n8 model mmedmod l 1u w 1u m mstrong n16 n6 n
3. 3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 Sta 6 12 13 8 SIAMOD Sib 13 12 13 8 SIBMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 98 3 MODEL DbodyMOD D IS 1 0E 11 N 1 05 RS 3 7e 3 TRS1 2 5e 3 TRS2 1 0e 6 CJO 1 2e 9 M 0 58 TT 3 75e 8 XT1 4 0 MODEL DbreakMOD D RS 15 TRS1 4 0e 3 TRS2 5 0e 6 MODEL DplcapMOD D CJO 3 8e 10 IS 1 0e 30 N 10 M 0 60 MODEL MmedMOD NMOS VTO 3 6 KP 3 IS 1e 40 N 10 TOX 1 L 1u W 1u RG 1 5 MODEL MstroMOD NMOS VTO 4 3 KP 59 IS 1e 30 N 10 TOX 1 L 1u W 1u MODEL MweakMOD NMOS VTO 3 09 KP 0 05 IS 1e 30 N 10 TOX 1 L 1u W 1u RG 15 RS 0 1 MODEL RbreakMOD RES TC1 9 0e 4 TC2 1 0e 7 MODEL RdrainMOD RES TC1 11 0e 3 TC2 5 0e 5 MODEL RSLCMOD RES TC1 3 0e 3 TC2 1 0e 6 MODEL RsourceMOD RES TC1 4 0e 3 TC2 1 0e 6 MODEL RvthresMOD RES TC1 3 5e 3 TC2 1 5e 5 MODEL RvtempMOD RES TC1 4 3e 3 TC2 1 5e 6 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 5 0 VOFF 3 5 RON 1e 5 ROFF 0 1 VON 3 5 VOFF 5 0 RON 1e 5 ROFF 0 1 VON 0 5 VOFF 0 3 RON 1e 5 ROFF 0 1 VON 0 3 VOFF 0 5 ENDS Note For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley
4. 5 Unclamped Inductive Switching Capability 80 _ 60 x E Z LU E T 40 S PULSE DURATION 80us a DUTY CYCLE 0 5 MAX a a 32 Ves 0 0 0 5 1 0 1 5 2 0 2 5 3 0 Vps DRAIN TO SOURCE VOLTAGE V Figure 7 Saturation Characteristics 2 5 PULSE DURATION 80us w DUTY CYCLE 0 5 MAX O E 20 e 9 wu es z Es 15 o a D z N 5 e lt 1 0 a o z Vas 10V Ip 44A 0 5 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C Figure 9 Normalized Drain to Source On Resistance vs Junction Temperature Typical Characteristics T 25 C unless otherwise noted 80 PULSE DURATION 80us DUTY CYCLE 0 5 MAX Vpp 15V 60 40 20 Ip DRAIN CURRENT A 3 5 40 Figure 6 Transfer Characteristics Ty 55 C 4 0 4 5 5 0 5 5 6 0 6 5 Vas GATE TO SOURCE VOLTAGE V 35 PULSE DURATION 80us DUTY CYCLE 0 5 MAX Vas 6V 30 25 10V 20 DRAIN TO SOURCE ON RESISTANCE m 9 Figure 8 Drain to Source On Resistance vs Drain 1 2 1 0 0 8 0 6 NORMALIZED GATE THRESHOLD VOLTAGE Figure 10 Normalized Gate Threshold Voltage vs 10 20 30 40 50 Ip DRAIN CURRENT A Current 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C Junction Temperature 2010 Fairchild Semicondu
5. are genuine parts have full traceability meet Fairchild s quality standards for handing and storage and provide access to Fairchild s full range of up to date technical and product information Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors PRODUCT STATUS DEFINITIONS Definition of Terms Product Status Definition Datasheet contains the design specifications for product development Specifications may change in any manner without notice Datasheet Identification Advance Information Formative In Design Datasheet contains preliminary data supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without Preliminary First Production notice to improve design Datasheet contains final specifications Fairchild Semiconductor reserves the right to Full Production make changes at any time without notice to improve the design No Identification Needed Datasheet contains specifications on a product that is discontinued by Fairchild Obsolete Not In Production Semiconductor The dat
6. thermal model th tl thermal c th tl cctherm ctherm1 th 6 3 2e 3 ctherm ctherm2 6 5 3 3e 3 ctherm ctherm3 5 4 3 4e 3 ctherm ctherm4 4 3 3 5e 3 ctherm ctherm5 3 2 6 4e 3 ctherm ctherm6 2 tl 1 9e 2 rtherm rtherm1 th 6 5 5e 4 rtherm rtherm2 6 5 5 0e 3 rtherm rtherm3 5 4 4 5e 2 rtherm rtherm4 4 3 10 5e 2 rtherm rtherm5 3 2 3 4e 1 rtherm rtherm6 2 tl 3 5e 1 RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERM5 RTHERM6 th JUNCTION CTHERM1 CTHERM2 CTHERM3 CTHERM4 CTHERM5 CTHERM6 2010 Fairchild Semiconductor Corporation FDD3672 Rev A2 cL9 004 arse esame FAIRCHILD FER SS SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such trademarks AccuPower FRFET PowerTrench The Power Franchise Auto SPM Global Power ResourceSM PowerXSTM o Build it Now Green FPS Programmable Active Droop CorePLUSTM Green FPS e Series QFE franchise CorePOWER Gmax QSTM Cen CROSSVOLT GTOTM Quiet Series TM Hi CR CTL IntelliMAX RapidConfigure TinyLogic Current Transfer Logic ISOPLANARTM TM T DEUXPEEDS MegaBuck CH TINYOPTO Dual Cool MICROCOUPLER Saving our world 1mW W kW at a time LL eae EcoSPARK MicroFET SignalWise TRANI v
7. 8 n8 model mstrongmod l 1u w 1u m mweak n16 n21 n8 n8 model mweakmod l 1u w 1u res rbreak n17 n18 1 tc1 9 0e 4 tc2 1 0e 7 res rdrain n50 n16 6 0e 3 tc1 11 0e 3 tc2 5 0e 5 res rgate n9 n20 1 5 res rsici n5 n51 1 0e 6 tc1 3 0e 3 tc2 1 0e 6 res rsic2 n5 n50 1 063 res rsource n8 n7 9 5e 3 tc1 4 0e 3 tc2 1 0e 6 res rvthres n22 n8 1 tc1 3 5e 3 tc2 1 5e 5 res rvtemp n18 n19 1 tc1 4 3e 3 tc2 1 5e 6 sw_vcsp s1a n6 n12 n13 n8 model stamod sw_vesp s1b n13 n12 n13 n8 model s1bmod sw_vesp s2a n6 n15 n14 n13 model s2amod sw_vesp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 gt n50 iscl iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 98 3 isl 1 0e 11 nl 1 05 rs 3 7e 3 trs1 2 5e 3 trs2 1 0e 6 cjo 1 2e 9 m 0 58 tt 3 75e 8 xti 4 0 6 ili Geen EBREAK LDRAIN DRAIN Se E RLDRAIN DBREAK 11 DBODY MWEAK 6 LSOURCE a SOURCE emo RLSOURCE RSOURCE RBREAK 17 18 RVTEMP 19 22 RVTHRES 2010 Fairchild Semiconductor Corporation FDD3672 Rev A2 cL9 004 SPICE Thermal Model REV May 2002 FDD3672 CTHERM1 TH 6 3 2e 3 CTHERM2 6 5 3 3e 3 CTHERMS 5 4 3 4e 3 CTHERM4 4 3 3 5e 3 CTHERMS 3 2 6 4e 3 CTHERM6 2 TL 1 9e 2 RTHERM1 TH 6 5 5e 4 RTHERM2 6 5 5 0e 3 RTHERM3 5 4 4 5e 2 RTHERM4 4 3 10 5e 2 RTHERMS 3 2 3 4e 1 RTHERM6 2 TL 3 5e 1 SABER Thermal Model SABER thermal model FDD3672 template
8. EfficentMaxTM MicroPakTM SmartMax TinyWire ul MicroPak2 SMART START TriFault Detect FP MillerDriveTM SPM2 Rei alla Fairchild MotionMax STEALTH uSerDes Fairchild Semiconductor Motion SPMTM SuperFET ZZ FACT Quiet Series OptiHiT SuperSOT 3 aides FAC OPTOLOGIC SuperSOT 6 UHC FAST OPTOPLANAR SuperSOT 8 Ultra FRFET FastvCore SupreMOS UniFETTM FETBench SyncFET VOXTM FlashWriter PDP SPMTM Sync Lock STEE FES Power SPM SYSTEM ag GENERAL Trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are 2 A critical component in any
9. I FAIRCHILD March 2010 ese a a 1 SEMICONDUCTOR FDD3672 N Channel UltraFET Trench MOSFET 100V 44A 28mQ Features Applications TDs ON 24MQ Typ Vag 10V Ip 44A e DC DC converters and Off Line UPS Qg tot 24nC Typ Vas 10V e Distributed Power Architectures and VRMs Low Miller Charge Low Qrr Body Diode e Primary Switch for 24V and 48V Systems SR SCH High Voltage Synchronous Rectifier Optimized efficiency at high frequencies UIS Capability Single Pulse and Repetitive Pulse Formerly developmental type 82760 DRAIN FLANGE GATE SOURCE TO 252AA MOSFET Maximum Ratings 1 25 C unless otherwise noted Symbol Parameter Ratings Voss Drain to Source Voltage 100 Gate to Source Voltage 120 Drain Current Continuous Tc 25 C Veg 10V 44 Continuous Tc 100 C Veg 10V 31 Continuous Tamb 25 C Veg 10V Roya 52 C W 6 5 Pulsed Figure 4 Single Pulse Avalanche Energy Note 1 120 Power dissipation 135 Derate above 25 C 0 9 Ty TsrG Operating and Storage Temperature 55 to 175 Thermal Characteristics Rec Thermal Resistance Junction to Case TO 252 Roya Thermal Resistance Junction to Ambient TO 252 Roa Thermal Resistance Junction to Ambient TO 252 1in copper pad area 52 Reliability data can be found at http www fairchildsemi com products discrete reliability index html All Fairchild Semiconductor p
10. acteristics Vas 10V ton Turn On Time 104 ns ta ON Turn On Delay Time 11 S ns t Rise Time Vpp 50V Ip 44A 59 ns ta OFF Turn Off Delay Time Vas 10V Reg 11 02 26 ns ti Fall Time S 44 S ns torr Turn Off Time 104 ns Drain Source Diode Characteristics g d Isp 44A 1 25 V V Source to Drain Diode Voltage SD E Isp 21A to V tr Reverse Recovery Time Isp 44A dlgp dt 100A us F 52 ns QRR Reverse Recovery Charge Isp 44A dlgp dt 100A us E 80 nc Notes 1 Starting Ty 25 C L 0 6mH las 20A 2 Pulse Width 100s 2010 Fairchild Semiconductor Corporation FDD3672 Rev A2 GL9 004 Typical Characteristics To 25 C unless otherwise noted 12 Tc CASE TEMPERATURE C Figure 1 Normalized Power Dissipation vs Ambient Temperature 30 Vas 10V 10 Li 40 ll z 5 lt 5 08 730 Ki D O 06 T lt o S z 20 n 04 lt a d Li a 0 2 10 a 0 0 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 Tc CASE TEMPERATURE C Case Temperature Figure 2 Maximum Continuous Drain Current vs
11. asheet is for reference information only Rev 147 2010 Fairchild Semiconductor Corporation
12. component of a life support device or intended for surgical implant into the body or b support or sustain life system whose failure to perform can be reasonably expected to cause and c whose failure to perform when properly used in accordance with the failure of the life support device or system or to affect its safety or instructions for use provided in the labeling can be reasonably effectiveness expected to result in a significant injury of the user ANTI COUNTERFEITING POLICY Fairchild Semiconductor Corporation s Anti Counterfeiting Policy Fairchild s Anti Counterfeiting Policy is also stated on our external website www Fairchildsemi com under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry All manufactures of semiconductor products are experiencing counterfeiting of their parts Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation substandard performance failed application and increased cost of production and manufacturing delays Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors
13. ctor Corporation FDD3672 Rev A2 cL9 004 1 2 Ip 2501A 1 1 1 0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 9 80 40 0 Breakdown Voltag 40 80 120 160 200 Ty JUNCTION TEMPERATURE C Figure 11 Normalized Drain to Source e vs Junction Temperature Vas GATE TO SOURCE VOLTAGE V WAVEFORMS IN DESCENDING ORDER AAA 10 15 20 25 Qu GATE CHARGE nC Figure 13 Gate Charge Waveforms for Constant Gate Currents C CAPACITANCE pF Ip DRAIN CURRENT A Typical Characteristics To 25 C unless otherwise noted 3000 1000 Ciss Cas Cap I fa Coss Cos Cap Crss Can 100 Ves OV f 1MHz 10 0 1 1 10 Figure 12 Capacitance vs Drain to Source Vps DRAIN TO SOURCE VOLTAGE V 100 Voltage 200 100 100 us THIS AREA IS gt SE LIMITED BY reien z d Iw SINGLE PULSE KA 1 ms Ty MAX RATED N Royo 1 11 C W SCT T 25 C a Dee c DC 0 1 LE LLL 1 10 100 300 Vps DRAIN to SOURCE VOLTAGE V Figure 14 Forward Bias Safe Operating Area 2010 Fairchild Semiconductor Corpo
14. de or both sides of the board 2 The number of copper layers and the thickness of the board The use of external heat sinks The use of thermal vias Air flow and board orientation O a A O For non steady state applications the pulse width the duty cycle and the transient thermal response of the part the board and the environment they are in Fairchild provides thermal information to assist the designer s preliminary application evaluation Figure 20 defines the Reja for the device as a function of the top copper component side area This is for a horizontally positioned FR 4 board with 10z copper after 1000 seconds of steady state power with no air flow This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2 or 3 Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square The area in square inches or square centimeters is the top copper area including the gate and source pads 23 84 Rot 33 32 S9t__ EQ 2 OJA 0 268 Area EQ Area in Inches Squared 154 Ra 33 32 _ EQ 3 8JA 1 73 Ar
15. ea Gee Area in Centimeters Squared Rosa C W 125 ita TTTTTI Roua 33 321 23 84 0 268 Area EQ 2 Porri horrid i0 Roya 33 324 154 1 73 Area EQ 3 75 50 25 0 01 0 1 1 10 0 0645 0 645 6 45 64 5 AREA TOP COPPER AREA in cm Figure 20 Thermal Resistance vs Mounting Pad Area 2010 Fairchild Semiconductor Corporation FDD3672 Rev A2 cL9 004 PSPICE Electrical Model SUBCKT FDD3672 2 1 3 rev May 2002 CA 12 85 8e 10 Cb 15 14 6 8e 10 LDRAIN Cin 6 8 1 6e 9 DPLCAP 5 Se DRAIN 02 Dbody 7 5 DbodyMOD 10 PER Dbreak 5 11 DbreakMOD RSLCI vena 51 Dplcap 10 5 Dplcap MOD RSLC2 Ebreak 11 7 17 18 105 ESLG 11 Eds 148581 50 Egs 138681 Esg 610681 gan RDRAIN con C DBODY Evthres 6 21 1981 gt EVTHRES a 5 Evtemp 20 6 18 22 1 E S ARR LGATE EVTEMP eare reste je t8171 ve S GOMMER RLGATE I 5 Sg Wahl Lgate 1 9 9 56e 9 LSOURCE Ldrain 2 5 1 0e 9 CIN 8 SOURCE Lsource 3 7 4 45e 9 T DE o 3 RSOURCE RLSOURCE RLgate 1 9 95 6 j RLdrain 2 5 10 tree a a ge RBREAK RLsource 3 7 44 5 2 g 17 18 Mmed 16 6 8 8 MmedMOD S1B 9 9S2B RVTEMP Mstro 16 6 8 8 MstroMOD CA 13 CB ey 19 Mweak 16 21 8 8 MweakMOD VBAT EGS EDS Rbreak 17 18 RbreakMOD 1 D i Rdrain 50 16 RdrainMOD 6 0e 3 B 7 Rgate 9 20 1 5 RVTHRES RSLC1 5 51 RSLCMOD 1 0e 6 RSLC2 5 50 1 063 Rsource 8 7 RsourceMOD 9 5e
16. ration FDD3672 Rev A2 cL9 004 Test Circuits and Waveforms VARY tp TO OBTAIN REQUIRED PEAK lag Ves ov Jangen Ves Figure 18 Switching Time Test Circuit BVpss tp Vos H las di a a i Vop H in nn gt tay lt Von Le Damon gt Ig REF 0 Figure 17 Gate Charge Waveforms ton r gt tore ta OFF 50 PULSE WIDTH Figure 19 Switching Time Waveforms 2010 Fairchild Semiconductor Corporation FDD3672 Rev A2 cL9 004 Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature Tjm and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation Ppy in an application Therefore the application s ambient temperature TA C and thermal resistance Rey C W must be reviewed to ensure that Tyy is never exceeded Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part TT Pom na EQ 1 E In using surface mount devices such as the TO 252 package the environment in which it is applied will have a significant influence on the parts current and maximum power dissipation ratings Precise determination of Ppp is complex and influenced by many factors 1 Mounting pad area onto which the device is attached and whether there is copper on one si
17. roducts are manufactured assembled and tested under ISO9000 and QS9000 quality systems certification 2010 Fairchild Semiconductor Corporation FDD3672 Rev A2 cL9 004 Package Marking and Ordering Information Device Marking Tape Width Quantity FDD3672 FDD3672 TO 252AA 2500 units Electrical Characteristics 1 25 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics Bypss Drain to Source Breakdown Voltage Ip 250A Vas OV 100 S a V Vps 80V 1 l Zero Gate Voltage Drain Current DSS a Veg 0V To 150 C eee E less Gate to Source Leakage Current Veg 220V 100 nA On Characteristics Vasi Gate to Source Threshold Voltage Vas Vos b 250A 2 DA TV Ip 44A Veg 10V 0 024 0 028 DS oN Drain to Source On Resistance Ip 21A Vas 6V 0 031 0 047 Q Ip 44A Vag 10V Te 1750C 0 054 0 068 Dynamic Characteristics Ciss Input Capacitance S 1710 pF Coss Output Capacitance 2 Sc Vas 0V 247 2 pF Crss Reverse Transfer Capacitance 5 62 z pF Qg TOT Total Gate Charge at 10V Ves OV to 10V 24 36 nc Qg TH Threshold Gate Charge Vas OV to 2V_ Vpp 50V 3 3 4 5 nc Qgs Gate to Source Gate Charge Ip 44A 8 6 nc Qgs2 Gate Charge Threshold to Plateau Ig 1 0mA 5 6 a nc Qga Gate to Drain Miller Charge 5 6 nc Resistive Switching Char
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FAIRCHILD FDD3672 Manual