FAIRCHILD PFCM Manual
Contents
1. 34 7 1 Fig 12 Schematic diagram of the implemented converter Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 15 FAIRCHILD SEMICONDUCTOR PFCM Design Guide Table 2 BOM of PFCM demo board C Ceramic 102 2012 C17 C18 C Ceramic 105 2012 1 15 19 24 25 44 5 6 183 2012 333 2012 C Elec 220uF 35V C ELEC 470uF 450V C FILM 105 630V Connector 7 pin 2 54mm pitch FAN connector 3 pin 2 54mm pitch Fuse 220V 20A Mosfet BSS138 Op Amp KA224 Opto coupler TLP181 PFCM FPDB30PH60 R Chip 1 2Kohm 1 8W J 2012 R40 R18 R Chip 1 8kohm 1 8W F 2012 SR6 R10 Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 16 FAIRCHILD SEMICONDUCTOR R Chip 100kohm 1 2W J 5025 R Chip 10Kohm 1 8W2. panas nana setas asm 6 Open Loop R SPpOnse 6 Current Loop Amplifier 5 7 Voltage Loop Amplifier 1 ano 7 Control Loop Implementation psa ate raa aec run 8 sl RE n 8 Voltage Loop u ul 9 Other Parameters e M 10 12 Over Voltage Protection 13 DC link Voltage Control 14 4 Experimental Results 15 Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 2 SSS FAIRCHILD SEMICONDUCTOR PFCM Design Guide 1 System Configurations Relay 7 a hnt Ju LA AAS s a a AN V WJ N F x Z YY SPM Ns 27 LVIC SENSE Control IC
3. u u u 2 o KIX bn e e A A II 11 lI s 8 S o 5 o x e Voltage Loop _ 419 f 5000 27f 0 001 380 5 Py SC our AV Gy A resistor Ryp is added between E A input and sensing resistor By virtue of large Rvp Cyr can be replaced by small SMD type capacitor 2120kQ Ry lt lt 120 gt Cye tuF fo 1 3Hz 1 ZAR bus fev FAIRCHILD SEMICONDUCTOR System Engineering Group Feb 2006 LIE Em FAIRCHILD ER SEMICONDUCTOR R Vdc VA C ve Ry Rvp EA V Rus ref EA out Fig 6 Voltage loop circuit Other Parameters Rr Switching frequency decision 0 6 f R C 15 kO C 1 nF gt F 40 kHz Ryo Refer to fig 4 Dc peak R 5042 0 002 jus 300x10 R MO 471 4700 Assuming the input current is 50 Vac 100 2 Ryo 470 O PFCM Design Guide Rsense 0 002 Q small resistance can cause distortions at low level current Rac amp Optocoupler circuit Optocuopler TLP180 Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 10 e FAIRCHILD SEMICONDUCTOR PFCM Design Guide VCC Optocoupler UCC3818 FF Fig 7 Input AC voltage sensing circuit Rax and R depend on optocoupler Vus max 2 _ 2710 42 T LINEAR _max 6x107 R 64 kQ AX gt 1841
4. Fig 1 Typical block diagram of PFCM system An inrush current prevention circuit is required due to the large DC link capacitance as shown in Fig 1 The relay of the circuit should be closed after DC link capacitor is charged far enough PFCM mini SPM and control IC can share single GND stage Usually this GND and the Nsense terminal of PFCM should have the same potential Large surge voltage is easily produced between P and N terminals by large current switching To reduce surge voltage it is important to shorten the DC link bus wiring between PFCM and DC link capacitor In addition good high frequency characteristic capacitor such as polypropylene film capacitor should be mounted near to P and N terminals as a snubber 2 Protection Circuits Following Fig 2 shows the timing chart of protection function There are two kind of protection level for both OCP and OVP Generally PFC control ICs have its own OCP and OVP function Also user can make the PFCM stop and output the FO signal under preset OC OV condition using its Csc input Over Current Protection OCP OCP Level1 PFCM PFCM can protect from over current situation When OC over current situation happens the PFCM stops operating and generates fault out signal during fault out duration time set by Crop And then after the duration it works again according to the input command Its total propagation delay time may depend on outer op amp speed We recommend using a low c
5. Vourpc Vin Lp_p JLVourpc Vourpc V 1 IN max 75A 3 L AI max Vourpc 380 207 20 40000 Current ripple is decided by switching frequency and inductance reduce current ripple high 475 fs 40kHz Switching frequency and large inductance value is required It means that employing higher switching frequency can reduce inductor size But the power losses will increase and it requires more efficient heat sink structure Open Loop Response vec w y J i 18 OVPIEN 10 4 18 V FOR UCC2817 ONLY 7 5V REFERENCE IH I ENABLE uno 16 V 10 V UCC2817 10 5 V 10 V UCC2818 ZERO POWER VOLTAGE ERROR AMP VSENSE CURRENT AMP 16 DRVOUT VFF MIRROR 2 1 AM ER uc e OSCILLATOR 2 PKLMT MOUT 5 lt usss a u RR Cac CAI CAOUT RT Fig 3 Block diagram of control Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 6 e FAIRCHILD SEMICONDUCTOR PFCM Design Guide The following is the block diagram of PFC controller ucc3818 The average current mode control is composed of two types of loops voltage loop and current loop The voltage loop controls the output DC Link voltage It
6. regulates the output voltage There is a 120 Hz ripple voltage in the output DC Link which is caused by the 60 Hz ac input current Hence the voltage loop must be designed to be slow enough to reject the 120 Hz ripple voltage In general CCM Continuous Current Mode PFC IC there is a multiplier It multiplies V the output of voltage loop by of input ac current shape and then divides it by Vgys reference of rms input voltage The output I yo Fac Fac RMS The difference between the voltage of pin output of the multiplier and the voltage of the current of a multiplier is the reference of the PFC s input current lAc sensing resister is amplified by the current loop The Vg4 output of the current loop is the reference voltage to the comparameter that generates the gating signal Current loop should be fast enough to catch up with the 120 Hz input ac current But too fast speed can distort the current shape due to the switching noise Therefore the current loop must be designed to be fast enough to catch up with the 120 Hz rectified input current but not too fast for switching noise immunity Current Loop Amplifier Eq 1 shows the open loop response of power stage Refer to UCC3818 datasheet 5 Voc Rs V nour 5 4sL where Vs Voltage of shunt resistor Gosr UCC3818 Eq 1 Viaout Voltage of Ryo DC link Voltage Shunt resistance fo
7. 8418 18 kQ 0 5 x 4 2W R PEAK 9 18 kQ Pi DONI R 390 Q Rez and an Ising off set compensation C 1 uF Rc O O Rc 150 O 1 4 V when input voltage Vac 90 Vac Ree 33 kO Cee 100 uF Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 11 LIE Em FAIRCHILD SR SEMICONDUCTOR Over Current Protection VREF 7 5V PFCM UCC3818 Fig 8 Over current protection circuit PFCM Design Guide The actual protection level can be slightly different from the calculated value It depends on PCB layout pattern About demo board the designed values are Rig Rao 1 2 kQ Rig Ra 82 kQ Ras 1 5 kQ And the expected OC levels are 1 OCP level 1 R R R V pre Royl pp R V R 38 _ 18 40 REF SH PK M9 m E REF 38 Rig Ry Rig Ry Ryo Ry Ry Ry AT 40A 2 OCP level 2 Rio Ra Ver Ls Rig Rou px R Ry lt I pg SOLA Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 12 e FAIRCHILD SEMICONDUCTOR PFCM Design Guide Over Voltage Protection Fig 9 Over voltage protection circuit About demo board the designed values are Rx 15 Ry 1 8 KO Rz 870 27042707330 kO And the expected OC levels are 1 OVP level 1 R V Ry R 886 8 X Y jee gt Voc Pk eae 8 4221V Ry Ry R
8. J 2012 R Chip 100hm 1 8W J 2012 R Chip 10ohm 1 8W J 2012 R Chip 120Kohm 1 8W J 2012 R Chip 150 1 8W J 2012 R Chip 15Kohm 1 8W J 2012 R Chip 18Kohm 1 4W J 3216 R Chip 18Kohm 1 8W J 2012 R Chip 1Mohm 1 8W J 2012 R Chip 20Kohm 1 8W J 2012 R Chip 270Kohm 1 4W F 3216 R Chip 3 3kohm 1 8W J 2012 R Chip 3 9Kohm 1 8W J 2012 R Chip 33Kohm 1 8W J 2012 R Chip 330Kohm 1 4W F 3216 R Chip 390ohm 1 8W J 2012 R Chip 4 7Kohm 1 8W J 2012 R Chip 470Kohm 1 4W F 3216 R Chip 470ohm 1 8W J 2012 R Chip 47Kohm 1 8W J 2012 R Chip 56ohm 1 8W J 2012 R Chip 82Kohm 1 8W J 2012 R Chip 9kohm 1 8W F 2012 Regulator KA78M12 Switch SW SPDT 1 Terminal VTR 250 TR KRC102 Transformer El 1916 TVS SMBJ170 Varistor SVC471D Voltage detector KA431A Zener Diode 1N4734A 5 6V Bridge Diode DF08S Feb 2006 SR7 SR8 SR4 R23 R24 R41 R13 SR1 R42 R48 R9 R25 R43 R4 R49 R50 R51 R22 R27 R28 R30 R31 R32 R34 R6 R7 R44 R45 R55 SR3 R29 R26 R54 R5 R8 R1 R3 R52 R53 R20 R21 R2 R17 R47 R19 R37 SR5 U7 PFC SW J1 J2 J5 J6 AC1 AC2 P N Q2 T1 PFCM Design Guide FAIRCHILD SEMICONDUCTOR System Engineering Group 17 es FAIRCHILD SEMICONDUCTOR PFCM Design Guide Voc 50V div In 10A div base 15 0 ms Trigger 50 0 10 0 A div 5 00 Stop 200 0
9. Lene p UU ES FAIRCHILD SEMICONDUCTOR PFCM Design Guide PFCM Design Guide with Analog PFC IC HP SPM amp System Engineering Group FAIRCHILD SEMICONDUCTOR 82 3 Dodang Dong Wonmi ku Puchon Kyonggi Do KOREA Tel 82 32 680 1834 Fax 82 32 680 1823 Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 1 Lene p UU ES FAIRCHILD a SEMICONDUCTOR PFCM Design Guide Contents 1 System Configurations 3 2 Protection me 3 Over Current Protection 23 u 1 u cxccsincdcndsinwartctesatacetsnscecndevanccecevaneeter condeteecvessdveeeardecarssede 3 Over Voltage Proleclion oiii eiit ente fede siiis Suse asas aH EE e Ee Es vus se 4 Under Voltage Protection RE e Ha sU eR xe ns 4 3 Design Example PFCM DEMO BOARD 5 Operating conditions of PFCM demo board 5 Output capacitance and Inductance design 5 Output Voltage Ripple amp Output Capacitances 5 Inductance amp Input Current Ripple u enne enean nnne
10. Ry R 2 OVP level 2 R V R R R 886 8 Vac x Y zy 7 5 443 V Ry GS R Vpc rk Ry 15 Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 13 e FAIRCHILD SEMICONDUCTOR PFCM Design Guide DC link Voltage Control Vdc d o Ry Fig 10 DC link voltage control circuit The relation between Vpc and parameters is R 1 1 R 1 R R R R Voc rf D F VD Ry m y E pI Ryp Ry Rys Rp The variable Vpc voltage is available by just changing voltage Vea the output of voltage error amplifier changes from 0 to 5 5V as its load current In no load condition Ve value is almost zero And the voltage of Voc will be the highest value The next graph shows and Vpc voltage The voltage of Vpc in low load condition is higher than that of max load condition Voc V Min load V Fig 11 DC link voltage vs control voltage Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 14 e FAIRCHILD SEMICONDUCTOR PFCM Design Guide 4 Experimental Results Fig 12 shows the overall schematics of implemented PFC converter Table 2 shows the components that are used for the implemented hardware Fig 13 shows the input ac current and DC link voltage waveforms These figures details are shown in table 3
11. V ofst 0 00 A offset 500 kS 10MSisfEdge Positive Fig 13 Full load test results lin 15Anus Table 3 Power factor and input power measurement ms 1 Vac and lac are RMS values Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 18
12. ecovers to the UV reset level OVP1 OvP2 DC Output Voltage x Output Current eae ore T E Mi IGBT Current UL a 57 Ww Control Supply Voltage J 5 Uv Fault Output Hr enc Fig 2 Timing chart of protection function Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 4 Lene pu EE FAIRCHILD SEMICONDUCTOR PFCM Design Guide 3 Design Example PFCM DEMO BOARD A general PFC example is implemented for 5 kW air conditioning applications whose input voltage is 187 276 V Operating conditions of PFCM demo board Table 1 The operating conditions Item Symbol Value Unit Output capacitance and Inductance design Output Voltage Ripple amp Output Capacitance 1 T VourRiPPLI lourpc4l ESR PEAK x Cour where fj line frequency ESR the ESR of the output capacitor Voltage ripple of Voc can be reduced by employing large Cour In demo board Cour is set to 940 uF 470 uF x 2 Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 5 es FAIRCHILD SEMICONDUCTOR PFCM Design Guide Inductance amp Input Current Ripple Vin Youtpe Et fLVourpc where Peak to peak current of PFC inductor Vin Input AC voltage Vourpc DC link Voltage f Switching frequency L Inductance of PFC inductor Vin
13. ost slow op amp solution with fast protection It is the OCP level2 protection described in next paragraph OCP Level2 SCP control IC By the peak current limit function of PFC control IC the system is protected from SC Short Circuit situation The recommended current limit of OCP level 2 is higher than Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 3 FAIRCHILD SEMICONDUCTOR PFCM Design Guide that of OCP level 1 It doesn t generate the fault out signal but its response is very fast It will protect the system from short circuit situation during the propagation delay time of OCP level1 Over Voltage Protection OV Over Voltage protection can be also implemented by dual protection The DC link voltage changes slowly because of its large capacitance So OVP does not need fast response Therefore it is optional to activate the OVP of PFC controller OVP Level 1 PFC controller OVP level 1 suppresses voltage overshoot in transient situation It doesn t generate fault out signal OVP Level 2 PFCM The voltage level of OVP level 2 is higher than that of OVP level 1 When OV situation happens the PFCM stops operating and generates fault out signal during fault out duration time set by Crop And then it works again Under Voltage Protection IGBT gate will be interrupted when control voltage drops below UV trip level and the protection will be realeased automatically if the control voltage r
14. r current sensing 2mohm L PFC inductance S jo j2mf Voltage Loop Amplifier Eq 2 shows the open loop response of power stage Refer to UCC3818 datasheet 5 AV BE where Input power Cou DC link capacitance Vourpc DC link voltage AVeaout Error amplifier output difference 5V S jo j 2zf 7 e FAIRCHILD SEMICONDUCTOR PFCM Design Guide Control Loop Implementation Current Loop Step 1 Crossover frequency Theoretical crossover frequency is given by following equation fc A gt 6 7kHz Eq 3 Step 2 Fz and Fp decision fz C f 67 20kHz Step 3 Rz Cp Cz decision Ri is same to Ryo Refer to other parameters in page 10 470 0 un 451 4 02 7 1 Therefore it requires 40dB boosting at fc 6 6kHz 0 0103 39 8dB In Eq 1 G psr fo 6 6kHz R is given by Eq 7 cl dB 201og 40dB gt R 47 kO From Eq 4 Eq 5 Cp and Cz is given C 180 pF C 1 nF 1 Jf Eq 4 2zR C C C Eq 5 2 C C R Fig 4 Current loop circuit Feb 2006 FAIRCHILD SEMICONDUCTOR System Engineering Group 8 FAIRCHILD PFCM Design Guide SEMICONDUCTOR Desired Current Error Amplifier ap e L al N I x Frequency Hz Fig 5 Desired current error amplifier response
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FAIRCHILD PFCM Manual