international IOR rectifier IR2111 HALF-BRIDGE DRIVER handbook
Contents
1. Figure 5 Deadtime Waveform Definitions B 44 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL International IGR Rectifier IR2111 ti il i 0 150 125 o o Y a Junction Temperature C Junction Temperature C 1E 2 1E 3 1E 4 1E 5 1E 6 1E 2 1E 3 1E 4 1E 5 1E 6 Frequency Hz Frequency Hz Figure 7 1R2111 Ty vs Frequency IRFBC20 Figure 8 1R2111 Ty vs Frequency IRFBC30 Recarte 330 Vcc 15V RGATE 220 Vcc 15V ov 140V Junction Temperature C Junction Temperature C Mt 2a TT A iim SUIT UNE N UUN 1E 2 1E 3 1E 4 1E 5 1E 6 1E 2 1E 3 1E 4 1E 5 1E 6 Frequency Hz Frequency Hz Figure 9 1R2111 Ty vs Frequency IRFBC40 Figure 10 1R2111 Ty vs Frequency IRFPE50 Reate 150 Vcc 15V Reate 109 Vcc 15V al SS ee ee ee pa E LD EAS Bea PRA E DE FE ON E IE A e Ey SSS gt CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B 452. 0018211 0 0 International Data Sheet No PD 6 028C ISR Rectifier IR2111 HALF BRIDGE DRIVER Features Product Summary E Floating channel designed for bootstrap operation Fully operational to 600V VOFFSET 600V max Tolerant to negative transient voltage lo 200 mA 420 mA dV dt immune E Gate drive supply range from 10 to 20V VOUT 10 20V E Undervoltage lockout for both channels E CMOS Schmitt triggered inputs with pull down ton off typ 850 amp 150 ns E Matched propagation delay for both channels E Internally set deadtime Deadtime typ 700 ns E High side output in phase with input Description Packages The IR2111 is a high voltage high speed power MOSFET and IGBT driver with dependent high and low side referenced output channels designed for half bridge applications Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction Logic input is compatible with standard CMOS outputs The output drivers feature a high pulse current buffer stage designed for minimum driver cross conduction Internal deadtime is provided to avoid shoot through in the output half bridge The floating channel can be used to drive an N channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts Typical Connection up to 600V CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B 39 International IR2111 IGR Rectifier Absolute Maximum Ratings Absolute Maximum Rati
3. ng the test circuit shown in Figure 3 Symbol Definition Min Typ Max Units Test Conditions ton Turn On Propagation Delay Turn On Propagation Delay 850 1 000 Vs 0 Vs 0V Turn Off Propagation Delay 150 180 Vs 600V eee u u H Turn Off Fall Time 40 65 e ld ell HS Turn Off to LS Turn On Delay Matching HS amp LS Turn On Off 30 Static Electrical Characteristics VBIAS Vcc Vgs 15V and Ta 25 C unless otherwise specified The Vin VTH and lin parameters are referenced to COM The Vo and Io parameters are referenced to COM and are applicable to the respective output leads HO or LO Symbol Definition Min Typ Max Units Test Conditions VIH Logic 1 Input Voltage for HO amp Logic 0 for LO C Vec 10V Vcec 10V Vcc 15V Vcc 20V 8 y Veo ew VIL Logic 0 Input Voltage for HO amp Logic 1 for LO Vcc 10V Vcc 15V Vcc 20V VOH High Level Output Voltage VBias Vo a Low Level Output Voltage Vo Output High Short Circuit Pulsed Current Output Low Short Circuit Pulsed Current 420 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B 41 Vo OV Vin Vcc PW lt 10 us Vo 15V Vin OV PW lt 10 us 3 aJs A s Il Il International IR2111 IGR Rectifier Functional Block Diagram LO COM Lead Definitions Lead Symbol Description Logic in
4. ngs indicate sustained limits beyond which damage to the device may occur All voltage parameters are absolute voltages referenced to COM The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions Additional information is shown in Figures 7 through 10 Parameter Definition dV yat Allowable Offset SupplyVoltage Transient Figure 2 o Package Power Dissipation WTA lt 25 C 8 Lead DIP UA 8 Lead SOIC ReJA Thermal Resistance Junction to Ambient 8 Lead DIP Baa 8 Lead SOIC T Junction Temperature Storage Temperature Lead Temperature Soldering 10 seconds Recommended Operating Conditions The Input Output logic timing diagram is shown in Figure 1 For proper operation the device should be used within the recommended conditions TheVs offset rating is tested with all supplies biased at 15V differential Parameter Value Definition Min Max Units High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage Notet 600 Mio iws O e w rme o o f e TA AmbientTemperature C Note 1 Logic operational for Vs of 5 to 600V Logic state held for Vs of 5V to Vps B 40 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL International IGR Rectifier IR2111 Dynamic Electrical Characteristics VIAS Vcc VBs 15V CL 1000 pF and Ta 25 C unless otherwise specified The dynamic electrical characteristics are measured usi
5. put for high side and low side gate driver outputs HO amp LO in phase with HO High side floating supply High side gate drive output Vs High side floating supply return COM 8 Lead DIP CR S O Part Number B 42 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL International IGR Rectifier IR2111 Device Information Process amp Design Rule HVDCMOS 4 0 um Transistor Count 164 Die Outline Connections Material Poly Silicon First Layer Spacing Thickness Material Second Layer Thickness Insulation Layer Material PSG SiO2 Thickness 1 5 um Passivation Material PSG SiOz Thickness Method of Saw Full Cut Method of Die Bond Ablebond 84 1 Wire Bond Method Thermo Sonic Material Au 1 0 mil 1 3 mil Leadframe Material Die Area Lead Plating Pb Sn 37 63 Package 8 Lead PDIP SO 8 Materials EME6300 MP150 MP190 Remarks CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B 43 International IR2111 T R Rectifier Van 15V HY 10 to 600V IN CC A HO OUTPUT eo PII MONITOR Eai Figure 1 Input Output Timing Diagram Figure 2 Floating Supply Voltage Transient Test Circuit Voc 15V oB IN LO UY 50 50 OV 0198001 IN HO 10 IN To ton tr tofi t 90 90 LO z HO 1 0 1 0 Figure 3 Switching Time Test Circuit Figure 4 Switching Time Waveform Definition 50 50 LO HO 10 MT MT 90 LO HO Figure 6 Delay Matching Waveform Definitions
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