ON NCP1200A handbook
Contents
1. TYPICAL CHARACTERISTICS 70 12 5 60 12 3 ae 124 T i 40 5 11 9 5 5 T x 30 E 117 20 S 115 gt 10 11 3 0 11 1 25 0 25 50 75 100 125 25 0 25 50 75 100 125 TEMPERATURE TEMPERATURE Figure 3 HV Pin Leakage Current vs Temperature Figure 4 Vcc or vs Temperature 10 2 10 1 10 0 E es 5 9 9 9 8 9 7 9 6 25 0 25 50 75 100 125 25 0 25 50 75 100 125 TEMPERATURE TEMPERATURE Figure 5 Vcc on vs Temperature Figure 6 ICC1 vs Temperature 110 100 kH 104 98 92 _ 86 T 80 d z i 68 62 56 50 44 38 25 0 25 50 75 100 125 25 0 25 50 75 100 125 TEMPERATURE TEMPERATURE Figure 7 2 vs Temperature Figure 8 Switching Frequency vs Temperature http onsemi com 5 HE www dzsc LATCHOFF V ww dzsc NCP1200A TYPICAL CHARACTERISTICS 5 50 490 545 460 430 5 40 400 5 35 lt 370 340 O 2 30 2 310 5 25 282. CL t0 n 5 Oupa Varage CL 1046 10 5 Current Comparator Pin 5 unloaded unless otherwise noted Input Bias Current 9 1 0 V Input Level on Pin 3 3 o2 uw 3 08 v rerai Curent Skp wa tw 3 9 av Propagation rom GurentDeestontoGatwOFF tme 3 9 9 Teading Eage Banking Duraton oe re 3 1 Internal Oscillator Vcc 11 V pin 5 loaded by 1 0 KQ OrctaionFequeney 5 Buin Frequency tw 59 T __ we 9 5 Built in Frequency Jittering fgy 60 kHz 4 Fequeney Up www we 9 Buin Frequency merno Maximum Duyoyee SS 9 Feedback Section Vcc 11 V pin 5 unloaded Internal Pullup Resistor Re 2 2 ke PnSwCwenSepinDWsonRdo Skip Cycle Generation Pin 1 1 Max value at Ty 0 C 2 Maximum value 25 C please see characterization curves 3 Pin 5 loaded by 1 0 nF http onsemi com 4 www dzsc 1200
3. TIME DRIVER PULSES TIME FAULT IS RELAXED TIME FAULT OCCURS HERE Figure 21 If the fault is relaxed during the Vcc natural fall down sequence the IC automatically resumes If the fault still persists when Vcc reached then the controller cuts everything off until recovery When this level crosses 5 4 V typical the controller enters a new startup phase by turning the current source on Vcc rises toward 12 V and again delivers output pulses at the UVLOy crossing point If the fault condition has been removed before UVLO approaches then the IC continues its normal operation Otherwise a new fault cycle takes place Figure 21 shows the evolution of the signals in presence of a fault Calculating the Vcc Capacitor As the above section describes the fall down sequence depends upon the level how long does it take for the line to go from 12 V to 10 V The required time depends on the startup sequence of your system i e when you first apply the power to the IC The corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12 V to 10 V otherwise the supply will not properly start The test consists wwwW dzsc 11 in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load Let s suppose that this time corresponds to 6 ms Therefore a fall time of 10 ms coul
4. 4 MAXIMUM MOLD PROTRUSION 0 15 0 006 PER SIDE 0 25 0 010 0 4 5 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR wr PROTRUSION SHALL BE 0 127 0 005 TOTAL IN EXCESS OF THE D DIMENSION MAXIMUM MATERIAL CONDITION 6 751 01 THRU 751 06 ARE OBSOLETE NEW STANDARD IS 751 07 MILLIMETERS INCHES MIN MAX MIN MAX 4 80 5 00 0 189 0 197 3 80 4 00 0 150 0 157 1 35 1 75 0 053 0 069 0 33 0 51 0 013 0 020 1 27 BSC 0 050 BSC 0 10 0 25 0 004 0 010 0 19 0 25 0 007 0 010 0 40 1 27 0 016 0 050 0 8 9 09 8 0 25 0 50 0 010 0 020 5 80 6 20 0 228 0 244 g z E SEATING a PLANE SS 0 10 0 004 J 0 25 0 010 2 YO z z c x Oo gt SOLDERING FOOTPRINT A 1 52 0 060 7 0 4 0 0 275 0 155 EE 0 6 l J hk 1270 0 024 0 050 SCALE 6 1 m additional information on our Pb Free strategy and soldering details please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual SOLDERRM D http onsemi com 14 HE www dzsc 1200 PACKAGE DIMENSIONS PDIP 8 P SU
5. LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website http onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 61312 Phoenix Arizona 85082 1312 USA Order Literature http www onsemi com litorder Phone 480 829 7710 or 800 344 3860 Toll Free USA Canada Japan ON Semiconductor Japan Customer Focus Center MEN Fax 480 829 7709 or 800 344 3867 Toll Free USA Canada 2 9 1 Kamimeguro Meguro ku Tokyo Japan 153 0051 For additional information please contact your gt 81 3 5773 3850 local Sales Representative NCP1200A D
6. applied to the gate To obtain the final IC current simply divide this result by lariver Fsw Qg 1 5 mA The total standby power consumption at no load will therefore heavily rely on the internal IC consumption plus the above driving current altered by the driver s efficiency Suppose that the IC is supplied from a 350 VDC line The current flowing through pin 8 is a direct image of the NCP1200A consumption neglecting the switching losses of the HV current source If ICC2 equals 2 3 mA Ty 25 C then the power dissipated lost by the IC is simply 350 x 2 3 m 805 mW For design and reliability reasons it would be interesting to reduce this source of wasted power which increases the die temperature This can be achieved by using different methods 1 Use a MOSFET with lower gate charge 2 Connect pin through a diode 1N4007 typically to one of the mains input The average value on pin 8 VMAINS peak 2 becomes Our power contribution example drops to 223 x 2 3 m 512 mW If a resistor is installed between the mains and the diode you further force the dissipation to migrate from the package to the resistor The resistor value should account for low line startups Permanently force the Vcc level above VCCg with an auxiliary winding It will automatically disconnect the internal startup source and the IC will be fully self supplied from this winding Again the total power drawn from the mains will si
7. capacitor and keeps activating the MOSFET ON and OFF with a peak current limited by Rsense Unfortunately if the quality coefficient Q of the resonating network formed by Lp and Cbulk is low e g the MOSFET Rdson Rsense are small conditions are met to make the circuit resonate and thus negatively bias the controller Since we are talking about ms pulses the amount of injected charge Q 2 I x t immediately latches the controller which brutally discharges its capacitor If this capacitor is of sufficient value its stored energy damages the controller Figure 22 depicts a typical negative shot occurring on the HV pin where the brutal Vcc discharge testifies for latchup 0 LEES Figure 22 negative spike takes place on the Bulk capacitor at the switch off sequence Simple and inexpensive cures exist to prevent from internal parasitic SCR activation One of them consists in inserting a resistor in series with the high voltage pin to keep the negative current to the lowest when the bulk becomes negative Figure 23 Please note that the negative spike is clamped to 2 x Vf due to the diode bridge Please refer to AND8069 D for power dissipation calculations Figure 23 A simple resistor in series avoids any latchup in the controller 12 Another option Figure 24 consists wiring a diode from Vcc to the bulk capacitor to force Voc to reach UVLOlow sooner and thus
8. naturally supplied from the high voltage rail and delivers a Vcc to the IC This system is called the Dynamic Self Supply 055 Dynamic Self Supply The DSS principle is based on the charge discharge of the bulk capacitor from a low level up to a higher level We can easily describe the current source operation with a bunch of simple logical equations POWER ON IF Vcc THEN Current Source is ON no output pulses IF Vcc decreasing gt THEN Current Source is OFF output is pulsing IF Vcc increasing THEN Current Source is ON output is pulsing Typical values are VCCy 12 V VCC 10 V To better understand the operational principle Figure 15 s sketch offers the necessary light Vripple 2V UVLOy 12 V Voc UVLO 10 V ON Current OFF Source OUTPUT PULSES 10 0 M 30 0 M 50 0 M 70 0 M 90 0 M Figure 15 The charge discharge cycle over a 10 uF Vcc capacitor HE wwwW dzsc The DSS behavior actually depends on the internal IC consumption and the MOSFET s gate charge Qg If we select a MOSFET like the MTP2N60E Qg max equals 22 nC With a maximum switching frequency of 68 kHz for the P60 version the average power necessary to drive the MOSFET excluding the driver efficiency and neglecting various voltage drops is Fsw Vcc with Fsw maximum switching frequency Qg MOSFET s gate charge Vcc Vas level
9. stops the switching activity before the bulk capacitor gets deeply discharged For security reasons two diodes can be connected in series D3 1N4007 Figure 24 or a diode forces to reach UVLOlow sooner http onsemi com 1200 ORDERING INFORMATION NCP1200AP40 1200440 PDP S0Unis Ral Units Rail EM F 40 kH LL 8 Units Rail SW 2 Pb Free NCP1200AD40R2 200A4 SOIC 8 2500 Units Reel E 1200 60 PDIP PDP S50Unts Ral Units Rail EIC MEN NE EE CENE 8 po Units Rail Pb Free Fow 60 kHz NCP1200AD60R2 20060 socs 8 2500 Units Reel Units Reel E 200AD60R2G Units Reel Pb Free NCP1200AP100 1200AP100 PDIP 8 50 Units Rail ELM 1200AP100 PDIP 8 50 Units Rail Pb Free Fsw 100 kHz NCP1200AD100R2 socs o 8 2500 Units Reel Units Reel EM 200AD100R2G LL LL NEIN Units Reel Pb Free TFor information on tape and reel specifications including part orientation and tape sizes please refer to our Tape and Reel Packaging Specifications Brochure BRD8011 D http onsemi com 13 OD f www dzsc 1200 PACKAGE DIMENSIONS SOIC 8 D SUFFIX CASE 751 07 ISSUE AC NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 CONTROLLING DIMENSION MILLIMETER DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION
10. the default has Figure 20 Another Way of Shutting Down the IC without a Definitive Latchoff State http onsemi com 9 1g E www dzsc 1200 Power Dissipation The NCP1200A is directly supplied from the DC rail through the internal DSS circuitry The average current flowing through the DSS is therefore the direct image of the NCP1200A current consumption The total power dissipation can be evaluated using ICC2 If we operate the device on a 250 VAC rail the maximum rectified voltage can go up to 350 VDC However as the characterization curves show the current consumption drops at high junction temperature which quickly occurs due to the DSS operation At T 50 ICC2 1 7 mA for the 61 kHz version over a 1 nF capacitive load As a result the NCP1200A will dissipate 350 1 7 mA QT 50 C 5905 mW SOIC 8 package offers junction to ambient thermal resistance Rey of 178 C W Adding some copper area around the PCB footprint will help decreasing this number 12 mm x 12 mm to drop RgjA down to 100 C W with 35 u copper thickness 1 oz or 6 5 mm x 6 5 mm with 70 copper thickness 2 oz With this later number we can compute the maximum power dissipation the package accepts at ambient of 50 TJmax TAmax _ 759 mW which is okay with our previous budget For the DIP8 package adding min pad area of 80 mm of 35 u copper 1 oz Rgj
11. the level at which the cycle skipping process takes place Shorting this pin to ground permanently disables the skip cycle feature 2 FB Sets the peak current setpoint By connecting an optocoupler to this pin the peak current setpoint is adjusted accordingly to the output power demand 3 C Current sense input This pin senses the primary current and routes it to the internal comparator via an L E B D V N GND The IC ground S Driving pulses The driver s output to an external MOSFET Supplies the IC This pin is connected to an external bulk capacitor of typically 10 uF PF NC This unconnected pin ensures adequate creepage distance HV Generates the Vcc from the line Connected to the high voltage rail this pin injects a constant current into the bulk capacitor http onsemi com 2 www dzsc 1200 SOURCE SKIP CYCLE COMPARATOR UVLO HIGH AND LOW INTERNAL Vc INTERNAL REGULATOR BERE Q FLIP FLOP SENSE 40 60 100 kHz LOCK SCO RESET OVERLOAD FAULT DURATION Figure 2 Internal Circuit Architecture MAXIMUM RATINGS Power Supply Voltage Thermal Resistance Junction to Air 8 Version Thermal Resistance Junction to Air SOIC Version ESD Capability HBM Model All pins except Vcc and HV ESD Capability Machine Model Maximum Voltage on Pin 8 HV Pin 6 Vcc Grounded Maximum Voltage on Pin 8 HV Pin 6 Vcc Decoupled to Gro
12. 0 2 5 20 a 220 5 15 190 25 0 25 50 75 100 125 25 0 25 50 75 100 125 TEMPERATURE Figure 9 Vcc Latchoff vs Temperature Figure 10 ICC3 vs Temperature 60 1 00 50 5 0 96 Source 40 2 0 92 30 T 5 0 88 20 5 Sink 0 84 10 d 0 0 80 25 0 25 50 75 100 125 25 0 25 50 75 100 125 TEMPERATURE C TEMPERATURE Figure 11 Drive and Source Resistance vs Figure 12 Current Sense Limit vs Temperature Temperature 1 40 87 1 35 85 1 30 Q 83 1 25 lt 1 20 79 1 15 1 10 77 1 05 75 1 00 73 25 0 25 50 75 100 125 25 0 25 50 75 100 125 TEMPERATURE Figure 13 vs Temperature TEMPERATURE Figure 14 Max Duty Cycle vs Temperature http onsemi com 6 1200 APPLICATION INFORMATION Introduction The NCP1200A implements a standard current mode architecture where the switch off time is dictated by the peak current setpoint This component represents the ideal candidate where low part count is the key parameter particularly in low cost AC DC adapters auxiliary supplies etc Due to its high performance High Voltage technology the NCP1200A incorporates all the necessary components normally needed in UC384X based supplies timing components feedback devices low pass filter and self supply This later point emphasizes the fact that ON Semiconductor s NCP1200A does NOT need an auxiliary winding to operate the product is
13. 0 0 1200 10051 1200 PWM Current Mode Controller for Universal Off Line Supplies Featuring Low Standby Power ON Somiconductor Housed in SOIC 8 or PDIP 8 package the NCP1200A enhances the previous NCP1200 series by offering a reduced optocoupler current together with an increased drive capability Due to its novel http onsemi com concept the circuit allows the implementation of complete off line MINIATURE PWM AC DC adapters battery charger or a SMPS where standby power is a CONTROLLER FOR HIGH Key parameter POWER AC DC WALL With an internal structure operating at a fixed 40 kHz 60 kHz or 100 kHz the controller supplies itself from the high voltage rail ADAPTERS AND OFFLINE avoiding the need of an auxiliary winding This feature naturally eases BATTERY CHARGERS the designer task in battery charger applications Finally current mode control provides an excellent audio susceptibility and inherent pulse by pulse control When the current setpoint falls below a given value e g the output power demand diminishes the IC automatically enters the so called skip cycle mode and provides excellent efficiency at light loads SOIC 8 MARKING DIAGRAMS ES Because this occurs at a user adjustable low peak current no acoustic 845 D SUFFIX 1 CASE 751 noise takes place The NCP1200A features an efficient protective circuitry which in presence of an overcurrent condition disables the output pulse
14. A drops from 100 C W to about 75 C W In the above calculations ICC2 is based on a 1 nF output capacitor As seen before ICC2 will depend on your MOSFET s Qg ICC2 Fsw Qg Final calculation shall thus accounts for the total gate charge your MOSFET will exhibit The same methodology can be applied for the 100 kHz version but care must be taken to keep Ty below the 125 C limit with the D100 SOIC version and activated DSS in high line conditions If the power estimation is beyond the limit other solutions are possible a add a series diode with pin 8 as suggested in the above lines and connect it to the half rectified wave As a result it will drop the average input voltage and lower the Pmax wwwW dzsc 10 350 2 dissipation to auxiliary winding to disable the DSS and decrease the power consumption to Vcc x ICC2 The auxiliary level should be thus that the rectified auxiliary voltage permanently stays above 10 V to not re activate the DSS and is safely kept below the 16 V maximum rating 1 7 380 mW b put an Overload Operation In applications where the output current is purposely not controlled e g wall adapters delivering raw DC level it is interesting to implement a true short circuit protection A short circuit actually forces the output voltage to be at a low level preventing a bias current to circulate in the optocoupler LED As a result the FB pin le
15. FFIX CASE 626 05 ISSUEL NOTES 1 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 2 PACKAGE CONTOUR OPTIONAL ROUND OR SQUARE CORNERS 8 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 MILLIMETERS INCHES DIM MIN MAX MIN MAX A 940 1016 0 370 0 400 B 610 660 0 240 0 260 394 445 0155 0 175 NOTE 2 D 038 051 0 015 0 020 L F 102 178 0 040 0 070 G 2 54 BSC 0 100 5 0176 127 0 030 0 050 f J o20 030 0 008 0 012 292 343 0115 0 135 L 7 62 BSC 0 300 BSC J m 7 w 10 T N 076 101 0 030 0 040 SEATING N PLANE M 46 0 K 0 13 0 005 D 0 B gpi http onsemi com 15 www dzsc 1200 product described herein NCP1200A may be covered by the following U S patents 6 271 735 6 362 067 6 385 060 6 429 709 6 587 357 There may be other patents pending ON Semiconductor and registered trademarks of Semiconductor Components Industries LLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation s
16. T Dynamic Range MODE OPERATION SKIP CYCLE OPERATION 333 mV RsENsE Figure 17 When FB is above the skip cycle threshold 1 V by default the peak current cannot exceed 1 V RsgNsE When the IC enters the skip cycle mode the peak current cannot go below 1 3 3 The user still has the flexibility to alter this 1 V by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level Grounding pin 1 permanently invalidates the skip cycle operation 1g E www dzsc H http onsemi com 1200 MAX PEAK 300 M CURRENT 200M SKIP CYCLE CURRENT LIMIT 315 40 882 70 1 450 2 017 2 585 Figure 19 The Skip Cycle Takes Place at Low Peak Currents which Guaranties Noise Free Operation We recommend a pin 1 operation between 400 mV and 1 3 disappeared This option can easily be accomplished V that will fix the skip peak current level between 120 mV through a single NPN bipolar transistor wired between FB RSENSE and 390 mV RSENSE and ground By pulling FB below the Adj pin 1 level the output pulses are disabled as long as FB is pulled below pin 1 As soon as FB is relaxed the IC resumes its operation Figure 20 depicts the application example Non Latching Shutdown In some cases it might be desirable to shut off the part temporarily and authorize its restart once
17. d be well appropriated in order to not trigger the overload detection circuitry If the corresponding IC consumption including the MOSFET drive establishes at 1 8 mA for instance we can calculate the required _AV C capacitor using the following formula i with AV 2 V Then for a wanted At of 10 ms C equals 9 uF or 22 uF for a standard value When an overload condition occurs the IC blocks its internal circuitry and its consumption drops to 350 uA typical This happens at 10 V and it remains stuck until Vcc reaches 5 4 V we are in latchoff phase Again using the calculated 22 uF and 350 uA current consumption this latchoff phase lasts 206 ms http onsemi com 1200 Protecting the Controller Against Negative Spikes As with any controller built upon a CMOS technology it is the designer s duty to avoid the presence of negative spikes on sensitive pins Negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors Sometimes the injection can be so strong that internal parasitic SCRs are triggered engendering irremediable damages to the IC if they are a low impedance path is offered between Vcc and GND If the current sense pin is often the seat of such spurious signals the high voltage pin can also be the source of problems in certain circumstances During the turn off sequence e g when the user unplugs the power supply the controller is still fed by its Vcc
18. gnificantly decrease Make sure the auxiliary voltage never exceeds the 16 V limit http onsemi com 1200 5 Figure 16 A simple diode naturally reduces the average voltage 8 Skipping Cycle Mode The NCP1200A automatically skips switching cycles when the output power demand drops below a given level This is accomplished by monitoring the FB pin In normal operation pin 2 imposes a peak current accordingly to the load value If the load demand decreases the internal loop asks for less peak current When this setpoint reaches a determined level the IC prevents the current from decreasing further down and starts to blank the output pulses the IC enters the so called skip cycle mode also named controlled burst operation The power transfer now depends upon the width of the pulse bunches Figure 18 Suppose we have the following component values Lp primary inductance 1 mH Fsw switching frequency 61 kHz Ip skip 200 mA or 333 mV RggNsE The theoretical power transfer is therefore 1 2 If this IC enters skip cycle mode with a bunch length of 20 ms over a recurrent period of 100 ms then the total power transfer is 1 2 0 2 2 240 mW Ip Few 1 2 better understand how this skip cycle mode takes place a look at the operation mode versus the FB level immediately gives the necessary insight FB 4 2 V FB Pin Open 3 2 V Upper NORMAL CURREN
19. pecial consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION
20. s while the device enters a safe burst mode trying to restart Once the default has gone the device auto recovers PDIP 8 1200 P SUFFIX AWL Features CASE 626 Pb Free Packages are Available No Auxiliary Winding Operation Specific Device Code Auto Recovery Internal Output Short Circuit Protection 40 60 or 100 Extremely Low No Load Standby Power y Specific Device Code S DE 4 for 40 6 for 60 1 for 100 Current Mode Control with Skip Cycle Capability A Assembly Location Internal Temperature Shutdown WL L Wafer Lot Internal Leading Edge Blanking Y YY Year W WW Work Week 250 mA Peak Current Capability Internally Fixed Frequency at 40 kHz 60 kHz and 100 kHz Direct Optocoupler Connection SPICE Models Available for TRANsient and AC Analysis Pin to Pin Compatible with NCP1200 Typical Applications AC DC Adapters for Portable Devices Offline Battery Chargers Auxiliary Power Supplies USB Appliances TVs etc Top View ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet stries LLC 2004 1 Publication Order Number NCP1200A D fg e wwwW dzsc 1200 1200 UNIVERSAL INPUT Please refer to the application information section Figure 1 Typical Application Example PIN FUNCTION DESCRIPTION Pin Description This pin lets you adjust
21. und with 10 uF Minimum Operating Voltage on Pin 8 HV Maximum ratings are those values beyond which device damage can occur Maximum ratings applied to the device are individual stress limit values not normal operating conditions and are not valid simultaneously If these limits are exceeded device functional operation is not implied damage may occur and reliability may be affected http onsemi com 3 www dzsc 1200 ELECTRICAL CHARACTERISTICS For typical values Ty 25 C for min max values Ty 0 C to 125 C Ty 150 C 11 V unless otherwise noted ww Dynamic Self Supply All frequency versions otherwise noted Vcc Increasing Level at which the Current Source Turns Off VCC ott Decreasing Level at which the Current Source Turns On VCC on Voc Decreasing Level at which the Latchoff Phase Ends VCC latch Internal IC Consumption No Output Load on Pin 5 Internal IC Consumption 1 0 nF Output Load on Pin 5 Few 40 kHz ICC2 Internal IC Consumption 1 0 nF Output Load on Pin 5 Few 60 kHz ICC2 Internal IC Consumption 1 0 nF Output Load on Pin 5 Fgw 100 kHz Internal IC Consumption Latchoff Phase Internal Startup Current Source gt 0 C pin 8 biased at 50 V High Voltage Current Source Vcc 10 V 8 40 70 Jma Figh Votage oso Drive Output
22. vel is pulled up to 4 2 as internally imposed by the IC The peak current setpoint goes to the maximum and the supply delivers a rather high power with all the associated effects Please note that this can also happen in case of feedback loss e g a broken optocoupler To account for this situation NCP1200A hosts a dedicated overload detection circuitry Once activated this circuitry imposes to deliver pulses in a burst manner with a low duty cycle The system auto recovers when the fault condition disappears During the startup phase the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over This period of time depends on normal output load conditions and the maximum peak current allowed by the system The time out used by this IC works with the Vcc decoupling capacitor as soon as the Vcc decreases from the UVLOy level typically 12 V the device internally watches for an overload current situation If this condition is still present when the UVLO level is reached the controller stops the driving pulses prevents the self supply current source to restart and puts all the circuitry in standby consuming as little as 350 uA typical ICC3 parameter As a result the Vcc level slowly discharges toward 0 http onsemi com 1200 OCCURS HERE REGULATION LATCHOFF PHASE Drv INTERNAL FAULT FLAG STARTUP PHASE
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ON NCP1200A handbook