MAXIM MAX1077/MAX1079 handbook(1)
Contents
1. _ Package Information ecifications For the latest package outline information A PIN 1 10 AY 0 35 X 45 24L QFN THIN EPS mg 4 ND 1 x sg I BOTTOM VIEW TERMINAL TP RALAS VILEXIL VI PROPRIETARY INFORMATION T PACKAGE OUTLINE 12 16 20 24L THIN QFN 4x4x0 8mm Ez RIVAL CONTROL 21 0139 COMMON DIMENSIONS EXPOSED PAD VARIATIONS PKG 121 4x4 16L_ 4x4 201 4x4 24L 4x4 PKG MAX MIN NOM CODES 0 75 080 080 070 075 1244 2 ooe 005 002 002 71244 3 71244 4 71644 2 71644 3 71644 4 72044 1 12044 2 12044 3 Te444 1 Te444 8 T8444 3 12444 4 NOTES 1 DIMENSIONING amp TOLERANCING CONFORM TO ASME 14 5 1994 2 ALL DIMENSIONS ARE IN MILLIMETERS ANGLES ARE IN DEGREES 3 N IS THE TOTAL NUNBER OF TERMINALS A THE TERMINAL 1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95 1 5 012 DETAILS OF TERMINAL 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED THE TERMINAL 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE A DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0 25 mm AND 0 30 mm FROM TERMINAL TIP A ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY 7 DEPOPULATION IS2. TMSS20C54 1079 Gli CNVST FSX FSR DOUT Figure 15 Interfacing to the TMS320C54_ Internal Clocks the TMS320C54 where the transmit serial clock CLKX drives the receive serial clock CLKR and SCLK and the transmit frame sync FSX drives the receive frame sync FSR and CNVST For continuous conversion set the serial port to trans mit a clock and pulse the frame sync signal for a clock period before data transmission The serial port config uration SPC register should be set up with internal frame sync 1 CLKX driven by an on chip clock source MCM 1 burst mode FSM 1 and 16 bit word length FO This setup allows continuous conversions provided that the data transmit register DXR and the data receive register DRR are serviced before the next conversion Alternatively autobuffering can be enabled when using the buffered serial port to execute conversions and read the data without CPU intervention Connect the VL pin to the TMS320C54 supply voltage when the MAX1077 MAX1079 are operating with an analog sup ply voltage higher than the DSP supply voltage The word length can be set to 8 bits with FO 1 to imple ment the power down modes The CNVST pin must idle high to remain in either power down state Another method of connecting the MAX1077 MAX1079 to the TMS320C54 is to generate the clock signals external to either device This connection is shown in Figure 16 where se
3. Detailed Description The MAX1077 MAX1079 use an input T H and succes sive approximation register SAR circuitry to convert an analog input signal to a digital 10 bit output The serial interface requires only three digital lines SCLK CNVST and DOUT and provides easy interfacing to microprocessors uPs and DSPs Figure shows the simplified internal structure for the MAX1077 MAX1079 True Differential Analog Input T H The equivalent circuit of Figure 4 shows the input archi tecture of the 1077 1079 which is composed of a T H a comparator and a switched capacitor digital to analog converter DAC The T H enters its tracking mode on the 14th SCLK rising edge of the previous conversion Upon power up the T H enters its tracking mode immedi ately The positive input capacitor is connected to AIN The negative input capacitor is connected to AIN The T H enters its hold mode on the falling edge of CNVST and the difference between the sampled positive and negative input voltages is converted The time required for the T H to acquire an input signal is determined by how quickly its input capacitance is charged If the input signal s source impedance is high the acquisition time lengthens The acquisition time tACQ is the minimum Exposed Paddle EP is internally connected to GND time needed for the signal to be acquired It is calculated by the following equation taca gt 8 x RS RIN x 16pF whe
4. LMX321AUK4 1 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference General Description Features The MAX1077 MAX1079 are low power high speed seri al output 10 bit analog to digital converters ADCs that operate at up to 1 5Msps and have an internal reference These devices feature true differential inputs offering bet ter noise immunity distortion improvements and a wider dynamic range over single ended inputs A standard SPI QSPI MICROWIRE interface provides the clock necessary for conversion These devices easily interface with standard digital signal processor DSP synchronous serial interfaces The MAX1077 MAX1079 operate from a single 2 7V to 3 6V supply voltage The MAX1077 MAX1079 include a 2 048V internal reference The MAX1077 has a unipolar analog input while the MAX1079 has a bipolar analog input These devices feature a partial power down mode and a full power down mode for use between conver sions which lower the supply current to 2mA typ and 1pA max respectively Also featured is a separate power supply input VL which allows direct interfacing to 1 8V to Vpp digital logic The fast conversion speed 1 5Msps Sampling Rate Only 22mW typ Power Dissipation Only 1pA max Shutdown Current High Speed SPI Compatible 3 Wire Serial Interface 61dB S N D at 525kHz Input Frequency Internal True Differential Track Hold T H
5. HIGH IMPEDANCE DOUT Figure 5 Interface Timing Sequence CNVST ONE 8 BIT TRANSFER CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE sex PL LILI LI UU UU 1ST SCLK RISING EDGE pour o X 0 X o X D8 X D7 X DB X D5 gt DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH MODE NORMAL REF ENABLED 2 048V Figure 6 SPI Interface Partial Power Down Mode CNVST 51 EXECUTE PARTIAL POWER DOWN TWICE FIRST 8 BIT TRANSFER SECOND 8 BIT TRANSFER 15 SCLK RISING EDGE DOUT ENTERS TRI STATE ONCE CNVST GOES HIGH 15 SCLK RISING EDGE Yw Yo 5 00 MODE NORMAL REF ENABLED 2 048V PPD RECOVERY FPD Figure 7 SPI Interface Full Power Down Mode partial power down mode Then repeat the same sequence to enter full power down mode see Figure 7 Drive CNVST low and allow at least 14 SCLK cycles to elapse before driving CNVST high to exit full power down mode While in full power down mode the refer ence is disabled to minimize power consumption Be sure to allow at least 2ms recovery time after exiting full power down mode for the reference to settle In 10 DISABLE partial full power down mode maintain a logic low or a logic high on SCLK to minimize power consumption Transfer Fu
6. 207 REFERENCE VOLTAGE V n2 n2 n2 A c MAX1077 79 toc25 REFERENCE VOLTAGE N A 1077 79 toc26 REFERENCE VOLTAGE V 2 8 3 Li DS 40 15 10 35 6 85 2 4 6 50 100 150 TEMPERATURE C LOAD CURRENT mA LOAD CURRENT uA 7 6L20LXVW ZZOLXVM MAX1077 MAX1079 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference Pin Description FUNCTION Negative Analog Input Reference Voltage Output Internal 2 048V reference output Bypass REF with a 0 01uF capacitor and 4 7yF capacitor to RGND Reference Ground Connect RGND to GND Positive Analog Supply Voltage 2 7V to 3 6V Bypass Vpp with a 0 01uF capacitor and a 10uF D capacitor to G No Connection Ground GND is internally connected to EP Positive Logic Supply Voltage 1 8V to Vpp Bypass VL with a 0 01uF capacitor and a 10uF capacitor to GND Serial Data Output Data is clocked out on the rising edge of SCLK Convert Start Forcing CNVST high prepares the part for a conversion Conversion begins on the falling edge of CNVST The sampling instant is defined by the falling edge of CNVST Serial Clock Input Clocks data out of the serial interface SCLK also sets the conversion speed Positive Analog Input
7. MAX1077 92 2 3 fin 500kHz SINAD 61 20 2 SNR 61 208 90 E THD 81 7dB SFDR 83 5dB 88 m SEX ca 86 lt 84 82 100 200 300 400 500 0 125 250 375 500 625 ANALOG INPUT FREQUENCY kHz ANALOG INPUT FREQUENCY kHz TOTAL HARMONIC DISTORTION vs SOURCE IMPEDANCE MAX1077 79 toc16 THD dB dB TWO TONE IMD PLOT MAX1077 7 4 250 102kHz 299 966 7 D 86 6dB MAX1077 79 S0 URCE 100 MPEDANC E Q 1000 AMPLITUDE mam 125 250 ANALOG INPUT F PI 375 50 REQUE diit THD dB AMPLITUDE dB AMPLITUDE dB 80 84 88 92 Vpp 8V VL Vpp fscLk 24 2 fsamPLe 1 5Msps TA to Tmax unless otherwise noted Typical values are at TA 25 C THD vs INPUT FREQUENCY MAX1077 79 toc12 200 300 400 ANALOG INPUT FREQUENCY kHz FFT PLOT MAX1079 fiy 500kHz SINAD 61 2d SNR 61 208 THD 91 3dB SFDR 88 708 1077 79 toc15 125 250 375 500 625 ANALOG INPUT FREQUENCY kHz TWO TONE IMD PLOT MAX1079 fit 250 102kHz fio 299 966kHz D 83 4dB MAX1077 79 toc18 125 250 ANALOG INPUT FREQUE 375 500 625 CY kHz T50 MAXIM 1 5Msps Single Supply Low Power True Differential 10
8. the first five harmonics and the DC offset Signal to Noise Plus Distortion Signal to noise plus distortion SINAD is the ratio of the fundamental input frequency s RMS amplitude to the RMS equivalent of all other ADC output signals SINAD aB 20 x log SignalnMs NoisenMS Effective Number of Bits Effective number of bits ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate An ideal ADC s error consists of quantiza tion noise only With an input range equal to the full scale range of the ADC calculate the ENOB as follows SINAD 1 76 6 02 ENOB 16 SUPPLIES GND GND RGND DGND Vy MAXIM MAX1077 DIGITAL CIRCUITRY MAX1079 Figure 20 Power Supply Grounding Condition Total Harmonic Distortion Total harmonic distortion THD is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself This is expressed as 2 2 2 2 M V V V THD 20xlog where V4 is the fundamental amplitude and V2 through V5 are the amplitudes of the 2nd through 5th order harmonics Spurious Free Dynamic Range Spurious free dynamic range SFDR is the ratio of the RMS amplitude of the fundamental maximum signal component to the RMS value of the next largest distor tion component Full Power Bandwidth Full power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full
9. Bit ADCs with Internal Reference Typical Operating Characteristics continued Vpp 8V VL 24 2 fsaMPLE 1 5Msps TA to Tmax unless otherwise noted Typical values are at TA 25 Vpp Vy FULL POWER DOWN Vi PARTIAL FULL POWER DOWN Vpp SUPPLY CURRENT SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE vs TEMPERATURE 1 00 100 amp 90 5 CONVERSION d 5 75 E lt 0 80 5 45 3 5 60 06 Z VL 1 8V SCLK 24MHz amp a amp VL 3V SCLK 24MHz gt Vi NO SCLK 50 45 ram 27 Aal 2 040 E z 2 o 30 ARTIAL POWER DOWN J S 25 S gt 020 15 0 0 0 0 85 0 85 40 45 10 35 60 85 TEMPERATURE TEMPERATURE TEMPERATURE Vpp SUPPLY CURRENT Vi SUPPLY CURRENT Vi SUPPLY CURRENT vs CONVERSION RATE vs TEMPERATURE vs CONVERSION RATE 8 E 0 50 g 250 3 z 2 _040 a CONVERSION Vi E 0 30 E 150 52 24 CONVERSION Vi o E 10 3 0 20 amp 10 LE E gt 010 50 0 0 0 0 250 500 750 1000 1250 1500 400 45 10 35 60 85 0 250 500 750 1000 1250 1500 KHz TEMPERATURE fsampLe KHz REFERENCE VOLTAGE REFERENCE VOLTAGE REFERENCE VOLTAGE vs TEMPERATURE vs LOAD CURRENT SOURCE vs LOAD CURRENT SINK
10. Internal 2 048V Reference No Pipeline Delays Small 12 Pin TQFN Package 9 9 9 9 9 9 9 low power dissipation excellent AC performance and DC Ordering Information accuracy x0 5 LSB INL make the MAX1077 MAX1079 ideal for industrial process control motor control and PART TEMP RANGE PIN INPUT base station applications PACKAGE The MAX1077 MAX1079 come in a 12 pin TQFN pack MAX1077C 0 70 12TQFN 12 Unipolar age and are available in the commercial 0 C to 70 C MAX1077E 40 C to 85 C 12 TQFN 12 Unipolar and extended 40 C to 85 C temperature ranges MAX1079C 0 C to 70 12 TQFN 12 Bipolar j 40 2 TQFN Bipol Applications MAX1079E 40 C to 85 C 12 TQFN 12 ipolar Data Acquisition Communications Bill Validation Portable Instruments Motor Control Pin Configuration Typical Operating Circuit TOP VIEW 0 SCLK 1 8V TO Vpp 2 7V TO 43 6V 10uF MAXIM DIFFERENTIAL DOUT 1077 _ a MAX1079 077 1079 CNVYST SCLK uC DSP SPI QSPI are trademarks of Motorola Inc MICROWIRE is a trademark of National Semiconductor Corp MAXIM Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Dallas Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 6L20LXVW ZZOLXVM MAX1077 MAX1079 1 5Msps Singl
11. _ family of DSPs from Analog Devices Inc Figure 19 shows the direct connection of the MAX1077 MAX1079 to the ADSP21_ _ _ There are two modes of operation that can be programmed to interface with the MAX1077 MAX1079 For continuous conver sions idle CNVST low and pulse it high for one clock cycle during the LSB of the previous transmitted word The ADSP21__ _ STCTL and SRCTL registers should be configured for early framing LAFR 0 and for an active high frame LTFS 0 LRFS 0 signal In this mode the data independent frame sync bit DITFS 1 MAKIN 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference DOUT CO CO X 0 AD D XDS Db ADI SI A90 0 Figure 18 DSP Interface Single Conversion Continuous Burst Clock can be selected to eliminate the need for writing to the transmit data register more than once For single conver sions idle CNVST high and pulse it low for the entire conversion The ADSP21 _ _ STCTL SRCTL regis ters should be configured for late framing LAFR 1 and for an active low frame LTFS 1 LRFS 1 signal This is also the best way to enter the power down modes by setting the word length to 8 bits SLEN 1001 Connect the VL pin to the ADSP21 _ _ supply voltage when the MAX1077 MAX1079 are operat
12. for VL gt 2 7V See the Typical Operating Characteristics section for recommended sampling speeds for VL lt 2 7 Note 8 Digital supply current is measured with the level equal to VL and the VIL level equal to GND CNVST 9 a tpouT gt GND a HIGH Z TO TO b HIGH Z TO VoL TO VoL AND Vou TO HIGH Z AND TO HIGH Z Figure 1 Detailed Serial Interface Timing Figure 2 Load Circuits for Enable Disable Times 4 MAKII 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference Typical Operating Characteristics Vpp 8V VL Vpp fscLkK 24 2 fsamPLE 1 5Msps TA to Tmax unless otherwise noted Typical values are at TA 25 C INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY MAXIMUM RECOMMENDED fsciy vs VL vs DIGITAL OUTPUT CODE MAX1077 vs DIGITAL OUTPUT CODE MAX1079 25 5 20 E 2 8 E 15 015 E 23 10 1 3 S g 005 005 2 2 4 Mp UM 5 os MA i E f P 15 15 17 0 20 02 18 21 24 27 30 33 36 0 256 512 768 1024 512 256 0 256 512 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARI
13. the 16th SCLK ris ing edges If CNVST stays low after the falling edge of the 16th SCLK cycle the DOUT line goes to a high impedance state on either CNVST s rising edge or the next SCLK s rising edge Partial Power Down and Full Power Down Modes Power consumption can be reduced significantly by placing the MAX1077 MAX1079 in either partial power down mode or full power down mode Partial power down mode is ideal for infrequent data sampling and fast wake up time applications Pull CNVST high after the 3rd SCLK rising edge and before the 14th SCLK rising edge to enter and stay in partial power down mode see Figure 6 This reduces the supply current to 2mA While in partial power down mode the refer ence remains enabled to allow valid conversions once the IC is returned to normal mode Drive CNVST low and allow at least 14 SCLK cycles to elapse before dri ving CNVST high to exit partial power down mode Full power down mode is ideal for infrequent data sam pling and very low supply current applications The MAX1077 MAX1079 have to be in partial power down mode to enter full power down mode Perform the SCLK CNVST sequence described above to enter 6L20LXVW ZZOLXVM MAX1077 MAX1079 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference V tsetup 05 4 POWER MODE SELECTION WINDOW gt 4 de nj sam
14. using the end points method Differential Nonlinearity Differential nonlinearity DNL is the difference between an actual step width and the ideal value of 1 LSB A DNL error specification of 1 LSB or less guarantees no missing codes and a monotonic transfer function Aperture Jitter Aperture jitter tau is the sample to sample variation in the time between the samples 15 6L20LXVW ZZOLXVM MAX1077 MAX1079 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference MAKI Vi VDDINT MAX1077 SCLK TCLK MAX1079 ADSP21__ _ RCLK CNVST TFS RFS DOUT DR Figure 19 Interfacing to the ADSP21__ _ Aperture Delay Aperture delay tap is the time defined between the falling edge of CNVST and the instant when an actual sample is taken Signal to Noise Ratio For a waveform perfectly reconstructed from digital sam ples signal to noise ratio SNR is the ratio of full scale analog input RMS value to the RMS quantization error residual error The theoretical minimum analog to digital noise is caused by quantization error and results directly from the ADC s resolution N bits SNR 6 02 x 1 76 dB In reality there are other noise sources besides quantiza tion noise including thermal noise reference noise clock jitter etc Therefore SNR is computed by taking the ratio of the RMS signal to the RMS noise which includes all spectral components minus the fundamental
15. IN AIN 1079 2 Absolute Input Voltage Range oo DC Current Differential Input Voltage Range VIN Input Current Average Time averaged at maximum throughput rate REFERENCE OUTPUT REF REF Output Voltage Range Static Ta 25 2 038 2048 2058 v Voltage Temperature Coefficient ISOURCE 0 to 2mA ISINK to 100A Load Regulation Input Voltage Low Input Voltage High Input Leakage Current DIGITAL OUTPUT DOUT Output Load Capacitance For stated timing performance Output Voltage Low 5 VL 1 8V Output Voltage High ISOURCE 1mA VL 2 1 8V Output Leakage Current Output high impedance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Static 24MHz Static no SCLK Operational 1 DP og Supply Current CLK 24M ial Power Down Mode P o SCLK og Supply Current CLK 24M Power Down Mode s SCLK Operational full scale input at 1 5Msps Static 24MHz Digital Supply Current Note 8 Partial full power down mode 24MHz Static no SCLK all modes Positive Supply Rejection Vpp 20 10 full scale input Analog Supply Current Normal Mode 3 6L20LXVW ZZOLXVM MAX1077 MAX1079 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference TIMING CHARACTERISTICS
16. NTIAL INPUT mode and DOUT to transition from high impedance to VOLTAGENESB being actively driven low A total of 16 SCLK cycles are required to complete a normal conversion If CNVST is Figure 8 Unipolar Transfer Function MAX1077 Only low during the 16th falling SCLK edge DOUT returns to high impedance on the next rising edge of CNVST or SCLK enabling the serial interface to be shared by multi OUTPUT CODE ple devices If CNVST returns high after the 14th but before the 16th SCLK rising edge DOUT remains active VREF FULL SCALE so continuous conversions can be sustained The high 011 111 TRANSITO est throughput is achieved when performing continuous 011 110 conversions Figure 10 illustrates a conversion using a typical serial interface FS 3 2 LSB _ VREF 1LSB 3024 Connection to Standard Interfaces The MAX1077 MAX1079 serial interface is fully compati ble with SPI QSPI and MICROWIRE see Figure 11 If a serial interface is available set the CPU s serial interface in master mode so the CPU generates the serial clock Choose a clock frequency up to 24MHz SPI and MICROWIRE When using SPI or MICROWIRE the MAX1077 MAX1079 are compatible with all four modes programmed with the CPHA and CPOL bits in the SPI or MICROWIRE control register Conversion begins with a CNVST falling edge DOUT goes low indicating a conversion is in progress DIFFERENTIAL INPUT Two consecutive 1 byte reads are required to get the full VOL
17. POSSIBLE IN A SYMMETRICAL FASHION A COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS 9 DRAWING CONFORMS TO MO220 EXCEPT FOR 72444 1 T2444 3 AND T2444 4 VILAXL VI PROPRETHEY MFORTION PACKAGE OUTLINE 12 16 20 24L THIN QFN 4 4 0 8 APPROVAL TOCUENT CONTROL 21 0139 REV Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at 18 2004 Maxim Integrated Products Printed USA MAXIM is any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 a registered trademark of Maxim Integrated Products
18. Single Conversion CPOL 1 CPHA 1 remains valid until tpHOLD after the following SCLK rising edge When using CPOL 0 and CPHA 0 or CPOL 1 and CPHA 1 the data is clocked into the uP on the following rising edge When using CPOL 0 and CPHA 1 or CPOL 1 and CPHA the data is clocked into the uP on the next falling edge See Figure 11 for connections and Figures 12 and 13 for timing See the Timing Characteristics section to determine the best mode to use QSPI Unlike SPI which requires two 1 byte reads to acquire the 10 bits of data from the ADC QSPI allows the mini mum number of clock cycles necessary to clock in the MAKIM data The MAX1077 MAX1079 require 16 clock cycles from the uP to clock out the 10 bits of data Figure 14 shows a transfer using CPOL 1 and CPHA 1 The conversion result contains three zeros followed by the 10 data bits 2 sub bits and a trailing zero with the data in MSB first format DSP Interface to the TMS320C54_ The MAX1077 MAX1079 can be directly connected to the TMS320C54_ family of DSPs from Texas Instruments Inc Set the DSP to generate its own clocks or use external clock signals Use either the standard or buffered serial port Figure 15 shows the simplest interface between the MAX1077 MAX1079 and 13 6L20LXVW ZZOLXVM MAX1077 MAX1079 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference MAXIM P DVpp 1077 5
19. TAGE LSB 10 bits from the ADC DOUT transitions on SCLK rising edges DOUT is guaranteed to be valid tpour later and Figure 9 Bipolar Transfer Function MAX1079 Only MAXUM 11 6L20LXVW ZZOLXVM MAX1077 MAX1079 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference CNVST suk LE LLL LLL LLL T DOUT CU KOK OX OTK DEK OE KOK KOKO KOKI KH XO 5 Figure 10 Continuous Conversion with Burst Continuous Clock CNVST SCLK DOUT 4 3V TO 51 MAXIM MAX1077 MAX1079 CNVST SCLK DOUT 3V TO 5V MAXIM MAX1077 MAX1079 B QSPI CNVST SCLK DOUT MAXIM MAX1077 MAX1079 C MICROWIRE Figure 11 Common Serial Interface Connections to the MAX1077 MAX 1079 12 MAKIN 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference CNVST HIGH Z DOUT N Figure 12 SP MICROWIRE Serial Interface Timing Single Conversion CPOL 0 1 PUI UDO LIE ET LT LI LI Le Figure 13 SPI MICROWIRE Serial Interface Timing Continuous Conversion CPOL 0 CPOL 1 HIGH Z HIGH Z A XX or X ns X 05 Xo Xos X 01 X po st X so Figure 14 QSPI Serial Interface Timing
20. TY DIFFERENTIAL NONLINEARITY OFFSET ERROR vs DIGITAL OUTPUT CODE MAX1077 vs DIGITAL OUTPUT CODE MAX1079 vs TEMPERATURE MAX1077 0 15 3 45 E 0 10 3 40 2 a 005 005 2 9 4 amp 1 00 i EX a 0 05 0 05 e e 0 10 10 1 50 0 15 15 0 20 0 20 2 00 0 256 512 768 1024 512 256 0 256 512 4 15 10 35 60 85 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE TEMPERATURE C OFFSET ERROR GAIN ERROR GAIN ERROR vs TEMPERATURE MAX1079 vs TEMPERATURE MAX1077 vs TEMPERATURE MAX1079 0 5 1 00 E 1 00 3 050 0 50 _ 050 2 8 3 5 amp 1 00 0 0 c 150 0 50 0 50 2 00 1 00 1 00 40 15 10 35 60 85 40 51 35 60 85 40 5 10 35 60 85 TEMPERATURE C TEMPERATURE C TEMPERATURE C 5 6L20LXVW ZZOLXVM MAX1077 MAX1079 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference Typical Operating Characteristics continued MAX1077 79 toc11 500 1077 79 10214 DYNAMIC PERFORMANCE DYNAMIC PERFORMANCE vs INPUT FREQUENCY MAX1077 vs INPUT FREQUENCY MAX1079 62 0 62 0 SNR AND SINAD E SNR AND SINAD 615 1 T 5 615 c cc cc 52 610 610 a Q ce ce 605 605 60 0 60 0 100 200 300 400 500 100 200 300 400 ANALOG INPUT FREQUENCY kHz ANALOG INPUT FREQUENCY kHz SFDR vs INPUT FREQUENCY FFT PLOT
21. Vpp 2 7V to 3 6V VL Vpp 24MHz 50 duty cycle TA to Tmax unless otherwise noted Typical values are at TA 25 PARAMETER SYMBOL CONDITIONS 2 7V to VDD SCLK Pulse Width High 1 8V to Vpp minimum recommended ote 7 2 7V to VDD SCLK Pulse Width Low 1 8V to VDD minimum recommended ote 7 L 30pF VL 2 7V to VDD L 30pF VL 1 8V to VDD DOUT Remains Valid After SCLK 1 8V to VDD CNVST Fall to SCLK Fall 1 8V to VDD CNVST Pulse Width 1 8V to VDD Power Up Time Full Power Down Restart Time Partial Power Down SCLK Rise to DOUT Transition Note 1 Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset error have been nulled Note 2 No missing codes over temperature Note 3 Conversion time is defined as the number of clock cycles 16 multiplied by the clock period Note 4 At sample rates below 10ksps the input full linear bandwidth is reduced to 5kHz Note 5 The listed value of three SCLK cycles is given for full speed continuous conversions Acquisition time begins on the 14th ris ing edge of SCLK and terminates on the next falling edge of CNVST The IC idles in acquisition mode between conversions Note 6 Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance Note 7 1 5Msps operation guaranteed
22. e Supply Low Power True Differential 10 Bit ADCs with Internal Reference ABSOLUTE MAXIMUM RATINGS VpDAO 4GND ch tet dte een edet 0 3V to 6V VL to GND 0 3V to the lower of Vpp 0 3V and 6V Digital Inputs to 0 3V to the lower of Vpp 0 3V and 6V Digital Output to 0 3V to the lower of VL 0 3V and 6V Analog Inputs and REF to GND 0 3V to the lower of Vpp 0 3V and 6V ROND O OND eb eed ree 0 3V to 0 3V Maximum Current into Any 2 2 50 Continuous Power Dissipation TA 70 12 Pin TQFN derate 16 9mW C above 70 1349mW Operating Temperature Ranges MAXIQY GIO s tette es 0 C to 70 C MAX107_ 409 to 85 Junction Temperature Storage Temperature Range a Lead Temperature soldering 105 300 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS Vpp 2 7V to 3 6V VL VDD 24MHz 50 duty cycle TA to Tmax
23. ing with a sup ply voltage higher than the DSP supply voltage see Figures 17 and 18 Layout Grounding and Bypassing For best performance use PC boards Wire wrap boards are not recommended Board layout should ensure that digital and analog signal lines are separat ed from each other Do not run analog and digital especially clock lines parallel to one another or digital lines underneath the ADC package Figure 20 shows the recommended system ground connections Establish a single point analog ground star ground point at GND separate from the logic ground Connect all other analog grounds and DGND to this star ground point for further noise reduction The ground return to the power supply for this ground should be low impedance and as short as possible for MAKIM noise free operation High frequency noise in the power supply can affect the ADC s high speed comparator Bypass this supply to the single point analog ground with 0 01uF and 10uF bypass capacitors Minimize capacitor lead lengths for best supply noise rejection Definitions Integral Nonlinearity Integral nonlinearity INL is the deviation of the values on an actual transfer function from a straight line This straight line can be either a best straight line fit or a line drawn between the end points of the transfer function once offset and gain errors have been nullified The static linearity parameters for the MAX1077 MAX1079 are mea sured
24. nction Figure 8 shows the unipolar transfer function for the MAX1077 Figure 9 shows the bipolar transfer function for the MAX1079 The MAX1077 output is straight binary while the MAX1079 output is two s complement MAKII 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference Applications Information OUTPUT CODE Internal Reference The MAX1077 MAX1079 have an on chip voltage refer FULL SCALE ence trimmed to 2 048V The internal reference output TRANSITION is connected to REF and also drives the internal capac 2110 itive DAC The output can be used as a reference volt age source for other components and can source up to 2mA Bypass REF with a 0 01uF capacitor and a 4 7uF capacitor to RGND The internal reference is continuously powered up dur ing both normal and partial power down modes In full power down mode the internal reference is disabled Be sure to allow at least 2ms recovery time after hard ware power up or exiting full power down mode for the reference to reach its intended value 41015 FS VREF 75 0 _ 115 1024 A How to Start Conversion An analog to digital conversion is initiated by CNVST and clocked by SCLK and the resulting data is clocked out on DOUT by SCLK With SCLK idling high or low a falling edge on CNVST begins a conversion This causes the analog input stage to transition from track to hold DIFFERE
25. re RIN 2000 and RS is the source impedance of the input signal Note tACQ is never less than 125ns and any source impedance below 120 does not significantly affect the ADC s AC performance Input Bandwidth The ADC s input tracking circuitry has a 15MHz small signal bandwidth making it possible to digitize high speed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques To avoid high fre quency signals being aliased into the frequency band of interest anti alias filtering is recommended Analog Input Protection Internal protection diodes that clamp the analog input to Vpp and GND allow the analog input pins to swing from GND 0 3V to Vpp 0 3V without damage Both inputs must not exceed Vpp or be lower than GND for accurate conversions MAXIM 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference CONTROL LOGIC AND TIMING MAXI VAI 1077 1079 Figure 3 Functional Diagram Serial Interface Initialization After Power Up and Starting a Conversion Upon initial power up the MAX1077 MAX1079 require a complete conversion cycle to initialize the internal cali bration Following this initial conversion the part is ready for normal operation This initialization is only required after a hardware power up sequence and is not required after exiting partial or full power do
26. rial clock CLOCK drives the CLKR and SCLK and the convert signal CONVERT drives the FSR and CNVST The serial port must be set up to accept an external receive clock and external receive frame sync The SPC register should be written as follows 0 external frame sync 14 MAXIM Vi DVpp MAX1077 MAX1079 SCLK CLKR TMS320054_ CNVST FSR DR CONVERT Figure 16 Interfacing to the 5320 54 External Clocks MCM 0 CLKX is taken from the CLKX pin FSM 1 burst mode FO 0 data transmitted received as 16 bit words This setup allows continuous conversion provided that the DRR is serviced before the next conversion Alternatively autobuffering can be enabled when using the buffered serial port to read the data without CPU intervention Connect the VL pin to the TMS3820C54_ supply voltage when the MAX1077 MAX1079 are oper ating with an analog supply voltage higher than the DSP supply voltage The MAX1077 MAX1079 can also be connected to the TMS320C54_ by using the data transmit DX pin to drive CNVST and the CLKX generated internally to drive SCLK A pullup resistor is required on the CNVST signal to keep it high when DX goes high impedance and 0001hex should be written to the DXR continuously for continuous conversions The power down modes can be entered by writing OOFFhex to the DXR see Figures 17 and 18 DSP Interface to the ADSP21__ The MAX1077 MAX1079 can be directly connected to the ADSP21_ _
27. scale input MAKII 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference Full linear bandwidth Full Linear Bandwidth is the frequency at which the sig nal to noise plus distortion SINAD is equal to 56dB Any device with nonl Intermodulation Distortion inearities creates distortion prod ucts when two sine waves at two different frequencies f1 and f2 are input into the device Intermodulation distortion IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency rela tive to the total input and f2 The individual power of the two input tones f1 input tone levels are at 7dBFS The intermodulation products are as follows e 2nd order intermodulation products IM2 f4 f2 fo fH e intermodulation products IM3 2f4 fo 2f2 4 29 fo 2fo fy e Ath order intermodulation products IM4 3f4 f2 314 fo 3fo f4 e 5th order intermodulation products IM5 3f1 2f2 2H 2fo 3fo 2f4 Chip Information TRANSISTOR COUNT 13 016 PACKAGE INFO T1244 3 PROCESS 5 17 6L20LXVW ZZOLXVM MAX1077MAX1079 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference The package drawing s in this data sheet may not reflect the most current sp go to www maxim ic com packages INDEX AREA 0 2 X 2 A
28. unless otherwise noted Typical values are at TA 25 PARAMETER SYMBOL CONDITIONS MIN TYP DC ACCURACY Resolution 10 Relative Accuracy Note 1 0 5 40 5 LSB LSB INL Differential Nonlinearity DNL 0 5 0 5 Offset Error LSB Offset Error Temperature Coefficient ppm C Gain Error Offset nulled LSB Gain Temperature Coefficient ppm C DYNAMIC SPECIFICATIONS fin 525kHz sine wave Vin Vref unless otherwise noted Signal to Noise Plus Distortion 60 6 Total Harmonic Distortion Up to the 5th harmonic dB Spurious Free Dynamic Range ntermodulation Distortion flN1 250kHz fiN2 300kHz Full Power Bandwidth point small signal method Full Linear Bandwidth CONVERSION RATE S N D gt 568B single ended inimum Conversion Time aximum Throughput Rate inimum Throughput Rate Track and Hold Acquisition Time Aperture Delay Aperture Jitter External Clock Frequency AVLAXL VI 1 5Msps Single Supply Low Power True Differential 10 Bit ADCs with Internal Reference ELECTRICAL CHARACTERISTICS continued Vpp 2 7V to 3 6V VL Vpp 24MHz 50 duty cycle TA to Tmax unless otherwise noted Typical values are at TA 25 PARAMETER SYMBOL CONDITIONS ANALOG INPUTS AIN AIN AIN AIN MAX1077 VREF A
29. wn mode To start a conversion pull CNVST low At CNVST s falling edge the T H enters its hold mode and a con version is initiated SCLK runs the conversion and the data can then be shifted out serially on DOUT Timing and Control Conversion start and data read operations are con trolled by the CNVST and SCLK digital inputs Figures 1 and 5 show timing diagrams which outline the serial interface operation A CNVST falling edge initiates a conversion sequence the T H stage holds the input voltage the ADC begins to convert and DOUT changes from high impedance to logic low SCLK is used to drive the conversion process and it shifts data out as each bit of the con version is determined SCLK begins shifting out the data after the 4th rising edge of SCLK DOUT transitions tpour after each SCLK s rising edge and remains valid 4ns tpHOLD after the next rising edge The 4th rising clock edge produces the MSB of the conversion at DOUT and the MSB remains valid 4ns after the 5th rising edge Since there are 10 data bits 2 sub bits 81 and SO and 3 leading zeros at least 16 rising clock edges are need MAKIM CAPACITIVE DAC AIN o CONTROL LOGIC CAPACITIVE DAC Vaz CONTROL LOGIC AIN o A uci e Cin HOLD CONVERSION MODE Figure 4 Equivalent Input Circuit ed to shift out these bits For continuous operation pull CNVST high between the 14th and
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MAXIM MAX1077/MAX1079 handbook(1)