RICOH Rx5C338A Manual
Contents
1. Vpp 3V External Ca 0pF ae Topt 25 C as standard 500 Topt 25 C 20 0 20 40 fea ee O 60 80 100 120 140 j Oscillation Start Time ms oan Frequency Deviation ppm 60 40 20 0 20 40 60 80 10 ft amp 8 Operating Temperature Topt C Supply Voltage VoD V 7 9 VoL vs lox INTR Pin 7 10 Input Current to CLKC Pin vs Supply Voltage i Topt 25 C 0 8 T x T 5 0 6 d fo a 2 0A e a S S 0 2 0 0 1 2 3 4 5 6 Supply Voltage VpD V RICOH Rx5C338A 8 Typical Software based Operations 8 1 Initialization at Power on Set Oscillation Adjustment Register and Control Registers 1 and 2 etc Warning of Backup Battery Run down 1 After power on from 0 volts the start of oscillation and the process of internal initialization require a time span on the order of 1 to 2 seconds so that access should be done after the lapse of this time span or more 2 The XSTP bit setting of 0 in the control register 1 indicates power on from backup battery and not from 0 volt The XSTP bit may fail to be set to 1 in the presence of any excessive chattering in power supply in such events as installing backup battery Should there be any possibility of this failure occurring it is recommended to initialize the RX5C338A regardless of the current XSTP bit setting For fur2. Wed Thu Fri Sat WWo WW1 WW2 WW3 WW4 WWs WWe Mondays to Fridays 11 59 p m on Mondays 10 hour hour 10min 1 min 10 hour L hour 10 min 1 min Wednesdays and Fridays Note that the correspondence between WWo to WW and the days of the week shown in the above table is only an example and not mandatory 2 8 Alarm_D Register at Address Bh and Ch 2 8 1 Alarm_D Minute Register at Address Bh 2 8 2 Alarm_D Hour Register at Address Ch D7 D6 D5 D4 D3 D2 D1 DO Default settings Default value means read written values when the XSTP bit is set to 1 due to power on from 0 volts or supply voltage drop The D5 bit represents DP A when the 12 hour mode is selected 0 for a m and 1 for p m and DH20 when the 24 hour mode is selected tens in the hour digits The Alarm_D registers should not have any non existent alarm time settings Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers may disable the alarm circuit When the 12 hour mode is selected the hour digits read 12 and 32 for 0 a m and 0 p m respectively see 2 1 2 12 24 12 24 hour Mode Selection Bit RICOH Rx5C338A USAGES 1 Data Transfer Formats 1 1 Timing Between CE Pin Transition and Data Input Output The RX5C338A adopt a 3 wire serial interface by which it uses the CE Chip Enable SCLK Serial Clock and SIO Serial Input Output pins to receive an
3. 3 This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data 4 This step is intended to set the CTFG bit to 0 in the control register 2 to cancel an interrupt to the CPU RICOH 46 Rx5C338A 8 4 Interrupt Process 8 4 1 Periodic Interrupt Set Periodic Interrupt Cycle Selection Bits Generate Interrupt to CPU y YES Periodic Interrupt Process Other Interrupt Y Processes Write x 1 x 1 x 0 1 1 to Control Register 2 8 4 2 Alarm Interrupt WALE or DALE 0 Set Alarm Minute Hour and Day of week Registers Y WALE or DALE 1 2 1 Generate Interrupt to CPU Y WAFG or DAFG 1 f YES Y Processes Write x 1 x 1 x 1 0 1 to Control Register 2 1 This step is intended to select the level mode as a waveform mode for the periodic interrupt function 2 This step is intended to set the CTFG bit to 0 in the control register 2 to cancel an interrupt to the CPU 1 This step is intended to once disable the alarm interrupt circuit by setting the WALE and DALE bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function 2 This step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings 3 This step is intended to once cancel the alarm inte
4. RV5C338A with a height of 1 2mm and a pin pitch of 0 5mm FEATURES e Timekeeping supply voltage ranging from 1 45 to 5 5 volts e Low supply current TYP 0 35uA MAX 0 84A at 3 volts at 25 C e Only three signal lines SCLK SIO and CE required for connection to the CPU Maximum clock frequency of 2 MHz with VDD of 5 volts e Time counters counting hours minutes and seconds and calendar counters counting years months days and weeks in BCD format 1900 2000 identification bit for Year 2000 compliance Interrupt circuit configured to generate interrupt signals with interrupts ranging from 0 5 seconds to 1 month to the CPU and provided with an interrupt flag and an interrupt halt circuit e 2 alarm circuits Alarm_W for week hour and minute alarm settings and Alarm_D for hour and minute alarm settings e 32 kHz clock circuit CMOS output equipped with a control pin e Oscillation halt sensing circuit which can be used to judge the validity of internal data Supply voltage monitoring circuit with two supply voltage monitoring threshold settings e Automatic identification of leap years up to the year 2099 Selectable 12 hour and 24 hour mode settings e Built in oscillation stabilization capacitors Cc and Cp e High precision oscillation adjustment circuit e CMOS process Ultra compact 10 pin SSOP RS5C338A with a height of 1 25mm and size of 6 4X3 5mm Ultra compact 10 pin SSOP G RV5C338A with a height of 1 20mm and siz
5. tl H 3 WIRE SERIAL INTERFACE REAL TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION Rx5C0338A NO EA 053 0208 OUTLINE The RX5C338A are CMOS real time clock ICs connected to the CPU by three signal lines CE Chip Enable SCLK Serial Clock and SIO Serial Input Output and configured to perform serial transmission of time and calendar data to the CPU These models incorporate different functional circuits The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0 5 seconds to 1 month The 2 alarm circuits generate interrupt signals at preset times The oscillation circuit is driven under constant voltage so that fluctuations in oscillation frequency due to voltage are small and supply current is also small TYP 0 354A at 3 volts The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power on The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings The 32 kHz clock output function is intended to output sub clock pulses for the external microcomputer The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator These models come in an ultra compact 10 pin SSOP RS5C338A with a height of 1 25mm and a pin pitch of 0 5mm and 10 pin SSOP G
6. ih Specifying Oh in the Reading from Specifying 1h in the Reading from Reading from address pointer the second address pointer the minute the hour counter Writing Ch in the counter Writing 4h in the counter at address 2h transfer format register at address Oh transfer format register at address 1h Bad Example 2 Where a time span of less than 31s is left until the start of the process of writing time data Time spanoflessthan31us SIO FOh Specifying Fh in the Writing to the Writing to the Writing tothe Writingtothe address pointer control register 2 second counter minute counter hour counter Writing Oh tothe ataddressFh ataddressOh ataddressih ataddress2h transfer format register Bad Example 3 Where a time span of less than 61us is left between the adjacent processes of reading time data Timespanof lessthan61us CE TF mooo SIO och M Daa OCh X Data Specifying Oh in the Reading from the Specifying Oh in the Reading from the address pointer second counter address pointer second counter Writing Chtothe ataddressOh Writing Ch to the ataddressOh_ transfer format register transfer format register Data transfer from the host Data transfer from the real time clocks RICON 26 Rx5C338A 2 Configuration of Oscillation Circuit and Correction of Time Count Deviations 2 1 Configuration of Oscillating Circ
7. 2Hz once per 0 5 seconds 1Hz once per 1 second 1 60Hz once per 1 minute 1 3600Hz once per 1 hour and monthly the first day of every month Further periodic interrupt signals also have two selectable waveforms of a normal pulse form with a frequency of 2Hz or 1Hz and special form adapted to interruption from the CPU in the level mode with second minute hour and month interrupts The register records of periodic interrupt signals can be monitored by using a polling function 7 32 kHz Clock Output Function The RX5C338A incorporate a 32 kHz clock circuit configured to generate clock pulses with the oscillation frequency of a 32 768 kHz crystal oscillator for output from the 32KOUT pin The 32KOUT pin is CMOS output and the output from this pin is enabled and disabled when the CLKC pin is held high and low or open respectively The 32 kHz clock output can be disabled by certain register settings But it cannot be disabled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the CPU The 32 kHz clock circuit is enabled at power on when the CLKC pin is held high RICOH Rx5C338A FUNCTIONAL DESCRIPTIONS 1 Address Mapping aE eee perf oe fee je foe fe fe DOODO fp Tete aio Minute Counter Counter Ma Moo Hour Counter a A peepee 1 Day ofweek Counter of Day ofweek Counter Counter nee eer Ep e i fercera f fef Year Counte
8. 41 in 7 bit coded decimal notation subtract 41 29h from 128 80h to obtain 57h In this instance write the settings of 1 0 1 0 1 1 1 in the Fe Fs F4 F3 F2 Fi and Fo bits in the oscillation adjustment register Thus an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h Oscillation adjustment involves an adjustment differential of approximately 1 5ppm from the target frequency at normal temperature 1 Oscillation adjustment does not affect the frequency of 32 768 kHz clock pulses output from the 32KOUT pin 2 Oscillation adjustment value range When the oscillation frequency is higher than the target frequency causing a time count gain an appropriate time count gain ranges from 3 05ppm to 189 2ppm with the settings of 0 0 0 0 0 1 0 to 0 1 1 1 1 1 1 written to the Fe Fs F4 F3 F2 Fi and Fo bits in the oscillation adjustment register thus allowing correction of a time count gain of up to 189 2ppm Conversely when the oscillation frequency is lower than the target frequency causing a time count loss an appropriate time count gain ranges from 3 05ppm to 189 2ppm with the settings of 1 1 1 1 1 1 1 to 1 0 0 0 0 1 0 written to the Fe Fs F4 F3 F2 F1 and Fo bits in the oscillation adjustment register thus allowing correction of a time count loss of up to 189 2ppm RICOH 31 32 Rx5C
9. Counter at Address 6h D7 D6 D5 D4 D3 D2 D1 DO Y80 Y40 Y20 Y10 Ys For writing Ys80 Y40 Y20 Y10 Ys Y4 For reading Default settings Default value means read written values when the XSTP bit is set to 1 due to power on from 0 volts or supply voltage drop 2 6 Oscillation Adjustment Register at Address 7h For writing For reading Default settings Default settings Default value means read written values when the XSTP bit is set to 1 due to power on from 0 volts or supply voltage drop 2 6 1 0 Bit The 0 bit should be set to 0 to allow writing to the oscillation adjustment register The 0 bit will be set to 0 when the XSTP bit is set to 1 in the control register 2 2 6 2 Fe to Fo The oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register when the second digits read 00 20 or 40 seconds Normally the second counter is incremented once per 32768 32 768 kHz clock pulses generated by the crystal oscillator Writing to the Fe to Fo bits activates the oscillation adjustment circuit The oscillation adjustment circuit will not operate with the same timing 00 20 or 40 seconds as the timing of writing to the oscillation adjustment register The F6 bit setting of 0 causes an increment of time counts by F5 F4 F3 F2 F1 Fo 1 x 2 The F bit setting of 1 causes a decrement of time counts b
10. particularly in systems with a temperature sensing function through oscillation adjustment in tune with temperature fluctuations RICOH Rx5C338A 5 Oscillation Halt Sensing Function and Supply Voltage Monitoring Function The RX5C338A incorporate an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt thereby identifying whether they are powered on from 0 volts or battery backed up As such the oscillation halt sensing circuit is useful for judging the validity of time data The RX5C338A also incorporate a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value Supply voltage monitoring threshold settings can be selected between 2 1 and 1 6 volts through internal register settings The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data Further the supply voltage monitoring circuit can be applied to battery supply voltage monitoring 6 Periodic Interrupt Function The RX5C338A incorporate a periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm circuit for output from the INTR pin Periodic interrupt signals have five selectable frequency settings of
11. simultaneously Operation above these absolute maximum ratings may cause degradation or permanent damage to the device These are stress ratings only and do not necessarily imply functional operation below these limits RECOMMENDED OPERATING CONDITIONS PENE E E eee sma m OO conons O un e a o RICON Rx5C338A DC ELECTRICAL CHARACTERISTICS Unless otherwise specified Vss 0V VDD 3V Topt 40 to 85 C seme mf re eos ao L Input Voltage SCLK CE SIO CLKC INTR VoL 0 4V L Output Current somom oon rt Vi 5 5V or Vss t Leak C t SCLK ii ii ii aw e vo 9 ay rtf fe jako Ran ee EE Pull down Resistance CLKC Input Current Vo 5 5V or Vss VDD 5 5V Vo 5 5V Output Off state Leakage Current Supply Voltage Monitoring Voltage H Topt 30 to 70 C Supply Voltage Monit upply Voltage Monitoring Topt 30 to 70 C Voltage L Internal Oscillation Capacitance 1 OSCIN Internal Oscillation Capacitance 2 OSCOUT P ll 1 For standby current for outputting 32 768 kHz clock pulses from the 32KOUT pin see USAGES 7 Typical Characteristics Vpp 3V CE OPEN Standby Current Output OPEN 32KOUT Off mode RICOH Rx5C338A AC ELECTRICAL CHARACTERISTICS Unless otherwisespecified Vss 0V Topt 40 to 85 C Input output conditions Vin 0 8 x VDD ViL 0 2 x VDD VoH 0 8 x VDD VoL 0 2 x VDD CL 50pF ji veneers mm ave max min TYP
12. the output of 32 768 kHz clock pulses from the 32KOUT pin 82KOUT output is disabled when CLKC pin is set to low The XSTP bit accepts only the writing of 0 which restarts the oscillation halt sensing circuit Conversely setting the XSTP bit to 1 causes no event 2 2 5 CLEN1 32 kHz Clock Output Bit 1 aaa Enabling the 32 kHz clock output Default setting Disabling the 32 kHz clock output Setting the CLEN1 bit or the CLEN2 bit D4 in control register 1 to 0 and the CLKC pin to high specifies generating clock pulses with the oscillation frequency of the 32 768 kHz crystal oscillator for output from the 32KOUT pin Conversely setting both the CLEN1 bit and the CLEN2 bit to 1 or the CLKC pin to low specifies disabling L such output 2 2 6 CTFG Periodic Interrupt Flag Bit i ae Periodic interrupt output H OFF Default setting Periodic interrupt output L ON The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTR pin L The CTFG bit accepts only the writing of 0 in the level mode which disables H the INTR pin until it is enabled L again in the next interrupt cycle Conversely setting the CTFG bit to 1 causes no event RICOH Rx5C338A 2 2 7 WAFG and DAFG Alarm_W Flag Bit and Alarm_D Flag Bit fF lo Indicating a mismatch between current time and preset alarm time Default setting Indicating a match between current time and prese
13. 338A 3 Oscillation Halt Sensing and Supply Voltage Monitoring The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32 768 kHz clock pulses The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2 1 or 1 6 volts For these functions the real time clock has two flag bits i e the XSTP bit for the former and the VDET bit for the latter in which 1 is set once and this setting is maintained until 0 is written When the XSTP bit is set to 1 for the oscillation halt sensing circuit the VDET bit is reset to 0 for the supply voltage monitoring circuit The relationship between the XSTP and VDET bits is shown in the table below The Oscillation halt sensing circuit operates only when the CE pin is Low The sensing result is maintained after the CE pin changes from L to H See 6 4 Connection of CE Pin XSTP VDET Conditions of supply voltage and oscillation oo o No drop in supply voltage below threshold voltage and no halt in oscillation oga Drop in supply voltage below threshold voltage and no halt in oscillation Halt on oscillation Threshold voltage 2 1 or 1 6 volts Supply voltage Normal voltage detector Supply voltage monitoring VDET Y Y Y i Oscillation halt sensing XSTP d i Internal initialization Setting XSTP and Setting VDET bit to 0 Setting XSTP and period VDET bits to 0 VD
14. Allows a maximum input voltage of 5 5 volts regard less of supply voltage The SIO pin is used to input and output data intended for writing and reading in 3 SIO Serial Input Output oak synchronization with the SCLK pin CMOS input output The INTR pin is used to output periodic interrupt signals to the CPU and alarm interrupt signals Alarm_W Alarm_D Disabled at power on from 0 volts Nch open drain output The 32KOUT pin is used to output 32 768 kHz clock pulses Enabled at power on from 0 volts CMOS output This pin is disabled if the CLKC pin is set to low or open The CLCK pin is used to control output of the 32KOUT pin The clock output is disabled and held low when the pin is set to low or open Incorporates a pull down resistor OSCIN Oscillation Circuit The OSCIN and OSCOUT pins are used to connect the 32 768 kHz crystal oscilla OSCOUT Input Output tor with all other oscillation circuit components built into the RX5C338A 10 VDD Positive Power Supply Input o in The VDD pin is connected to the power supply The VSS pin is grounded 5 VSS Negative Power Supply Input RICOH Rx5C338A ABSOLUTE MAXIMUM RATINGS CO e oe e fo Output Voltage 2 0 3 to 6 5 oee O o e e Serme PS ABSOLUTE MAXIMUM RATINGS Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions Moreover such values for any two items must not be reached
15. CPU for output at preset times The alarm circuit allows two types of alarm settings specified by the Alarm_W registers and the Alarm_D registers The Alarm_W registers allow week hour and minute alarm settings including combinations of multiple day of week settings such as Monday Wednesday and Friday and Saturday and Sunday The Alarm_D regis ters allow hour and minute alarm settings Both Alarm_W and Alarm_D signals are output from the INTR pin The current alarm settings specified by these two registers can be checked from the CPU by using a polling function 4 High precision Oscillation Adjustment Function The RX5C338A have built in oscillation stabilization capacitors CG and Cp which can be connected to an external crystal oscillator to configure an oscillation circuit To correct deviations in the oscillation frequency of the crystal oscillator the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to 1 5 ppm at 25 C from the CPU within a maximum range of approximately 189 ppm in increments of approximately 3 ppm Such oscillation frequency adjustment in each system has the following advantages Allows timekeeping with much higher precision than conventional real time clocks while using a crystal oscillator with a wide range of precision variations Corrects seasonal frequency deviations through seasonal oscillation adjustment Allows timekeeping with higher precision
16. ET bits to 0 1 to 2 seconds When the XSTP bit is set to 1 in the control register 2 the 0 F to Fo WALE DALE 12 24 CLEN2 TEST CT2 CT1 CTO VDSL VDET SCRATCH CLEN1 CTFG WAFG and DAFG bits are reset to 0 in the oscillation adjustment register the control register 1 and the control register 2 When the CE pin is H at power on from 0 volts the XSTP bit is undefined and the above bits are undefined See 6 4 Connection of CE Pin The XSTP bit is also set to 1 at power on from 0 volts Note that the XSTP bit may be locked to 0 and the internal register broken upon instantaneous power down RICOH Rx5C338A Considerations in Using Oscillation Halt Sensing Circuit Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following 1 Instantaneous power down on the VDD 2 Condensation on the crystal oscillator 3 On board noise to the crystal oscillator 4 Applying to individual pins voltage exceeding their respective maximum ratings In particular note that the XSTP bit may fail to be set to 1 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation Further give special considerations to prevent excessive chattering to power supply VDD nil lt Supply Voltage Sensing Circuit gt The supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7 8ms per seco
17. a time count gain or loss respectively should be replaced with another one having a smaller and greater CL value respectively until another one having an optimum CL value is selected In this case the bit settings disabling the oscillation adjustment circuit see 2 4 Oscillation Adjustment Circuit should be written to the oscillation adjustment register RICOH 29 30 Rx5C338A Another advisable way to select a crystal oscillator having an optimum CL value is to contact the manufacturer of the crystal oscillator intended for use with the RX5C338A Incidentally the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external oscillation stabilization capacitor CGouT as illustrated in the diagram below RX5C338A 1 The CaouT should have a capacitance ranging from 0 to 15pF VoD Ccout L T Course D It is necessary to select the crystal oscillator in the same manner as in Course C as well as correct errors in the time count of each real time clock in the same manner as in Course B by the method described in 2 4 Oscillation Adjustment Circuit 2 4 Oscillation Adjustment Circuit The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1 second clock pulses once per 20 seconds When such oscillation adjustment is not to be made the oscillation adjustment circuit can be disabled by
18. applied the SO and O System power supply 32KOUT pins 32 768kHz OSCOUT VDD RICOH Rx5C338A 6 2 Connection of INTR Pin The INTR pin follows the N channel open drain output logic and contains no protective diode on the power supply side As such it can be connected to a pull up resistor of up to 5 5 volts regardless of supply voltage RX5C338A System power supply 1 Depending on whether the INTR pin is to be used during bat tery backup it should be connected to a pull up resistor at the following different positions INTR OSCIN 1 Position A in the left diagram when it is not to be used during Backup power supply battery backup OSCOUT 32 768kHz 2 Position B in the left diagram when it is to be used during iia battery backup e VDD VSS 6 3 Connection of 32KOUT Pin As the 32KOUT pin is CMOS output the voltages of the RX5C338A and any devices to be connected should be the same When the device is powered down the 32KOUT output should be disabled When the CLKC pin is connected to the system power supply through the pull up resistor the pull up resistor should be 0 to 10kQ and the 32KOUT pin should be connect to the host through the resistor approx 10kQ System power supply RX5C338A RX5C338A System power supply i 0 to 10kQ oy CLKC Voltage detector IC 1 CLKC ANV gt 32KOUT 32KOUT OSCIN Approx 10kQ Bac
19. circuit can be adjusted by varying procedures depending on the usage of the RX5C338A in the system into which they are to be built and on the allowable degree of time count errors The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system ae za YES oo Use 32 kHz NO Allowable time count precision is on order of oscillation To Course A fe aA it frequency variations of crystal oscillator plus NO eres GITGUI frequency variations of real time clock YES To Course B Use 32 kHz clock circuit without regard to its frequency precision no Allowable time count precision is on order of oscillation frequency variations of crystal oscillator plus frequency variations of real time clock 3 gt To Course C NO gt To Course D 1 Generally crystal oscillators for commercial use are classified in terms of their center frequency depending on their load capacitance CL and further divided into ranks on the order of 10 20 and 50 ppm depending on the degree of their oscillation frequency variations 2 Basically the RX5C338A are configured to cause frequency variations on the order of 5 to 10ppm at normal temperature 3 Time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristics and other properties of crysta
20. d send data to and from the CPU The 3 wire serial interface provides two types of input output timings with which the output and input from the SIO pin output and input are synchronized with the rising and falling edges of the SCLK pin input respectively and vice versa The RX5C338A are configured to select either one of two different input output timings depending on the level of the SCLK pin in the low to high transition of the CE pin Namely when the SCLK pin is held low in the low to high transition of the CE pin the models will select the timing with which the output and input from the SIO pin are synchronized with the rising and falling edges of the SCLK pin input respectively as illustrated in the timing chart below tcEs CE SCLK sra oP SIO tRD Input to the real time clock SIO en ees Output from the real time clock Conversely when the SCLK pin is held high in the low to high transition of the CE pin the models will select the timing with which the output and input from the SIO pin are synchronized with the falling and rising edges of the SCLK pin input respectively as illustrated in the timing chart below CE SCLK SIO Input to the real time clock SIO Output from the real time clock RICON 21 22 Rx5C338A 1 2 Data Transfer Formats Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low transition Data transfer is conducted serially in mul
21. dar Data above need not be conducted This step is detailed in 1 5 Considerations in Reading and Writing Time Data 3 This step is intended to set the CTFG bit to O in the control register 2 to cancel an interrupt to the CPU RICOH Rx5C338A 8 3 3 Applied Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt Function Time data need not be read from all the time counters when used for such ordinary purposes as time count indication This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading For Time Indication in Day of month Day of week Hour Minute and Second Format Write x x x x 0 1 0 0 to control Register 1 Write x 1 x 1 x 0 1 1 to Control Register 2 Generate Interrupt to CPU YES 2 Other Interrupt Second Digit 00 Processes i YES Read Minute Hour Day of week Use Previous Minute and Day of month Counters Hour Day of week and Day of month Data Write x 1 x 1 x 0 1 1 to Control Register 2 4 1 This step is intended to select the level mode as a waveform mode for the periodic interrupt function 2 If this step is completed within 1 second the step of waiting described in 8 3 1 Ordinary Process of Reading Time and Calendar Data above need not be conducted This step is detailed in 1 5 Considerations in Reading and Writing Time Data
22. e of 4 0X2 9mm RICOH Rx5C338A BLOCK DIAGRAM ALARM_W REGISTER 32KOUT 32kHz COMFARATOREW MIN HOUR WEEK CLKC OUTPUT CONTROL A ONPARATOR D ALARM_D Re VOLTAGE 2 MIN w DETECT D TIME COUNTER vSS E SEC MIN HOUR WEEK DAY MONTH YEAR a ADDRESS M ADDRESS CE sc k DECODER E g am OSCIN OSCOUT CONTROL INTR INTERRUPT CONTROL SHIFT REGISTER m CE 77T APPLICATIONS e Communication devices multi function phone portable phone PHS or pager e OA devices fax portable fax e Computer desk top and mobile PC portable word processor PDA electric note or video game e AV components portable audio unit video camera camera digital camera or remote controller e Home appliances rice cooker electric oven e Other car navigation system multi function watch PIN CONFIGURATION 10 pin SSOP G 10 pin SSOP 32KOUT O 1000 VDD SCLK 2 9 OSCIN SIO 3 8 1 OSCOUT CE 4 7 CLKC VSS 5 6 O INTR RICON Rx5C338A PIN DESCRIPTIONS CET T The CE pin is used for interfacing with the CPU Should be held high to allow access to the CPU Incorporates a pull down resistor Should be held low or open 4 CE Chip Enable Input i when the CPU is powered off Allows a maximum input voltage of 5 5 volts regard less of supply voltage The SCLK pin is used to input clock pulses synchronizing the input and output of 2 SCLK Serial Clock Input data to and from the SIO pin
23. ess 1 in the transfer to address 7h pointer format register pointer format register Data transfer from the host Data transfer from the real time clocks RICOH Rx5C338A 1 3 2 Burst Writing Data Transfer Format The second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of Oh to the transfer format register The address pointer is incremented for each transfer of 1 byte data and cycled from Fh to 0h This burst writing data transfer can be completed by driving the CE pin low Example of Burst Writing Data Transfer For Writing Data to Addresses Eh Fh and Oh Specifying Eh Settiig0h Writing data Writing data Writing data in the address in the transfer to address Eh to address Fh to address Oh pointer format register Data transfer from the host Data transfer from the real time clocks 1 4 Reading Data Transfer Formats 1 4 1 1 byte Reading Data Transfer Format The first type of reading data transfer format is designed to transfer 1 byte data at a time and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then the setting of writing Ch to the transfer format register This 1 byte reading data trans
24. ess than 1 second driving the INTR pin low Level mode CTFG bit INTR pin A Setting CTFG bittoO Setting CTFG bit to 0 y Increment of Increment of Increment of second counter second counter second counter 5 32 kHz Clock Output 32 768 kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the control register 2 or the CLEN2 bit in the control register 1 is set to 0 when the CLKC pin is set to high If the conditions described above are not satisfied the output is set to high CLEN1 CLEN2 CLKC pin output 32KOUT pin output D3 at Address Fh D4 at Address Eh pee CMOS output Clock pulses The 32KOUT pin output is synchronized with the CLEN1 CLEN2 bit and CLKC pin settings as illustrated in the tim ing chart below CLEN1 or CLEN2 bit setting MAX 76 3us RICOH 37 Rx5C338A 6 Typical Applications 6 1 Typical Power Circuit Configurations Sample circuit configuration 1 RX5C338A 1 Install bypass capacitors for high frequency and low frequency applications in parallel in close vicinity to the OSCIN RX5C338A Q System power supply VDD H J A T Z ZZZZ VSS d d 777 Sample circuit configuration 2 RX5C338A 1 When using an OR diode as a power supply for the RX5C338A ensure that voltage exceeding the absolute OSCIN maximum rating of Vop 0 3 volts is not
25. etween current time f and preset alarm time occurs i o MAX 61 1us INTR pin Setting WALE Match between Setting WALE Setting WALE Setting WALE Match between and DALE current time and and DALE and DALE and DALE current time and bit to 1 preset alarm time bit to 0 bit to 1 bit to0 preset alarm time in the day of week in the day of week and hour settings i and hour settings INTR pin j lt 1 Setting WALE Match between Setting WAFG i Match between and DALE currenttimeand and DAFG i current time and bit to 1 preset alarm time bit to 0 preset alarm time in the day of week i in the day of week and hour settings i and hour settings RICON 35 36 Rx5C338A 4 2 Periodic Interrupt Setting of the periodic selection bits CT2 to CTo enables periodic interrupt to the CPU There are two waveform modes pulse mode and level mode In the pulse mode the output has a waveform duty cycle of around 50 In the level mode the output is cyclically driven low and when the CTFG bit is set to 0 the output is set to high OFF Waveform Mode Cycle and Falling Timing Description CT2 CT1 CTo Waveform mode Cycle and falling timing pepe owen Dt fo f 1 o Pulse Mode 2Hz Duty cycle of 50 o o i pee wowo 1 0 0 fine orere re Sreo e o i eee oee eons 2 fine orero oo 1 Pulse Mode 2 Hz and 1 Hz clock pulses are output in synchronization with the increment of the second counter as illu
26. fer can be completed by driving the CE pin low or continued by specifying a new head address in the address pointer and setting the transfer format Example of 1 byte Reading Data Transfer For Reading Data from Addresses Eh and 2h ce sio 1 1 Jof ofo i Data ioi of o fol 1 ofo Data ioi m Specifying Eh SettingCh Reading data Specifying 2h SettingCh Reading data in the address in the transfer from address Eh in the address in the transfer from address 2h pointer format register pointer format register Data transfer from the host Data transfer from the real time clocks RICOH 23 24 Rx5C338A 1 4 2 Burst Reading Data Transfer Format The second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the transfer format register The address pointer is incremented for each transfer of 1 byte data and cycled from Fh to 0h This burst reading data transfer can be completed by driving the CE pin low Example of Burst Reading Data Transfer For Reading Data from Addresses Fh 0h and 1h SIO 0 Specifying Fh Setting4h Reading data Reading data i Reading data in the address inthe transfer from address Fh from address Oh from addre
27. ing the WAFG DAFG and CTFG bit settings in the control register 2 RICOH Rx5C338A 4 1 Alarm Interrupt The alarm circuit is controlled by the enable bits i e the WALE and DALE bits in the control register 1 and the flag bits i e the WAFG and DAFG bits in the control register 2 The enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0 When intended for reading the flag bits can be used to monitor alarm interrupt signals When intended for writing the flag bits will cause no event when set to 1 and will drive high dis able the alarm circuit when set to 0 The enable bits will not be affected even when the flag bits are set to 0 In this event therefore the alarm circuit will continue to function until it is driven low enabled upon the next occurrence of a match between current time and preset alarm time The alarm function can be set by presetting desired alarm time in the alarm registers the Alarm_W registers for the day of week digit settings and both the Alarm_W registers and the Alarm_D registers for the hour and minute digit settings with the WALE and DALE bits once set to 0 and then to 1 in the control register 1 Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function Interval 1 minute during which a match b
28. ister and is represented in 7 bit coded decimal notation RICOH Rx5C338A 2 4 2 When Oscillation Frequency is Equal to Target Frequency There is Neither a Time Count Gain nor a Time Count Loss Writing the oscillation adjustment value setting of 0 1 64 or 63 to the oscillation adjustment register disables the oscillation adjustment circuit 2 4 3 When Oscillation Frequency is Lower than Target Frequency There is a Time Count Loss Oscillation frequency Target frequency Oscillation frequency x 3 051 x 10 6 Oscillation adjustment value Oscillation frequency Target frequency X 10 Oscillation adjustment value calculations are exemplified below 1 For an oscillation frequency of 32768 85Hz and a target frequency of 32768 05Hz Oscillation adjustment value 32768 85 32768 05 0 1 32768 85 X 3 051 Xx 10 6 32768 85 32768 05 x 10 1 9 001 9 In this instance write the settings of 0 0 0 1 0 0 1 to the Fe Fs F4 F3 F2 F1 and Fo bits in the oscillation adjustment register Thus an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h 2 For an oscillation frequency of 32763 95Hz and a target frequency of 32768 05Hz Oscillation adjustment value 32763 95 32768 05 32763 95 x 3 051 x 10 32763 95 32768 05 x 10 41 015 41 To represent an oscillation adjustment value of
29. kup power L supply 32 768kHz OSCIN Backup power supply 32 768kHz OSCOUT OSCOUT VDD VDD VSS VSS 1 RNSVLXXC by RICOH RICOH 39 40 Rx5C338A 6 4 Connection of CE Pin Observe the following precautions when you connect the CE pin 1 The CE pin is configured to enable the oscillation halt sensing circuit only when driven low As such it should be driven low or open at power on from 0 volts 2 The CE pin should also be driven low or open immediately upon the host going down see 1 5 Considerations in Reading and Writing Time Count Data 3 The reading function should be disrupted when the CE signal goes to low during read cycle While the upper 4 bits of the data might be written to the inner shift register when the CE signal goes to low during write cycle Because the writing function is executed 4 bits by 4 bits In either case after the CE signal returns to High no trouble will occur in the next read or write cycle Lower limit operating voltage J for the CPU uae fa Backup voltage CONTROL CE i f 4 a ee t 0 2xVDD ji oi it 4 gt MIN Ous MIN Ops MIN Ous RICOH 7 Typical Characteristics e Test Circuit RX5C338A OSCOUT 32KOUT 7 1 Timekeeping Current vs Supply Voltage F 32 768kHz VSS with no 32 kHz clock output Timekeeping Current IbDD uA CE Open Output Open Topt 25 C X
30. l oscillators RICOH Rx5C338A Course A When the time count precision of each real time clock is not to be adjusted the crystal oscillator intended for use with that real time clock may have any CL value requiring no presetting The crystal oscillator may be subject to frequency variations which are selectable within the allowable range of time count precision Several crystal oscillators and real time clocks should be used to find the center frequency of the crystal oscillators by the method described in 2 2 Measurement of Oscillation Frequency and then calculate an appropriate oscillation adjustment value by the method described in 2 4 Oscillation Adjustment Circuit for writing this value to the RX5C338A Course B When the time count precision of each real time clock is to be adjusted within the oscillation frequency variations of the crystal oscillator plus the frequency variations of the real time clock ICs it becomes necessary to correct deviations in the time count of each real time clock by the method described in 2 4 Oscillation Adjustment Circuit Such oscillation adjustment provides crystal oscillators with a wider range of allowable settings of their oscillation frequency variations and their CL values The real time clock IC and the crystal oscillator intended for use with that real time clock IC should be used to find the center frequency of the crystal oscillator by the method described in 2 2 Measuremen
31. max TYP TYP MAX CE Set up Time 400 200 ns CE Hold Time 400 200 ns cenecneytimw _ fe sxc fo fe fame saxen o fe saxe fe fm ON O o o e Ce pomo S e a E Ce omoare O O o E After Falling of CE CE SCLK SIO Write cycle SIO Read cycle For read write timing see Paragraph USAGES 1 5 Considerations in Reading and Writing Time Data RICOH Rx5C338A GENERAL DESCRIPTION 1 Interface with CPU The RX5C338A are connected to the CPU by three signal lines CE Chip Enable SCLK Serial Clock SIO Serial Input Output through which it reads and write data from and to the CPU The CPU can access when the CE pin is held high Access clock pulses have a maximum frequency of 2MHz at 5 volts allowing high speed data transfer to the CPU 2 Clock and Calendar Function The RX5C338A read and write time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year The calendar year will automatically be identified as a leap year when its last two digits are a mul tiple of 4 Also available is the 1900 2000 identification bit for Year 2000 compliance Consequently leap years up to the year 2099 can automatically be identified as such The year 2000 is a leap year while the year 2100 is not a leap year 3 Alarm Function The RX5C338A incorporate an alarm circuit configured to generate interrupt signals to the
32. n days of the week and the day of week digits are user definable e g Sunday 0 0 0 The writing of 1 1 1 to W4 W2 W1 is prohibited except when days of the week are unused 2 5 Calendar Counters at Address 4h to 6h The calendar counters are configured to display the calendar digits in BCD format by using the automatic calen dar function as follows The day of month digits D20 to D1 range from 1 to 31 for January March May July August October and December from 1 to 30 for April June September and November from 1 to 29 for February in leap years from 1 to 28 for February in ordinary years The day of month digits are carried to the month digits in reversion from the last day of the month to 1 The month digits MO10 to MO1 range from 1 to 12 and are carried to the year digits in reversion from 12 to 1 The year digits Yso to Y1 range from 00 to 99 00 04 08 92 and 96 in leap years and are carried to the 19 20 digits in reversion from 99 to 00 The 19 20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits Any carry from lower digits with the writing of non existent calendar data may cause the calendar counters to mal function Therefore such incorrect writing should be replaced with the writing of existent calendar data 2 5 1 Counter Address 2 5 2 Month Counter Century Bit at Address 5h D7 D6 D5 D4 D3 D2 D1 DO RICOH 17 18 RS5C338A 2 5 3 Year
33. n the OSCIN and OSCOUT pins and the printed circuit board 4 Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins 5 Take extreme care not to cause condensation which leads to various problems such as oscillation halt Other Relevant Considerations 1 For external input of 32 768 kHz clock pulses to the OSCIN pin DC coupling Prohibited due to an input level mismatch AC coupling Permissible except that the oscillation halt sensing circuit does not guarantee perfect operation because it may cause sensing errors due to such factors as noise 2 To maintain stable characteristics of the crystal oscillator avoid driving any other IC through 32 768 kHz clock pulses output from the OSCOUT pin RICOH 27 28 Rx5C338A 2 2 Measurement of Oscillation Frequency RxX5C338A VDD OSCIN OSCOUT 32 768kHz CLKC 32KOUT VSS Frequency counter 1 The RX5C338A are configured to generate 32 768 kHz clock pulses for output from the 32KOUT pin at power on conditionally on setting the XSTP bit to 1 in the control register 2 2 A frequency counter with 6 more preferably 7 or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation fre quency of the oscillation circuit 3 The CLKC input should be connected to the Vpp pin with a pull up resistor 2 3 Adjustment of Oscillation Frequency The oscillation frequency of the oscillation
34. nd to check for a drop in supply voltage below a threshold voltage of 2 1 or 1 6 volts for the VDSL bit setting of 0 the default setting or 1 respectively in the control register 2 thus minimizing supply current requirements as illustrated in the timing chart below This circuit suspends a sampling operation once the VDET bit is set to 1 in the control register 2 Threshold voltage of 2 1 or 1 6 volts XSTP 7 8ms Internal initialization period 1 or 2 seconds Sampling operation by supply voltage monitoring circuit VDET ZZ D6 at address Fh Setting 0 to XSTP Setting VDET bit to 0 and VDET bits RICOH 33 34 Rx5C338A 4 Alarm and Periodic Interrupt The RX5C338A incorporate the alarm circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals respectively for output from the INTR pin as described below 1 Alarm Circuit The alarm interrupt circuit is configured to generate alarm signals for output from the INTR which is driven low enabled upon the occurrence of a match between current time read by the time counters the day of week hour and minute counters and alarm time preset by the alarm registers the Alarm_W registers intended for the day of week hour and minute digit settings and the Alarm_D registers intended for the hour and minute digit set tings 2 Periodic Interrupt Circuit The periodic interru
35. onized with second counter increment 1 0 1 Level Mode Once per minute at 00 seconds of every minute Fifi o Level Mode Once per hour at 00 minutes and 00 seconds of every hour Level Mode Once per month at 00 hours 00 minutes and 00 seconds of first day of every month 1 Pulse Mode 2 Hz and 1 Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page RICOH 11 Rx5C338A 2 Level Mode periodic interrupt signals are output with selectable interrupt cycle settings of 1 second 1 minute 1 hour and 1 month The increment of the second counter is synchronized with the falling edge of periodic interrupt signals For example periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below 3 When the oscillation adjustment circuit is used the interrupt cycle will fluctuate once per 20 seconds as follows Pulse Mode the L period of output pulses will increment or decrement by a maximum of 3 784ms For example 1 Hz clock pulses will have a duty cycle of 50 0 3784 Level Mode a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3 784ms Relation Between the Mode Waveform and the CTFG Bit Pulse mode cron Lf Lf LJ Approx 92us Increment of second c
36. ounter Rewriting of the second counter readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real time clocks by approximately 1 second In the pulse mode the increment of the second counter is delayed by approximately 92us from the falling edge of clock pulses Consequently time Rewriting the second counter will reset the other time counters of less than 1 second driving the INTR pin low Level mode CTFG bit INTR pin o H Setting CTFG bitto0 Setting CTFG bit to 0 Y Increment of Increment of Increment of second counter second counter second counter n RICOH Rx5C338A 2 2 Control Register 2 at Address Fh D7 D6 D5 D4 D3 D2 D1 DO Default settings Default value means read written values when the XSTP bit is set to 1 due to power on from 0 volts or supply voltage drop 2 2 1 VDSL Supply Voltage Monitoring Threshold Selection Bit oo Selecting the supply voltage monitoring threshold setting of 2 1 volts Default setting Selecting the supply voltage monitoring threshold setting of 1 6 volts The VDSL bit is intended to select the supply voltage monitoring threshold settings 2 2 2 VDET Supply Voltage Monitoring Result Indication Bit Indicating supply voltage above the supply voltage monitoring threshold settings Default setting Indicating supply voltage below the supply voltage monitoring th
37. pectively Table of Time Digit Indications 24 hour mode 12 hour mode 24 hour mode 12 hour mode 12 AM12 32 PM12 01 AM 1 21 PM 1 02 AM 2 22 PM 2 03 AM 3 23 PM 3 04 AM 4 24 PM 4 05 AM 5 25 PM 5 06 AM 6 26 PM 6 07 AM 7 27 PM 7 08 AM 8 28 PM 8 09 AM 9 29 PM 9 10 AM10 30 PM10 11 AM11 31 PM11 Setting the 12 24 bit should precede writing time data RICOH Rx5C338A 2 1 3 CLEN2 32 kHz Clock Output Bit 2 Enabling the 32 kHz clock circuit Default setting Disabling the 32 kHz clock circuit For the RX5C338A setting the CLEN2 bit or the CLEN1 bit D3 in the control register 2 to 0 and the CLKC pin to high specifies generating clock pulses with the oscillation frequency of the 32 768 kHz crystal oscillator for output from the 32KOUT pin Conversely setting both the CLEN1 and the CLEN2 bit to 1 or CLKC pin to low specifies disabling L such output 2 1 4 TEST Test Bit Normal operation mode Default setting The TEST bit is used only for testing in the factory and should normally be set to 0 2 1 5 CT2 CT1 and CTo Periodic Interrupt Selection Bits Description CT2 CT1 CTo Waveform mode Interrupt cycle and falling timing olojo Off H Default setting op e pama o 1 0 Pulse Mode 2Hz Duty cycle of 50 o f 1 1 Pulse Mode 1Hz Duty cycle of 50 Fa o fo Level Mode Once per 1 second Synchr
38. pt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level mode for output from the INTR pin depending on the CT2 CT1 and CTo bit settings in the control reg ister 1 The above two types of interrupt signals are monitored by the flag bits i e the WAFG DAFG and CTFG bits in the control register 2 and enabled or disabled by the enable bits i e the WALE DALE CT2 CTi and CTo bits in the control register 1 as listed in the table below Alarm signals WAFG bit WALE bit under control of Alarm_W registers D1 at Address Fh D7 at Address Eh Alarm signals DAFG bit DALE bit under control of Alarm_D registers DO at Address Fh D6 at Address Eh PERNE CTFG bit CT2 CT1 and CTo bits D2 to DO at Address Eh Periodic interrupt signals D2 at Address Fh these bit settings of 0 disable the periodic interrupt circuit At power on when the WALE DALE CT2 CT1 and CTo bits are set to 0 in the control register 1 the INTR pin is driven high disabled When two or more types of interrupt signals are output simultaneously from the INTR pin the output from the INTR pin becomes an OR waveform of their negative logic Example Combined Output of Alarm Interrupt Signals from the INTR pin Under Control of Alarm_D and Alarm_W Registers Alarm_W ar Mm Alarm_D rs es INTR rn es In this event which type of interrupt signal is output from the INTR pin can be confirmed by read
39. r Oscillation Adjustment Register 3 Cd WH20 ale fe fo ae neil ia WA DEONONT Ma o o i eere om owe on DH20 EEEH oe i JBR DP A a 1 1 1 1 All the data listed above accept both reading and writing 2 The data marked with is invalid for writing and reset to 0 for reading 3 When the XSTP bit is set to 1 in control register 2 all the bits are reset to 0 in oscillation adjustment register 1 control register 1 and control register 2 excluding the XSTP bit 4 Writing to the oscillation adjustment register requires zero filling the 0 bit RICOH 10 Rx5C338A 2 Register Settings 2 1 Control Register 1 at Address Eh D7 D6 D5 D4 D3 D2 D1 DO Default settings Default value means read written values when the XSTP bit is set to 1 due to power on from 0 volts or supply voltage drop 2 1 1 WALE DALE Alarm_W Enable Bit and Alarm_D Enable Bit Disabling the alarm interrupt circuit under the control of the settings of the Alarm_W registers and the Alarm_D registers Default setting 1 Enabling the alarm interrupt circuit under the control of the settings of the Alarm_W registers and the Alarm_D registers 2 1 2 12 24 hour Mode Selection Bit 12 24 hour Time Display System Selection bit i a Selecting the 12 hour mode with a m and p m indications Selecting the 24 hour mode Setting the 12 24 bit to 0 and 1 specifies the 12 hour mode and the 24 hour mode res
40. rcuit 2 7 Alarm_W Register at Address 8h to Ah 2 7 1 Alarm_W Minute Register at Address 8h D7 D6 D5 D4 D3 D2 D1 DO ore vat ane Twat wate we a 2 7 2 Alarm_W Hour Register at Address 9h D7 D6 D5 D4 D3 D2 D1 DO E E p e e e e 2 7 3 Alarm_W Day of week Register at Address Ah D7 D6 D5 D4 D3 D2 D1 DO E po p e e e o Default settings Default value means read written values when the XSTP bit is set to 1 due to power on from 0 volts or supply voltage drop For writing For writing For writing The D5 bit of the Alarm_W hour register represents WP A when the 12 hour mode is selected 0 for a m and 1 for p m and WH20 when the 24 hour mode is selected tens in the hour digits The Alarm _W registers should not have any non existent alarm time settings Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers may disable the alarm circuit When the 12 hour mode is selected the hour digits read 12 and 32 for 0 a m and 0 p m respectively see 2 1 2 12 24 12 24 hour Mode Selection Bit WWo to WW e correspond to W4 W2 and W1 of the day of week counter with settings ranging from 0 0 0 to 1 1 0 WWo to WWe with respective settings of 0 disable the outputs of the Alarm_W registers RICOH 19 20 Rx5C338A Example of Alarm Time Setting Day of week 12 hour mode 24 hour mode Preset alarm time Sun Mon Tue
41. reshold settings Once the VDET bit is set to 1 the supply voltage monitoring circuit will be disabled while the VDET bit will hold the setting of 1 The VDET bit accepts only the writing of 0 which restarts the supply voltage monitoring circuit Conversely setting the VDET bit to 1 causes no event 2 2 3 SCRATCH Scratch Bit C a The SCRATCH bit is intended for scratching and accepts the reading and writing of 0 and 1 The SCRATCH bit will be set to 0 when the XSTP bit is set to 1 in the control register 2 RICOH 13 14 Rx5C338A 2 2 4 XSTP Oscillator Halt Sensing Bit ste eseription OOOO O Pe Sensing a normal condition of oscillation Sensing a halt of oscillation Default setting The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator The oscillation halt sensing circuit operates only when the CE pin is L The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as pow er on from 0 volts and a drop in supply voltage The XSTP bit will hold the setting of 1 even after the restart of oscillation As such the XSTP bit can be applied to judge the validity of clock and calendar data after power on or a drop in supply voltage When the XSTP bit is set to 1 all bits will be reset to 0 in the oscillation adjustment register control register 1 and control register 2 stopping the output from the INTR pin and starting
42. rrupt function by writing the settings of x 1 x 1 x 1 0 1 and x 1 x 1 x 1 1 0 to the Alarm_W registers and the Alarm_D registers respectively RICOH
43. s range as shown in 2 1 2 12 24 12 24 hour Mode Selection Bit and are carried to the day of month and day of week digits in transition from PM11 to AM12 or from 23 to 00 Any writing to the second counter resets divider units of less than 1 second Any carry from lower digits with the writing of non existent time may cause the time counters to malfunction Therefore such incorrect writing should be replaced with the writing of existent time data 2 3 1 Second Counter at Address Oh For writing For reading Default settings For writing For reading 0 Indefinite Indefinite Indefinite Indefinite Indefinite Default settings 2 3 3 Hour Counter at Address 2h D7 D6 D5 D4 D3 D2 D1 DO Default settings Default value means read written values when the XSTP bit is set to 1 due to power on from 0 volts or supply voltage drop RICOH Rx5C338A 2 4 Day of week Counter at Address 3h D7 D6 D5 D4 D3 D2 D1 DO For writing For reading Pe ee ee Defeat settings Default settings Default value means read written values when the XSTP bit is set to 1 due to power on from 0 volts or supply voltage drop The day of week counter is incremented by 1 when the day of week digits are carried to the day of month digits Day of week display incremented in septimal notation W4 W2 W1 0 0 0 0 0 1 1 1 0 0 0 0 Correspondences betwee
44. ss 1h pointer format register Data transfer from the host Data transfer from the real time clocks 1 4 3 Combination of 1 byte Reading and Writing Data Transfer Formats The 1 byte reading and writing data transfer formats can be combined together and further followed by any other data transfer format Example of Combination of 1 byte Reading and Writing Data Transfer For Reading and Writing Data from and to Address Fh E SIO Tididiti1 0 00 Data Specifying Fh SettingCh Reading data Specifying Fh Setting8h Writing data in the address in the transfer from address Fh in the address in the transfer i to address Fh pointer format register pointer format register Data transfer from the host Data transfer from the real time clocks The reading and writing data transfer formats correspond to the settings in the transfer format register as shown in the table below eee l 1 byte transfer Burst Successive transfer Writing data transfer Oh for writing to real time clock 1 0 0 0 0 0 0 0 4h 8h Reading data transfer Ch for reading from real time clock 1 1 0 0 0 1 0 0 RICOH Rx5C338A 1 5 Considerations in Reading and Writing Time Data Any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data For example suppose a carry out of 13 59 59 into 14 00 00 occ
45. strated in the timing chart on the next page 2 Level Mode periodic interrupt signals are output with selectable interrupt cycle settings of 1 second 1 minute 1 hour and 1 month The increment of the second counter is synchronized with the falling edge of periodic interrupt signals For example periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart on the next page 3 When the oscillation adjustment circuit is used the interrupt cycle will fluctuate once per 20 seconds as follows Pulse Mode the L period of output pulses will increment or decrement by a maximum of 3 784ms For example 1 Hz clock pulses will have a duty cycle of 50 0 3784 Level Mode a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3 784ms RICON Rx5C338A Relation Between the Mode Waveform and the CTFG Bit Pulse mode come L_ Lf L _fJs_ Approx 92us Increment of second counter Rewriting of the second counter readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real time clocks by approximately 1 second In the pulse mode the increment of the second counter is delayed by approximately 92 us from the falling edge of clock pulses Consequently time Rewriting the second counter will reset the other time counters of l
46. t alarm time The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1 which is caused approximately 61s after any match between current time and preset alarm time specified by the Alarm_W registers and the Alarm_D registers The WAFG and DAFG bits accept only the writing of 0 which disables H the INTR pin until it is enabled L again at the next preset alarm time Conversely setting the WAFG and DAFG bits to 1 causes no event The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0 The settings of the WAFG and DAFG bits are synchronized with the output of the INTR pin as shown in the timing chart below Output Relationships Between the WAFG or DAFG Bit and INTR Approx 61us Approx 61s Settings of WAFG DAFG bit Output of NTR pin i Writing of Oto WAFG Writing of 0 to WAFG y DAFG bit y DAFG bit Match between current time Match between current time Match between current time and preset alarm time and preset alarm time and preset alarm time RICOH 15 16 Rx5C338A 2 3 Time Counters at Addresses Oh to 2h Time digit display BCD format as follows The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00 The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00 The hour digit
47. t of Oscillation Frequency and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit At normal temperature the oscillation frequency of the oscillator circuit can be adjusted by up to approximately 1 5ppm Course C Course C together with Course D requires adjusting the time count precision of each real time clock as well as the frequency of 32 768 kHz clock pulses output from the 32KOUT pin Normally the oscillation frequency of the crystal oscillator intended for use with the real time clocks should be adjusted by adjusting the oscillation stabilizing capacitors Cc and Cp connected to both ends of the crystal oscillator The RX5C338A which incorporate the Cc and the Cp require adjusting the oscillation frequency of the crystal oscillator through its CL value Generally the relationship between the CL value and the Cc and Cp values can be represented by the following equation _CGX Cp Cea p Cs where Cs represents the floating capacity of the printed circuit board The crystal oscillator intended for use with the RX5C338A is recommended to have the CL value on the order of 6 to 8pF Its oscillation frequency should be measured by the method described in 2 2 Measurement of Oscillation Frequency Any crystal oscillator found to have an excessively high or low oscillation frequency causing
48. tal 32 768kHz R1 30kQ TYP CL 6pF to 8pF Topt 25 C Output pins Open Frequency counter Rx5C338A 7 2 Timekeeping Current vs Supply Voltage with 32 kHz clock output CE Open Output Open Topt 25 C T 0 8 g 29 2 0 6 5 gt 1 5 0 4 D 1 0 2 05 H 0 0 0 1 2 3 4 5 6 0 1 2 Supply Voltage Vpp V 3 4 5 o Supply Voltage Vpp V 7 3 CPU Access Current vs SCLK Clock Frequency 7 4 Timekeeping Current vs Operating Temperature with no 32 kHz clock output CPU Access Current IDD uWA Output Open Topt 25 C 50 0 0 500 1000 1500 2000 60 40 20 0 SCLK Clock Frequency kHz CE Open Output Open Topt 25 C 0 5 Timekeeping Current IDD uA 20 40 60 80 60 Operating Temperature Topt C RICOH 41 Rx5C338A 7 5 Oscillation Frequency Deviation vs External Ca 7 6 Oscillation Frequency Deviation vs Supply Voltage VpD 38V Topt 25 C E External ee 0pF as standard A Topt 25 C Vop 3V as standard a 10 2 5 S 5 s 4 0 S 3 a 5 2 gt 10 gt 1 c Cc g 15 g 0 ef 20 Z I 25 L p a c 2 30 S 3 amp amp 3 35 5 4 40 5 9 O So i 2 3 4 5 6 eer e Supply Voltage Vpop V 7 7 Oscillation Frequency Deviation vs 7 8 Oscillation Start Time vs Supply Voltage Operating Temperature
49. ther details see 3 Oscillation Halt Sensing and Supply Voltage Monitoring 3 This step is not required when the supply voltage monitoring circuit is not used 4 This step involves ordinary initialization including the oscillation adjustment register and interrupt cycle settings 8 2 Writing of Time and Calendar Data 1 This step of waiting is detailed in 1 5 Considerations in Reading and Writing Time Data Wait for 31 2 Any writing to the second counter will reset divider units lower than ait for 31s l the second digits Write to Time Counter and Calendar Counter RICON 43 44 Rx5C338A 8 3 Reading Time and Calendar Data 8 3 1 Ordinary Process of Reading Time and Calendar Data Wait for 31us 1 Read from Time Counter and Calendar Counter 1 This step of waiting is detailed in 1 5 Considerations in Reading and Writing Time Data 8 3 2 Basic Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt Set Periodic Interrupt Cycle Selection Bits 4 Generate Interrupt in CPU ira y YES Read from Time Counter Other Interrupt and Calendar Counter Processes Write x 1 x 1 x 0 1 1 to Control Register 2 1 This step is intended to select the level mode as a waveform mode for the periodic interrupt function 2 If this step is completed within 1 second the step of waiting described in 8 3 1 Ordinary Process of Reading Time and Calen
50. tiple units of 1 byte 8 bits The former 4 bits are used to specify in the address pointer a head address with which data transfer is to be commenced from the host The latter 4 bits are used to select either reading data transfer or writing data transfer and set the transfer format register to specify an appropriate data transfer format All data transfer formats are designed to transfer the most significant bit MSB first Setting the address i Setting the transfer ___ Writing data transfer pointer i format register Reading data transfer Two types of data transfer formats are available for reading data transfer and writing data transfer each 1 3 Writing Data Transfer Formats 1 3 1 1 byte Writing Data Transfer Format The first type of writing data transfer format is designed to transfer 1 byte data at a time and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 8h to the transfer format register This 1 byte writing data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the address pointer and setting the transfer format Example of 1 byte Writing Data Transfer For Writing Data to Addresses Fh and 7h Specifying Fh Setting8h Writing data Specifying 7h Setting8h Writing data vin the address in the transfer to address Fh in the addr
51. to the start of access to address es Oh to 6h in order that any ongoing carry of the time digits may be completed within this time span 4 Leave a time span of 61ps or more from the high to low transition of the CE pin to its low to high transition in order that any ongoing carry of the time digits during the high interval of the CE pin may be adjusted within this time span 5 The considerations listed in 1 3 and 4 above are not required when the process of reading or writing time data is obviously free from any carry of the time digits e g reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function Good and bad examples of reading and writing time data are illustrated on the next page RICOH 25 Rx5C338A Good Example Any address other than addresses 0h to 6h permits of immediate reading or writing without requiring a time span of 31us CE SIO Fah X Daa yK Daa X Daa X Data Specifying Fh in the Reading from the Reading from Reading from Reading from address pointer control register 2 the second the minute the hour counter Writing 4h to the at address Fh counter at counter at at address 2h transfer format register address Oh address 1h Bad Example 1 Where the CE pin is once driven low in the process of reading time data Time span of Timespanof 31s or more 31usormore SIO
52. uit RX5C338A Typical externally equipped element VDD Vp X tal 32 768kHz R1 30kQ TYP CL 6pF to 8pF i 30kHz Standard values of internal elements Rr 15MQ TYP OSCOUT RD 120k2 TYP Co Cp 12pF TYP ma The oscillation circuit is driven at a constant voltage of approximately 1 2 volts relative to the level of the Vss pin input As such it is configured to generate an oscillating waveform with a peak to peak voltage on the order of 1 2 volts on the positive side of the Vss pin input Considerations in Handling Crystal Oscillators Generally crystal oscillators have basic characteristics including an equivalent series resistance R1 indicating the ease of their oscillation and a load capacitance CL indicating the degree of their center frequency Particularly crystal oscillators intended for use with the RX5C338A are recommended to have a typical R1 value of 30kQ and a typical CL value of 6 to 8pF To confirm these recommended values contact the manufacturers of crystal oscillators intended for use with these particular models Considerations in Installing Components around the Oscillation Circuit 1 Install the crystal oscillator in the closest possible vicinity to the real time clock ICs 2 Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit particularly in the area marked A in the above figure 3 Apply the highest possible insulation resistance betwee
53. urs in the process of reading time data in the middle of shifting from the minute digits to the hour digits At this moment the second digits the minute digits and the hour digits read 59 seconds 59 minutes and 14 hours respectively indicating 14 59 59 to cause the reading of time data deviating from actual time virtually 1 hour A similar error also occurs in writing time data To prevent such errors in reading and writing time data the RX5C338A have the function of temporarily locking any carry of the time digits during the high interval of the CE pin and unlocking such a carry in its high to low transition Note that a carry of the second digits can be locked for only 1 second during which time the CE pin should be driven low 13 59 59 14 00 00 14 00 01 Actual time a SSS SSS ge boc l MAX 61us 13 59 59 44 00 00 14 00 01 Time counts within real time clocks J MlM The effective use of this function requires the following considerations in reading and writing time data 1 Hold the CE pin high in each session of reading or writing time data 2 Ensure that the high interval of the CE pin lasts within 1 second Should there be any possibility of the host going down in the process of reading or writing time data make arrangements in the peripheral circuitry as to drive the CE pin low or open at the moment that the host actually goes down 3 Leave a time span of 311s or more from the low to high transition of the CE pin
54. writing the settings of x 0 0 0 0 0 representing 0 or 1 to the Fe Fs F4 F3 F2 F1 and Fo bits in the oscillation adjustment circuit Conversely when such oscillation adjustment is to be made an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit 2 4 1 When Oscillation Frequency is Higher than Target Frequency There is a Time Count Gain Oscillation frequency Target frequency 0 1 Oscillation frequency X 3 051 x 10 6 Oscillation adjustment value Oscillation frequency Target frequency X 10 1 1 Oscillation frequency Frequency of clock pulses output from the 32KOUT pin at normal temperature in the manner described in 2 2 Measurement of Oscillation Frequency 2 Target frequency Desired frequency to be set Generally a 32 768 kHz crystal oscillator has such temperature characteristics as to have the highest oscillation frequency at normal temperature Consequently the crystal oscillator is recommended to have target frequency settings on the order of 32 768 to 32 76810kHz 3 05ppm relative to 32 768kHz Note that the target frequency differs depending on the environment or location where the equipment incorporating the real time clocks is expected to be operated 3 Oscillation adjustment value Value that is to be finally written to the Fo to Fe bits in the oscillation adjustment reg
55. y Fs F4 F3 F2 F1 Fo 1 x 2 The settings of x 0 0 0 0 0 x x representing either 0 or 1 in the Fe Fs F4 F3 F2 F1 and Fo bits cause neither an increment nor decrement of time counts Example When the second digits read 00 20 or 40 the settings of 0 0 0 0 1 1 1 in the Fe Fs F4 F3 F2 Fi and Fo bits cause an increment of the current time counts of 32768 by 7 1 x 2 to 32780 a current time count loss When the second digits read 00 20 or 40 the settings of 0 0 0 0 0 0 1 in the Fe Fs F4 F3 F2 F1 and Fo bits cause neither an increment nor a decrement of the current time counts of 32768 When the second digits read 00 20 or 40 the settings of 1 1 1 1 1 1 0 in the Fe Fs F4 F3 F2 Fi and Fo bits cause a decrement of the current time counts of 32768 by 2 x 2 to 32764 a current time count gain RICOH Rx5C338A An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3ppm 2 82768 x 20 3 05lppm Conversely a decrease of two clock pulses once per 20 seconds causes a time count gain of 3ppm Consequently deviations in time counts can be corrected with a precision of 1 5ppm Note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32 768 kHz clock pulses For further details see USAGE 2 4 Oscillation Adjustment Ci
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RICOH Rx5C338A Manual