MAXIM MAX101 500Msps 8-Bit ADC with Track/Hold handbook
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1. Reference Voltage VART VBRT Operating Junction Temperature Note 2 Reference Voltage VARB VBRB 1 5V to 0 3V Storage Temperature Range Clock Input Voltage VIH VIL nn 2 3V to OV Lead Temperature soldering 10sec Note 1 The digital control inputs are diode protected However limited protection is provided on other pins Permanent damage may occur on unconnected units under high energy electrostatic fields Keep unused units in supplied conductive carrier or shunt the terminals together Note 2 Typical thermal resistance junction to case ReJc 5 C W and thermal resistance junction to ambient MAX101CFR ReJA 12 C W if 200 lineal ft min airflow is provided See Package Information Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS 5 2V Voc 5V RL 1000 to 2V VART VBnr 1 02V 1 02V Ta 25 C unless otherwise noted TmIN to Tmax 0 C to 70 C Note 3 PARAMETER SYMBOL CONDI2. 0 MAXI01CFRQ 0 ATION EVALU AILABLE 19 0296 Rev 0 8 94 ton KIT MANUAL 500Msps 8 Bit ADC with Track Hold General Description The MAX101 ECL compatible 500Msps 8 bit analog to digital converter ADC allows accurate digitizing of analog signals from DC to 250MHz Nyquist frequen cy Dual monolithic converters driven by the track hold T H operate on opposite clock edges time inter leaved Designed with Maxim s proprietary advanced bipolar processes the MAX101 contains a high perfor mance T H amplifier and two quantizers in an 84 pin ceramic flat pack The innovative design of the internal T H assures an exceptionally wide 1 2GHz input bandwidth and aper ture delay uncertainty of less than 2ps resulting in a high 7 0 effective bits at the Nyquist frequency Special comparator output design and decoding circuitry reduce out of sequence code errors The probability of erroneous codes due to metastable states is reduced to less than 1 error per 1015 clock cycles And unlike other ADCs that can have errors resulting in false full scale or zero scale outputs the MAX101 keeps the error magnitude to less than 1LSB The analog input is designed for either differential or single ended use with 270mV range Sense pins for the reference input allow full scale calibration of the input range or facilitate ratiometric use Phase adjustment is available to adjust the relative sampling of the converter halves
3. e 1270 BSC 0 050 BSC E 29 184 29 794 1 149 1 173 44 196 44 704 1 740 1 760 4 0 075 020 6 25 298 25 502 0 996 1 004 pb A2 A1 EQUAL SPACES 3 28 194 28 702 1 110 1 130 S 1 930 2 184 0 076 0 086 D3 28 448 28 829 1 120 1 135 Y 5 EE p mim mm 84 PIN CERAMIC FLAT PACK WITH HEAT SINK 4 gt 5 6 4 0 060 005 4 E3 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 16 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 1994 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products
4. 101 MC100E116 14 MAXIM 1 2 MAX412 200 047uF 5 332 CMPSH 3 202 047uF SE MC100E151 1 2 MAX412 330 CMPSH 3 4 7 37 40 46 7 15 18 24 27 30 34 29 32 69 80 49 57 60 64 67 68 70 71 74 77 78 79 82 84 lt 0 001 0 1uF AVLAZCLAWI 500Msps 8 Bit ADC with Track Hold MAX101 Pin Configuration MAXIM MAX101 511918 S 8118 Bl Bl Bl S 5 8 8 amp ESN 9 ao as ao ao va Ceramic Flat 15 MAX101 500Msps 8 Bit ADC with Track Hold Package Information PIN FIN HEATSINK FORCED CONVECTION PARAMETERS 200 300 400 500 ELOGITY ft min DIRECTION CF AIRFLOW ACROSS HEATSINK MILLIMETERS INCHES MIN MAX MIN MAX 2 _ 17 272 18 288 0 680 0 720 A1 1 041 1 270 10 041 0 050 i 0 060 005 7x _ 2 3 048 3 302 0 120 0 130 b 0 406 0 508 0 016 0 020 m C 0 228 0 279 0 009 0 011 D 29 184 29 794 1 149 1 173 D D1 44 196 44 704 1 740 1 760 m D2 25 298 25 502 0 996 1 004 Bu TIT
5. 24 hours a day this would translate to less than one metastable state error every 46 days Integral Nonlinearity Integral nonlinearity is the deviation of the transfer func tion from a reference line measured in fractions of 1LSB using a best straight line determined by a least square curve fit Differential Nonlinearity Differential nonlinearity DNL is the difference between the measured LSB step and an ideal LSB step size between adjacent code transitions DNL is expressed in LSBs and is calculated using the following equation VMEAS VMEAS 1 LSB DNL LSB LSB where VMEAS 1 is the measured value of the previous code A DNL specification of less than 1LSB guarantees no missing codes and a monotonic transfer function AVLAZCLAWI 500Msps 8 Bit ADC with Track Hold Detailed Description Converter Operation The parallel or flash architecture used by the MAX101 provides the fastest multibit conversion of all common integrated ADC designs The basic element of a flash as with all other ADC architectures is the comparator which has a positive input a negative input and an output If the voltage at the positive input is higher than the nega tive input connected to a reference the output will be high If the positive input voltage is lower than the refer ence the output will be low A typical n bit flash consists of 2N 1 comparators with negative inputs evenly spaced at 1LSB increments fro
6. INPUT CLOCK PHASING Figure 3 Output Timing Test Mode DIV10 GND MAKI 8 TOTXVIN MAX101 500Msps 8 Bit ADC with Track Hold Definitions of Specifications Signal to Noise Ratio and Effective Bits Signal to noise ratio SNR is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other analog to digital A D out put signals The theoretical minimum A D noise is caused by quantization error and is a direct result of the ADC s resolution SNR 6 02N 1 76 dB where N is the number of effective bits of resolution Therefore a perfect 8 bit ADC can do no better than 50dB The FFT plots in the Typical Operating Characteristics show the output level in various spectral bands Effective bits is calculated from a digital record taken from the ADC under test The quantization error of the ideal converter equals the total error of the device In addition to ideal quantization error other sources of error include all DC and AC nonlinearities clock and aperture jitter missing output codes and noise Noise on references and supplies also degrades effective bits performance The ADC s input is a sine wave filtered with an anti aliasing filter to remove any harmonic content The digi tal record taken from this signal is compared against a mathematically generated sine wave DC offsets phase and amplitudes of the mathematical model are adjusted until a best fit sine wave is foun
7. input comparators Internal processing of the sampled data takes an addi tional 15 clock cycles before it is available at the out puts AData and BData See Figures 1 3 for timing Applications Information Analog Input Ranges Although the normal operating range is 270mV the MAX101 can be operated with up to 500mV on each input with respect to ground This extended input level includes the analog signal and any DC common mode voltage To obtain full scale digital output with differential input drive a nominal 270mV must be applied between AIN and AIN That is AIN 135mV and AIN 135mV with no DC offset Mid scale digital output code occurs when there is no voltage difference across the analog inputs Zero scale digital output code with differential 270mV drive occurs when AIN 135mV and AIN 135mV Table 2 shows how the output of the converter stays at all ones full scale when over ranged or all zeros zero scale when under ranged 11 TOTXVIN MAX101 500Msps 8 Bit ADC with Track Hold Table 2 Input Voltage Range AIN AIN OUTPUT MSB to INPUT mV mV CODE LSB 4135 135 11111111 full scale Differential 0 0 10000000 mid scale 135 135 00000000 zero scale 4270 0 11111111 ful scale Single Ended 0 0 10000000 mid scale 270 0 00000000 scale An offset VIO as specified in the DC electrical paramters will be present at the input C
8. resistor at the buffer s output see Typical Operating Circuit This resistor and capacitor combination should be located within 0 5 inches of the MAX101 package Any noise on these pins will directly affect the code uncertainty and degrade the ADC s effective bits performance 12 POSITIVE REFERENCE PARASITIC RESISTANCE o gt TO COMPARATORS R r PARASITIC RESISTANCE NEGATIVE REFERENCE Figure 5 Reference Ladder AVLAZCLAWI 500Msps 8 Bit ADC with Track Hold CLK and DCLK All input and output clock signals are differential The input clocks CLK and CLK are the primary timing sig nals for the MAX101 CLK pins 2 62 and CLK pins 3 61 are fed to the internal circuitry through an internal 500 transmission line One set of CLK CLK inputs should be driven and the other pair terminated by 50Q to 2V Either set of inputs can be used as the driven inputs input lines are balanced for easy circuit con nection A minimum pulse width is required for CLK and CLK Figures 1 3 For best performance and consistent results use a low phase jitter clock source for CLK and CLK Phase jitter larger than 2ps from the input clock source reduces the converter s effective bits performance and causes inconsistent results The clock supplied to the MAX101 is internally divided by two reshaped and buffered This divided clock becomes the internal s
9. unless otherwise noted INTEGRAL NONLINEARITY vs OUTPUT CODE INL LSBs MAX101 TOC 256 DIFFERENTIAL NONLINEARITY vs OUTPUT CODE DNL LSBs AVLAZCLAWI 500Msps 8 Bit ADC with Track Hold Typical Operating Characteristics continued VEE 5 2V Voc 5V RL 1000 to 2V VAnr VBnr 1 02V VBRB 1 02V Ta 25 C unless otherwise noted FFT PLOT FFT PLOT fain 251 4462MHz fain 10 4462M Hz 9 fak 500MHz 0 fak 250MHz 10 SER 44 50B 10 SER 47 2dB 20 NOISE FLOOR 67 30B 20 NOISE FLOOR 70 50 30 SPURIOUS 58 2dB 30 SPURICUS 61 8dB 40 40 g 50 50 60 60 70 70 80 80 90 90 100 100 0 25 50 75 100 125 MHz EFFECTIVE BITS vs ANALOG INPUT EFFECTIVE BITS vs CLOCK FREQUENCY fain FREQUENCY fcik fcLk 500MHz Vin 95 FS fain 500MHz Vin 95 FS 8 8 e e 5 5 7 7 6 6 0 50 100 150 200 250 300 0 100 200 300 400 500 600 fain MHZ a MHz 5 TOTXVIN MAX101 500Msps 8 Bit ADC with Track Hold Typical Operating Characteristics continued VEE 5 2V Voc 5V RL 1000 to 2V VART VBnr 1 02V VBRB 1 02V Ta 25 C unless otherwise noted DATA CLOCK DCLK DATA CLOCK DCLK FALL TIME RISE TIME 526ps D
10. ITIONS MIN TYP MAX UNITS REFERENCE INPUT Reference String Resistance RREF to VARB 100 175 Q Reference String Resistance 0 02 arc Temperature Coefficient LOGIC INPUTS Digital Input Low Voltage VIL CLK CLK Ta TMIN to TMAX 1 50 V Digital Input High Voltage ViH CLK CLK TA TMIN to TMAX 1 1 V Digital Input High Current DIV10 OV TMIN to TMAX 11 3 1 mA Input Bias Current TMIN to 40 pA p CLK CLK 0 8V z Clock Input Bias Current termination TMIN to TMAX 50 yA LOGIC OUTPUTS Note 8 25 1 95 1 60 AData BData ai TMIN to TMAX 1 95 1 50 Digital Output Low Voltage VoL V 25 1 3 1 00 DCLK DCLK TMIN to TMAX 1 4 0 9 DE a AData BData TA 25 C 1 02 0 70 Digital Output High Voltage M V 9 9 9 on DCLK DCLK TA TMIN to TMAX 1 10 0 60 Digital Output Voltage DCLK Ta TMIN to TMAX 275 445 mV POWER REQUIREMENTS Ta 25 C 550 765 1065 Positive Supply Current Vcc 5 0V mA voc e TA TMIN to TMAX 1130 Negative Supply Current 5 2V PO IVi 0 9 MEE EE TA TMIN to TMAX 975 Common Mode Rejection Ratio CMRR VINCM 0 5V TMIN to TMAX 35 dB Jur Vcc nom 0 25V 40 Power Supply Rejection Ratio PSRR TA Tmn to dB PIA VEE nom 0 25 T 40 MAXIM 3 TOTXVIN MAX101 500Msps 8 Bit ADC wi
11. IV10 OPEN 352ps DIV10 OPEN 550mV 550mV MAX101 TOC7 MAX101 100mV div 100mV div 1 55V 1 55V 4 18ns 5 2ns 418ns 5 2ns BDATA RISE TIME 855ps BDATA FALL TIME 714ps DIV10 OPEN DIV10 OPEN 825mV 825mV 8 100mV div 100mV div 1 825V 1 825V 4 98ns 5 02ns 4 98ns 5 02ns DU LL IW AKIZA 500Msps 8 Bit ADC with Track Hold Pin Description PIN NAME FUNCTION 1 PAD Internal connection leave open 2 62 CLK Complementary Differential Clock Inputs Can be driven from standard 10KH ECL with the following considerations Internally pins 2 62 and 3 61 are the ends of a 50Q transmission line Either end 3 61 CLK can be driven with the other end terminated with 50Q to 2V See Typical Operating Circuit 4 7 15 18 24 27 30 34 37 40 ES et 1 GND Power Supply Ground 68 70 71 74 77 78 79 82 84 5 59 TRK1 Phasing inputs normally left open See Applications Information section 6 58 TRK1 E De VCC Positive Power Supply 5V 5 nominal 9 VBRB B side negative reference voltage input Note 9 10 VBRBS B side negative reference voltage sense Note 9 11 TP4 Internal connection leave pin open 12 TP3 Internal connection leave pin open 13 VBRTS B side positive reference voltage sense Note 9 14 VBRT B side positive reference voltage input
12. Note 9 16 48 63 N C No Connect no internal connection to these pins 29 SUB Circuit Substrate contact This pin must be connected to VEE 31 DCLK Complementary Differential Clock Outputs Used to synchronize following circuitry Outputs A0 A7 are valid after DCLK s rising edge BO B7 output data are valid after DCLK s falling edge see Figure 1 33 DCLK for output timing information 32 69 80 VEE Negative Power Supply 5 2V 5 nominal 35 DIV10 Divide by 10 mode Leave open for normal operation Selects test mode when grounded 36 38 39 41 42 44 7 45 47 AData and BData Outputs AO and BO are the LSBs and A7 and B7 are the MSBs AData and BData outputs conform to ECL logic swings and drive 100Q transmission lines Terminate with 100Q to 2V 28 26 25 1200 for Tj gt 100 C See Figures 1 3 23 22 20 B7 B0 19 17 MAKU e e n LU e E TOTXVIN MAX101 500Msps 8 Bit ADC with Track Hold Pin Description continued PIN NAME FUNCTION 50 VART A side positive reference voltage input Note 9 51 VARTS A side positive reference voltage sense Note 9 52 TP1 Internal connection leave pin open 53 TP2 Internal connection leave pin open 54 VARBS A side negative reference voltage sense Note 9 55 VARB A side negative reference voltage input Note 9 65 TP5 Internal connection leave pin open 66 TP6 Internal connection leave p
13. TIONS MIN TYP MAX UNITS ACCURACY Resolution 8 Bits 25 0 50 Integral Nonlinearity Note 4 INL AData BData LSB 9 ity TMIN to TMAX 0 75 AData BData TA 25 C 0 75 Differential Nonlinearity DNL no missing codes Ta TMIN to TMAX 085 LSB DYNAMIC SPECIFICATIONS folk 500MHz fAIN 10MHz 7 6 Effective Bits ENOB VIN 95 full scale fAIN 125MHz 7 1 Bits Note 5 fain 250MHz 6 7 7 0 DO fAIN 125MHz 500MHz Signal to Noise Ratio SNR VIN 95 full scale Note 6 44 5 dB Maximum Conversion Rate fcLK Note 7 500 Msps Analog Input Bandwidth 1 2 GHz Aperture Width tAW Figure 4 270 ps Aperture Jitter tAJ Figure 4 2 ps ANALOG INPUT AIN to AIN Table 2 Full scale 230 315 Vol Ri V Range N TA TMIN to TMAX Zero scale 305 215 P Input Offset Voltage AIN AIN TA TMIN to 17 32 mV Least Significant Bit Size LSB TA TMIN to TMAX 1 8 2 5 mV Input Resistance AIN AIN to GND 49 51 Q Input Resistance 0 008 arc Temperature Coefficient 2 MAXIM 500Msps 8 Bit ADC with Track Hold ELECTRICAL CHARACTERISTICS continued VEE 5 2V Voc 5V RL 1000 to 2V VART VBRT 1 02V VARB VBRB 1 02V TA 25 C unless otherwise noted TMiN to Tmax 0 C to 70 C Note 3 PARAMETER SYMBOL COND
14. d After sub tracting this sine wave from the digital record the resid ual error remains The rms value of the error is applied in the following equation to yield the ADC s effective bits measured rms error Effective bits N logo ideal rms error where N is the resolution of the converter In this case N 8 The worst case error for any device will be at the con verter s maximum clock rate with the analog input near the Nyquist rate one half the input clock rate Aperture Width and J itter Aperture width is the time the T H circuit takes to dis connect the hold capacitor from the input circuit i e to turn off the sampling bridge and put the T H in hold mode Aperture jitter is the sample to sample variation in aperture delay Figure 4 Error Rates Errors resulting from metastable states may occur when the analog input voltage at the time the sample is taken falls close to the decision point for any one of the input comparators The resulting output code for many 10 SAMPLED DATA T H wq p HOLD TRACK APERTURE DELAY tap APERTURE WIDTH taw APERTURE JITTER tay Figure 4 T H Aperture Timing typical converters can be incorrect including false full or zero scale output The MAX101 s unique design reduces the magnitude of this type of error to 1LSB and reduces the probability of the error occurring to less than one in every 1015 clock cycles If the MAX101 were operated at 500MHz
15. for optimizing convert er performance Input clock phasing is also available for interleaving several MAX101s for higher effective sampling rates MAXIM MAX101 Features 500Msps Conversion Rate 7 0 Effective Bits Typical at 250MHz 1 2GHz Analog Input Bandwidth Less than 1 2LSB INL 500 Differential or Single Ended Inputs 270mV Input Signal Range Ratiometric Reference Inputs Dual Latched Output Data Paths Low Error Rate Less than 10 15 Metastable States 84 Pin Ceramic Flat Pack Applications High Speed Digital Instrumentation High Speed Signal Processing Medical Systems Radar Signal Processing High Energy Physics Communications Ordering Information PART TEMP RANGE PIN PACKAGE 84 Ceramic Flat Pack MAX101CFR with heatsink 0 C to 70 C Contact factory for 84 pin ceramic flat pack without heatsink Functional Diagram VARB AAA FLASH CONVERTER 8 BIT FLASH CONVERTER WV PHap VBRrs MAXIM Maxim Integrated Products 1 Call toll free 1 800 998 8800 for free literature LOLXVIA MAX101 500Msps 8 Bit ADC with Track Hold ABSOLUTE MAXIMUM RATINGS Supply Voltages DIV10 Input Voltage VIH VEE to OV Output Current TJ lt 100 100 C lt TJ lt 125 Operating Temperature Range
16. ignal to 270mV differential assuming a 1 02V reference 2 It provides a differential 50Q input that allows easy interface to the MAX101 _____________________________________ Table 1 Output Mode Control DCLK DIV10 MHz MODE DESCRIPTION Normal AData and BData valid on oppo OPEN 250 Divide site DCLK edges AData on rise by 2 BData on fall AData and BData valid on oppo Test site DCLK edges AData on rise GND 50 Divide BData on fall Data sampled at by 10 input CLK rate but 4 out of every 5 samples discarded Input clocks CLK CLK 500MHz for all above combinations In all modes the output clock DCLK will be a 50 duty cycle signal Data Flow The MAX101 s internal T H amplifier samples the analog input voltage for the ADC to convert The T H is split into two sections that operate on alternate negative clock edges The input clock CLK is conditioned by the T H and fed to the A D section The output clock DCLK used for output data timing will be divided by 2 or 10 from the input clock CLK Table 1 This would result in an output data rate of 250Mbps on each output port in normal mode and 50Mbps in test mode The differential inputs AIN and AIN are tracked continuously between data samples When a negative strobe edge is sensed one half of the T H goes into the hold mode Figure 4 When the strobe is low the just acquired sample is presented to the ADC s
17. ignal used as strobes for the converters DCLK and DCLK are output clock signals derived from the input clocks and are used for external timing of the AData and BData outputs AData is valid after the ris ing edge of DCLK and BData is valid after the falling edge They are fixed at one half the rate of the input clocks in normal mode Table 1 The MAX101 is char acterized to work with 500MHz maximum input clock frequencies See Typical Operating Circuit Output Mode Control DIV10 When DIV10 is grounded it enables the test mode where the input incoming clock is divided by ten This reduces the output data and clock rates by a factor of 5 allowing the output clock duty cycle to remain at 50 The clock to output phasing remains the same and four out of every five sampled input values are dis carded When left open this input DIV10 is pulled low by inter nal circuitry and the converter functions in its normal mode MAKLM Layout Grounding and Power Supplies A 5V 5 supply as well as a 5 2V 5 supply is needed for proper operation Bypass the VEE and VCC supply pins to GND with high quality and 0 001 ceramic capacitors located as close to the package as possible Connect all ground pins to a ground plane to optimize noise immunity and highest device accuracy Phase Adjust This control pin affects the point in time that one half of the converter samples the input signal relative to the other half PHADJ i
18. in open 72 78 AIN Analog Inputs internally terminated with 50Q to ground Full scale linear input range is approximately 270mV Drive AIN and AIN differentially for best high frequency performance 75 76 AIN 83 PH Phase adjustment for T H Normally connected to ground A phase adjustment of approximately 18ps ADJ can be made by varying this pin s bias point to optimize interleaving between sides A and B Note 10 Note 9 VART VBnr and should be adjusted separately from a well bypassed reference circuit to ensure proper amplitude and offset matching The sense connections to each of these terminals allows precision setting of the reference voltage The reference ladder is similar for both converter halves check electrical section for values Any noise on these terminals will severely reduce overall performance Note 10 Good results are obtained by connecting the PHApJ input to ground Improve performance by applying a voltage between 1 25V to this input The time that the A T H bridge samples relative to the time that the T H bridge samples can be varied through a 18ps range Figure 1 Output Timing Normal Mode DIV10 OPEN 85 MAXIM 500Msps 8 Bit ADC with Track Hold NE Ax ADATA Y BDATA y tpp2 NOTE DATA ARBITRARY ON START UP FOR SIDE A OR B SEE
19. m the bottom to the top of the ref erence ladder For n 8 there are 255 comparators For any input voltage all the comparators with negative inputs connected to the reference ladder below the input voltage will have outputs of 1 and all comparators with negative inputs above the input voltage will have outputs of 0 Decode logic is provided to convert this information into a parallel n bit digital word the output corresponding to the number of LSBs minus 1 that the input voltage is above the bottom of the ladder The comparators contain latch circuitry and are clocked This allows the comparators to function as described previously when for example clock is low When clock goes high samples the comparator will latch and hold its state until the clock goes low again The MAX101 uses a monolithic dual interleaved parallel quantizer chip with two separate 8 bit converters These converters deliver results to the A and B output latches on alternate negative edges of the input clock Track Hold As with all ADCs if the input waveform is changing rapidly during the conversion the effective bits and SNR will decrease The MAX101 has an internal track hold T H that increases attainable effective bits performance and allows more accurate capture of ana log data at high conversion rates The internal T H circuit provides two important circuit functions for the MAX101 1 Its nominal voltage gain of 4 reduces the input dri ving s
20. ompensate for this offset by adjusting the reference voltage Offsets may be different between side A and side B For single ended operation 1 Apply a DC offset to one of the analog inputs or leave one input open Both AIN and AIN are ter minated internally with 50O to analog ground 2 Drive the other input with a 270mV offset to obtain either full or zero scale digital output If a DC common mode offset is used the total voltage swing allowed is X500mV analog signal plus offset with respect to ground Reference The ADC s reference resistor is a Kelvin sensed resis tor string that sets the ADC s LSB size and dynamic operating range Normally the top and bottom of this string are driven with an external buffer amplifier It will need to supply approximately 21mA due to the 1000 minimum resistor string impedance A 1 02V refer ence voltage is normally applied to inputs VART VBRT and This reference voltage can be adjust ed up to 1 2V to accommodate extended input requirements accuracy specifications are guaranteed with 1 02V references The reference inputs VARTS VARBS VBRrTS and VBngs allow Kelvin sensing of the applied voltages to increase precision An RC network at the ADC s reference terminals is needed for best performance This network consists of a 33Q resistor connected in series with the buffer out put that drives the reference A 0 47uF capacitor must be connected near the
21. s normally connected to ground OV but can be adjusted over a 1 25V range that typically provides a 18ps adjustment between the A side T H bridge strobe and the B side T H bridge strobe Input Clock Phasing TRK1 TRK1 At power up the clock edge from which AData and BData are synchronized is undetermined The convert er can work from a specific input clock edge as described in the following paragraph TRK1 and TRK1 are differential inputs that are used in addition to the normal input clock CLK to set data phasing A signal at one half the input clock rate with the proper setup and hold times setup and hold typi cally 300ps is applied to these inputs Choose AData by applying a logic 1 to TRK1 0 to TRK1 before CLK s negative transition Choose BData by applying a logic 0 at CLK s negative edge 1 to TRK1 In this manner several MAX101s can be interleaved to obtain faster effective sampling rates Voltages at the TRK1 input between 50mV are interpreted as logic 1 and voltages between 350mV and 500mvV are interpreted as logic 0 13 TOTXVIN MAX101 500Msps 8 Bit ADC with Track Hold Typical Operating Circuit WATKINS JOHNSON SMRA 89 1 2x MAXIM 1 2 MAX412 202 0 47 UF 8 21 43 56 81 MC100E D 330 CMPSH 3 20k MAXIM 1 2 MAX412 200 047yF 330 55 VAR CMPSH 3 MAXIM
22. th Track Hold TIMING CHARACTERISTICS VEE 5 2V Voc 5V RL 1000 to 2V VART VBRT 1 02V 1 02V Ta 25 C unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Pulse Width Low tPWL CLK CLK 0 9 2 5 ns Clock Pulse Width High tPWH CLK CLK 0 9 2 5 ns CLK to DCLK Propagation Delay tPD1 DIV10 0 Figures 1 2 1 2 2 3 3 4 ns DCLK to A BData Propagation Delay tpp2 DIV10 0 Figures 1 2 0 7 1 3 1 8 ns Rise Time t 20 to 80 DOLK 300 s R ee DATA 850 p DCLK 400 Fall Ti 20 5 all Time tF 0 to 80 DATA 700 p Pipeline Delay See Figures 2 3 TX Clock Latency NPD and Table 1 Divide bysiomode 18 19 Cycles Note 3 All devices are 100 production tested at 25 C are guaranteed by design for TA Tmin to Tmax as specified Note 4 Deviation from best fit straight line See Integral Nonlinearity section Note 5 See the Signal to Noise Ratio and Effective Bits section in the Detailed Description of Specifications Note 6 SNRcalculated from effective bits performance using the following equation SNR dB 1 76 6 02 x effective bits Note 7 Clock pulse width minimum requirements tpw and tpwH must be observed to achieve stated performance Note 8 Outputs terminated through 100Q to 2 0V Typical Operating Characteristics VEE 5 2V Vcc 5V RL 1000 to 2V VART 1 02V VBRB 1 02V TA 25 C
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MAXIM MAX101 500Msps 8 Bit ADC with Track/Hold handbook