PHILIPS UDA1344TS handbook
Contents
1. Digital dB linear volume control low microcontroller load via L3 microcontroller Digital de emphasis for 32 44 1 and 48 kHz e Soft mute ORDERING INFORMATION BITSTREAM CONVERSION Advanced audio configuration e Stereo single ended input configuration e Stereo line output under microcontroller volume control no post filter required e High linearity dynamic range and low distortion GENERAL DESCRIPTION The UDA1344TS is a single chip stereo Analog to Digital Converter ADC and Digital to Analog Converter DAC with signal processing features employing bitstream conversion techniques The low power consumption and low voltage requirements make the device eminently suitable for use in low voltage low power portable digital audio equipment which incorporates recording and playback functions The UDA1344TS supports the 1 S bus data format with word lengths of up to 20 bits the MSB justified data format with word lengths of up to 20 bits and the LSB justified data format with word lengths of 16 18 and 20 bits The UDA1344TS also supports three combined data formats with MSB justified data output and LSB justified 16 18 and 20 bits data input The UDA1344TS can be controlled either via static pins or via the L3 interface In the L3 mode the UDA1344TS has special Digital Sound Processing DSP features in playback mode such as de emphasis volume control bass boost treble and soft mute TYPE NUMBER PA2. Low voltage low power stereo audio UDA1344TS CODEC with DSP features PACKAGE OUTLINE SSOP28 plastic shrink small outline package 28 leads body width 5 3 mm SOT341 1 N Lp HF detail X DIMENSIONS mm are the original dimensions A UNIT max A4 A3 bp mm 2 0 Note 1 Plastic or metal protrusions of 0 20 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT341 1 MO 150 E e 2 ISSUE DATE 2000 Feb 04 22 Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology A more in depth account of soldering ICs can be found in our Data Handbook IC26 Integrated Circuit Packages document order number 9398 652 90011 There is no soldering method that is ideal for all surface mount IC packages Wave soldering is not always suitable for surface mount ICs or for printed circuit boards with high population densities In these situations reflow soldering is often used Reflow soldering Reflow soldering requires solder paste a suspension of fine
3. 18 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS TIMING Vppp VppA Vppo 2 7 to 3 6 V Tamb 40 to 85 C RL 5 KQ all voltages referenced to ground unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN Tvr MAX UNIT System clock input see Fig 7 system clock cycle time fsys 256f 88 262 ns fsys 512f 44 132 ns system clock HIGH time fsys lt 19 2 MHz 0 30Tsys ns fsys 2 19 2 MHz 0 40Tsys 0 60T sys system clock LOW time fsys lt 19 2 MHz 0 30T sys 0 70T sys ns fj 2 19 2 MHz 0 40T sys 0 60T sys ns bit clock frequency Hz Serial interface input output data see Fig 8 bit clock cycle time Toys cycle time of ns bit clock HIGH time rise time word select set up time tsu DATAl data input set up time 20 E oo sample frequency th DATAO data output hold time ta DATAO BCk data output to bit clock delay from BCK falling edge ta DATAO ws data output to word select delay from WS edge for MSB justified format L3 interface input see Figs 4 and 5 Tey CLK L3 L3CLOCK cycle time 500 ns tCLK L3 L L3CLOCK LOW time 250 ns th L3 A L3MODE hold time for address mode 190 L3MODE set up time for data transfer e mode th L3 D L3MODE hold time for data transfer mode 190 ns tsu L3 DA L3DATA set up time in data transfer and 190 add
4. 256f and 384f as given in Table 7 Table 7 System clock selection PIN MP3 SELECTION LOW HIGH 256f clock frequency 384f clock frequency 2000 Feb 04 Preliminary specification UDA1344TS MUTE AND DE EMPHASIS The level definition of pin MP2 pin is given in Table 8 Table 8 Levels for pin MP2 PIN MP2 SELECTION no de emphasis and mute de emphasis 44 1 kHz mute INPUT OUTPUT DATA FORMAT SELECTION The input output data format can be selected using pins MP1 and MP5 as given in Table 9 Table 9 Data format selection PIN MP1 PIN MP5 SELECTION LOW LOW _ input MSB justified LOW HIGH input I S bus input LSB justified 20 bits output MSB justified input LSB justified 16 bits output MSB justified HIGH HIGH ADC INPUT VOLTAGE SELECTION AND POWER DOWN In the static pin mode the three level pin MP4 is used to select 0 or 6 dB gain and power down Table 10 Levels for pin MP4 PIN MP4 LOW 0 5Vppp HIGH SELECTION ADC power down 6 dB gain 0 dB gain Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features L3 mode The UDA1344TS is set to the L3 mode by setting both pins MC1 and MC2 to LOW level The static pins in this mode are used for e ADC output overload detection e L3 interface signal input e ADC input voltage selection The controllable features via the L3 interface and the definition of t
5. RMS 1 V RMS 1 V RMS 0 5 V RMS RESISTOR 12 ko INPUT GAIN SWITCH Present Present Absent Absent Decimation filter ADC The decimation from 128f to 1f is performed in 2 stages The first stage realizes 3rd order sx characteristic This filter decreases the sample rate by 16 The second stage a Finite Impulse Response FIR filter consists of 3 half band filters each decimating by a factor of 2 Table 2 Decimation filter characteristics ITEM CONDITIONS VALUE dB Pass band ripple 0 0 45f 60 Stop band gt 0 55f 108 1 16 Dynamic range An optional Infinite Impulse Response IIR high pass filter is provided to remove unwanted DC components The operation is selected by the microcontroller via the L3 interface The filter characteristics are given in Table 3 Overall gain with 0 dB input to the ADC DC cancellation filter ADC Table3 DC cancellation filter characteristics ITEM CONDITIONS VALUE dB Pass band ripple none 0 at 0 00000036f gt 40 Pass band gain Droop Attenuation at DC Dynamic range Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features Mute ADC On recovery from power down or switching on of the System clock the serial data output on pin DATAO is held at LOW level until valid data is available from the decimation filter This time depends on whether the DC cancellation filter is
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7. of data and control information between the microcontroller and the UDA1344TS is accomplished through a serial hardware interface comprising the following lines L3DATA microcontroller interface data line L3MODE microcontroller interface mode line L3CLOCK microcontroller interface clock line Information transfer via the microcontroller bus is LSB first and is organized in accordance with the so called L3 format in which two different modes of operation can be distinguished address mode and data transfer mode The address mode is required to select a device communicating via the L3 interface and to define the destination registers for the data transfer mode Data transfer for the UDA1344TS can only be in one direction input to the UDA1344TS to program its sound processing and other functional features Address mode The address mode is used to select a device for subsequent data transfer and to define the destination registers The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK accompanied by 8 data bits The fundamental timing is shown in Fig 4 Data bits 7 to 2 represent a 6 bit device address with bit 7 being the MSB and bit 2 the LSB The address of the UDA1344TS is 0001 01 bits 7 to 2 2000 Feb 04 11 Preliminary specification UDA1344TS Data bits 1 and 0 indicate the type of subsequent data transfer as given in Table 13 Table 13 Selection of data transfer
8. selected e DC cancel off 41024 oar t 283 2 ms at f 44 1 kHz S e DC cancel on 12288 bp a t 279 ms at f 44 1 kHz S Interpolation filter DAC The digital filter interpolates from 1f to 128f by means of a cascade of a recursive filter and an FIR filter Table4 Interpolation filter characteristics ITEM CONDITIONS VALUE dB Pass band ripple 0 0 45f 0 03 Stop band Dynamic range Gain DC 3 5 Noise shaper DAC The 3rd order noise shaper operates at 128f It shifts in band quantization noise to frequencies well above the audio band This noise shaping technique enables high signal to noise ratios to be achieved The noise shaper output is converted into an analog signal using a Filter Stream Digital to Analog Converter FSDAC Filter stream DAC The FSDAC is a semi digital reconstruction filter that converts the 1 bit data stream of the noise shaper to an analog output voltage The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier In this way very high signal to noise performance and low clock jitter sensitivity is achieved A post filter is not needed due to the inherent filter function of the DAC On board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output The output voltage of the FSDAC scales proportionally with the power supply
9. solder particles flux and binding agent to be applied to the printed circuit board by screen printing stencilling or pressure syringe dispensing before package placement Several methods exist for reflowing for example infrared convection heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 100 and 200 seconds depending on heating method Typical reflow peak temperatures range from 215 to 250 C The top surface temperature of the packages should preferable be kept below 230 C Wave soldering Conventional single wave soldering is not recommended for surface mount devices SMDs or printed circuit boards with a high component density as solder bridging and non wetting can present major problems To overcome these problems the double wave soldering method was specifically developed 2000 Feb 04 23 Preliminary specification UDA1344TS If wave soldering is used the following conditions must be observed for optimal results e Use a double wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave For packages with leads on two sides and a pitch e larger than or equal to 1 27 mm the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed circuit board smaller than 1 27 mm the footprint longitudinal axis must be parallel to the transport direction of the printed
10. 0 0 UDAI 0 O INTEGRATED CIRCUITS DATA SHEET BITSTREAM CONVERSION UDA1344TS Low voltage low power stereo audio CODEC with DSP features Preliminary specification 2000 Feb 04 Supersedes data of 2000 Jan 27 File under Integrated Circuits IC01 Philips PHILIPS Semiconductors D fal l L Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS FEATURES General Low power consumption 3 0 V power supply System clock of 256f 384f and 512f Supports sampling frequencies from 8 to 55 kHz Non inverting ADC plus integrated high pass filter to cancel DC offset ADC supports 2 V RMS input signals Overload detector for easy record level control Separate power control for ADC and DAC Integrated digital interpolation filter plus non inverting DAC Functions controllable either via L3 microcontroller interface or via static pins UDA1344TS is pin and function compatible with UDA1340M Small package size SSOP28 Easy application Multiple format input interface e S bus MSB justified or LSB justified 16 18 and 20 bits format compatible e Three combined data formats with MSB justified output and LSB justified 16 18 and 20 bits input e 1f input and output format data rate DAC digital sound processing The sound processing features of the UDA1344TS can be used in the L3 mode only Digital tone control bass boost and treble
11. CKAGE VERSION UDA1344TS SSOP28 NAME DESCRIPTION plastic shrink small outline package 28 leads body width 5 3 mm SOT341 1 2000 Feb 04 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Supplies VDDA ADO ADC analog supply voltage VDDA DAC DAC analog supply voltage Vppo operational amplifier supply voltage Vppp digital supply voltage IDDA ADC ADC analog supply current IDDA DAC DAC analog supply current operating 4 0 Ippo operational amplifier supply current operating 4 0 peo omr pe digital supply current ambient temperature Analog to digital converter Vi rms input voltage RMS value notes 1 and 2 1 0 V THD N S total harmonic distortion plus noise to at 0 dB 85 80 dB S N signal to noise ratio Vi 0 V A weighted 95 dB total harmonic distortion plus noise to signal ratio dB dB Power performance PADDA power consumption in record and playback mode power consumption in playback mode power consumption in record mode Ppp power consumption in power down mode 17 mW Notes 1 The input voltage can be up to 2 V RMS when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor 2 The input voltage to the ADC is inver
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13. ON Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 60134 SYMBOL PARAMETER CONDITIONS Vppp digital supply voltage Txtal max maximum crystal temperature Tstg storage temperature Tamb ambient temperature Ves electrostatic handling voltage 3000 3000 V 300 4300 V Notes 1 Equivalent to discharging a 100 pF capacitor via a 1 5 kQ series resistor 2 Equivalent to discharging a 200 pF capacitor via a 2 5 uH series inductor THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rih a thermal resistance from junction to ambient in free air 90 KW DC CHARACTERISTICS Vppp Vppa Vppo 3 0 V Tamb 25 C Ri 5 KQ all voltages referenced to ground unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supplies note 1 Vppa apc ADC analog supply voltage VppA pac DAC analog supply voltage Vppo operational amplifier supply voltage Vppp digital supply voltage Ippaapo ADC analog supply current operating ADC power down Ippa pac DAC analog supply current operating DAC power down Ippo operational amplifier supply current operating DAC power down Ippp digital supply current operating DAC power down ADC power down Digital inputs Vi
14. Postbus 90050 5600 PB EINDHOVEN Bldg VB Tel 31 40 27 82785 Fax 31 40 27 88399 New Zealand 2 Wagener Place C P O Box 1041 AUCKLAND Tel 64 9 849 4160 Fax 64 9 849 7811 Norway Box 1 Manglerud 0612 OSLO Tel 47 22 74 8000 Fax 47 22 74 8341 Pakistan see Singapore Philippines Philips Semiconductors Philippines Inc 106 Valero St Salcedo Village P O Box 2108 MCC MAKATI Metro MANILA Tel 63 2 816 6380 Fax 63 2 817 3474 Poland Al Jerozolimskie 195 B 02 222 WARSAW Tel 48 22 5710 000 Fax 48 22 5710 001 Portugal see Spain Romania see Italy Russia Philips Russia Ul Usatcheva 35A 119048 MOSCOW Tel 7 095 755 6918 Fax 7 095 755 6919 Singapore Lorong 1 Toa Payoh SINGAPORE 319762 Tel 65 350 2538 Fax 65 251 6500 Slovakia see Austria Slovenia see Italy South Africa S A PHILIPS Pty Ltd 195 215 Main Road Martindale 2092 JOHANNESBURG P O Box 58088 Newville 2114 Tel 27 11 471 5401 Fax 27 11 471 5398 South America Al Vicente Pinzon 173 6th floor 04547 130 SAO PAULO SP Brazil Tel 55 11 821 2333 Fax 55 11 821 2382 Spain Balmes 22 08007 BARCELONA Tel 34 93 301 6312 Fax 34 93 301 4107 Sweden Kottbygatan 7 Akalla S 16485 STOCKHOLM Tel 46 8 5985 2000 Fax 46 8 5985 2745 Switzerland Allmendstrasse 140 CH 8027 ZURICH Tel 41 1 488 2741 Fax 41 1 488 3263 Taiwan Philips Semiconductors 6F No 96 Chien Kuo N Rd Sec 1 TAIPEI
15. TRANSFER data volume bass boost treble de emphasis mute mode and power control 0 1 not used 1 0 status system clock frequency data input output format and DC filter 1 1 not used In the event that the UDA1344TS receives a different address it will deselect its microcontroller interface logic Data transfer mode The selection preformed in the address mode remains active during subsequent data transfers until the UDA1344TS receives a new address command The fundamental timing of data transfers is essentially the same as in the address mode and is shown in Fig 5 The maximum input clock and data rate is 64f All transfers are byte wise i e they are based on groups of 8 bits Data will be stored in the UDA1344TS after the eighth bit of a byte has been received A multibyte data transfer is illustrated in Fig 6 Programming the sound processing and other features The sound processing and other feature values are stored in independent registers The first selection of the registers is achieved by the choice of data type that is transferred This is performed in the address mode by bit 1 and bit O see Table 13 The second selection is performed by the 2 MSBs of the data byte bit 7 and bit 6 The other bits in the data byte bits 5 to 0 is the value that is placed in the selected registers Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC wi
16. VC4 VC3 VC2 VC1 VCO VC volume control 6 bits see Table 19 BB bass boost 4 bits see Table 20 TR treble 2 bits see Table 21 DE de emphasis 2 bits see Table 22 MT mute 1 bit see Table 23 M filter mode 2 bits see Table 24 1 1 0 0 0 0 PC1 PCO PC power control 2 bits see Table 25 2000 Feb 04 13 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS SYSTEM CLOCK FREQUENCY VOLUME CONTROL A 2 bit value to select the used external clock frequency A 6 bit value to program the left and right channel volume attenuation The range is from 0 to e dB in steps of 1 dB Table 16 System clock frequency settings Table 19 Vol i SELECTION able 19 Volume settings oi o not used DATA INPUT FORMAT A 3 bit value to select the used data format Table 17 Data format settings IF2 IF1 FORMAT I S bus BASS BOOST A 4 bit value to program the bass boost setting The used set depends on the mode bits M1 and MO input LSB justified 16 bits Table 20 Bass boost settings output MSB justified input LSB justified 18 bits BASS BOOST SETTING output MSB justified BB3 BB2 BB1 BBO FLAT MIN MAX 1 1 1 input LSB justified 20 bits dB dB dB output MSB justified 0 0 0 DC FILTER o 2 o AJN AJN A 1 bit v
17. a AI e o 000 o sug 8L LVWHOS G3ldlLSnf 8s1 XE aper sure PAN AS Ne ad Na Na ase Jf V Vows L St OL ZL 8L SL OL ZL 8L J E a4 mS HN o SM sug 9L LVWHOS AJIHILSNMA ASI La PEA EN TN NAA MY TAPIN TAAA VUV VV VVV VJ Xon J a WOM E E E a f sm LVWHOS GAlsILSNr asw Yea YasnXasiy X X X Xe YaswXasrX X Pees Ree hae I ES Be BUR ORO RW ee alee Bee ee IRSIY 1431 SM 1VINHO Sh8 Szl yes X CX XO Xe EPI e e mE uw en gt ues 1H914_ GH sm 2000 Feb 04 Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features Static pin mode The UDA1344TS is set to static pin mode by setting both pins MC1 and MC2 to HIGH level The controllable features in this mode are e System clock frequency selection e Data input output format selection e De emphasis and mute control e Power down and ADC input level selection PINNING DEFINITION The pinning definition in the static pin mode is given in Table 6 Table6 Pinning definition in static pin model DESCRIPTION data input output setting three level pin to select no de emphasis de emphasis or mute 256f or 384f system clock selection three level pin to select ADC power down ADC input 1 V RMS or ADC input 2 V RMS MP5 data input output setting SYSTEM CLOCK In the static pin mode the options are
18. alue to enable the digital DC filter Table 18 DC filtering o2 o o o o DC SELECTION 0 no DC filtering 1 DC filtering OoO o i ojlo LA Oo Oj ojojojoj ojoj ojo o Olojojoj j ojo o o o o e k Co NO PO hw oO o O ojo o a a a a N AB De x m nmm ABE 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 k 2000 Feb 04 14 Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features TREBLE A 2 bit value to program the treble setting The used set depends on the mode bits M1 and MO Table 21 Treble settings TREBLE SETTING 0 0 1 1 DE EMPHASIS A 2 bit value to enable the digital de emphasis filter Table 22 De emphasis settings DEO DE1 SELECTION no de emphasis 0 0 0 1 de emphasis 32 kHz 1 0 de emphasis 44 1 kHz 1 1 de emphasis 48 kHz MUTE A 1 bit value to enable the digital mute Table 23 Mute M SELECTION T 0 no muting 1 muting 2000 Feb 04 Preliminary specification UDA1344TS MODE A 2 bit value to program the mode of the sound processing filters of bass boost and treble Table 24 Flat min max switch POWER CONTROL A 2 bit value to disable the ADC and or DAC to reduce power consumption Table 25 Power control settings SELECTI
19. circuit board The footprint must incorporate solder thieves at the downstream end For packages with leads on four sides the footprint must be placed at a 45 angle to the transport direction of the printed circuit board The footprint must incorporate solder thieves downstream and at the side corners During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Typical dwell time is 4 seconds at 250 C A mildly activated flux will eliminate the need for removal of corrosive residues in most applications Manual soldering Fix the component by first soldering two diagonally opposite end leads Use a low voltage 24 V or less soldering iron applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE REFLOW BGA LFBGA SQFP TFBGA not suitable suitable HBCC HLQFP HSQFP HSOP HTQFP HTSSOP SMS not suitable suitable PLCCO SO SOJ suitable sui
20. he control registers are given in Section L3 interface PINNING DEFINITION The pinning definition in the L3 mode is given in Table 11 Table 11 Pinning definition in L3 mode FUNCTION ADC output overload detection L3MODE input L3CLOCK input L3DATA input ADC input voltage selection 1 V RMS or 2 V RMS 2000 Feb 04 Preliminary specification UDA1344TS ADC OUTPUT OVERLOAD DETECTION In practice the output is used to indicate whenever the output data in either the left or right channel is greater than 1 dB actual figure is 1 16 dB of the maximum possible digital swing When this condition is detected pin MP1 is forced to HIGH level for at least 512f cycles 11 6 ms at fs 44 1 kHz This time out is reset for each infringement ADC INPUT VOLTAGE SELECTION In the L3 mode pin MP5 is used to select 0 or 6 dB gain Table 12 Levels for pin MP5 LOW HIGH 0 dB gain 6 dB gain Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features L3 INTERFACE The UDA1344TS has a microcontroller input mode In the microcontroller control mode all the digital sound processing features and the system controlling features can be controlled by the microcontroller The controllable features are e System clock frequency Data input format Power control e DC filtering De emphasis Volume e Flat min max switch Bass boost Treble e Mute The exchange
21. iconductors Date of release 2000 Feb 04 Document order number 9397 750 06836 Lott make things bello S PHILIPS
22. n HIGH level input voltage Vppp 0 5 IV ViL LOW level input voltage 0 5 0 2Vppp V Hul input leakage current Ci input capacitance 10 pF 2000 Feb 04 16 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS SYMBOL PARAMETER CONDITIONS MIN Digital outputs Vou HIGH level output voltage lou 2 mA 0 85Vppp VoL LOW level output voltage lo 2 mA Three level inputs pins MP2 and MP4 HIGH level input voltage 0 9Vppp Vppp 0 5 MIDDLE level input voltage 0 4Vppp 0 6Vppp LOW level input voltage 0 5 0 1Vppp Analog to digital converter Vret A reference voltage referenced to 0 45VppA O 5VppA 0 55VppA 2 V SSA ADC o refA output resistance on pin Vret A Ri input resistance fi 1 kHz 9 8 ao n m input capacitance Sia to analog converter reference voltage referenced to 0 45Vppa 0 5Vppa Vssa DAC output resistance on pin Vret D output resistance of DAC maximum output current THD N S lt 0 1 96 RL 5kQ load resistance load capacitance Notes 1 All power supply pins Vpp and Vss must be connected to the same external power supply unit 2 When higher capacitive loads must be driven a 100 Q resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier 2000 Feb 04 17 Philips Semiconductors Low v
23. nary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS NOTES 2000 Feb 04 26 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS NOTES 2000 Feb 04 27 Philips Semiconductors Argentina see South America Australia 3 Figtree Drive HOMEBUSH NSW 2140 Tel 61 2 9704 8141 Fax 61 2 9704 8139 Austria Computerstr 6 A 1101 WIEN P O Box 213 Tel 43 1 60 101 1248 Fax 43 1 60 101 1210 Belarus Hotel Minsk Business Center Bld 3 r 1211 Volodarski Str 6 220050 MINSK Tel 375 172 20 0733 Fax 375 172 20 0773 Belgium see The Netherlands Brazil see South America Bulgaria Philips Bulgaria Ltd Energoproject 15th floor 51 James Bourchier Blvd 1407 SOFIA Tel 359 2 68 9211 Fax 359 2 68 9102 Canada PHILIPS SEMICONDUCTORS COMPONENTS Tel 1 800 234 7381 Fax 1 800 943 0087 China Hong Kong 501 Hong Kong Industrial Technology Centre 72 Tat Chee Avenue Kowloon Tong HONG KONG Tel 852 2319 7888 Fax 852 2319 7700 Colombia see South America Czech Republic see Austria Denmark Sydhavnsgade 23 1780 COPENHAGEN V Tel 45 33 29 3333 Fax 45 33 29 3905 Finland Sinikalliontie 3 FIN 02630 ESPOO Tel 358 9 615 800 Fax 358 9 6158 0920 France 51 Rue Carnot BP317 92156 SURESNES Cedex Tel 33 1 4099 6161 Fax 33 1 4099 6427 Germany HammerbrookstraBe 69 D 20097
24. oltage low power stereo audio Preliminary specification UDA1344TS CODEC with DSP features AC CHARACTERISTICS Vppp Vppa Vppo 3 0 V fi 1 KHZ Tamb 25 C Rq 5 KQ all voltages referenced to ground unless otherwise specified SYMBOL PARAMETER CONDITIONS TYP MAX UNIT Analog to digital converter input voltage RMS value notes 1 and 2 unbalance between channels total harmonic distortion plus noise to signal ratio signal to noise ratio at 0 dB at 60 dB A weighted Vi 2 0 V A weighted PSRR channel separation power supply rejection ratio fripple 1 kHz V ripple 300 mV p p Digital to ana log converter output voltage RMS value notes 3 and 4 unbalance between channels total harmonic distortion plus noise to signal ratio signal to noise ratio at 0 dB at 60 dB A weighted code 0 A weighted PSRR channel separation power supply rejection ratio fripple 1 KHz V ripple 300 mV p p 100 100 Notes 1 The input voltage can be up to 2 V RMS when the current through the ADC input pin is limited to approximately 1 mA by us ing a series resistor 2 The input voltage to the ADC is inversely proportional with the supply voltage 3 The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M 4 The output of the DAC scales proportionally with the supply voltage 2000 Feb 04
25. ress mode th L3 DA L3DATA hold time in data transfer and 3s address mode 2000 Feb 04 19 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS MGL443 Fig 7 System clock timing p WS E 7 ta DATAO BCk eh ja BCK BCKL ja lj ta DATAO WS th DATAO Tcy BCK DATAO su DATAI gt n DATAI lt Fig 8 Serial interface timing MGS756 2000 Feb 04 20 Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features APPLICATION INFORMATION Preliminary specification UDA1344TS VDD1 Vpp2 R21 R28 1Q C2 mm R24 C9 IE 1k L1 nn Vi 8LM32A07 pbi L2 00 M 8LM32A07 DD2 C12 1 100 uF uF system R30 SYSCLK clock 470 DATAO BCK overload 4 MP1 flag 1 left X4 He VINL input L 47 uF 1 16 V x C6 right 7 J input L 47 uF 16 V c22 C8 100nF 47 uF Lev INL VOUTL m R23 AS dett Q output 47 UF lag 1 ig 16V 10Ka UDA1344TS yl E on L ee MGL444 VSSA DAC C27 Vpp1 Vpp1 Fig 9 Application diagram 2000 Feb 04 21 Philips Semiconductors Preliminary specification
26. sely proportional to the supply voltage 3 The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M 4 The output of the DAC scales proportionally with the supply voltage 2000 Feb 04 3 Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features BLOCK DIAGRAM Preliminary specification UDA1344TS VDDA ADC VSSA ADC VADCN VADCP Vref A 3 0 dB 6 dB NOE SWITCH d VDDO Vsso 0 dB 6 dB VINR SWITCH ADC ADC MC1 DECIMATION FILTER ooo MP5 SSD DC CANCELLATION FILTER Ce DATAO MP2 BCK L3 BUS us DIGITAL INTERFACE INTEHPADE MP3 DATAI MP4 SYSCLK MP1 DSP FEATURES E INTERPOLATION FILTER UDA1344TS NOISE SHAPER VOUTL VOUTR VDDA DAC VSSA DAC Fig 1 Block diagram MGL441 Vref D 2000 Feb 04 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS PINNING SYMBOL DESCRIPTION Vssaapc 1 ADC analog ground Vppaiapc 2 ADC analog supply voltage VINL 3 ADC input left Vret A 4 ADCreference voltage VINR 5 ADC input right VADCN 6 ADC negative reference voltage VSSA ADC Vref D VADCP 7 ADOC positive reference voltage VDDA ADC Vsso MC1 8 mode control 1 input pull down VINL VOUTL MP1 9 multi purpose pin 1 output Vref A ang Vppp 10 digital supply voltage VING vofa Vs
27. sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 2000 Feb 04 24 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS NOTES 2000 Feb 04 25 Philips Semiconductors Prelimi
28. sp 11 digital ground TUN PN SYSCLK 12 system clock input 256fs 384f or 512f VADCP TE VSSA DAC MP2 13 multi purpose pin 2 input MC1 MC2 MP4 15 multi purpose pin 4 input VBED DATAI BCK 16 bit clock input Usep DATNO WS 17 word select input DATAO 18 data output iud iux data input Me BOK multi purpose pin 5 output MP3 MP4 MC2 pull down mode control 2 input pull down VSSA DAC VDDA DAC DAC analog ground DAC analog supply voltage VOUTR Vppo DAC output right operational amplifier supply voltage VOUTL Vsso DAC output left operational amplifier ground Viet D 2000 Feb 04 DAC reference voltage MGL442 Fig 2 Pin configuration Philips Semiconductors Low voltage low power stereo audio CODEC with DSP features FUNCTIONAL DESCRIPTION The UDA1344TS accommodates slave mode only this means that in all applications the system devices must provide the system clock The system clock must be locked in frequency to the digital interface input signals The BCK clock can be up to 128f or in other words the BCK frequency is 128 times the Word Select WS frequency or less fgck lt 128 x fws Remarks 1 The WS edge MUST fall on the negative edge of the BCK clock at all times for proper operation of the digital I O data interface 2 The sampling frequency range is from 5 to 55 kHz 3 For MSB and LSB justified formats it is important to ha
29. table LQFP QFP TQFP not recommended s 4 suitable SSOP TSSOP VSO not recommended suitable Notes 1 All surface mount SMD packages are moisture sensitive Depending upon the moisture content the maximum temperature with respect to time and body size of the package there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them the so called popcorn effect For details refer to the Drypack information in the Data Handbook IC26 Integrated Circuit Packages Section Packing Methods 2 These packages are not suitable for wave soldering as a solder joint between the printed circuit board and heatsink at bottom version can not be achieved and as solder may stick to the heatsink on top version 3 If wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 4 Wave soldering is only suitable for LQFP TQFP and QFP packages with a pitch e equal to or larger than 0 8 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 65 mm 5 Wave soldering is only suitable for SSOP and TSSOP packages with a pitch e equal to or larger than 0 65 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 5 mm DEFINITIONS Data sheet status Objective specification This data
30. th DSP features UDA1344TS L3MODE th L3 A isu L3 A tCLK L3 L e tsusya M th Laya lt L3CLOCK EN Le Tcy CLK L3 lsu L3 DA th L3 DA MGL723 Fig 4 Timing in address mode stp L3 tstp L3 L3MODE tCLK L3 L i Tcy CLK L3 th L3 D isu L3 D PX ce gt m id T L3CLOCK 2 tsu L3 DA lt th L3 DA L3DATA WRITE MGL882 Fig 5 Timing in data transfer mode 2000 Feb 04 12 Philips Semiconductors Preliminary specification Low voltage low power stereo audio CODEC with DSP features UDA1344TS tstp L3 Adr L3MODE L3CLOCK address data byte 1 data byte 2 address MGL725 Fig 6 Multibyte data transfer L3 interface registers When the data transfer of type status is selected the features system clock frequency data input format and DC filter can be controlled Table 14 Data transfer of type status SC system clock frequency 2 bits see Table 16 IF data input format 3 bits see Table 17 DC DC filter 1 bit see Table 18 When the data transfer of type data is selected the features volume bass boost treble de emphasis mute mode and power control can be controlled Table 15 Data transfer of type data BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO REGISTER SELECTED 0 0 VC5
31. ve a WS signal with a duty factor of 5096 Analog to Digital Converter ADC The stereo ADC of the UDA1344TS consists of two 3rd order Sigma Delta modulators They have a modified Ritchie coder architecture in a differential switched capacitor implementation The oversampling ratio is 128 In contrast to the UDA1340M the UDA1344TS supports 1 V RMS input signals and can be set via an external resistor to support 2 V RMS input signals Analog front end The analog front end is equipped with a selectable 0 dB or 6 dB gain block The pin to select the gain switch is given in Section L3 mode This block can be used in applications in which both 1 V RMS and 2 V RMS input signals are available In applications in which a 2 V RMS input signal is used a 12 kQ resistor must be connected in series with the input of the ADC This makes a voltage divider with the internal ADC resistor and makes sure only 1 V RMS maximum is input to the IC Using this application for a 2 V RMS input signal the gain switch must be set to 0 dB When a 1 V RMS input signal is input to the ADC in the same application the gain switch must be set to 6 dB An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1 2000 Feb 04 Preliminary specification UDA1344TS Table 1 Application modes using input gain stage MAXIMUM INPUT VOLTAGE 2 V
32. voltage 2000 Feb 04 Preliminary specification UDA1344TS Multiple format input output interface The UDA1344TS supports the following data input output formats e S bus format with data word length of up to 20 bits e MSB justified serial format with data word length of up to 20 bits e LSB justified serial format with data word lengths of 16 18 or 20 bits in L3 mode only e Combined data formats L3 mode MSB justified data output and LSB justified 16 18 and 20 bits data input Static pin mode MSB justified data output and LSB justified 16 and 20 bits data input The formats are illustrated in Fig 3 Left and right data channel words are time multiplexed Control mode selection The UDA1344TS can be used under L3 microcontroller interface control or static pin control The mode can be set via the mode control pins MC1 and MC2 see Table 5 Table 5 Mode control pins PIN MC2 PIN MC1 LOW LOW MODE L3 mode Static pin mode HIGH HIGH Important in the L3 mode the UDA1344TS is completely pin and function compatible with the UDA1340M UDA1344TS Preliminary specification Low voltage low power stereo audio CODEC with DSP features Philips Semiconductors Ssjieuuo eoejejui euas g Ob LT8I SLI 02 LVWHOS G3ldi LSnf as 1 XasiXeray AER Cure SEIN ue SU CURIA Me RISER eee Re Reese ee Boe Jf X Voss L t 8t 6 0c SL OL ZL 8t 6L 0c e 1H H
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