PHILIPS UDA1324TS handbook
Contents
1. Indu eoejiejur epa ei izan 2 1 GAISLLSN 8S1 ea Y sa X za Y 99 X sa Yva Yea viva YasiXeza V VY Y ou d in 7V ae si u u G UV Von ZL 8 6 IZ v t ve Zi 8 6 0 LHOIY 1471 sm SLI 02 LVWHOS 9315115 951 AP SEPP NN PAP cal CP AE ET NED NP NEE P MAN V oos St 9 ZL 8 6L 0c SL 9 ZL 8t 6L OZ Jj m oe EE o uu f sm SLI 8L LVWHOS 0215115 951 SUA ESSIEN MN PEIN N EASIEST al ES CM St 9 ZL 8 91 9 ZL 8L J 7 uu AED E a ____ LVWHOS 9315115 98 1 X X XX za YaswX asiX X ASE ai sh MSI al Ne ee Bae eo Be 1H9IH 1491 SM 1VINHOJ SNE Szl asn A YeaYesny Y Y Y X Yea VEEP PPP NPN oe Shogo ge 1HOl an V SM 2000 Jan 20 Philips Semiconductors Ultra low voltage stereo filter DAC L3 INTERFACE The following system and digital sound processing features can be controlled in the L3 mode of the UDA1324TS e System clock frequency e Data input format De emphasis for 32 44 1 and 48 kHz Volume Soft mute The exchange of data and control information between the microcontroller and the UDA1324TS is accomplished through a serial interface compris2. 1 All surface mount SMD packages are moisture sensitive Depending upon the moisture content the maximum temperature with respect to time and body size of the package there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them the so called popcorn effect For details refer to the Drypack information the Data Handbook IC26 Integrated Circuit Packages Section Packing Methods 2 These packages are not suitable for wave soldering as a solder joint between the printed circuit board and heatsink at bottom version can not be achieved and as solder may stick to the heatsink on top version 3 If wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 4 Wave soldering is only suitable for LQFP TQFP and QFP packages with a pitch e equal to or larger than 0 8 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 65 mm 5 Wave soldering is only suitable for SSOP and TSSOP packages with a pitch e equal to or larger than 0 65 it is definitely not suitable for packages with a pitch e equal to or smaller than 0 5 mm DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data shee
3. 4 Short circuit test at Tamb 0 C and Vppa 3 V DAC operation after short circuiting cannot be warranted HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling However to be totally safe it is desirable to take normal precautions appropriate to handling MOS devices THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rih a thermal resistance from junction to ambient in free air 190 KAN QUALITY SPECIFICATION In accordance with SNW FQ 611 E DC CHARACTERISTICS Vppp 2 0 V Tamb 25 C Ry 5 all voltages referenced to ground pins Vssa and Vssp unless otherwise specified SYMBOL PARAMETER CONDITIONS Supplies VDDA analog supply voltage note 1 Vppp digital supply voltage note 1 IDDA analog supply current operating Ippp digital supply current operating 1 5 mA 2000 Jan 20 11 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS SYMBOL Digital inputs PARAMETER Vin HIGH level input voltage Vit LOW level input voltage Hu input leakage current Ci input capacitance Three level input pin APPSEL Vin HIGH level input voltage Vit LOW level input voltage DAC Vref DAC 0 7Vppp 0 2Vppp reference voltage referenced to VssA THD NJ S 0 195 lo max maximum output current 5kQ Ro output resistance CL load cap
4. 380 44 268 0461 United Kingdom Philips Semiconductors Ltd 276 Bath Road Hayes MIDDLESEX UBS 5BX Tel 44 208 730 5000 Fax 44 208 754 8421 United States 811 East Arques Avenue SUNNYVALE CA 94088 3409 Tel 1 800 234 7381 Fax 1 800 943 0087 Uruguay see South America Vietnam see Singapore Yugoslavia PHILIPS Trg N Pasica 5 v 11000 BEOGRAD Tel 381 11 3341 299 Fax 381 11 3342 553 Internet http www semiconductors philips com SCA69 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Printed in The Netherlands 545002 25 03 pp20 Philips Semiconductors Date of release 2000 Jan 20 Document order number 9397 750 06676 4 make things better S PHILIPS
5. Table 9 Data input format settings rom 25 Hi e LSB justified 18 bits 0 LSB justified 20 bits 1 MSB justified 1 not used not used not used MUTE DE EMPHASIS Mute is a 1 bit value to enable the digital mute De emphasis is a 2 bit value to enable the digital de emphasis filter Table 12 Mute setting Table 10 settings MT FUNCTION FUNCTION no muting no de emphasis muting RR de emphasis 32 kHz 0 de emphasis 44 1 kHz 1 de emphasis 48 kHz 2000 Jan 20 10 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 60134 SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Vppp digital supply voltage note 1 5 0 V VDDA analog supply voltage Txtai max maximum crystal temperature Tstg storage temperature ambient temperature electrostatic handling voltage 3000 43000 note 3 9300 300 short circuit current of DAC note 4 output short circuited to VssA pac output short circuited to VppA pAC Notes 1 All supply connections must be made to the same power supply 2 Equivalent to discharging a 100 pF capacitor via a 1 5 series resistor except pin 14 which can withstand ESD pulses of 2500 to 2500 V 3 Equivalent to discharging a 200 pF capacitor via a 2 5 uH series inductor
6. 0 UDA1224TS O U INTEGRATED CIRCUITS DATA SHEET BITSTREAM CONVERSION UDA1324TS Ultra low voltage stereo filter DAC Preliminary specification 2000 Jan 20 Supersedes data of 1999 Oct 12 File under Integrated Circuits ICO1 Philips PHILIPS Semiconductors D fal L Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS FEATURES General Low power consumption e Ultra low power supply voltage from 1 9 to 2 7 V Selectable control via L3 microcontroller interface or via static pin control System clock frequencies of 25615 384f and 512f selectable via L3 interface or 256f and 384f via static pin control Supports sampling frequencies fs from 16 to 48 kHz Integrated digital filter plus non inverting Digital to Analog Converter DAC No analog post filtering required for DAC Slave mode only applications Easy application Small package size SSOP16 Multiple format input interface e 13 mode 125 MSB justified or LSB justified 16 18 and 20 bits format compatible e Static pin mode 125 or LSB justified 16 18 and 20 bits format compatible e 1f input format data rate DAC digital sound processing Digital logarithmic volume control in L3 mode Digital de emphasis selection for 32 44 1 and 48 kHz sampling frequencies in L3 mode or 44 1 kHz sampling frequency in static pin mode Soft mute control in static pin mode or in
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8. For packages with leads on four sides the footprint must be placed at a 45 angle to the transport direction of the printed circuit board The footprint must incorporate solder thieves downstream and at the side corners During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Typical dwell time is 4 seconds at 250 C A mildly activated flux will eliminate the need for removal of corrosive residues in most applications Manual soldering Fix the component by first soldering two diagonally opposite end leads Use a low voltage 24 V or less soldering iron applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE REFLOW BGA LFBGA SQFP TFBGA not suitable suitable HBCC HLQFP HSQFP HSOP HTQFP HTSSOP SMS not suitable suitable PLCCO SO SOJ suitable suitable LQFP QFP TQFP not recommended s 4 suitable SSOP TSSOP VSO not recommended suitable Notes
9. L3 mode Advanced audio configuration Stereo line output volume control in L3 mode e High linearity wide dynamic range and low distortion ORDERING INFORMATION TYPE BITSTREAM CONVERSION APPLICATIONS Portable digital audio equipment GENERAL DESCRIPTION The UDA1324TS is a single chip stereo DAC employing bitstream conversion techniques The ultra low voltage requirements make the device eminently suitable for use in portable digital audio equipment which incorporates playback functions The UDA1324TS supports the 125 data format with word lengths of up to 20 bits the MSB justified data format with word lengths of up to 20 bits and the LSB justified serial data format with word lengths of 16 18 and 20 bits The UDA1324TS can be used in two modes L3 mode or static pin mode In the L3 mode all digital sound processing features must be controlled via the L3 interface including the selection of the system clock setting In the two static modes the UDA1324TS can be operated in the 256f and 38415 system clock mode Muting de emphasis for 44 1 kHz and four digital input formats I2S bus or LSB justified 16 18 and 20 bits can be selected via static pins The L3 interface cannot be used in this application mode so volume control is not available in this mode PACKAGE NUMBER NAME DESCRIPTION VERSION UDA1324TS SSOP16 2000 Jan 20 plastic shrink small outline package 16 leads bod
10. acitance note 2 50 Notes 1 All supply connections must be made to the same external power supply unit 2 When the DAC drives a capacitive load above 50 pF a series resistance of 100 must be used to prevent oscillations in the output operational amplifier AC CHARACTERISTICS Vppp 2 0 V fi 1 KHZ Tamb 25 C Ry 5 all voltages referenced to ground pins Vssa Vssp unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT DAC output voltage RMS value THD N S unbalance voltage between channels total harmonic distortion plus noise to signal ratio signal to noise ratio at 0 dB at 60 dB A weighted code 0 A weighted channel separation power supply ripple rejection ratio fripple 1 KHz Viipple 100 mV p p 2000 Jan 20 12 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS TIMING Vppp Vppa 1 9 to 2 7 V Tamp 40 to 85 C Ry 5 all voltages referenced to ground pins and Vssp unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT System clock see Fig 7 system clock cycle time fsys 912 LOW level system clock pulse width fsys lt 19 2 MHz fsys 2 19 2 MHz HIGH level system clock pulse width fsys lt 19 2 MHz fsys 2 19 2 MHz Digital interfac
11. an 20 Preliminary specification UDA1324TS FUNCTIONAL DESCRIPTION System clock The UDA1324TS operates in the slave mode only Therefore in all applications the system devices must provide the system clock The system frequency fsys is selectable and depends on the application mode The options are 25615 384f and 512f for the L3 mode and 256f or 384f for the static pin mode The system clock must be locked in frequency to the digital interface input signals The UDA1324TS supports sampling frequencies fs from 16 to 48 kHz Application modes The application mode can be set with the three level pin APPSEL see Table 1 e 3 mode e Static pin mode with fs 384f e Static pin mode with fsys 256 Table 1 Selecting application mode and system clock frequency via pin APPSEL VOLTAGE ON PIN APPSEL Vssp L3 mode static pin mode VDDD The function of an application input pin active HIGH depends on the application mode see Table 2 MODE ho 256 384 or 512f Table2 Functions of application input pins FUNCTION PIN L3 MODE STATIC PIN MODE TEST MUTE L3CLOCK DEEM L3MODE SFO L3DATA SF1 APPLO APPL1 APPL2 APPL3 For example in the static pin mode the output signal can be soft muted by setting pin APPLO to HIGH De emphasis can be switched on for 44 1 kHz by setting pin APPL1 to HIGH setting pin APPL1 to LOW will disable de emphasis Philips S
12. ary specification Ultra low voltage stereo filter DAC UDA1324TS PACKAGE OUTLINE SSOP16 plastic shrink small outline package 16 leads body width 4 4 mm SOT369 1 pin 1 index DIMENSIONS mm are the original dimensions UNIT Ai A2 A3 1 1 4 2 Note 1 Plastic or metal protrusions of 0 20 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT369 1 MO 152 E406 39 004 ISSUE DATE 2000 Jan 20 16 Philips Semiconductors Ultra low voltage stereo filter DAC SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology A more in depth account of soldering ICs can be found in our Data Handbook IC26 Integrated Circuit Packages document order number 9398 652 90011 There is no soldering method that is ideal for all surface mount IC packages Wave soldering is not always suitable for surface mount ICs or for printed circuit boards with high population densities In these situations reflow soldering is often used Reflow soldering Reflow soldering requires solder paste a suspension of fine solder particles flux and binding agent to be applied to the printed circuit board by s
13. creen printing stencilling or pressure syringe dispensing before package placement Several methods exist for reflowing for example infrared convection heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 100 and 200 seconds depending on heating method Typical reflow peak temperatures range from 215 to 250 C The top surface temperature of the packages should preferable be kept below 230 C Wave soldering Conventional single wave soldering is not recommended for surface mount devices SMDs or printed circuit boards with a high component density as solder bridging and non wetting can present major problems To overcome these problems the double wave soldering method was specifically developed 2000 Jan 20 17 Preliminary specification UDA1324TS If wave soldering is used the following conditions must be observed for optimal results e Use a double wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave For packages with leads on two sides and a pitch e larger than or equal to 1 27 mm the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed circuit board smaller than 1 27 mm the footprint longitudinal axis must be parallel to the transport direction of the printed circuit board The footprint must incorporate solder thieves at the downstream end
14. e registers is achieved by the choice of data type that is transferred This is performed in the address mode using bit 1 and bit 0 see Table 5 Table5 Selection of data transfer BIT 1 BITO TRANSFER data volume de emphasis mute 1 0 status system clock frequency data input format not used The second selection is performed by the 2 MSBs of the data byte bit 7 and bit 6 The other bits in the data byte bit 5 to bit 0 represent the value that is placed in the selected registers The status settings are given in Table 6 and the data settings are given in Table 7 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS L3MODE m th Laya tsu L3 A Am tgu L3 A S og in L3 A L3CLOCK Tcy CLK L3 su L3 DA h L3 DA MGL723 Fig 4 Timing address mode tstp L3 tstp L3 L3MODE tCLK L3 L Toy CLK L3 th L3 D isu L3 D P L3CLOCK tsu L3 DA 9 1 lt th L3 DA L3DATA WRITE MGL882 Fig 5 Timing data transfer mode 2000 Jan 20 8 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS tstp L3 L3MODE L3CLOCK address data byte 1 data byte 2 address MGL725 Fig 6 Mul
15. e with I2S bus see Fig 8 Tey BCk bit clock cycle time tBCKL bit clock LOW time ti fall time th DATAI data input hold time tsu ws word select set up time thws word select hold time Control L3 interface see Figs 4 and 5 tCLK L3 H L3CLOCK HIGH time tCLK L3 L L3CLOCK LOW time tsu L3 a L3MODE set up time for address mode L3MODE hold time for address mode L3MODE set up time for data transfer mode L3MODE hold time for data transfer mode L3DATA set up time for data transfer and address mode L3DATA hold time for data transfer and address mode tstp L3 se aes stop time for data transfer 190 ns mode 2000 Jan 20 13 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS MGR984 Fig 7 System clock timing WS BCK tsu DATAI gt th DATAI 4 Toy BCK gt Fig 8 I S bus timing MGL880 2000 Jan 20 14 Philips Semiconductors Ultra low voltage stereo filter DAC APPLICATION INFORMATION system clock BCK WS DATAI APPSEL 2000 Jan 20 analog supply voltage ile e 10 digital supply voltage R3 19 UDA1324TS Preliminary specification UDA1324TS Vref DAC C7 100 nF 63 V 77 Fig 9 Application diagram 15 C4 7 47 uF V MBK771 Philips Semiconductors Prelimin
16. emiconductors Ultra low voltage stereo filter DAC In the L3 mode pin APPLO must be set to LOW It should be noted that when the L3 mode is used an initialization must be performed when the IC is powered up Digital interface DATA FORMATS The digital interface of the UDA1324TS supports multiple format inputs see Fig 3 Left and right data channel words are time multiplexed The WS signal must have a 50 duty factor for all LSB justified formats The clock can be up to 64f or in other words the BCK frequency is 64 times the Word Select WS frequency or less lt 64 x fws Important the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital interface The UDA1324TS also accepts double speed data for double speed data monitoring purposes L3 MODE S bus format with data word length of up to 20 bits e MSB justified format with data word length up to 20 bits LSB justified format with data word length of 16 18 or 20 bits STATIC PIN MODE e 2S bus format with data word length of up to 20 bits LSB justified format with data word length of 16 18 or 20 bits These four formats are selectable via the static pin codes SFO and SF1 see Table 3 Table 3 Input format selection using SFO and SF1 FORMAT SFO 125 0 0 LSB justified 16 bits 0 LSB justified 18 bits 1 0 LSB justified 20 bits 1 1 2000 Jan 20 Pre
17. ing the following signals e L3DATA e L3MODE e L3CLOCK Information transfer through the microcontroller bus is organized in accordance with the L3 interface format in which two different modes of operation can be distinguished address mode and data transfer mode Address mode The address mode see Fig 4 is required to select a device communicating via the L3 interface and to define the destination registers for the data transfer mode Data bits 7 to 2 represent a 6 bit device address where bit 7 is the MSB The address of the UDA1324TS is 000101 bit 7 to bit 2 If the UDA1324TS receives a different address it will deselect its microcontroller interface logic Data transfer mode The selected address remains active during subsequent data transfers until the UDA1324TS receives a new address command 2000 Jan 20 Preliminary specification UDA1324TS The fundamental timing of data transfers see Fig 5 is essentially the same as the address mode The maximum input clock frequency and data rate is 64f Data transfer can only be in one direction consisting of input to the UDA1324TS to program sound processing and other functional features All data transfers are by 8 bit bytes Data will be stored in the UDA1324TS after reception of a complete byte A multi byte transfer is illustrated in Fig 6 Registers The sound processing and other feature values are stored in independent registers The first selection of th
18. liminary specification UDA1324TS Interpolation filter The digital filter interpolates from 1f to 12815 by cascading a recursive filter and a FIR filter see Table 4 Table4 Interpolation filter characteristics ITEM CONDITION VALUE dB Pass band ripple 0 1 Stop band Dynamic range 0 to 0 45f gt 0 55f 0 to 0 45f Noise shaper The 3rd order noise shaper operates at 128f It shifts in band quantization noise to frequencies well above the audio band This noise shaping technique enables high signal to noise ratios to be achieved The noise shaper output is converted into an analog signal using a Filter Stream Digital to Analog Converter FSDAC Filter stream DAC The FSDAC is a semi digital reconstruction filter that converts the 1 bit data stream of the noise shaper to an analog output voltage The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier In this way very high signal to noise performance and low clock jitter sensitivity is achieved A post filter is not needed due to the inherent filter function of the DAC On board amplifiers convert the FSDAC output current to an output voltage capable of driving a line output The output voltage of the FSDAC scales linearly with the power supply voltage ion t Iminary specitica Prel Philips Semiconductors UDA1324TS Ultra low voltage stereo filter DAC Syeuuo
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21. t contains preliminary data supplementary data may be published later Product specification This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 2000 Jan 20 18 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS NOTES 2000 Jan 20 19 Philips Semiconductors Argentina see South America Australia 3 Figtree Drive HOMEBUSH NSW 2140 Tel 61 2 9704 8141 Fax 61 2 9704 8139 Austria Com
22. tibyte data transfer Programming the features When the data transfer of type status is selected the features for the system clock frequency and the data input format can be controlled Table 6 Data transfer of type status BIT 7 BIT6 BIT5 BIT4 BIT3 BIT 2 BIT1 BITO REGISTER SELECTED 0 0 SC1 SCO IF2 IF1 IFO 0 SC system clock frequency 2 bits see Table 8 IF data input format 3 bits see Table 9 not used When the data transfer of type data is selected the features for volume de emphasis and mute can be controlled Table 7 Data transfer of type data BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO REGISTER SELECTED 0 0 VC5 VC4 VC3 VC2 VC1 VCO VC volume control 6 bits see Table 11 not used DE de emphasis 2 bits see Table 10 MT mute 1 bit see Table 12 default setting 2000 Jan 20 9 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS SYSTEM CLOCK FREQUENCY VOLUME CONTROL The system clock frequency is a 2 bit value to select the The volume control is a 6 bit value to program the volume external clock frequency attenuation from 0 to 60 dB and dB in steps of 1 dB Table 8 System clock settings Table 11 Volume settings 0 15121 1 384f 1 0 256f 1 1 not used DATA FORMAT The data format is a 3 bit value to select the used data format
23. y width 4 4 mm SOT369 1 Philips Semiconductors Preliminary specification Ultra low voltage stereo filter DAC UDA1324TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Supplies VDDA analog supply voltage digital supply voltage 1 9 IppA analog supply current VppAa 2 0 V output voltage RMS value note 2 total harmonic distortion plus noise to at 0 dB signal ratio at 60 dB A weighted signal to noise ratio code 0 A weighted Tamb ambient temperature 40 70 G Notes 1 The analog performance figures are measured at 2 0 V supply voltage 2 The DAC output voltage scales linearly with the power supply voltage BLOCK DIAGRAM VDDD 5 APPSEL BCK APPLO ws APPL1 DATAI APPL2 APPL3 UDA1324TS SYSCLK VOUTL VOUTR MBK770 VDDA VSSA Vret DAC Fig 1 Block diagram 2000 Jan 20 3 Philips Semiconductors Ultra low voltage stereo filter DAC PINNING SYMBOL PIN DESCRIPTION BCK 1 bit clock input WS 2 word select input Vppp 4 digital supply voltage SYSCLK 6 system clock input 256 384f and 512 application mode select input APPL3 application input pin 3 a APPL1 10 application input pin 1 Vret DAC 12 DAC reference voltage VDDA VOUTL eft channel output analog ground for DAC right channel output Vssa 1 VOUTR 1 Fig 2 Pin configuration 2000 J
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PHILIPS UDA1324TS handbook