PHILIPS UDA1321 handbook
Contents
1. N 1998 Oct 06 16 Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC Preliminary specification UDA1321 BASS USB DAC dB BASS USB SIDE dB minimum maximum 19 25 13 7 19 2 31 75 DYNAMIC BASS BOOST CONTROL Bass boost is one of the sound features as defined in the USB Device Class Definition for Audio Devices The bass boost control request data bBassBoost controls the position of the bass boost switch The position can be either on or off When bBassBoostis true the bass boost is activated When bBassBoost is false the bass boost is off When clipping prevention is active the bass is reduced to avoid clipping with high volume settings Bass boost is selectable via the configuration map see Table 6 If byte 19H is loaded with 00H bass boost is not reported to the USB host by the device 1998 Oct 06 Clipping prevention If the maximum of the bass plus volume gives clipping the Bass is reduced Clipping prevention is selectable via the configuration map De emphasis De emphasis is one of the properties which is not supported by the USB De emphasis for 44 1 kHz can be predefined in the configuration map selected at start up of the UDA1321 Philips Semiconductors Preliminary specification Un2. kon a 8582 2 04 aon VD EEPM27128 3 yn internal ROM EI ko external ROM 2 J1 1 P8 l SDA Roxb 2 0509 GP4 BCKO GP3 WSO GP2 DO RTCB L13 BLM32A07 KG 47 uF 100 nF 16V 12 63 v 10 R18 R19 TVA Tc 1 BLM32A07 il C22 100 nF Je V C10 ii BCK WS DO digital output MGM843 Fig 12 Application diagram QFP64 continued from Fig 11 1998 Oct 06 37 Preliminary specification Philips Semiconductors Universal Serial Bus USB UDA1321 Digital to Analog Converter DAC 2641015 pue 8205 e L614 Z0veeW1g 1 Van eui siseujueJed ui 8014 da 00 49 adz me SM 1 eubip ted OSNEdO ZHW 8 an OF Z1WLX Ager 0L lreervan T zm oT s sz e e d 8 AAA 8 AE E t 91 ISIWSdO a 519 920 yo 1109 099 ox ox 0L 0L Aget
3. 38 1998 Oct 06 Philips Semiconductors Preliminary specification Universal Serial Bus USB Me UDA1321 Digital to Analog Converter DAC PACKAGE OUTLINES QFP64 plastic quad flat package 64 leads lead length 1 95 mm body 14 x 20 x 2 8 mm SOT319 2 1 Res gt Lp re f detail X DIMENSIONS mm are the original dimensions A max UNIT Ai A3 bp mm 3 20 0 25 1 Plastic metal protrusions of 0 25 mm maximum per side not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT319 2 97 08 01 ISSUE DATE 1998 Oct 06 39 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 SO28 plastic small outline package 28 leads body width 7 5 mm SOT136 1 detail X 5 Scale DIMENSIONS inch dimensions are derived from the original mm dimensions UNIT Ar A2 18
4. MBC611 60 8 THIGH Fig 7 Definition of timing of the I2C bus 1998 Oct 06 19 Philips Semiconductors Universal Serial Bus USB Preliminary specification Me UDA1321 Digital to Analog Converter DAC Table 6 Control options for the UDA1321 via the EEPROM configuration map note 1 BYTE REGISTER HEX NAME COMMENTS BIT VALUE recognition pattern do not change it recognition pattern do not change it ASR control register robust word clock serial 125 output format phase inversion 00 125 01 16 bit LSB 10 18 bit LSB 11 20 bit LSB 0 mono phase inversion off 1 mono phase inversion on bits per sample modi 00 reserved 01 8 bit audio 10 16 bit audio 11 24 bit audio audio mode ASR register start up mode 0 mono 1 stereo ADAC mode register 0 1998 Oct 06 selection ADAC mode register audio feature mode de emphasis 00 flat minimum minimum maximum 0 de emphasis off 1 de emphasis on channel manipulation O L gt L R gt R 1 gt synchronous asynchronous control mute control 0 asynchronous 1 synchronous 0 mute 1 mute active reset ADAC 20 0 no reset ADAC 1 reset ADAC Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC REGISTER NAME COMME
5. LEFT Fig 9 Timing of digital I O input signals 1998 Oct 06 26 Preliminary specification Philips Semiconductors UDA1321 Digital to Analog Converter DAC Universal Serial Bus USB ZOOMOW Ssyeuuo 1ndu 01614 02 LVINHO 51411 1 27 1998 Oct 06 Philips Semiconductors Universal Serial Bus USB Preliminary specification Digital to Analog Converter DAC LIMITING VALUES In accordance with the Absolute Maximum Rating System IEC 134 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT All digital I Os Vio DC input output voltage range 0 5 V lo output current 4 Temperature junction temperature 0 125 storage temperature 55 150 operating ambient temperature 0 25 70 Electrostatic handling Ves electrostatic handling note 1 3000 3000 V Notes 1 Equivalent to discharging a 100 pF capacitor through a 1 5 kO series resistor 2 Equivalent to discharging a 200 pF capacitor through a 2 5 uH series inductor and 25 resistor For pin Vppo the electrostatic handling is limited to 250 V THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rih a thermal resistance from junction to ambient in free air QFP64 48 K W SDIP32 57 K W 028 65 K W 1998 Oct 06 Philips Semiconductors Universal Seri
6. _ a a _ 9 E 0 1 1 1 1 1 1 1 1 The treble control is available for the master channel of the UDA1321 Treble can be regulated in three modes minimum flat and maximum mode The preferred mode is selected via the configuration map The corner frequency is 3000 Hz for the minimum mode and 1500 Hz for the maximum mode The treble range is from 0 to 6 dB discrete steps 0 4 and 6 dB It should be noted that the negative treble values as defined in the USB Device Class Definition for Audio Devices are not supported by the UDA1321 the 0 dB value is returned as 0 dB Table 4 gives the mapping of the bTreble value upon the actual treble setting of the USB DAC 1998 Oct 06 34 Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC Table 11 Treble control characteristics Preliminary specification UDA1321 bTREBLE TREBLE USB SIDE dB UJ olo olo ololololo olo olo olo olo olo amp TREBLE USB DAC dB minimum The power saving mode is not
7. The Philips Serial Interface Engine PSIE The Memory Management Unit MMU The Audio Sample Redistribution ASR module THE PHiLIPS SERIAL INTERFACE ENGINE AND MEMORY MANAGEMENT UNIT PSIE AND MMU The PSIE and MMU translate the electrical USB signals into bytes and signals Depending upon the USB device address and the USB endpoint address the USB data is directed to the correct endpoint buffer on the PSIE and MMU interface The data transfer could be of the bulk isochronous control or interrupt type The USB device address is configured during the enumeration process The UDA1321 has three endpoints These are Control endpoint 0 Status interrupt endpoint sochronous data sink endpoint The amount of bytes per packet on the control endpoint is limited by the PSIE and MMU hardware to 8 bytes per packet 1998 Oct 06 Preliminary specification UDA1321 The PSIE is the digital front end of the USB processor This module recovers the 12 MHz USB clock detects the USB sync word and handles all low level USB protocols and error checking The MMU is the digital back end of the USB processor It handles the temporary data storage of all USB packets that are received or sent over the bus Three types of packets are defined on the USB These are Token packets e Data packets Handshake packets The token packet contains information about the destination of the data packet The audio data is tr
8. n a n a external access active LOW general purpose 1 or data input PSEN n a n a program store enable active LOW address latch enable active HIGH GP2 DO general purpose pin 2 or data output for extra DSP P2 0 Port 2 0 of the microcontroller P2 1 n a n a Port 2 1 of the microcontroller GP3 WSO ae general purpose pin or master word select output for extra DSP chip GP4 BCKO general purpose pin 4 or master bit clock output for extra DSP chip SHTCB shift clock TCB input active HIGH Port 2 2 of the microcontroller Port 2 3 of the microcontroller positive data line of the differential data bus conform to the USB standard Port 2 4 of the microcontroller Port 2 5 of the microcontroller Port 2 6 of the microcontroller Port 2 7 of the microcontroller digital supply voltage core 10 digital ground I O pins oat ope 13 11 crystal oscillator ground et tr 15 13 crystal oscillator output 2 u essen 18 15 reference output voltage 2 m magsyota 21 18 right channel output voltage eS 1998 Oct 06 6 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 PIN PIN operational amplifie
9. the UDA1321 N101 see Chapter USB DAC UDA1321 N101 Firmware sw 2 1 1 7 1998 Oct 06 15 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 BASS CONTROL The bass control is available for the master channel of the UDA1321 Bass can be regulated in three modes minimum flat and maximum mode The preferred mode is selected at start up of the device configuration map The Bass range is from 0 to about 14 dB minimum mode or about 24 dB maximum mode in steps of 2 dB It should be noted that the negative bass values as defined in the USB Device Class Definition for Audio Devices are not supported by the UDA1321 the 0 dB value is returned as 0 dB The maximum Bass value which will be reported to the host is always 24 dB independent of the mode The maximum mode is the most accurate mode when the Bass values are reported to the host The corner frequency is 100 Hz for the minimum mode and 75 Hz for the maximum mode Table 5 gives the mapping of the bBass value upon the actual bass setting of the USB DAC Table5 Bass control characteristics BASS USB BASS USB DAC dB SIDE dB minimum 0 00 0 Uu N U N Ay Atl i ojojojo ojojojo
10. Fax 45 31 57 0044 Finland Sinikalliontie 3 FIN 02630 ESPOO Tel 358 9 615800 Fax 358 9 61580920 France 51 Rue Carnot BP317 92156 SURESNES Cedex Tel 33 1 40 99 6161 Fax 33 1 40 99 6427 Germany HammerbrookstraBe 69 D 20097 HAMBURG Tel 49 40 23 53 60 Fax 49 40 23 536 300 Greece No 15 25th March Street GR 17778 TAVROS ATHENS Tel 30 1 4894 339 239 Fax 30 1 4814 240 Hungary see Austria India Philips INDIA Ltd Band Box Building 2nd floor 254 D Dr Annie Besant Road Worli MUMBAI 400 025 Tel 91 22 493 8541 Fax 91 22 493 0966 Indonesia PT Philips Development Corporation Semiconductors Division Gedung Philips Jl Buncit Raya Kav 99 100 JAKARTA 12510 Tel 62 21 794 0040 ext 2501 Fax 62 21 794 0080 Ireland Newstead Clonskeagh DUBLIN 14 Tel 353 1 7640 000 Fax 353 1 7640 200 Israel RAPAC Electronics 7 Kehilat Saloniki St PO Box 18053 TEL AVIV 61180 Tel 972 3 645 0444 Fax 972 3 649 1007 Italy PHILIPS SEMICONDUCTORS Piazza IV Novembre 3 20124 MILANO Tel 39 2 6752 2531 Fax 39 2 6752 2557 Japan Philips Bldg 13 37 Kohnan 2 chome Minato ku TOKYO 108 8507 Tel 81 3 3740 5130 Fax 81 3 3740 5077 Korea Philips House 260 199 Itaewon dong Yongsan ku SEOUL Tel 82 2 709 1412 Fax 82 2 709 1415 Malaysia No 76 Jalan Universiti 46200 PETALING JAYA SELANGOR Tel 60 3 750 5214 Fax 60 3 757 4880 Mexico 5900 Gateway East Suite 200 EL PASO TE
11. 1 7 6 0 10 17 7 7 4 0 71 0 30 0 69 0 29 inches Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT136 1 075E06 MS 013AE 97 05 22 ISSUE DATE 1998 Oct 06 40 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 SDIP32 plastic shrink dual in line package 32 leads 400 mil SOT232 1 4 seating plane DIMENSIONS mm are the original dimensions A A max min max UNIT b bi 1 3 mm 4 7 0 51 3 8 0 8 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION 0 232 1 ISSUE DATE 1998 Oct 06 41 Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC SOLDERING Introduction There is no soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and surface mounted components are mixed on one printed circuit board However wave soldering is not always suitable for surface mounted ICs or for pri
12. 1 kHz unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN UNIT Driver characteristics D and D full speed mode tr rise time fall time t ttm matching rise fall time Vor output signal crossover voltage 0 f rf Rio driver driver output resistance kHz 12 03 Mbits s 1 0005 ns source differential jitter to next j transition source differential jitter for paired 5 ns transitions source End Of Packet EOP width ns tEOP dif differential to EOP transition skew Unt receiver data jitter tolerance to next transition receiver data jitter tolerance for paired transitions EOP width at receiver must reject as EOP tEoPR2 EOP width at receiver must accept as EOP Serial input output data timing see Fig 9 folk sys system clock frequency fitws word select input frequency tr rise time t fall time tBCK H bit clock HIGH time tBCK L bit clock LOW time th DAT data hold time th ws word select hold time 10 ns 1998 Oct 06 31 Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC SYMBOL PARAMETER CONDITIONS Preliminary specification UDA1321 SDA and SCL lines standard I2C bus see Fig 7 scL SCL clock frequency tBur bus free time between a STOP and START condition tHD STA hold time repeated START condition SCL LOW time t
13. changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Printed in The Netherlands 545102 750 04 pp44 Philips Semiconductors Date of release 1998 Oct 06 Document order number 9397 750 04262 make things belli S PHILIPS
14. supported no power management The content of the four internal configuration maps is written in the sw 2 1 1 7 configuration maps document This document is available at your local Philips Semiconductors Field Application Engineer 1998 Oct 06 35 Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC APPLICATION DIAGRAM Preliminary specification UDA1321 1 BLM32A07 BCK digital input ws DI GP1 DI Tc P5 L9 jet i 8 2 2 7 17 3 3 6 4 5 20 26 C5 C27 10 22 pF 22 pF e 50 V V Je v 10nF 7 4 4 50 V L10 3 n xm qon 1588 63 V C6 12 63 V 48 MHz ei XTAL1 d 47 50 L15 VA ext o VA BLM32A07 114 BLM32A07 2 116 Voen o BLM32A07 yl Tis cal ez 100 uF 100 uF 100 pF Tasvy Taev GND 2 be connected to 5 V max 5 V tolerant UDA1321H Fig 11 Application diagram QFP64 continued in Fig 12 1998 Oct 06 36 Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC Preliminary specification UDA1321 D7 06 05 04 03 02 74HCT373D D2
15. to Analog Converter DAC The Asynchronous Digital to Analog Converter ADAC The ADAC receives USB audio information from the USB processor or from the digital l O bus The ADAC is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing After processing the audio signal is up sampled noise shaped and converted to analog output voltages capable of driving a line output The ADAC consists of A Sample Frequency Generator SFG First In First Out FIFO registers An audio feature processing DSP Two digital up sample filters A variable hold register A digital Noise Shaper NS A Filter Stream DAC FSDAC with integrated filter and line output drivers THE SAMPLE FREQUENCY GENERATOR SFG The SFG controls the timing signals for the asynchronous digital to analog conversion By means of a digital PLL the SFG automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing DSP and the up sample filters FiRST IN FIRST OUT FIFO REGISTERS The FIFO registers are used to store the audio samples temporarily coming from the USB processor or from the digital input The use of a FIFO register in conjunction with the SFG is necessary to remove all jitter present on the incoming audio signal THE AUDIO FEATURE PROCESSING DSP A DSP processes the sound features The control and mapping of t
16. 0 0 96 1321 OD INTEGRATED CIRCUITS DATA SHEET UNIVERSAL SERIAL BUS UDA1321 Universal Serial Bus USB Digital to Analog Converter DAC Preliminary specification 1998 Oct 06 Supersedes data of 1998 May 12 File under Integrated Circuits 1001 Philips PHILIPS Semiconductors D fal L Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC ICD UNIVERSAL SERIAL BUS FEATURES General Universal Serial Bus USB stereo Digital to Analog Converter DAC system with adaptive 5 to 55 kHz 20 bits digital to analog conversion and filtering USB compliant audio and Human Interface Device HID Supports 12 Mbits s full speed serial data transmission Supports multiple audio data formats 8 16 and 24 bits Supports headphone and line output Fully automatic Plug and Play operation High linearity Wide dynamic range Superior signal to noise ratio typical 95 dB Low total harmonic distortion typical 90 dB 3 3 V power supply Efficient power management Low power consumption On chip master clock oscillator only an external crystal is required Partly programmable USB descriptors and configuration via 2 5 Sound processing Separate digital volume control for left and right channel Soft mute Digital bass and treble tone control External Digital Sound Processo
17. 1 Digital to Analog Converter DAC Table 3 Volume control characteristics note 1 wVOLUME UJ A UJ UJ U VOLUME USB SIDE dB VOLUME USB DAC dB _ k ojo 1 The volume control characteristics of this table are in accordance with the latest Audio Device Class Definition The volume control characteristics of the UDA1321 N101 are slightly different see Chapter USB DAC UDA1321 N101 Firmware sw 2 1 1 7 MUTE CONTROL Mute is one of the sound features as defined in the USB Device Class Definition for Audio Devices The mute control request data bMute controls the position of the mute switch The position can be either on or off When bMute is true the feature unit is muted When bMute is false the feature unit is not muted When the mute is active for the master channel the value of the sample is decreased smoothly to zero following a raised cosine curve There are 32 coefficients used to step down the value of the data each one being used 32 times before stepping to the next 1998 Oct 06 This amounts to a mute transition of 23 ms at fs 44 1 kHz When the mute is released the samples are returned to the full level again following a raised cosine curve
18. 224 16 x 2 x 56 24 bit PCM mono 168 25 x 1 x 56 24 bit PCM stereo 336 2 x 2 x 56 The maximum number of audio data samples within a USB packet arriving on the isochronous sink endpoint is restricted by the buffer capacity of this isochronous endpoint The maximum buffer capacity is 336 bytes ms For each alternate setting with audio a maximum bandwidth is claimed as indicated in the standard isochronous audio data endpoint descriptor field To allow a small overshoot in the number of audio samples per packet the top sample frequency of 55 kHz is taken in the calculation of the bandwidth for each alternate setting For each alternate setting with its own isochronous audio data endpoint descriptor field is then defined as described in Table 2 Although in a specific UDA1321 application no endpoint control properties can be used upon the isochronous adaptive sink endpoint the descriptors are still necessary to inform the host about the definition of this endpoint isochronous adaptive sink continuous sampling frequency at input side of this endpoint with lower bound of 5 kHz and upper bound of 55 kHz The audio class specific descriptors can be requested with the Get descriptor configuration request which returns all the descriptors except the device descriptor HUMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS The inputs defined on the UDA1321 are transmi
19. 5 uH 410 C 10 nF 10 The series resistance of the crystal must be below 60 4 7 pF 10 12 1 0 2 Strongly depends on the external decoupling capacitor connected to Vret 3 Use for calculation of the power on reset set up time the value in uF The audio information from the USB interface is fed directly to the ADAC APPLICATION INFORMATION The UDA1321 is designed to be used as a self powered device The I2C bus EEPROM is optional and can be used e g to program your own Vendor ID and Product ID In order to help customers with defining there own configuration map a special program called Configuration map editor has been developed It is available from your local Philips Semiconductors Field Application Engineer More information about the firmware descriptors and configurations can be obtained from several application notes 1998 Oct 06 33 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC USB DAC UDA1321 N101 FIRMWARE SW 2 1 1 7 The following items are different for the UDA1321 N101 compared to the general content of this data sheet Volume control Treble control Power management Table 10 Volume control characteristics wVOLUME VOLUME USB SIDE VOLUME USB DAC Bi5 B14 B13 B12 B11 B10 B9 B8 dB dB o ojo oio
20. A1321 will scan the logical levels of GP3 and GPO With these two pins it is possible to select one of the four possible vendor specific configuration maps This selection can be achieved via a diode matrix see Fig 6 1998 Oct 06 18 After selecting a configuration map the user cannot change the chosen settings for the GP pins internal configuration descriptors etc For more information about the four vendor specific configuration maps and the diode matrix see the application documentation CONFIGURATION OPTIONS OF THE UDA1321 AN I2 C BUS EEPROM If an EEPROM is detected reading byte 0 as AAH and byte 1 as 55H the UDA1321 will use the configuration map in the EEPROM instead of one of four configuration maps The layout of the configuration map is fixed the values except bytes 0 and 1 are user definable see Table 6 If the user wants to change these values the manufacturers name for instance this can be achieved via the EEPROM code The communication between the UDA1321 and the external I2C bus device is based on the standard 2 protocol given in the Philips specification The 2 and how to use it including specifications which can be ordered using the code 9398 393 40011 The I2C bus has two lines a clock line SCL and a serial data line SDA see Fig 7 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321
21. AGE DESCRIPTION VERSION UDA1321H N101 plastic quad flat package 64 leads lead length 1 95 mm SOT319 2 TYPE NUMBER body 14 x 20 x 2 8 mm UDA1321T N101 SO28 plastic small outline package 28 leads body width 7 5 mm SOT136 1 UDA1321PS N101 SDIP32 plastic shrink dual in line package 32 leads 400 mil SOT232 1 1998 Oct 06 4 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 BLOCK DIAGRAM TC ANALOG FRONT END SCL B JI SDA USB PROCESSOR PSEN P ALE y P20 GP4 BCKO GP2 DO DE gt GP1 DI GPO BCKI GP5 WSI CONTROLLER pag V P0 3 SAMPLE DE FREQUENCY AUDIO FEATURE DE P0 4 GENERATOR PROCESSING DSP BELT UP SAMPLE FILTERS 1 VDDE V xTaLt UDA1321H 55 xra2 osc TIMING y UDA1321T V UDA1321PS Vbibo 3rd ORDER Y NOISE SHAPER 550 VOUTL Vref MGM839 Fig 1 Block diagram 1998 Oct 06 5 Philips Semiconductors Preliminary specification Universal Serial Bus USB ir UDA1321 Digital to Analog Converter DAC PINNING PIN PIN PIN SYMBOL QFP64 SDIP32 S028 1 0 DESCRIPTION GP5 WSI 2 29 25 general purpose pin 5 or word select input 3 serial clock input 12 4 serial data input output 1 C bus 7 5 Port 0 7 of the microcontroller NIO
22. HIGH SCL HIGH time set up time for a repeated START condition set up time for a STOP condition tHD DAT data hold time tsu DAT data set up time tr rise time of both SDA and SCL signals t fall time of both SDA and SCL signals CL bus load capacitance for each bus line Oscillator note 1 fosc oscillator frequency duty factor 6 transconductance Ro output resistance i XTAL1 parasitic input capacitance at XTAL1 Ci XTAL2 parasitic input capacitance at XTAL2 Istart start current Power on reset lsu POR power on reset set up time notes 2 and 3 Filter Stream DAC FSDAC resolution full scale output voltage RMS value supply voltage ripple rejection of fripple 1 kHz VppA and V ripple p p 0 1V channel unbalance maximum volume Oct crosstalk between channels 5 95 dB 1998 Oct 06 32 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 SYMBOL PARAMETER CONDITIONS THD N S total harmonic distortion plus noise fs 44 1 kHz to signal ratio 5 input signal of 1 kHz 0 dB at input signal of 1 kHz 60 dB S N5z signal to noise ratio at bipolar zero A weighted at code 0000H Notes 1 A 3rd overtone crystal of 48 MHz must be used in combination with a filter connected to the oscillator output XTAL2 L 1
23. NTS BIT ADAC mode register 1 selection ADAC mode register 1 digital PLL lock speed 00 lock after 512 samples 01 lock after 2048 samples 10 lock after 4096 samples 11 lock after 16384 samples digital PLL lock mode 4 0 adaptive 1 fixed digital PLL mode 00 adaptive 01 fixed state 1 10 fixed state 2 11 fixed state 3 serial 125 input format 00 25 01 16 bit LSB 10 18 bit LSB 11 20 bit LSB I O selection register clipping 0 clipping prevention off 1 clipping prevention on 25 usage 0 no I S bus used 1 125 used 4 6 pins 125 see Section only 25 is used general purpose pins GPO to GP5 0 4 pins 125 1 25 0 function 1 1 function 2 see Tables 7 8 and 9 FIT Fage if HID selected reserved GP3 Usage Page if HID selected reserved UDA1321 1998 Oct 06 21 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 REGISTER NAME COMMENTS BIT GP1 and GP2 outputs reserved definition register reserved application GP2 function 2 0 HID output 2 1 LED output 2 activated when DBB is active application GP1 function 2 0 HID output 1 1 LED output 1 activated when mute is active polarity GP2 function 1 normal or inversed output polarity GP1 function 1 functi
24. O It is possible to overwrite this configuration map with a configuration map loaded from 2 C bus EEPROM AUDIO DEVICE CLASS SPECIFIC DESCRIPTORS The audio device class is partly specified with standard descriptors and partly with specific audio device class descriptors The standard descriptors specify the number and the type of the interface or endpoint The UDA1321 supports 7 different audio modes 8 bit Pulse Code Modulation PCM mono or stereo audio data 16 bit PCM mono or stereo audio data e 24 bit PCM mono or stereo audio data e Zero bandwidth mode Each mode is defined as an alternate setting of the audio interface selectable with the standard audio streaming interface descriptor bAlternateSetting field The seven alternate settings are described in more detail by the specific audio device class descriptors The UDA1321 supports the Input Terminal IT Output Terminal OT and the Feature Unit FU descriptors The input and output terminals are not controllable via the USB The feature unit provides the basic manipulation of the incoming logical channels The supported sound features are Volume control Mute control Treble control Bass control Bass boost control 1998 Oct 06 Table 2 Audio bandwidth at each audio mode AUDIO MODE wMaxPacketSize 8 bit PCM mono 56 8x 1 x 56 8 bit stereo 112 86 x 2 x 56 16 bit PCM mono 112 195 x 1 x 56 16 bit PCM stereo
25. TPUT FUNCTION digital Filter characteristics The overall filter characteristic of the UDA1321 in flat mode is given in Fig 8 The overall filter characteristic of the UDA1321 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC fs 44 1 kHz DSP extension port An external DSP be used for adding extra sound processing features via the digital l O bus The UDA1321 supports the standard 125 data protocol and the LSB justified serial data input format with word lengths of 16 18 and 20 bits Using the 4 pins digital l O bus the UDA1321 device acts as a master controlling the and WS signals The period of the WS signal is determined by the number of samples in the 1 ms frame of the USB This implies that the WS signal does not have a constant period time but is jittery Using the 6 pins digital GP2 and GP4 are the output pins master and GP1 and GP5 are the input pins slave For characteristic timing of the 125 input interface see Figs 9 and 10 1998 Oct 06 25 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 MGM110 20 dB 100 120 140 Fig 8 Overall filter characteristics of the UDA1321
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27. al Bus USB Preliminary specification Me UDA1321 Digital to Analog Converter DAC RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP MAX UNIT supply voltage DC input voltage for D and D Vio DC input voltage for the digital I Os Vpp DC CHARACTERISTICS Vpp 3 3 V Vss 0 V Tamb 25 48 MHz fs 44 1 kHz unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supplies VDDE digital supply voltage pins 3 0 3 3 3 6 V Vppi digital supply voltage core 3 0 3 3 3 6 V VppA analog supply voltage 3 0 3 3 3 6 V operational amplifier supply voltage 3 0 3 3 3 6 V Vppx crystal oscillator supply voltage 3 0 3 3 3 6 V IDDE digital supply current I O pins note 1 3 mA Ippi digital supply current core 36 IDDA analog supply current 4 2 Ippo operational amplifier supply current 4 0 Ippx crystal oscillator supply current 2 1 15 0 Prot total power dissipation 165 mW Ptot ps total power dissipation in note 3 60 mW power save mode Inputs outputs and D Vi static DC input voltage 0 5 Vppi V static DC output voltage HIGH 15 to ground 2 8 Vppi V VoL static DC output voltage LOW 1 5kQto3 6V 0 3 V high impedance state data line 10 output leakage current AV dit differential input sen
28. al serial bus performs an extensive error detection and separates control information input and output and audio information input only Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC The control information becomes accessible at the microcontroller The audio information becomes available at the digital I O output or is fed directly to the ADAC The microcontroller handles the high level USB protocols translates the incoming control requests and manages the user interface via General Purpose GP pins and an I2C bus The ADAC enables the wide and continuous range of input sampling frequencies By means of a Sample Frequency Generator SFG the ADAC is able to reconstruct the average sample frequency from the incoming audio samples The ADAC also performs the sound processing QUICK REFERENCE DATA 1321 The ADAC consists of FIFO registers a unique audio feature processing DSP the SFG digital up sampling filters a variable hold register a Noise Shaper NS and a Filter Stream DAC FSDAC with integrated filter and line output drivers The audio information is applied to the ADAC via the USB processor or via the digital I O input An external DSP can be used for adding extra sound processing features via the digital l O bus The UDA1321 supports the standard 125 data input format and the LSB justified serial data input format with word len
29. ansferred via an isochronous data sink endpoint and consequently no handshaking mechanism is used The MMU also generates 1 kHz clock that is locked to the USB Start Of Frame SOF token THE AUDIO SAMPLE REDISTRIBUTION ASR MODULE The ASR module reads the audio samples from the MMU and distributes these samples equidistant over a 1 ms frame period The distributed audio samples are translated by the digital module to standard 125 format Japanese digital I O format The ASR module generates the bit clock and the word select signal of the digital I O The digital I O formats the received audio samples to one of the four specified serial digital audio formats standard I S bus 16 18 or 20 bits LSB justified The microcontroller The microcontroller receives the control information selected from the USB by the USB processor It handles the high level USB protocols and the user interfaces The major task of the software process that is mapped upon the microcontroller is to control the different modules of the UDA1321 in such a way that it behaves as a USB device Therefore the microcontroller Interprets the USB requests and maps them upon the UDA1321 application Controls the internal operation of the UDA1321 and the digital I O pins Communicates with the external world EEPROM using the I C bus facility and the general purpose I O pins Philips Semiconductors Universal Serial Bus USB Digital
30. e defined items By examining all of these items the HID class driver is able to determine the size and composition of data reports from the device The main items of the UDA1321 are input and output reports Input reports are sent via the interrupt pipe UDA1321 USB address 3 Input and output reports can be requested by the host via the control endpoint USB address 0 The UDA1321 supports a maximum of three pushbuttons which represents a certain feature of the UDA1321 If pressed by the user the pushbutton will go to its ON state if not pressed the pushbutton will go backto its OFF state The UDA1321 supports a maximum of two outputs for e g user LEDs For more information about the input and output functions of the UDA1321 see the application documentation of the device 1998 Oct 06 Preliminary specification 1321 Controlling the USB Digital to Analog Converter DAC This section describes the functionality of the feature unit of the UDA1321 The mapping of this functionality onto USB descriptors is as implemented in the firmware The sound features as defined in the USB Device Class Definition for Audio Devices are mapped on the UDA1321 specific feature registers by the microcontroller These specific sound features are Volume control separate for left and right stereo channels no master channel Mute control only master channel Treble control only master channel Bass control onl
31. escription of the USB control options is available in the USB Device Class Definition for Audio Devices 2 The serial number is only supported in the external configuration map and not in the four internal configuration maps The general purpose pins GPO to GP5 UDA1321 has 6 General Purpose GP pins these are pins GPO to GP5 These can be used either for digital I O functions or for general purposes The configurations presented are as implemented in the standard firmware There are basically three port configurations e No digital communication 4 pins digital communication 6 pins digital communication These port configurations can be selected via the configuration map at start up of the UDA1321 The user can make a selection between two functions for each of the pins GPO to GP4 see byte 5 in Table 6 except if digital communication is selected see Tables 7 8 and 9 1998 Oct 06 23 Philips Semiconductors Preliminary specification Universal Serial Bus USB Ms UDA1321 Digital to Analog Converter DAC Table 7 No digital communication PIN INPUT OUTPUT FUNCTION 1 FUNCTION 2 output not programmable note 2 connect disconnect connect disconnect inputs programmable note 1 alarm mute note 3 HID input 3 HID input 2 HID input 2 HID input 1 HID input 1 outputs programmable standby note 4 HID LED output 2 note 6 mute note 5 HID LED output 1 note 6 1 The input pins m
32. for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale PURCHASE OF PHILIPS 12 COMPONENTS Purchase of Philips 2 components conveys a license under the Philips 122 patent to use the components the 12C system provided the system conforms to the I C specification defined by Philips This specification can be ordered using the code 9398 393 40011 1998 Oct 06 Philips Semiconductors Argentina see South America Australia 34 Waterloo Road NORTH RYDE NSW 2113 Tel 61 2 9805 4455 Fax 61 2 9805 4466 Austria Computerstr 6 A 1101 WIEN Box 213 Tel 43 160 1010 Fax 43 160 101 1210 Belarus Hotel Minsk Business Center Bld 3 r 1211 Volodarski Str 6 220050 MINSK Tel 375 172 200 733 Fax 375 172 200 773 Belgium see The Netherlands Brazil see South America Bulgaria Philips Bulgaria Ltd Energoproject 15th floor 51 James Bourchier Blvd 1407 SOFIA Tel 359 2 689 211 Fax 359 2 689 102 Canada PHILIPS SEMICONDUCTORS COMPONENTS Tel 1 800 234 7381 China Hong Kong 501 Hong Kong Industrial Technology Centre 72 Tat Chee Avenue Kowloon Tong HONG KONG Tel 852 2319 7888 Fax 852 2319 7700 Colombia see South America Czech Republic see Austria Denmark Prags Boulevard 80 PB 1919 DK 2300 COPENHAGEN S Tel 45 32 88 2636
33. gths of 16 18 and 20 bits The wide dynamic range of the bitstream conversion technique used in the UDA1321 guarantees a high audio sound quality SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Supplies Vpp supply voltage note 1 3 0 3 3 3 6 V Ipp tot total supply current 50 Ipp ps supply current in power save note 3 18 Dynamic performance DAC total harmonic distortion plus noise to signal ratio at input signal of 1 kHz 60 dB fs 44 1 KHz RL 5 at input signal of 1 kHz 0 dB S N5z signal to noise ratio at bipolar A weighted at code 0000H zero Vo FS rms full scale output voltage Vpp 3 3 V 0 66 V RMS value General characteristics fitsample audio sample input frequency 5 55 kHz Tamb operating ambient temperature 0 25 70 Notes 1 Vppis the supply voltage on pins and Vppx Vss is the ground pins Vgga Vsse and All Vpp and Vss pins must be connected to the same supply or ground respectively 2 The audio information from the USB interface is fed directly to the ADAC 3 The power save mode power management is not supported in the UDA1321 N101 see Chapter USB DAC UDA1321 N101 Firmware sw 2 1 1 7 1998 Oct 06 3 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 ORDERING INFORMATION PACK
34. he sound features is explained in Section Controlling the USB Digital to Analog Converter DAC Depending on the sampling rate fs the DSP has four frequency domains in which the treble and bass are regulated see Table 1 The domain is chosen automatically THE UP SAMPLE FILTERS AND VARIABLE HOLD REGISTER After the audio feature processing DSP two up sample filters and a variable hold register increase the oversampling rate to 128f 1998 Oct 06 Preliminary specification UDA1321 Table 1 Frequency domains for audio processing DOMAIN SAMPLE FREQUENCY kHz 1 5 to 12 2 12 to 25 3 25 to 40 4 40 to 55 THE NOISE SHAPER A noise shaper converts the oversampled data to a noise shaped bitstream for the FSDAC The in band quantization noise is shifted to frequencies well above the audio band THE FiLTER STREAM DAC FSDAC The FSDAC is a semi digital reconstruction filter that converts the 1 bit data stream of the noise shaper to an analog output voltage The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier In this way very high signal to noise performance and low clock jitter sensitivity is achieved A post filter is not needed because of the inherent filter function of the DAC On board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output USB Digital to Analog Co
35. high upward pressure followed by a smooth laminar wave soldering technique should be used The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners SO Wave soldering techniques can be used for all SO packages if the following conditions are observed A double wave a turbulent wave with high upward pressure followed by a smooth laminar wave soldering technique should be used The longitudinal axis of the package footprint must be parallel to the solder flow The package footprint must incorporate solder thieves at the downstream end Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC Method QFP and SO During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Maximum permissible solder temperature is 260 and maximum duration of package immersion in solder is 10 seconds if cooled to less than 150 within 6 seconds Typical dwell time is 4 seconds at 250 A mildly activated flux will eliminate the need for removal of corrosive residues in most applications DEFINITIONS Data sheet status Objective specification Preliminary specification UDA1321 REPAIRING SOLDERED JOINTS Fix the component by fi
36. iversal Serial Bus USB Digital to Analog Converter DAC UDA1321 33V 33V 33V 3 3 V 22 22 22 I T 9 2 Y Viis swi swe 1 v 1 5 22 T D2 2 22 22 USB B GP5 connector mat Tre 5 77 zz 22 1 Vous 220 H2 D 3 pi D 4 220 MGM109 6 10nF 22 pF 22 pF 10 nF Fig 6 Diode matrix selection Start up and configuration of the UDA1321 START UP OF THE UDA1321 After power on an internal power on reset signal becomes HIGH after a certain RC time 5 and C During 10 ms after power on reset the UDA1321 has to initiate the internal settings After the power on reset the UDA1321 becomes master of the 2 The UDA1321 tries to read the eventually connected EEPROM and if an EEPROM is detected the internal descriptors are overwritten and the selected port configuration is applied If no EEPROM is detected the UDA1321 tries to read the logical levels of GP3 and GPO A choice can be made from four configuration maps via these two pins CONFIGURATION SELECTION OF THE UDA1321 VIA A DIODE MATRIX The UDA1321 uses a configuration map to hold a number of specific configurable data on hardware product component and USB configuration level At start up without EEPROM the UD
37. lmes 22 08007 BARCELONA Tel 34 93 301 6312 Fax 34 93 301 4107 Sweden Kottbygatan 7 Akalla S 16485 STOCKHOLM Tel 46 8 5985 2000 Fax 46 8 5985 2745 Switzerland Allmendstrasse 140 CH 8027 Z RICH Tel 41 1 488 2741 Fax 41 1 488 3263 Taiwan Philips Semiconductors 6F No 96 Chien Kuo N Rd Sec 1 TAIPEI Taiwan Tel 886 2 2134 2865 Fax 886 2 2134 2874 Thailand PHILIPS ELECTRONICS THAILAND Ltd 209 2 Sanpavuth Bangna Road Prakanong BANGKOK 10260 Tel 66 2 745 4090 Fax 66 2 398 0793 Turkey Talatpasa Cad No 5 80640 G LTEPE ISTANBUL Tel 90 212 279 2770 Fax 90 212 282 6707 Ukraine PHILIPS UKRAINE 4 Patrice Lumumba str Building B Floor 7 252042 KIEV Tel 380 44 264 2776 Fax 380 44 268 0461 United Kingdom Philips Semiconductors Ltd 276 Bath Road Hayes MIDDLESEX 5BX Tel 44 181 730 5000 Fax 44 181 754 8421 United States 811 East Arques Avenue SUNNYVALE CA 94088 3409 Tel 1 800 234 7381 Uruguay see South America Vietnam see Singapore Yugoslavia PHILIPS Trg N Pasica 5 v 11000 BEOGRAD Tel 381 11 625 344 Fax 381 11 635 777 Internet http www semiconductors philips com SCA60 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be
38. nted circuits with high population densities In these situations reflow soldering is often used This text gives a very brief insightto a complex technology A more in depth account of soldering ICs can be found in our Data Handbook IC26 Integrated Circuit Packages order code 9398 652 9001 1 SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C solder at this temperature must not be in contact with the joint for more than 5 seconds The total contact time of successive solder waves must not exceed 5 seconds The device may be mounted up to the seating plane but the temperature of the plastic body must not exceed the specified maximum storage temperature If the printed circuit board has been pre heated forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron less than 24 V to the lead s of the package below the seating plane or not more than 2 mm above it If the temperature of the soldering iron bit is less than 300 it may remain in contact for up to 10 seconds If the bit temperature is between 300 and 400 C contact may be up to 5 seconds QFP and SO REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP and SO packages The choice of heating method may be influenced by larger plastic QFP packages 44 leads or mo
39. nverter DAC descriptors In a typical USB environment the USB host has to know which kind of devices are connected For this purpose each device contains a number of USB descriptors These descriptors describe from different points of view USB configuration USB interface and USB endpoint the capabilities of a device Each of them can be requested by the host The collection of descriptors is denoted as a descriptor map This descriptor map will be reported to the USB host during enumeration and on request The full descriptor map is implemented in the firmware exploiting the full functionality of the UDA1321 The USB descriptors and their most important fields in relationship to the characteristics of the UDA1321 are briefly explained below GENERAL DESCRIPTORS The UDA1321 supports one configuration containing a control interface an audio interface and a HID interface The descriptor map that describes this configuration is partly fixed and partly programmable Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC INPUT TERMINAL FEATURE UNIT Preliminary specification UDA1321 OUTPUT TERMINAL MBK530 Fig 5 Audio function topology The programmable part can be retrieved from one of four configuration maps located in the firmware or from an 2 EEPROM At start up one of four configuration maps can be selected depending on the logical combination of GP3 and GP
40. onality polarity GP2 function 2 1 inversed polarity GP1 function 2 GP1 Usage Page if HID selected GP1 Usage if HID selected GP2 Usage Page if HID selected GP2 Usage if HID selected time between releasing standby and enabling the audio output steps of 20 ms time between isochronous data present and activating the mute output steps of 1 s only applicable for function 1 no digital I O communication time between activating the mute output and activating the standby output steps of 5 s only applicable for function 1 no digital I O communication when filled in with zero standby will not be activated default bass boost value on top of bass boost register value if Bass USB DAC for Dynamic Bass bass boost Bass USB DAC Boost DBB see Table 5 is larger then the maximum value of Table 5 the maximum value is used no bass boost in flat mode default volume value of USB DAC volume register value idVendor high byte idProduct high byte maximum power steps of 2 mA with maximum 500 mA 1998 Oct 06 22 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 REGISTER NAME COMMENTS BIT wTerminalType high byte wTerminalType low byte pointer manufacturer string 36 32 gt language string product string serial number note 2 1 extensive d
41. r DSP option possible via standard I S bus or Japanese digital I O format Selectable clipping prevention Selectable Dynamic Bass Boost DBB On chip digital de emphasis 1998 Oct 06 UDA1321 Document references USB Specification USB Common Class Specification USB Device Class Definition for Audio Devices e Device Class Definition for Human Interface Devices HID USB Usage Table APPLICATIONS USB monitors USB speakers USB headsets USB telephone answering machines e USB links in consumer audio devices GENERAL DESCRIPTION The UDA1321 is a stereo CMOS digital to analog bitstream converter designed for USB compliant audio playback devices and multimedia audio applications The UDA1321 is an adaptive asynchronous sink USB audio device with a continuous sampling frequency fs range from 5 to 55 kHz It contains a USB interface an embedded microcontroller and an Asynchronous Digital to Analog Converter ADAC The USB interface is the interface between the USB the and the microcontroller The USB interface consists of an analog front end and a USB processor The analog front end transforms the differential USB data to a digital data stream The USB processor buffers the input and output data from the analog front end and handles all low level USB protocols The USB processor selects the relevant data from the univers
42. r supply voltage left channel output voltage test control input active HIGH n a n a Port 0 0 of the microcontroller oS n a Port 0 2 of the microcontroller n a n a Port 0 4 of the microcontroller zi asynchronous reset input for test control box active HIGH n a n a Port 0 5 of the microcontroller GPO BCKI purpose 0 master bit clock input n c 1 A 26 5 12 17 n a not connected 27 28 31 28 33 34 35 40 41 43 47 48 50 52 54 1998 Oct 06 7 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 64 GPO BCKI 63 6 62 P0 5 61 RTCB 60 4 59 P0 3 58 P0 2 57 1 56 P0 0 55 TC 53 VOUTL 54 52 GP5 WSI n c SCL Vsso SDA n c 7 n c EA 6 VOUTR GP1 DI VDDA PSEN 8 VSSA ALE 9 GP2 DO VREF P2 0 2 1 GP3 WSO GP4 BCKO XTAL2 SHTCB XTAL1 Vssx D 2 2 2 3 850 0 2 4 2 5 P2 6 P2 7 VDDI n c n c VDDE Fig 2 Pin configuration QFP64 1998 Oct 06 8 Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC GP1 DI SDA SCL GP5 WSI GPO BCKI RTCB TC UDA1321T VOUTL Vsso VOUTR VDDA VSSA Vref MGM840 Fig 3 Pin config
43. re If infrared or vapour phase heating is used and the large packages are not absolutely dry less than 0 196 moisture content by weight vaporization of the small amount of moisture in them can cause cracking of the plastic body 1998 Oct 06 Preliminary specification 1321 For details refer to the Drypack information in the Data Handbook 26 Integrated Circuit Packages Section Packing Methods Reflow soldering requires solder paste a suspension of fine solder particles flux and binding agent to be applied to the printed circuit board by screen printing stencilling or pressure syringe dispensing before package placement Several methods exist for reflowing for example infrared convection heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 50 and 300 seconds depending on heating method Typical reflow peak temperatures range from 215 to 250 WAVE SOLDERING QFP Wave soldering is not recommended for QFP packages This is because of the likelihood of solder bridging due to closely spaced leads and the possibility of incomplete solder penetration in multi lead devices CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch e equal or less than 0 5 mm If wave soldering cannot be avoided for QFP packages with a pitch e larger than 0 5 mm the following conditions must be observed double wave a turbulent wave with
44. rst soldering two diagonally opposite end leads Use only a low voltage soldering iron less than 24 V applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C This data sheet contains target or goal specifications for product development Preliminary specification Product specification This data sheet contains preliminary data supplementary data may be published later This data sheet contains final product specifications Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Where application information is given it is advisory and does not form part of the specification LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips customers using or selling these products
45. sitivity 0 2 V VcM dif differential common mode voltage 0 8 2 5 V VsE RX th single ended receiver threshold 0 8 2 0 V voltage Ci TRX transceiver input capacitance pin to ground 20 Digital inputs outputs Vu LOW level input voltage 0 3Vppi V HIGH level input voltage 0 7Vppi V VoL LOW level output voltage 0 4 V HIGH level output voltage Vppi 0 4 V input leakage current 1 Ci input capacitance pin to ground 5 1998 Oct 06 29 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC SYMBOL PARAMETER CONDITIONS MIN Filter stream DAC reference voltage common mode output voltage UDA1321 output load resistance 20 l output load capacitance pF Notes output resistance at pins VOUTL Q and VOUTR 20 1 This value depends strongly on the application The specified value is the typical value obtained using the application as given in Fig 12 2 Atstart up of the oscillator 3 The power save mode power management is not supported in the UDA1321 N101 see Chapter USB DAC UDA1321 N101 Firmware sw 2 1 1 7 1998 Oct 06 30 Philips Semiconductors Preliminary specification Universal Serial Bus USB Ms UDA1321 Digital to Analog Converter DAC AC CHARACTERISTICS Vpp 3 3 V Vss 0 V Tamb 25 fos 48 MHz fs 44
46. tted via the USB to the host according to the HID class The host Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC responds with the appropriate settings via the audio device class for the audio related parts or via the HID class for the HID related inputs and outputs of the UDA1321 A HID descriptor is necessary to inform the host about the conception of the user interface The host communicates via the HID device driver using either the control pipe or the interrupt pipe The UDA1321 uses USB endpoint 0 control pipe to respond to the HID specific Get set report request to receive or transmit data from or to the UDA1321 The UDA1321 uses the status interrupt endpoint as interrupt pipe for polling asynchronous data The UDA1321 is a high speed device The maximum transaction size is 64 bytes per USB frame and the polling rate is defined at a maximum of every 1 ms The host requests the configuration descriptor which includes the standard interface descriptor the HID endpoint descriptor and the HID descriptor The HID device driver of the host then requests the report descriptor Report descriptors are composed of pieces of information about the device Each piece of information is called an item All items have a 1 byte prefix that contains the item tag type and size In the UDA1321 only the short item basic type is used The hosts HID device driver will parse the report descriptor and th
47. uration 028 GP2 DO GP3 WSO GP4 BCKO SHTCB D 0 Vpp Vss VSSE VDDE Vssx XTAL1 XTAL2 VDDX Preliminary specification MGM841 UDA1321 GP1 DI SDA SCL GP5 WSI GPO BCKI RTCB TC VOUTL Vppo Vsso VOUTR VDDA VSSA Vret n c Fig 4 Pin configuration SDIP32 1998 Oct 06 Philips Semiconductors Universal Serial Bus USB Digital to Analog Converter DAC FUNCTIONAL DESCRIPTION All bold faced parameters given in this data sheet such as bAlternateSetting are part of the USB specification as described in USB Device Class Definition for Audio Devices The Universal Serial Bus USB Data and power are transferred via the USB by a 4 wire cable The signalling occurs via two wires and point to point segments The signals on each segment are differentially driven into a cable of 90 Q intrinsic impedance The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection The analog front end The analog front end is an on chip generic USB transceiver It is designed to allow voltage levels up to Vpp from standard or programmable logic to interface with the physical layer of the USB It is capable of receiving and transmitting serial data at full speed 12 Mbits s The USB processor The USB processor forms the interface between the analog front end the ADAC and the microcontroller The USB processor consists of
48. ust have a pull up resistor Notes 2 Connect disconnect holds the USB disconnected as long as the initialization is not finished 3 Alarm mute input to switch the sound off specially used if the USB host program does not respond to the control This pin acts directly on the sound and passes the mute to the USB host 4 Standby is switched on output becomes LOW after a programmable time if mute is active see Byte 18 of Table 6 5 Mute is switched on output becomes LOW after a programmable time if the isochronous data flow is interrupted see Byte 17 of Table 6 6 For selection between HID LED application see configuration map byte 11 output is active HIGH Table 8 4 pins digital communication PIN INPUT OUTPUT FUNCTION 1 FUNCTION 2 GP5 output not programmable note 1 connect disconnect connect disconnect digital O bus BCKO GP2 GPO input programmable HID input 1 alarm mute note 2 Notes 1 Connect disconnect holds the USB disconnected as long as the initialization is not finished 2 Alarm mute input to switch the sound off specially used if the USB host program does not respond to the control This pin acts directly on the sound and passes the mute to the USB host 1998 Oct 06 24 Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 Table 9 6 digital communication PIN INPUT OU
49. with the same coefficients being used in reversed order The mute on the master channel is synchronized to the sample clock so that operation always takes place on complete samples A mute can be given via the host or by pressing a predefined GP pin Philips Semiconductors Preliminary specification Universal Serial Bus USB Digital to Analog Converter DAC UDA1321 TREBLE CONTROL The treble control is available for the master channel of the UDA1321 Treble can be regulated in three modes minimum flat and maximum mode The preferred mode is selected at start up of the device configuration map The corner frequency is 3000 Hz for the minimum mode and 1500 Hz for the maximum mode The treble range is from 0 to 6 dB in steps of 2 dB It should be noted that the negative treble values as defined in the USB Device Class Definition for Audio Devices are not supported by the UDA1321 the 0 dB value is returned as 0 dB Table 4 gives the mapping of the bTreble value upon the actual treble setting of the USB DAC Table4 Treble control characteristics note 1 bTREBLE TREBLE USB TREBLE USB DAC dB B3 SIDE dB minimum maximum 0 0 00 0 0 _ quem 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 31 75 6 0 6 1 The2 dB step is not supported
50. y master channel e Dynamic bass boost control only master channel These specific features can be activated via the host audio device class requests or via the GP pins HID plus audio device class requests Via the I2C bus the user is able to download the necessary configuration data for different applications definition of the function of the GP pins with or without digital functionality etc The mapping and control of the standard USB audio features and UDA1321 specific features is described below VOLUME CONTROL Volume control is possible via the host or via predefined GP pins The setting of 0 dB is always referenced to the maximum available volume setting Table 3 gives the mapping of wVolume value as defined in the USB Device Class Definition for Audio Devices upon the actual volume setting of the USB DAC When using the UDA1321 the range is 0 down to 60 dB in steps of 1 dB and dB Independant control of left right volume is possible It should be noted that wVolume bits B7 to BO not used Values above 0 are returned as 0 dB The volume value at start up of the device is defined in the selected configuration map Balance control is possible via the separate volume control option of both channels Therefore the characteristics of the balance control are equal to the volume control characteristics Philips Semiconductors Universal Serial Bus USB Preliminary specification UDA132
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