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AMD SR5690 Databook MANUAL

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1. GPP2 W6 GPP2 RX6N 4 GPP2 RX6P Y5 GPP2 RX7N 5 GPP2 RX7P AA6 GPP2_RX8N AB4 GPP2_RX8P ABS GPP2_RX9N AD1 GPP2_RX9P AD2 GPP2_TXON P1 GPP2 TXOP P2 GPP2 TX10N AE2 GPP2 TX10P GPP2 TX11N GPP2 TX11P AG4 GPP2_TX12N AH6 GPP2_TX12P AG6 GPP2_TX13N GPP2 TX13P AF7 GPP2_TX14N AH8 GPP2 TX14P AG8 GPP2_TX15N AG9 GPP2 TX15P AF9 GPP2 TX1N R2 GPP2 TX1P R3 GPP2 TX2N T1 GPP2 TX2P T2 GPP2 U2 GPP2 U3 GPP2 V1 GPP2 V2 GPP2 5 W2 GPP2_TX5P GPP2 TX6N Y1 GPP2 TX6P Y2 GPP2 TX7N AA2 43869 SR5690 Databook 2 10 Appendix A 10 GPP2 TX7P 2 TX8N AB1 GPP2 TX8P AB2 GPP2 TX9N AC2 GPP2 TX9P REFCLKN 14 GPP3 REFCLKP AA15 GPP3 AG20 RXOP AH20 GPP3 RX1N AC19 GPP3 AD19 GPP3 RX2N AD18 GPP3 RX2P AE18 GPP3 AC17 GPP3 RXSP AD17 GPP3 4 AD16 GPP3 4 AE16 GPP3 RX5N AC15 GPP3 RX5P AD15 GPP3 RX6N AD14 GPP3 RX6P 14 GPP3 RX7N AC13 GPP3 RX7P AD13 GPP3 RX8N AD12 GPP3 RX8P AE12 GPP3 RX9N AC11 GPP3 RX9P AD11 GPP3 TXON AF19 GPP3 TXOP AG19 GPP3 TX1N AG18 GPP3 AH18 GPP3 TX2N AF17 GPP3 TX2P AG17 GPP3 AG16 GPP3 AH16 GPP3 AF15 GPP3 AG15 GPP3 5 AG14 GPP3 TXSP AH14 GPP3 TX6N AF13 GPP3 TX6P AG13 GPP3 TX7N AG12 GPP3 TX7
2. 2 2 2 GPP3 lane 1 x1 x4 x4 GPP3 lane 2 x1 x1 GPP3a x2 x2 GPP3 lane 3 x1 x1 GPP3 lane 4 x1 x1 x1 x1 x2 x2 GPP3 lane 5 x1 x1 x1 x1 2 7 External Clock Chip On the SR5690 platform an external clock chip provides the CPU PCI Express and A Link Express II reference clocks For requirements on the clock chip please refer to the 800 Series IGP Express AMD Platform External Clock Generator Requirements Specification for Server Platforms 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 2 14 Proprietary Chapter 3 Pin Descriptions and Strap Options This chapter gives the pin descriptions and the strap options for the SR5690 To jump to a topic of interest use the following list of hyperlinked cross references Pin Assignment Top View on page 3 2 SR5690 Interface Block Diagram on page 3 4 CPU HyperTransport Interface on page 3 4 PCI Express Interfaces on page 3 5 PCI Express Interface for General Purpose External Devices on page 3 5 A Link Express II Interface to Southbridge on page 3 5 Miscellaneous PCI Express Signals on page 3 6 Clock Interface on page 3 6 Power Management Pins on page 3 7 Miscellaneous Pins on page 3 7 Power Pins on page 3 8 Ground Pins on page 3 9 Strapping Options on page 3 10 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 1
3. H28 27 K28 TXCADAP K27 127 126 6 M28 TXCAD6P M27 TXCAD7N N27 TXCAD7P N26 HT TXCAD8N E24 HT TXCAD8P E23 HT TXCAD9N F25 HT TXCAD9P F24 HT TXCALN D27 HT TXCALP D28 HT TXCLKON J27 TXCLKOP J26 HT TXCLK1N J24 TXCLK1P J23 HT TXCTLON P28 TXCTLOP P27 TXCTL1N P25 HT TXCTL1P P24 2 B20 I2C DATA C20 LDTSTOP E15 OSCIN B17 PCE_BCALRN AD20 PCE_BCALRP AE20 PCE_RCALRN AD10 PCE_RCALRP AE10 PCE TCALRN E14 PCE TCALRP F14 PCIE RESET GPIO1 B19 PCIE RESET GPIO2 D17 PCIE RESET GPIO3 D19 PCIE RESET GPIO4 E19 PCIE RESET GPIO5 E17 POWERGOOD A17 PWM GPIO1 E16 PWM GPIO2 Bis PCIE INT PWM GPIO3 F16 PWM GPIO4 A15 PWM GPIO5 C16 PWM GPIO6 B16 SB AH26 SB AG26 SB RXIN AG25 SB AF25 SB RX2N AE22 SB RX2P AD22 SB_RX3N AD21 SB_RX3P 21 SB TXON AH24 SB AG24 SB TXIN AG23 SB 23 SB TX2N AG21 SB TX2P AF21 SB TX3N 22 SB TX3P AG22 STRP DATA E21 SYSRESET D15 TESTMODE A19 THERMALDIODE N AA21 THERMALDIODE P Y21 VDD18 A18 VDD18 B18 VDD18 C18 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 Appendix A 11 5 5690 Pin Listing Sorted by Ball Refe
4. R12 VDDC R13 VSS R14 VDDC R15 VSS R16 VDDC R17 VSS R18 VSS R2 GPP2_TX1N R21 VDDHT R22 VSS R23 RXCTL1N R24 HT RXCTL1P R25 VSS R26 HT_RXCTLON R27 HT_RXCTLOP R28 VSS R3 GPP2_TX1P R4 VSS R5 GPP2 RX1N R6 GPP2 R7 VSS R8 VDDPCIE T1 GPP2_TX2N T11 VSS T12 VSS T13 VDDC T14 VSS T15 VDDC T16 VSS T17 VDDC T18 VSS T2 GPP2_TX2P T21 VSS T22 VDDHT T23 VSS T24 HT_RXCAD15N HT_RXCAD15P T25 T26 VSS T27 HT_RXCAD7N T28 HT_RXCAD7P T3 VSS T4 GPP2_RX2N T5 GPP2_RX2P T6 VSS T7 VDDPCIE T8 VSS U1 VSS U11 VSS U12 VSS U13 VSS U14 VDDC U15 VSS U16 VDDC U17 VSS U18 VSS U2 GPP2_TX3N U21 VDDHT U22 VSS U23 HT_RXCAD14N U24 HT_RXCAD14P U25 VSS U26 HT_RXCAD6N U27 HT_RXCAD6P U28 VSS U3 GPP2_TX3P U4 VSS 05 GPP2 U6 GPP2_RX3P U7 VSS U8 GPP2_REFCLKN V1 GPP2 V11 VDDA18PCIE 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 Appendix A 7 SR5690 Pin Listing Sorted by Ball Reference W7 VSS ws VDDPCIE Y1 GPP2_TX6N Y2 GPP2 TX6P Y24 THERMALDIODE P Y22 VDDHT Y23 VSS Y24 HT_RXCLK1N Y25 HT Y26 VSS Y27 HT_RXCLKON Y28 RXCLKOP VSS Y4 GPP2_RX6N
5. 2 ex ex o At 99 e 366 90 O COCCO 356 YOK 999 d 70 5 5 5 3 1 Pressure Specification To avoid damages to the ASIC die or solder ball joint cracks caused by improper mechanical assembly of the cooling device follow the recommendations below It is recommended that the maximum load that is evenly applied across the contact area between the thermal management device and the die does not exceed 6 lbf Note that a total load of 4 6 lbf is adequate to secure the thermal management device and achieve the lowest thermal contact resistance with a temperature drop across the thermal interface material of no more than 3 C Also the surface flatness of the metal spreader should be 0 001 inch 1 inch Pre test the assembly fixture with a strain gauge to make sure that the flexing of the final assembled board and the pressure applying around the ASIC package will not exceed 600 micron strain under any circumstances 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 5 5 Package Information 5 3 2 Ensure that any distortion bow or twist of the board after SMT and cooling device assembly is within industry guidelines IPC EIA J STD 001 For measurement method refer to the industry approved technique described in the manual IPC TM 650 section 2 4 22 Board Solder Reflow Process Recommendations 5 3 2 1 Stencil Opening Size for Solderba
6. 3 6 Table 3 6 Power Management Ping uu Ra E de AM tenes INE RAN 3 7 Table 3 7 Miscellaneous Pins iu odis nase anid DOR Dus bo INE re DURAN ADR A Un MI MNA 3 7 Table 3 8 Power Pins dee intei UAR ARIS Bonae igni M f anm 3 8 Fable 3 9 Ground pt 3 9 Table 3 10 Strap Definitions for the SR5690 22222 22 110000000000 0000 3 10 Table 3 11 Strap Definition for STRAP PCIE a 3 10 Table 4 1 Timing Requirements for Differential Clocks REFCLK GPP2 REFCLK and GPP3 REFCLK at 4 1 Table 4 2 Timing Requirements for HyperTransport Reference Clock 100 2 9 4 1 Table 4 3 Timing Requirements for OSCIN Reference Clock 14 3181818 2 4 2 Table 4 4 Power Rail Groupings for SR5690 4 2 Table 4 5 SR5690 Power Rail Power up Sequence Table 5 1 Power Rail Maximum and Minimum Voltage Ratings MSIE M UE LI LUI 5 1 Table 5 2 Power Rail Current Ratings ase a ieee ee a PA OPI NND ING 5 1 Table 5 1 DC Characteristics for
7. de ti vii tdi d arab dn iu Ad rena i reditu kd 7 5 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary List of Figures 1 This page 15 left blank intentionally 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc List of Figures 2 Proprietary List of Tables Table 1 1 Device IDs for SR5690 5670 5650 Chipset Family 1 3 Table 1 2 Pin Vy pe COGS quM canada a ELA RE KM Nf pt UM AU 1 4 Table 1 3 Acronyms and ADbreviatlIOls APR DUE XU DUX RS un 1 5 Table 2 1 SR5690 HyperTransport Flow Control Buffers 2 3 Table 2 2 Types of Errors Detectable by the SR5690 AER Implementation sese eee mene 2 10 Table 2 3 Types of HyperTransport Errors Supported by the SR5690 2 11 Table 2 4 Possible Configurations for the PCI Express General Purpose Links 2 12 Table 2 5 GPP3a Ports with PCIe amp Hot Plug Support Shaded 2 14 Table 3 12 HyperTransport M nter aco 3 4 Table 3 2 PCI Express Interface for General Purpose External Devices sse eee 3 5 Table 3 3 1 x 4 Lane A Link Express II Interface for Nobb M 3 5 Table 3 4 Miscellaneous PCI Express Signals Table 3 52 Clock Interface
8. pei ed raped ante e p E b 7 1 7 3 2 Description of the Tree for the 5 5690 7 2 T33 XOR Tree Activation daos EE MER RN Hulu se 7 2 7 34 XOR Tree for th SR5690 7 3 T Test SIMA 7 4 741 Brief Description of a VOH VOL 7 4 4742 VOH VOL Trec ROREM D BRE NEU qM eras unen MP Matar a ee NUUS 7 5 TAS list A 7 6 Appendix A Pin Listings 7 5 SR5690 Pin Listing Sorted by Ball Reference A 2 585690 Pin Listing Sorted by Pin 9 Appendix Revision History 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary Table of Contents 3 This page 15 left blank intentionally 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Table of Contents 4 Proprietary List of Figures Figure 1 1 SR5690 Branding Diagram for A21 Production ASIC Eutectic Part 1 3 Figure 1 2 SR5690 Branding Diagram for A21 Production ASIC Lead Free Part 1 3 Figure 1 3 SR5690 Alternate Branding for A21 Production ASIC Lead Free sss 1 4 Figure 2 12
9. 1 5 Chapter 2 Functional Descriptions 2 2HyperTransport M Interfaces aeuo V Midi LA ADMI 2 1 mr 2 1 2 1 2 HyperTransport Flow Control 2 3 2 2 TOMMU tle uia m M Sad d rn im ai dap ens 2 4 2 3 Multiple Northbridge Support uadit oat ec dbi bti on hpc cde dba d 2 4 DA Tan be er up tal ara lta 532225 ation vilia UN addu Used dup dub ERI 2 4 24 1 Legacy INTX Handling RDUM I bM DATI M 2 4 2 4 2 JNon SBJOAPIC darti eri dad cu iaa en MR DE Mua RD c ZO daa p 2 4 243 TIntesrated IOAPIC SupPOrt 2 5 2 44 Interrupt Handling and MSI to HT Interrupt Conversion 253 245 Intemally Generated 2 5 2 4 6 JOMMU Interrupt Remap pimp RAPI EUM A cine uti e popa UE RE DUM ad Uu 2 5 2477 JInterr pt Routing GARE HERE NDARE AA RGR TEES 2 5 2 5 AI M GIU RUD 2 7 2 5 D n inlata m dn 2 7 2 5 2 SERR FAT
10. Overall Preheat Room temp to 220 C 2 mins to 4 min Soaking Time 130 C to 170 C Typical 60 80 seconds Liquidus 220 C Typical 60 80 seconds Ramp Rate Ramp up and Cooling lt 2 C second Peak Max 245 C 235 C 5 C Temperature at peak 240 C to 245 C 10 30 seconds within 5 C 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Proprietary Package Information Solder Part Surface Temp Peak Temp 235 C 5 typ 245 C PEIUS 220 deg C lt 2 0 fee P E Soaking Zone Soldering Zone 60 120 sec max 100 9 P e 2 0 C Sec 45 90 sec Max 60 80 sec typical 60 80 sec typical Pre heating Zone 50 2 min to 4 min Max Heating Time Figure 5 4 RoHS Lead Free Solder SAC305 405 Tin Silver Copper Reflow Profile 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 5 7 Package Information This page is left blank intentionally 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 5 8 Proprietary Chapter 6 Power Management and ACPI 6 1 ACPI Power Management Implementation This chapter describes the support for ACPI power management provided by the SR5690 The SR5690 system controller supports ACPI Revision 2 0 The hardware system BIOS and drivers
11. 2011 Advanced Micro Devices Inc 1 2 Proprietary Device ID The SR5690 is a member of the AMD chipset family which consists of different devices designed to support different platforms Each device is identified by a device ID which is stored in the NB DEVICE ID register The device IDs for 1 4 Device ID the SR5650 5690 5670 chipset family are as follows Table 1 1 Device IDs for the SR5690 5670 5650 Chipset Family SR5690 5A10h SR5670 5A12h SR5650 5A13h 1 5 Branding Diagrams Northbridge YYWW AN MADE IN TAIWAN WXXXXX 215 0716022 AMD Logo AMD Product Type Date Code Country of Origin Wafer Lot Number Part Number YY Assembly Start Year WW Assembly Start Week Note Branding can be in laser ink or mixed laser and ink marking Figure 1 1 SR5690 Branding Diagram for A21 Production ASIC Eutectic Part Northbridge YYWW MADE IN TAIWAN WXXXXX 215 0716038 AN AMD Logo AMD Product Type Date Code Country of Origin Wafer Lot Number Part Number YY Assembly Start Year WW Assembly Start Week Note Branding can be in laser ink or mixed laser and ink marking Figure 1 2 SR5690 Branding Diagram for A21 Production ASIC Lead Free Part 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 1 3 Conventions and Notations AMD Product Typ
12. D8 GPP1_RX4N F7 GPP1_RX4P E7 GPP1_RX5N E6 GPP1_RX5P D6 GPP1_RX6N C5 GPP1_RX6P BS GPP1_RX7N D1 GPP1_RX7P D2 GPP1_RX8N F4 GPP1_RX8P F5 1 RX9N G5 1 RX9P G6 GPP1 C11 GPP1 TXOP B11 GPP1 TX10N H1 GPP1 TX10P H2 GPP1 TX11N J2 GPP1 TX11P J3 GPP1_TX12N K1 GPP1_TX12P K2 GPP1_TX13N L2 GPP1_TX13P L3 GPP1_TX14N M1 GPP1_TX14P M2 GPP1_TX15N N2 GPP1_TX15P N3 GPP1_TX1N B10 GPP1_TX1P A10 GPP1_TX2N C9 GPP1 TX2P B9 GPP1 B8 GPP1 A8 GPP1_TX4N C7 GPP1_TX4P B7 GPP1_TX5N B6 GPP1 TXSP A6 GPP1 TX6N 4 GPP1 TX6P A4 GPP1 TX7N E2 GPP1 TX7P E3 GPP1 TX8N F1 GPP1 TX8P F2 GPP1 TX9N G2 GPP1 TX9P G3 GPP2 REFCLKN U8 GPP2 REFCLKP V8 GPP2 RXON P4 GPP2 RXOP P5 GPP2 RX10N AF1 GPP2 RX10P AF2 GPP2 5 GPP2 AF5 GPP2 RX12N AEG GPP2 RX12P AD6 GPP2 RX13N AD7 GPP2_RX13P AC7 GPP2_RX14N AE8 GPP2 RX14P AD8 GPP2 RX15N AD9 GPP2 RX15P 9 GPP2 RX1N R5 GPP2 R6 GPP2 RX2N T4 GPP2 RX2P T5 GPP2 US GPP2_RX3P U6 GPP2_RX4N V4 GPP2_RX4P V5 GPP2_RX5N W5 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 Appendix A 9 SR5690 Pin Listing Sorted by Ball Reference
13. S5 Soft Off G3 Mechanical Off System is off OS re boots when the system transitions to the working state Occurs when system power AC or battery is not present or is unable to keep the system in one of the other states 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 6 1 Power Management Implementation This page intentionally left blank 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 6 2 Proprietary Chapter 7 Testability 7 1 Test Capability Features The SR5690 system controller has integrated test modes and capabilities These test features cover both the ASIC and board level testing The ASIC tests provide a very high fault coverage and low DPM Defect Per Million ratio of the part The board level tests modes can be used for motherboard manufacturing and debug purposes The following are the test modes of the SR5690 system controller e Full scan implementation on the digital core logic that provides about 97 fault coverage through ATPG Automatic Test Pattern Generation Vectors e Dedicated test logic for the on chip custom memory macros to provide complete coverage on these modules e Improved access to the analog modules PLLs in the SR5690 system controller in order to allow full evaluation and characterization of these modules e test mode which is not entirely compliant to the IEEE 1149 1 stand
14. Wait 5 or more 2 cycles 2 3 4 5 6 Load JTAG instruction register with the instruction 0001 1111 7 Load JTAG instruction register with the instruction 0010 0000 8 Load JTAG instruction register with the instruction 0101 1101 9 Go to Run Test Idle state 10 Set POWERGOOD to 1 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 7 5 VOH VOL Test 7 4 3 VOH VOL pin list Table 7 5 below shows the SR5690 VOH VOL Tree There is no specific order of connection Under the Control column an Odd or Even indicates that the logical output of the pin is same as the input to the 5 ODD or the TEST EVEN pin respectively When a differential signal pair appear in the table as a single entry the output of the positive pin is indicated in the Control column see last paragraph for explanations and the output of the negative pin N will be of the opposite value E g for entry no on the tree when TEST EVEN is 1 HT TXCADOP will give a value of 1 and HT TXCADON will give a value of 0 Table 7 5 SR5690 VOH VOL Tree 1 HT TXCADOP N E26 E27 Even 90 Jude Oda 2 HT_TXCAD1P N F27 F28 Odd 31 KASI Even 3 TXCAD2P N G26 G27 Even i LEE 4 HT TXCAD3P N H
15. 585690 CPU I CPU Device IOMMU PCI E Endpoint Device PCI Express IOAPIC SR5690 INTx Message from PCI Express device attached to SR5690 Internal interrupt Remapped HT Interrupt SB Figure 2 5 Interrupt Routing Paths in Legacy Mode with Integrated IOAPIC 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 2 6 Proprietary RAS Features 2 4 7 3 2 5 2 5 1 2 5 1 1 2 5 1 2 2 5 2 MSI Mode For both the primary and secondary SR5690s MSI interrupt requests are remapped by the IOMMU and sent up to the processor complex The routing path 15 illustrated in Figure 2 6 below PCI E Endpoint SR5690 m CPU 4 gt CPU Device HT IOMMU PCI E Endpoint J eue Device 585690 MSI Interrupt from PCI Express device attached to 585690 Remapped HT Interrupt SB Figure 2 6 Interrupt Routing Path in MSI Mode RAS Features Parity Protection memories in SR5690 are parity protected to reduce the possibility of silent data corruption Multiple parity words are interleaved to convert burst errors multiple physically adjacent bits corrupted into multiple single bit detectable errors to increase robustness The minimum number of interleaved parity words
16. bebe De rubet nU acea on Ron 1 1 1 24 Processor Support ERE ba Fab rap irt ii 1 2 12 5 Multiple Northbridge Support code eic auque led ded 1 2 1 2 0 PowerManapement Features dde ou ebria 1 2 12 7 PC Design Guide Compliatice ss cni i onere eb 1 2 1 2 8 Test Capability Features 1 2 1249 Mm Bcc hac 1 2 1 3 Software FEA ties E c dar OU Ud LER 1 2 1 4 0 1 3 1 5 Branding Diaprams ea 1 3 1 6 Conventions and dl cpi dance se lUa depend oen 1 4 L6 Pin 1 4 16 22 ERE 1 4 1 63 Numeric Representation oed ARR 1 4 164 Hyperlinks AMD MM D dM M MM Uis AM 1 5 L6 Acronymsand ADDreviatiofis
17. G26 HT_TXCAD2P G27 HT_TXCAD2N G28 VSS G3 GPP1_TX9P G4 VSS G5 GPP1_RX9N G6 GPP1_RX9P G7 VDDPCIE G8 VDDPCIE G9 VSS H1 GPP1_TX10N H10 VSS H11 VDDPCIE H12 VDDA18PCIE H13 VDDA18PCIE H14 VDDA18PCIE H15 VSS H16 VSS H17 VSS H18 VSS H19 VSS H2 GPP1_TX10P H20 VSS H21 VSS 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 Appendix A 5 SR5690 Pin Listing Sorted by Ball Reference H22 VDDHTTX H23 VSS H24 HT_TXCAD11P H25 HT_TXCAD11N H26 VSS H27 HT_TXCAD3P H28 HT_TXCAD3N H3 VSS H4 GPP1_RX10N H5 GPP1_RX10P H6 VSS H7 VDDPCIE H8 GPP1_REFCLKN H9 VDDPCIE J1 VSS J2 GPP1_TX11N J21 HT_REFCLKN J22 VSS J23 HT_TXCLK1P J24 HT_TXCLK1N J25 VSS J26 HT_TXCLKOP J27 HT_TXCLKON J28 VSS J3 GPP1 TX11P J4 VSS J5 GPP1_RX11N J6 GPP1 J7 VSS J8 GPP1_REFCLKP K1 GPP1_TX12N K2 GPP1_TX12P K21 HT_REFCLKP K22 VDDHT K23 VSS K24 HT_TXCAD12P 43869 SR5690 Databook 2 10 Appendix A 6 K25 HT_TXCAD12N K26 VSS K27 HT_TXCAD4P K28 HT_TXCAD4N K3 VSS K4 GPP1_RX12N K5 GPP1 RX12P K6 VSS K7 VDDPCIE K8 VSS L1 VSS L11 VDDA18PCIE L12 VSS L13 VSS L14 VDDC L15 VSS L16 VDDC L17 VSS L18 VSS L2 GPP1_TX13N L21 VDDHT L22 VSS L23 HT_TXCAD13
18. Note If the pin straps instead of strap values from EEPROM are used the GPP3 configuration will then be determined according to this table and cannot be changed after the system has been powered up 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 3 10 Proprietary Chapter 4 Timing Specifications 4 1 HyperTransport Bus Timing For HyperTransport bus timing information please refer to specifications by AMD 4 2 PCI Express Differential Clock AC Specifications Table 4 1 Timing Requirements for PCle Differential Clocks GPP1_REFCLK GPP2_REFCLK and GPP3_REFCLK at 100MHz a SSS ee eee l Rising Edge Rate Rising Edge Rate 0 6 4 0 Vins Falling Edge Rate Falling Edge Rate 0 6 4 0 Vins AVG Average Clock Period Accuracy 100 100 ppm ABS Absolute Period including jitter and spread spectrum 9 847 10 203 ns modulation TecJITTER Cycle to Cycle Jitter 150 ps Duty Cycle Duty Cycle 40 60 Rise Fall Matching Rising edge rate REFCLK to falling edge rate 20 REFCLK matching 4 3 Hyper Transport Reference Clock Timing Parameters Table 4 2 Timing Requirements for HyperTransport Reference Clock 100MHz AVcross Change in Crossing point voltage over all edges 140 mV 1 F Frequency 99 5 100 MHz 2 ppm Long Term Accuracy 100 100 Ppm 3 SFALL Output falling edge slew rate 10 0 5 Vins
19. PLL Power GPIO 1 8V I O Power HyperTransport Interface Power Grounds Other 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 3 3 585690 Interface Block Diagram 32 SR5690 Interface Block Diagram Figure 3 1 shows the different interfaces on the SR5690 Interface names in blue are hyperlinks to the corresponding sections in this chapter HT RXCAD 15 0 P HT RXCAD 15 0 N HT RXCLK 1 0 P HT RXCLK 1 0 N HT RXCTL 1 0 P HT RXCTL 1 0 N HT TXCAD 15 0 P HT TXCAD 15 0 N HT TXCLK 1 0 P HT TXCLK 1 0 N HT TXCTL 1 0 P HT TXCTL 1 0 N HT RXCALP HT RXCALN HT TXCALP HT TXCALN SB TX 3 0 P SB TX 3 0 N SB RX 3 0 P SB RX 3 0 N SYSRESET POWERGOOD LDTSTOP ALLOW_LDTSTOP PWM_GPIO 6 1 DBG_GPIO3 NON_FATAL_CORR DBG GPIO2 PCIE HP SDA GPIO1 PCIE SCL DBG_GPIO0 SERR_FATAL I2C CLK I2C DATA STRP DATA DFT_GPIO5 SYNCFLOODIN DFT_GPIO 4 1 DFT_GPIOO NMI TESTMODE THERMALDIODE_P THERMALDIODE_N PWM GPIO 6 3 1 PWM GPIO2 PCIE HP INT L vss PCle Interface GPP1_TX 15 0 P GPP4_TX 15 0 N GPP1_RX 15 0 P GPP1_RX 15 0 N GPP2 TX 15 0 P GPP2_TX 15 0 N Purpose GPP2 RX 15 0 P GPP2 RX 15 0 N External GPP3 TX 9 0 P GPP3 TX 9 0 N Devices GPP3 RX 9 0 P GPP3 RX 9 0 N HyperTransport Interface for General A Link Express Interface PCE_BCALRP PCE_BCALRN PCE RCALRP PCE RCALRN PCE TCALRP PCE TCALRN Signals PCIE RESE
20. Y5 GPP2_RX6P Y6 VSS Y7 VDDPCIE Y8 VSS V12 VSS V13 VSS V14 VSS V15 VSS V16 VSS V17 VSS V18 VDDA18PCIE V2 GPP2 V21 VSS V22 VDDHT V23 VSS V24 HT_RXCAD13N V25 HT_RXCAD13P V26 VSS V27 HT_RXCAD5N V28 HT_RXCAD5P V3 VSS V4 GPP2_RX4N V5 GPP2_RX4P V6 VSS V7 VDDPCIE V8 GPP2 REFCLKP W1 VSS W2 GPP2 5 W21 VDDHT W22 VSS W23 HT_RXCAD12N W24 HT_RXCAD12P W25 VSS W26 HT_RXCAD4N W27 HT_RXCAD4P W28 VSS W3 GPP2_TX5P WA VSS W5 2 5 W6 GPP2 5 43869 SR5690 Databook 2 10 Appendix A 8 2011 Advanced Micro Devices Inc Proprietary SR5690 Pin Listing Sorted by Ball Reference A 2 SR5690 Pin Listing Sorted by Pin Name ALLOW_LDTSTOP D21 4 C22 en pes cr DBG_GPIO3 A21 NON FATAL 26 GPIO1 25 GPIO2 24 25 4 23 MENS GPP1 REFCLKN H8 GPP1 REFCLKP J8 GPP1 RXON F11 GPP1 RXOP E11 GPP1 RX10N H4 GPP1_RX10P H5 GPP1_RX11N J5 GPP1_RX11P J6 GPP1_RX12N K4 GPP1_RX12P K5 GPP1_RX13N L5 GPP1_RX13P L6 GPP1 RX14N M4 GPP1_RX14P M5 GPP1_RX15N N5 GPP1_RX15P N6 GPP1_RX1N E10 GPP1_RX1P D10 GPP1_RX2N F9 GPP1_RX2P E9 GPP1 RX3N E8 GPP1
21. 2011 Advanced Micro Devices Inc List of Tables 2 Proprietary Chapter 1 Overview 1 1 1 2 Introducing the SR5690 The SR5690 formerly RD890S is the system logic of the latest server workstation platform from AMD that enables its next generation CPUs The SR5690 has a total of 46 PCI Express PCIe lanes 42 lanes are dedicated for external PCIe devices and 4 are dedicated for the A Link Express II interface to AMD s Southbridges such as the SP5100 formerly SB700S The SR5690 also comes equipped with the new HyperTransport 3 and PCIe Gen 2 technologies of these are achieved by a highly integrated thermally efficient design in a 29mm x 29mm package The SR5690 introduces a variety of Reliability Availability and Serviceability RAS capabilities These include parity protection for on chip memories PCI Express Advanced Error Reporting AER and advanced error handling capabilities for HyperTransport The SR5690 also supports a revision 1 26 compliant IOMMU Input Output Memory Management Unit implementation for address translation and protection services This feature allows virtual addresses from PCI Express endpoint devices to be translated to physical memory addresses On chip caching of address translations is provided to improve I O performance The device 15 also compliant with revision 1 0 of the PCI Express Address Translation Services ATS specification to enable ATS compliant endpoint devices t
22. 4 5 SRISE Output rising edge slew rate 0 5 10 Vins 4 5 max Jitter cycle to cycle 150 6 Tj accumulated Accumulated jitter over a 10 us period 1 1 ns 7 Vp PK PK Peak to Peak Differential Voltage 400 2400 mV 8 Vp Differential Voltage 200 1200 mV 9 AVp Change in cycle to cycle 75 75 mV 10 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 4 1 OSCIN Reference Clock Timing Parameters Table 4 2 Timing Requirements for HyperTransport Reference Clock 100MHz Continued DC Duty Cycle 45 55 96 11 Notes More details are available in AMD HyperTransport 3 0 Reference Clock Specification and AMD Family 10h Processor Reference Clock Parameters document 34864 1 Single ended measurement at crossing point Value is maximum minimum over all time DC Value of common mode is not important due to blocking cap 2 Minimum frequency is a consequence of 0 596 down spread spectrum 3 Measured with spread spectrum turned off 4 Only simulated at the receive die pad This parameter is intended to give guidance for simulation It cannot be tested on a tester but is guaranteed by design 5 Differential measurement through the range of x100mvV differential signal must remain monotonic and within slew rate specification when crossing through this region 6 is the maximum difference of tcyc_e between any two adjacent cycles 7 Accumulated over 10ys time period measured with
23. Core power VDDPCIE 1 1V 39 PCI Express interface main I O and PLL power VDDHTTX 1 2V 11 022 023 E22 F22 G22 HyperTransport Transmit Interface I O power H22 VDDA18HTPLL 1 8V 1 G21 HyperTransport interface 1 8V PLL Power Total Power Pin Count 116 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 3 8 Proprietary Ground Pins 3 9 Ground Pins Table 3 9 Ground Pins VSS 261 A11 A14 A16 A20 A22 A24 26 5 AT A9 AAT AA11 AA13 AA17 AA19 AA20 AA25 AA28 AA4 AAT 9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB23 AB26 AB3 AB6 AB8 AC1 AC10 AC12 AC14 AC16 AC18 AC20 AC25 AC28 ACA 5 AC8 AD26 AD3 AD4 AE1 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AES AE7 9 10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AF4 AF6 AF8 AG27 AH11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AHS B14 B27 B3 C10 C14 C15 C17 C19 C2 C21 C23 CA C6 C8 D11 D14 D16 D20 D26 D3 D5 D7 D9 E1 E20 E25 E28 E4 F10 F15 F17 F18 F19 F20 F21 F23 F26 F3 F8 G1 G11 G15 G16 G17 G18 G19 G20 G25 G28 G4 G9 H10 H15 H16 H17 H18 H19 H20 H21 H23 H26 H3 H6 J1 J22 J25 J28 J4 97 K23 K26 L1 L12 L13 L15 L17 L18 L22 L25 L28 L4 L7 M11 M12 M14 M16 M17 M18 M21 M23 M26 M3 M6 M8 N1 N11 N13 N15 N17
24. GPIO1 PWM 2 CIE HP INT L PWM_GPIO6 OSCIN PWM_GPIO5 J PCIE_RESET_ 1075 Gril i PCIE RESET LDTSTOP amp PWM GPIO1 EP STRP DATA PWM GPIO3 VDDA18HTPL HT REFCLKN GPIO4 HT REFCLKP VDDA18PCIE THERMALDIO DEP VDDPCIE psu Enid GPP3_RX1P PCE BCALRN SB RX3N ON GPP3 REFCL KP VDDPCIE GPP3 RX5N GPP3 RX3N GPP3 RX4N GPP3 4P GPP3_RX2P PCE_BCALRP GPP3_TX4N GPP3_TX2N PIO1 GPIO0 S ERR FATAL SB RX2P SB Si 4P GPP3 GPP3 TX3N TX2P GPP3 RXON SB SB TXIN SB TX3N SB EN EN 2218 19 15 16 17 18 20 22 24 DFT GPIO4 DFT GPIO2 DF BET iMd SB SB SB RXON AG AH 26 27 28 CPU Interface A Link Express II Interface Clock Interface PCle GPP1 General Purpose Interface PCle GPP2 General Purpose Interface PCle GPP3 General Purpose Interface Power Management Interface Core Power PCIe Main Power 1 8V Power
25. GPP2_RX8P AB6 VSS AB7 VDDPCIE AB8 VSS AB9 VDDPCIE AC1 VSS AC10 VSS AC11 GPP3 RX9N AC12 VSS AC13 GPP3_RX7N AC14 VSS AC15 GPP3_RX5N AC16 VSS AC17 GPP3_RX3N AC18 VSS AC19 GPP3_RX1N AC2 GPP2_TX9N AC20 VSS AC21 5 22 VDDHT AC23 RXCAD9N AC24 RXCAD9P AC25 VSS AC26 HT_RXCAD1N AC27 HT_RXCAD1P 2011 Advanced Micro Devices Inc Proprietary SR5690 Pin Listing Sorted by Ball Reference AC28 VSS AC3 GPP2_TX9P AC4 VSS AC5 VSS AC6 VDDPCIE AC7 GPP2_RX13P AC8 VSS 9 GPP2 RX15P AD1 GPP2 RX9N AD10 PCE RCALRN AD11 RX9P AD12 RX8N AD13 GPP3_RX7P AD14 GPP3_RX6N AD15 GPP3_RX5P AD16 GPP3_RX4N AD17 GPP3_RX3P AD18 GPP3_RX2N AD19 GPP3_RX1P AD2 GPP2_RX9P AD20 PCE_BCALRN AD21 SB AD22 SB RX2P AD23 VDDHT AD24 RXCAD8N AD25 RXCAD8P AD26 VSS AD27 HT_RXCADON AD28 HT_RXCADOP AD3 VSS AD4 VSS AD5 VDDPCIE AD6 GPP2 RX12P AD7 GPP2_RX13N AD8 GPP2_RX14P AD9 GPP2 RX15N AE1 VSS AE10 PCE_RCALRP AE11 VSS AE12 GPP3_RX8P AE13 VSS AE14 GPP3_RX6P AE15 VSS AE16 GPP3_RX4P AE17 VSS AE18 GPP3_RX2P AE19 VSS AE2 GPP2_TX10N AE20 PCE_BCALRP AE21 VSS AE22 SB_RX2N AE23 VSS AE24 VDDHT AE25 VDDHT AE26 VDDHT AE27 VDDHT AE2
26. Pin Assignment Top View 3 1 Assignment Top View 3 AG VDDPCIE VDDPCIE AH 12 13 VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDPCIE VDDPCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDPCIE VDDPCIE VDDA18PCIE VDDA18PCIE VDDA18PCIE VDDPCIE VDDPCIE VDDA18PCIE VDDPCIE VDDPCIE VDDPCIE VDDPCIE VDDA18PCIE VDDPCIE VDDPCIE VDDPCIE VDDPCIE VDDPCIE MEME PCE RCALRN PCE RCALRP VDDPCIE VDDPCIE CPU Interface A Link Express II Interface Clock Interface GPP1 General Purpose Interface PCle GPP2 General Purpose Interface PCle GPP3 General Purpose Interface Power Management Interface Core Power PCIe Main Power 1 8 Power PLL Power GPIO 1 8V I O Power HyperTransport Interface Power Grounds Other 43869 SR5690 Databook 2 10 3 2 2011 Advanced Micro Devices Inc Proprietary Pin Assignment Top View 15 16 17 21 23 25 27 28 DEG GPIO NON FATAL RR POWERGOO D PWM 4 TESTMODE SYNCFLOODIN DFT
27. VDDHTTX C28 VDDPCIE H9 VDDC 15 VDDHTTX D22 VDDPCIE K7 VDDC P17 VDDHTTX D23 VDDPCIE L8 VDDC R12 VDDHTTX E22 VDDPCIE M7 VDDC R14 VDDHTTX F22 VDDPCIE N8 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Appendix A 12 Proprietary SR5690 Pin Listing Sorted by Ball Reference VDDPCIE P7 VSS AB3 VSS AF24 VDDPCIE R8 VSS AB6 VSS AF26 VDDPCIE T7 VSS AB8 VSS AF28 VDDPCIE 7 vss AC1 vss AF4 VDDPCIE ws vss AC10 vss AF6 VDDPCIE Y7 vss AC12 vss AF8 vss A11 vss AC14 vss AG27 VSS A14 VSS AC16 VSS AG3 VSS A16 VSS AC18 VSS AH11 VSS A20 VSS AC20 VSS AH13 VSS A22 VSS AC25 VSS AH15 VSS A24 VSS AC28 VSS AH17 VSS A26 VSS AC4 VSS AH19 VSS A5 VSS AC5 VSS AH21 VSS A7 VSS AC8 VSS AH23 VSS A9 VSS AD26 VSS AH25 VSS AA1 VSS AD3 VSS AH3 VSS AA11 VSS AD4 VSS AH5 VSS AA13 VSS AE1 VSS AH7 VSS AA17 VSS AE11 VSS AH9 VSS AA19 VSS AE13 VSS B14 VSS AA20 VSS AE15 VSS B27 VSS AA25 VSS AE17 VSS B3 VSS AA28 VSS AE19 VSS C10 vss AA4 vss AE21 vss C14 vss AAT vss AE23 vss C15 VSS AA9 VSS AE5 VSS C17 VSS AB10 VSS AE7 VSS C19 VSS AB12 VSS AE9 VSS C2 vss AB14 vss AF10 VSS C21 vss AB16 vss AF12 vss C23 vss AB18 VSS AF14 VSS C4
28. of the SR5690 have the logic required for meeting the power management specifications of PC2001 OnNow and the Windows Logo Program and Device Requirements version 2 1 Table 6 1 ACPI States Supported by the SR5690 describes the ACPI states supported by SR5690 system controller Table 6 1 ACPI States Supported by the SR5690 Processor States 50 0 Working State Working State The processor is executing instructions S0 C1 Halt CPU Halt state No instructions are executed This state has the lowest latency on resume and contributes minimum power savings S0 C2 Stop Grant Caches Snoopable Stop Grant or Cache Snoopable CPU state This state offers more power savings but has a higher latency on resume than the C1 state S0 C3 Stop Grant Caches Snoopable Processor is put into the Stop Grant state Caches are still snoopable The HyperTransport link may be disconnected and put into a low power state System memory may be put into self refresh System States S1 Standby System is in Standby mode This state has low wakeup latency on resume OEM support of this state is Powered On Suspend optional S3 Standby Suspend to RAM System is off but context is saved to RAM System memory is put into self refresh S4 Hibernate Suspend to Disk System is off but context is saved to disk When the system transitions to the working state the OS is resumed without a system re boot
29. requests which are translated by the IOMMU before they are delivered up to the processor complex Secondary SR5690 Legacy INTx messages are routed over HyperTransport through the processor complex to the primary SR5690 which forwards them to the SB IOAPIC The SB IOAPIC generates upstream interrupt requests which are translated by the IOMMU before being delivered up to the processor complex The routing paths are illustrated in Figure 2 4 below 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 2 5 Interrupt Handling CPU PCI E PCI E Endpoint 569 SR5690 Endpoint Device Device SB INTx Message from device attached to primary SR5690 INTx Message from device attached to secondary SR5690 Interrupts from SB IOAPIC Figure 2 4 Interrupt Routing Paths in Legacy Mode 2 4 7 2 Legacy Mode with Integrated IOAPIC For both the primary and secondary SR5690s legacy INTx messages are routed to the integrated IOAPICs of the SR5690s which generates interrupt requests These requests are remapped by the IOMMU before being delivered up to the processor complex If an INTx message gets directed to an IOAPIC table entry that is not enabled the IOAPIC sends the INTx message back to the IOC to go to the SB PIC IOAPIC The routing paths are illustrated in Figure 2 5 below PCI E gt Endpoint gt
30. strap must be pulled low In the multi NB mode special PCI Express messages for functions such as PME may be passed from a secondary SR56x0 to the primary SR56x0 or the Southbridge over the HyperTransport bus If the SR56x0 s internal IOAPIC is not used INTx messages may also be forwarded over the HyperTransport bus to the Southbridge IOAPIC Peer to peer writes between PCI Express endpoints are also allowed between any SR56x0 and another by routing peer to peer requests over the HyperTransport bus Note As it is possible to mix and match SR5650 SR5670 and SR5690 on the same system whenever a multiple SR5690 configuration is being referred to in this document it actually represents any combination of SR5650 SR5670 and SR5690 possible under that situation Some constrains may apply Interrupt Handling Legacy INTx Handling In legacy interrupt mode all INTx messages must be routed to the Southbridge IOAPIC The primary NB directs all INTx messages directly down to the Southbridge IOAPIC Secondary NBs direct INTx messages up to the processor complex where they are broadcast down to all HT devices See Section 2 3 Multiple Northbridge Support on page 2 4 for details The 4 legacy interrupts sent by endpoint devices INT A B C D may undergo a 2 stage programmable swizzling process that maps them onto the 8 possible internal INTx messages INT A B C D E F G H The first swizzling stage 15 performed by rotating the interrupt message nu
31. the motherboard General Purpose 3 Transmit Data Differential Pairs SIS VDDA18PCIE VSSA PCIE 90 between Connect to connector s for general purpose external GPP3 TX 9 0 N complements device s on the motherboard General Purpose 3 Receive Data Differential Pairs SEES VDDA18PCIE VSSA PCIE Between Connect to connector s for general purpose external GPP3 RX 9 0 N complements device s on the motherboard 3 4 2 A Link Express II Interface to Southbridge Table 3 3 1x 4 Lane A Link Express II Interface for Southbridge Southbridge Transmit Data Differential Pairs Connect to the PB VDDAI8PCIE vssa PciE 200 between orresponding Receive Data Differential Pairs on the SB TX 3 0 N complements Southbridge Southbridge Receive Data Differential Pairs Connect to the VDDA18PCIE VSSA 200 between Transmit Data Differential Pairs on the SB RX 3 0 N complements Southbridge 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 3 5 Clock Interface 3 4 3 3 5 43869 SR5690 Databook 2 10 Miscellaneous PCI Express Signals Table 3 4 Miscellaneous PCI Express Signals PCE BCALRN VDDA18PCIE VSSA PCIE N Channel Driver Compensation Calibration for Rx and Tx Channels on Bottom Side PCE BCALRP VDDA18PCIE VSSA PCIE P Channel Driver Compensatio
32. 0 is optimized to interface with Shanghai and subsequent series of AMD server workstation and desktop processors through sockets AM3 G34 and C32 SR5690 supports HyperTransport 3 HT3 as well as HyperTransport 1 for backward compatibility and for initial boot up For a detailed description of the interface please refer to the HyperTransport Link Specification from the HyperTransport Consortium Figure 2 2 HyperTransport Interface Block Diagram illustrates the basic blocks of the host bus interface of the SR5690 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 2 1 HyperTransport Interface 104 GB s to CPU 10 4 GB s from CPU Tx PHY Tx PHY Interface X Protocol Transmitter Rx PHY Y Rx PHY Interface Protocol Receiver Upstream Arbitration Response Interface Host Interface Host read responses DMA requests IOMMU requests DMA read response ata Host read Host I responses requests IOMMU L2 Cores Controller Figure 2 2 HyperTransport Interface Block Diagram The SR5690 HyperTransport bus interface consists of 16 unidirectional differential Command Address Data pins and 2 differential Control pins and 2 differential Clock pins in both the upstream and do
33. 12P N W24 W23 15 HT_RXCAD13P N V25 V24 16 HT_RXCAD14P N U24 U23 17 HT_RXCAD15P N T25 T24 18 HT_RXCTL1P N R24 R23 19 GPP1_RXOP N E11 F 11 20 GPP1_RX1P N D10 E10 21 GPP1_RX2P N E9 F9 22 1 RX3P N D8 E8 23 1 RX4P N E7 F7 24 GPP1_RX5P N D6 E6 25 GPP1_RX6P N B5 C5 26 GPP1 7 D2 D1 27 1 RX8P N 5 4 28 GPP1_RX9P N G6 G5 29 RX10P N H5 H4 30 GPP1_RX11P N J6 J5 31 GPP1_RX12P N K5 K4 32 GPP1_RX13P N L6 L5 33 GPP1_RX14P N M5 M4 34 GPP1_RX15P N N6 N5 35 GPP2 RXOP N 5 4 36 GPP2 RX1P N R6 R5 37 GPP2 RX2P N 75 74 38 GPP2 U6 U5 39 GPP2 5 4 40 GPP2 W6 W5 41 GPP2 RX6P N 5 4 42 GPP2 7 AAG AAS 43 GPP2_RX8P N ABS AB4 44 GPP2_RX9P N AD2 AD1 45 GPP2 RX10P N AF2 AF 1 46 GPP2 AF5 AG5 47 GPP2 RX12P N AD6 AE6 48 GPP2_RX13P N AC7 AD7 49 GPP2_RX14P N 8 50 GPP2 RX15P N AC9 AD9 51 GPP3 RXOP N AH20 AG20 52 GPP3_RX1P N AD19 AC19 53 GPP3 RX2P N AE18 AD18 54 AD17 AC17 55 GPP3 AE16 AD16 56 GPP3 RX5P N AD15 AC15 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 7 3 VOH VOL Test 74 7 4 1 57 SB RXOP N AG26 AH26 58 SB RX1P N AF25 AG25 59 SB RX2P N AD22 AE22 60 SB_RX3P N AC21 AD21 61 GPP3_RX6P N AE14 AD14 62 GPP3 RX7P N AD13 AC13 63 GPP3_RX8P N A
34. 27 H28 Odd id 1 Even 5 HT_TXCAD4P N K27 K28 Even 36 pug 6 L26 L27 Odd 99 ORES FIN PAPA Even 7 HT TXCAD6P N M27 M28 Even 3B lhe Quo 8 HT_TXCAD7P N N26 N27 Odd 37 rN Even 9 HT_TXCTLOP N P27 P28 Even usya Odd 10 HT_TXCAD8P N E23 E24 Odd 39 GEPA TAARN VAIN Even 11 HT TXCAD9P N F24 F25 Even m Ao Te 12 HT_TXCAD10P N G23 G24 Odd Even 13 HT TXCAD 11P N H24 H25 Even ane 14 HT_TXCAD12P N K24 K25 Odd ABAABI Even 15 HT TXCAD13P N L23 L24 Even i ACHAGA 16 HT TXCAD14P N M24 M25 Odd m TURIN Even 17 HT TXCAD15P N N23 N24 Even 46 GEPSCIAHPIN AGAM odd E mem m 47 GPP2 TX12P N AGG AHG Even 19 GPP1 B11 C11 Even 5 9ga m nun 49 GPP2 14 8 Even Gn GEN m 50 GPP2 TX15P N Odd GERI SEN pon odd 51 GPP3 TXOP N AGA9 AF19 Even 31 ERIS 52 GPP3 TX1P N AH18 AG18 Odd A o 53 GPP3 TX2P N AGI7 AF17 Even m mme pv n 54 GPP3 TX3P N AH16 AG16 Odd a Gee EN 55 GPP3 TX4P N AGI5 AF15 Even 5 Ree 56 GPP3 TX5P N AH14 AG14 Odd m GEH ES od 57 SB AG24 AH24 Even 29 GPP1 TX10P N H2 H1 Even 5 AF29 AG23 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 7 6 Propriet
35. 4 x4 x4 x4 x4 GPP3 lane 8 GPP3 lane 9 e PCIE SB The Southbridge port provides a dedicated x4 link to the Southbridge also referred to as the A Link Express II interface Each port supports the following PCIe functions e PCleGen 1 link speeds e ASPM LOs and L1 states e ACPI power management e Endpoint and root complex initiated dynamic link degradation e Lane reversal e Alternative Routing ID Interpretation ARI e Access Control Services ACS e Advanced Error Reporting AER e Address Translation Services ATS 2 62 PCIe Reset Signals Reset signals to non hot plug PCIe slots as well as embedded PCIe devices must be controlled through one or more software controllable GPIO pins instead of the global system reset It is recommended that unique GPIO pins be used for 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 2 12 Proprietary PCI Express amp 2 6 3 each slot or device Hot plug PCIe slots must have their reset signals connected to unique individually controllable GPIO pins SR5690 has four GPIO pins that may be used for the purpose of driving reset signals PCIE GPIO RESET S5 4 and PCIE GPIO 2 11 Additional reset GPIO pins may be driven by platform specific means such as a super I O or an I O expander PCIe Hot Pug The SR5690 supports hot plug function for up to eight PCIe slots Firmware support available from AMD is required fo
36. 5 2 2 Thermal Diode Characteristics The SR5690 has an on die thermal diode with its positive and negative terminals connected to the THERMALDIODE P and THERMALDIODE N pins respectively Combined with a thermal sensor circuit the diode temperature and hence the ASIC junction temperature can be derived from a differential voltage reading AV The equation relating the temperature to AV 15 given below AV yx Kx Tx q where AV Difference of two base to emitter voltage readings one using current I and the other using current N x I N Ratio of the two thermal diode currents 10 when using an ADI thermal sensor e g ADM 1020 1030 7 Ideality factor of the diode Boltzman s Constant T Temperature in Kelvin q Electron charge The series resistance of the thermal diode must be taken into account as it introduces an error in the reading for every 1 00 approximately 0 8 C is added to the reading The sensor circuit should be calibrated to offset the Ry induced plus any other known fixed errors Measured values of diode ideality factor and series resistance for the diode circuit are defined in Thermal Design and Analysis Guidelines for SR5650 5670 5690 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 5 3 Package Information 53 Package Information Figure 5 2 and Table 5 6 describe the physical dimensions of the SR5690 package Figure 5 3 shows the detailed ball arrangement f
37. 6 VSS P8 VSS R1 VSS R11 VSS R13 VSS R15 VSS R17 2011 Advanced Micro Devices Inc Proprietary SR5690 Pin Listing Sorted by Ball Reference VSS R18 VSS R22 VSS R25 VSS R28 VSS R4 VSS R7 VSS T11 VSS T12 VSS T14 VSS T16 VSS T18 VSS T21 VSS T23 VSS T26 VSS T3 VSS T6 VSS T8 VSS 01 VSS U11 VSS U12 VSS U13 VSS U15 VSS U17 VSS U18 VSS U22 VSS U25 VSS U28 VSS U4 VSS U7 VSS V12 VSS V13 VSS V14 VSS V15 VSS V16 VSS V17 VSS V21 VSS V23 VSS V26 VSS V3 VSS V6 VSS W1 VSS W22 VSS W25 VSS W28 VSS W4 VSS W7 VSS Y23 VSS Y26 VSS Y3 VSS Y6 VSS Y8 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 Appendix A 15 SR5690 Pin Listing Sorted by Ball Reference This page is left blank intentionally 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Appendix A 16 Proprietary Appendix Revision History Rev 2 00 Dec 2010 e First release of the public version Rev 2 10 June 2011 e Added alternate branding ASIC A21 in Section 1 5 Branding Diagrams 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 00 Proprietary Appendix B 1 This page intentionally left blank 43869 SR5690 Databook 2 00 2011 Ad
38. 8 VDDHT AE3 GPP2_TX10P AE4 VDDPCIE AES VSS AE6 GPP2_RX12N AE7 VSS AE8 GPP2 RX14N AE9 VSS AF1 GPP2 10 AF10 VSS AF 11 GPP3_TX8N AF12 VSS AF13 GPP3_TX6N AF 14 VSS AF15 GPP3_TX4N AF16 VSS AF17 GPP3_TX2N AF18 VSS AF19 GPP3_TXON AF2 GPP2_RX10P AF20 VSS AF 21 SB_TX2P AF22 VSS AF23 SB_TX1P AF24 VSS AF25 SB_RX1P AF26 VSS AF27 VDDHT AF28 VSS VDDPCIE AF4 VSS AF5 GPP2 RX11P AF6 VSS AF7 GPP2_TX13P AF8 VSS AF9 GPP2_TX15P AG10 GPP3_TX9N AG11 GPP3_TX8P AG12 GPP3_TX7N AG13 GPP3_TX6P AG14 GPP3_TX5N AG15 GPP3_TX4P AG16 GPP3_TX3N AG17 GPP3_TX2P AG18 GPP3_TX1N AG19 TXOP AG2 VDDPCIE AG20 RXON AG21 SB TX2N AG22 SB AG23 SB TX1N AG24 SB TXOP AG25 SB_RX1N AG26 SB_RXOP AG27 VSS 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 Appendix A 3 SR5690 Pin Listing Sorted by Ball Reference VSS AG4 GPP2_TX11P AGS GPP2_RX11N AG6 GPP2_TX12P AG7 GPP2_TX13N AG8 GPP2_TX14P AG9 GPP2 TX15N AH10 GPP3 TX9P AH11 VSS AH12 GPP3_TX7P AH13 VSS AH14 GPP3 TXSP AH15 VSS AH16 GPP3_TX3P AH17 VSS AH18 GPP3_TX1P AH19 VS
39. 90 Pin Listing Sorted by Ball Reference 027 TXCALN 028 TXCALP 03 VSS D4 VDDPCIE D5 VSS D6 GPP1_RX5P D7 VSS D8 GPP1_RX3P D9 VSS E1 VSS E10 GPP1_RX1N E11 GPP1_RXOP E12 VDDA18PCIE E13 VDDA18PCIE E14 PCE_TCALRN E15 LDTSTOP E16 PWM_GPIO1 pole 18 VDD18 2 GPP1 TX7N E20 VSS E21 STRP_DATA E22 VDDHTTX E23 HT_TXCAD8P E24 HT_TXCAD8N E25 VSS E26 HT_TXCADOP E27 HT_TXCADON E28 VSS E3 GPP1_TX7P E4 VSS E5 VDDPCIE E6 GPP1_RX5N E7 GPP1_RX4P E8 GPP1_RX3N E9 GPP1_RX2P F1 GPP1_TX8N F10 VSS F11 RXON F12 VDDA18PCIE F13 VDDA18PCIE F14 PCE TCALRP F15 VSS F16 PWM_GPIO3 F17 VSS F18 VSS F19 VSS F2 GPP1_TX8P F20 VSS F21 VSS F22 VDDHTTX F23 VSS F24 HT_TXCAD9P F25 TXCAD9N F26 VSS F27 HT_TXCAD1P F28 HT_TXCAD1N F3 VSS F4 GPP1_RX8N F5 GPP1 F6 VDDPCIE F7 GPP1_RX4N F8 VSS F9 1 RX2N G1 VSS G10 VDDPCIE G11 VSS G12 VDDA18PCIE G13 VDDA18PCIE G14 VDDA18PCIE G16 VSS G17 VSS G18 VSS G19 VSS G2 GPP1_TX9N G20 VSS G21 VDDA18HTPLL G22 VDDHTTX G23 HT_TXCAD10P G24 HT_TXCAD10N G25 VSS
40. AL and NON FATAL CORR 5 2 7 253 and SYNCELOODINH UM dr 2 8 2 5 4 Suggested Platform Level RAS Sideband Signal Connections sss 2 8 2 5 5 Error Reporting and ber MIR DUI RE dea IM 2 9 2 5 6 Interrupt Generation ETTO t bob Robe nescio dg oes aon el a ado eade 2 11 25 Poisoned Data Support a T ep 2 11 258 PCIeG State stude abu 2 11 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 Table of Contents 1 2 5 9 Syncflood Based ion PCIe 2 12 2 0 PCI Express D Te E 2 12 26 4 rcm 2 12 26 2 PCIe Reset Signal E 2 12 263 aR O AE A E 2 13 2 External Clock Chip prr 2 14 Chapter 3 Pin Descriptions and Strap Options 3 1 Pin Assignment VIeW iin dene esas ili 3 2 3 2 585690 Interface Block 3 4 3 3 Hyper Transport d de eed Le
41. AMD AMD SR5690 Databook Technical Reference Manual Rev 2 10 P N 43869 sr5690 ds pub 2011 Advanced Micro Devices Inc Trademarks AMD the AMD Arrow logo AMD PowerNow AMD Virtualization AMD V and combinations thereof are trademarks of Advanced Micro Devices Inc HyperTransport is a licensed trademark of the HyperTransport Technology Consortium Microsoft Windows and Windows Server are registered trademarks of Microsoft Corporation PCI Express and PCIe are registered trademarks of PCI SIG Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies Disclaimer The contents of this document are provided in connection with Advanced Micro Devices Inc AMD products AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to this document including but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD shall not be liable for any damage loss expense or claim of loss of any kind or character including without limitation direct indirect consequential exemplary punitive special incidental o
42. E12 AD12 64 GPP3_RX9P N AD11 AC11 65 PWM GPIO1 E16 67 PWM GPIO3 F16 68 PWM GPIO4 A15 69 PWM GPIO5 C16 70 PCIE RESET 1 B19 71 PCIE RESET GPIO4 E19 72 PCIE RESET GPIO5 E17 73 DFT GPIOO B26 74 DFT GPIO1 A25 75 DFT GPIO2 B24 76 DFT GPIO3 B25 77 DFT GPIO4 B23 78 GPIO5 A23 79 DBG GPIOO C22 mem m mmm 82 DBG GPIO3 A21 83 ALLOW_LDTSTOP D21 84 LDTSTOP E15 VOH VOL Test Brief Description of a VOH VOL Tree The VOH VOL logic provides signal output on I O s when test patterns are applied to the TEST ODD and TEST EVEN pins A sample of a generic VOH VOL tree is shown in the figure below 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Proprietary VOH VOL Test TEST ODD TEST EVEN VOH VOL mode Figure 7 2 Sample of a Generic VOH VOL Tree The following is the truth table for the above VOH VOL tree Table 7 4 Truth Table for the VOH VOL Tree Outputs gt Refer to Table 7 5 below for the list of pins that are on the VOH VOL tree 7 4 2 VOH VOL Tree Activation To activate the VOH VOL tree and run a VOH VOL test perform the sequence below 1 Supply a 10MHz clock to 2 CLK Test Mode Clock and a differential clock pair to the REFCLKP N REFCLKP N GPP2 REFCLKP N and GPP3 REFCLKP N pins Set POWERGOOD to 0 Set TESTMODE to 1 Set PCIE RESET GPIO2 to 0
43. JIT2 TIE at 50 interval 8 S the overall magnitude of the differential signal 9 Vp min is the amplitude of the ring back differential measurement guaranteed by design that the ring back will not cross Vp Vp max is the largest amplitude allowed 10 The difference in magnitude of two adjacent Vppc measurements is the stable post overshoot and ring back part of the signal 11 Defined as tuich teycLe 4 4 5 Reference Clock Timing Parameters Table 4 3 Timing Requirements for OSCIN Reference Clock 14 3181818MHz REFCLK Period 0 037 1 1 us 1 FIP REFCLK Frequency 0 9 27 MHz 2 TIH REFCLK High Time 2 0 5 TIL REFCLK Low Time 2 0 5 REFCLK Rise Time 1 5 5 TIF REFCLK Fall Time 1 5 5 TIJCC REFCLK Cycle to Cycle Jitter Requirement 200 ps REFCLK Peak to Peak Jitter Requirement 200 ps 1 REFCLK Long Term Jitter Requirement 1us after _ 500 ps Scope trigger Notes 1 Time intervals measured at 50 threshold point 2 FIP is the reciprocal of TIP 4 5 Power Rail Sequence For the purpose of power rail sequencing the power rails of the SR5690 are divided into groupings described in Table 4 4 below Table 4 4 Power Rail Groupings for the SR5690 VDDC VDDC 1 1V 50 52 Core power VDDPCIE VDDPCIE 1 1V S0 S2 PCI Express main IO power VDDHTTX VDDHTTX 1 2V S0 S2 HyperTransport transmit int
44. N18 N22 N25 N28 4 N7 P11 P12 P14 P16 P18 P21 P23 P26 P3 P6 P8 R1 R11 R13 R15 R17 R18 R22 25 R28 R4 R7 711 T12 T14 T16 T18 T21 T23 T26 T6 T8 U1 U11 U12 U13 U15 U17 U18 U22 025 U28 04 07 V12 V13 V14 V15 V16 V17 V21 V23 V26 V3 V6 W1 W22 W25 W28 W4 W7 Y23 26 Y3 Y6 Y8 Common Ground 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 3 9 Strapping Options 3 10 Strapping Options The SR5690 provides strapping options to define specific operating parameters The strap values are latched into internal registers after the assertion of the POWERGOOD signal to the SR5690 Table 3 10 Strap Definitions for the SR5690 shows the definitions of all the strap functions These straps are set by one of the following four methods e Allowing the internal pull up resistors to set all strap values s automatically e Attaching pull down resistors to specific strap pins listed in Table 3 10 to set their values to 07 e Downloading the strap values from an 12 serial EEPROM for debug purpose only contact your AMD FAE representative for details e Setting through an external debug port if implemented contact your AMD FAE representative for details Table 3 10 Strap Definitions for the SR5690 PRIMARY NB 5 Indicates whether the device is a primary or a secondary Northbridge on a multipl
45. P L24 HT_TXCAD13N L25 VSS L26 HT TXCADSP L27 HT_TXCADSN L28 VSS L3 GPP1 TX13P L4 VSS L5 1 RX13N L6 GPP1 RX13P L7 VSS L8 VDDPCIE M1 GPP1 TX14N M11 VSS M12 VSS M13 VDDC M14 VSS M15 VDDC M16 VSS M17 VSS M18 VSS M2 GPP1_TX14P M21 VSS M22 VDDHT M23 VSS M24 HT_TXCAD14P M25 HT_TXCAD14N M26 VSS M27 HT_TXCAD6P M28 HT_TXCAD6N M3 VSS M4 GPP1_RX14N M5 GPP1_RX14P M6 VSS M7 VDDPCIE M8 VSS N1 VSS N11 VSS N12 VDDC N13 VSS N14 VDDC N15 VSS N16 VDDC N17 VSS N18 VSS N2 GPP1_TX15N N21 VDDHT N22 VSS N23 HT_TXCAD15P N24 HT_TXCAD15N 2011 Advanced Micro Devices Inc Proprietary SR5690 Pin Listing Sorted by Ball Reference 25 vss N26 HT_TXCAD7P N27 HT_TXCAD7N N28 vss N3 GPP1_TX15P N4 vss N5 GPP1 RX15N N6 GPP1 RX15P N7 vss N8 VDDPCIE P1 GPP2 TXON VSS P12 VSS P13 VDDC P14 vss P15 VDDC P16 vss P17 VDDC P18 vss P2 GPP2 P21 vss P22 VDDHT P23 vss P24 HT_TXCTL1P P25 HT TXCTL1N P26 vss P27 HT_TXCTLOP P28 HT_TXCTLON P3 vss P4 GPP2 RXON P5 GPP2 P6 VSS P7 VDDPCIE P8 VSS R1 vss R11 VSS
46. P AH12 TX8N AF11 GPP3 TX8P AG11 GPP3 TX9N AG10 GPP3 TX9P AH10 HT REFCLKN J21 HT REFCLKP K21 RXCADON AD27 HT RXCADOP AD28 HT RXCAD10N AB24 HT RXCAD10P AB25 HT RXCAD11N AA23 HT RXCAD11P AA24 HT RXCAD12N W23 HT RXCAD12P W24 HT RXCAD13N V24 HT RXCAD13P V25 HT RXCAD14N U23 HT RXCAD14P U24 HT RXCAD15N T24 HT RXCAD15P T25 HT RXCAD1N AC26 HT RXCAD1P AC27 HT_RXCAD2N AB27 HT_RXCAD2P AB28 HT_RXCAD3N AA26 HT_RXCAD3P AA27 HT_RXCAD4N W26 HT_RXCAD4P W27 HT_RXCADSN V27 2011 Advanced Micro Devices Inc Proprietary SR5690 Pin Listing Sorted by Ball Reference HT RXCADSP V28 RXCADGN U26 RXCAD6P U27 RXCAD7N T27 RXCAD7P T28 RXCAD8N AD24 HT RXCAD8P AD25 RXCAD9N AC23 HT RXCAD9P AC24 RXCALN D24 RXCALP D25 RXCLKON Y27 HT_RXCLKOP Y28 HT_RXCLK1N Y24 HT RXCLK1P Y25 HT RXCTLON R26 HT RXCTLOP R27 RXCTL1N R23 HT RXCTL1P R24 HT TXCADON E27 TXCADOP E26 HT TXCAD10N G24 HT TXCAD10P G23 TXCAD11N H25 TXCAD11P H24 HT TXCAD12N K25 TXCAD12P K24 HT TXCAD13N L24 HT TXCAD13P L23 HT TXCAD14N M25 TXCAD14P M24 HT TXCAD15N N24 TXCAD15P N23 HT TXCAD1N F28 TXCAD1P F27 HT TXCAD2N G27 HT TXCAD2P G26
47. PCle Differential Clocks REFCLK GPP2 REFCLK and GPP3 REFCLK at 100MHz r 5 1 Table 5 3 DC Characteristics 1 8V GPIO Pads 2 1 22 211600000000000 000000000500 5 2 Table 5 4 DC Characteristics for the HyperTransport 100MHz Differential Clock 5 2 Table 5 5 SR5690 Ehennal Limits dann pda acne Atte 5 2 Table 5 6 SR5690 692 Pin Package Physical Dimensions 5 4 Table 5 7 Recommended Board Solder Reflow Profile RoHS Lead Free Solder sss 5 6 Table 6 1 ACPI States Supported by the SR5690 ee 6 1 712 Pinsionithe Lest Interta ce 7 1 Table 7 2 Example of an XOR Treesa 7 2 Table 7 3 5690 7 3 Table 7 4 Truth Table for the VOH VOL Tree 7 5 Table 7 5 SR5690 VOH VOL Tree 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary List of Tables 1 This page intentionally left blank 43869 SR5690 Databook 2 10
48. R5690 is up and ready Signal High means all power planes are valid It is not observed internally POWERGOOD l vss until it has been high for more than 6 consecutive REFCLK cycles The rising edge of this signal is deglitched SYSRESET VDD18 VSS Global Hardware Reset This signal comes from the Southbridge Miscellaneous Pins Table 3 7 Miscellaneous Pins 12C_CLK VDD18 VSS interface clock signal Can also be used as GPIO 2 DATA VDD18 VSS interface data signal Can also be used as GPIO interface data signal for external EEPROM based strap loading SIR Als ue 7 See the SR5690 Strap Document for details on the operation TESTMODE VDD18 vss When High puts the SR5690 in test mode and disables the SR5690 from operating normally Output for DFT TESTMODE or Syncflood input for triggering a HyperTransport syncflood event DFT GPIO5 Because the pin is used as a pin strap during the power on of the SYNCFLOODIN VDD18 VSS Pull Up SR5690 an external device must not drive the pin until after SYSRESET is deasserted Also the pin is not 3 3V tolerant and needs a level shifter when interfacing to a 3 3V line The pin cannot be used for general GPIO functions GPIO 4 1 lO VDD18 vss Pull Up Outputs for DFT TESTMODE These pins cannot be used for general GPIO functions Output for DFT TESTMODE or NMI input for triggering an upstream NMI pa
49. S AH20 AH21 VSS AH22 SB_TX3N AH23 VSS AH24 SB_TXON AH25 VSS AH26 SB_RXON AH3 VSS AH4 GPP2_TX11N AH5 VSS AH6 GPP2_TX12N AH7 VSS AH8 GPP2_TX14N AH9 VSS B10 GPP1_TX1N B11 GPP1 TXOP B12 VDDA18PCIE B13 VDDA18PCIE B14 VSS 43869 SR5690 Databook 2 10 Appendix A 4 PWM GPIO2 PCIE HP INT B16 PWM_GPIO6 B17 OSCIN B18 VDD18 m B2 VDDPCIE B20 CLK EE Tr 822 B23 GPIO4 B24 DFT GPIO2 B25 DFT B26 DFT_GPIOO NMI B27 VSS B3 VSS B4 GPP1_TX6N B5 GPP1_RX6P B6 GPP1_TX5N B7 GPP1_TX4P B8 GPP1_TX3N B9 GPP1_TX2P C1 VDDPCIE C10 VSS GPP1 12 VDDA18PCIE C13 VDDA18PCIE C14 VSS C15 VSS C16 PWM GPIO5 C17 VSS C18 VDD18 C19 VSS c2 VSS C20 2 C21 VSS C23 VSS C24 VDDHTTX C25 VDDHTTX C26 VDDHTTX C27 VDDHTTX C28 VDDHTTX C3 VDDPCIE C4 VSS C5 GPP1 RX6N C6 VSS B GPP1_TX4N C8 VSS C9 GPP1_TX2N D1 GPP1_RX7N D10 GPP1 RX1P 011 VSS D12 VDDA18PCIE D13 VDDA18PCIE D14 VSS D15 SYSRESET D16 VSS D18 VDD18 Bs PEE RESET LORI D2 GPP1 RX7P D20 VSS T ALLOW LDTSTO D22 VDDHTTX D23 VDDHTTX D24 HT RXCALN D25 HT RXCALP D26 VSS 2011 Advanced Micro Devices Inc Proprietary SR56
50. SR5690 Internal Blocks and 2 1 Figure 2 2 HyperTransport Interface Block Diagram 2 2 Figure 2 3 SR5690 HyperTransport M Interface Signals nir eibAn p RUE ERE RER DAS 2 3 Figure 2 4 Interrupt Routing Pathsim Legacy Mode SERA IRE A ARRA AE MAREM 2 6 Figure 2 5 Interrupt Routing Paths in Legacy Mode with Integrated IOAPIC sese 2 6 Figure 2 6 Interrupt Routing Path in MSI Mode 2 7 Figure 2 7 Suggested Platform Level RAS Sideband Signal Connections 2 9 Figtite 2 8 Hot plug Interface Connections pta bin uM DA a IS Mr QU Ape APA RM EO E IE Rea MEER 2 13 Figure 2 9 Hot plug Signals between PCIe amp Slot and Expander 2 14 Figure 3 1 SR5690 Interface Block Diagram 3 4 Figure 4 1 SR5690 Power Rail Power Up Sequence PRIN AE AT ORS 4 3 Figure 5 2 SR5690 692 Pin FCBGA Package Outline 5 4 Figure 5 3 585690 Ball Arrangement Bottom View 5 5 Figure 5 4 RoHS Lead Free Solder SAC305 405 Tin Silver Copper Reflow Profile 5 7 7 1 XOR Wee A 7 2 Figure 7 2 Sampleot a Generic VOH VOL Tree
51. T GPIO 5 1 Management Interface OSCIN HT REFCLKP HT REFCLKN Clock Interface GPP3 REFCLKP GPP3 REFCLKN GPP1 REFCLKP GPP1 REFCLKN GPP2 REFCLKP GPP2 REFCLKN Misc Signals VDD18 VDDPCIE VDDA18PCIE VDDC VDDHT VDDHTTX VDDA18HTPLL Grounds Figure 3 1 SR5690 Interface Block Diagram 3 3 CPU HyperTransport Interface Table 3 1 HyperTransport Interface HT RXCAD 15 0 P HT RXCADI 15 0 N VDDHT VSS Receiver Command Address and Data Differential Pairs HT RXCLK 1 0 P VDDHT vss Receiver Clock Signal Differential Pair Forwarded clock signal Each byte of HT RXCLK 1 0 N RXCAD uses a separate clock signal Data is transferred on each clock edge RXCTL 1 0 P VDDHT vss Receiver Control Differential Pair The pair is for distinguishing control packets HT_RXCTL 1 0 N from data packets Each byte of RXCAD uses a separate control signal PIE 15 0 VDDHT VSS Transmitter Command Address and Data Differential Pairs HT TXCAD 15 0 N 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Proprietary PCI ExpressQ Interfaces Table 3 1 HyperTransport Interface Continued TXCLK 1 0 P Transmitter Clock Signal Differential Pair Forwarded clock signal Each byte TXCLK VDDHT VSS 2 uses a separate clock signal Data is transferred on each clock HT TXCTL 1 0 P T
52. VDDC 1 1V VDDC ramps together with or after VDDHTTX See Note 1 and 2 Notes 1 Power rail A ramps after power rail B means that the voltage of rail A does not exceed that of rail B at any time 2 Power rail A ramps together with power rail B means that the two rails are controlled by the same enable signal and the difference in their ramping rates is only due to the differences in the loadings 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 4 3 Power Rail Sequence 4 5 2 Power Down For power down the rails should either be turned off simultaneously or in the reversed order of the power up sequence Variations in speeds of decay due to different capacitor discharge rates can be safely ignored 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 4 4 Proprietary Chapter 5 Electrical Characteristics and Physical Data 5 1 5 1 1 5 1 2 Electrical Characteristics Maximum and Minimum Ratings Table 5 1 Power Rail Maximum and Minimum Voltage Ratings VDDC 1 1 1 067 1 133 1 045 1 155 V Core power VDD18 1 8 1 746 1 854 1 71 1 89 V 1 8V I O Powers VDDPCIE 1 1 1 067 1 133 1 045 1 155 PCI Express Interface I O Power VDDA18PCIE 18 1 746 4 854 171 4 89 PCI Express interface 1 8V and PLL power TM VDDHT 1 1 1 067 1 133 1 045 1 155 HyperTransport Interface digital power VDDHTTX 12 1 164 1 236 114 1 26 H
53. abook 2 10 7 2 2011 Advanced Micro Devices Inc Proprietary XOR Tree 7 3 4 Tree for the SR5690 The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO Pin Refer to Table 7 3 for the list of the signals included on the XOR tree There is no specific order to these signals in the tree A toggle of any of these balls in the XOR tree will cause the output to toggle When the XOR tree is activated any pin on the XOR tree must be either pulled down or pulled up to the I O voltage of the pin Only pins that are not on the XOR tree can be left floating When differential signal pairs are listed as single entries on the XOR tree opposite input values should be applied to the two signals in each pair e g for entry no on the tree when 1 is applied to HT RXCADOP 0 should be applied to HT RXCADON Table 7 3 SR5690 XOR Tree Pin Name 1 HT RXCADOP N AD28 AD27 2 HT RXCAD1P N AC2TIAC26 3 HT RXCAD2P N AB28 AB27 4 HT 27 26 5 RXCADAP N W27 W26 6 HT V28 V27 7 HT_RXCAD6P N U27 U26 8 HT RXCAD7P N T28 T27 9 HT RXCTLOP N R27 R26 10 HT RXCAD8P N AD25 AD24 11 HT RXCAD9P N AC24 AC23 12 HT RXCAD10P N AB25 AB24 13 HT RXCAD11P N AA24 AA23 14 HT_RXCAD
54. ard in order to allow board level testing of neighboring devices e An TREE test mode on all the digital I O s to allow for proper soldering verification at the board level VOH VOL test mode on all digital I O s to allow for proper verification of output high and output low voltages at the board level These test modes can be accessed through the settings on the instruction register of the JTAG circuitry 7 2 Test Interface Table 7 1 Pins on the Test Interface TESTMODE A19 TEST EN Test Enable IEEE 1149 1 test port reset PCIE RESET D19 TMS Test Mode Select IEEE 1149 1 test mode select 2 DATA C20 TDI Test Mode Data In IEEE 1149 1 data in 2 820 TCLK Test Mode Clock IEEE 1149 1 clock PWM 6 B16 TDO Test Mode Data Out IEEE 1149 1 data out PWM GPIO4 A15 TEST ODD Control ODD output in VOH VOL test PWM F16 TEST EVEN Control EVEN output VOH VOL test POWERGOOD A17 Reset 73 Tree 7 3 1 Brief Description of an XOR Tree A sample of a generic tree is shown in the figure below 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 7 1 Tree XOR Start Signal Figure 7 1 XOR Tree Pin A is assigned to the output direction and pins B through F are assigned to the input direction It can be seen that after all pins B to F are assigned to l
55. ary VOH VOL Test 59 SB TX2P N AF21 AG21 Even 60 SB TX3P N AG22 AH22 Odd 61 GPP3 TX6P N AG13 AF13 Even 62 GPP3 TX7P N AH12 AG12 Odd 63 GPP3 TX8P N AG11 AF 11 Even 64 GPP3 TX9P N AH10 AG10 Odd 65 PWM GPIO1 E16 Even 66 B15 Odd 67 PWM GPIO5 C16 Even 68 PCIE RESET 1 B19 Odd 69 PCIE RESET GPIO4 E19 Even 70 PCIE RESET GPIO5 E17 Odd 71 DFT GPIOO B26 Even 72 DFT GPIO1 A25 Odd 73 DFT GPIO2 B24 Even 74 DFT GPIO3 B25 Odd 75 DFT GPIO4 B23 Even 76 GPIO5 A23 Odd 77 DBG GPIOO C22 Even 8 a i odi 79 S SDA GEM B21 Even 80 DBG GPIO3 A21 Odd 81 ALLOW LDTSTOP D21 Even 82 LDTSTOP E15 Odd 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 7 7 VOH VOL Test This page intentionally left blank 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 7 8 Proprietary Appendix Pin Listings This appendix contains pin listings for the SR5690 sorted in different ways To go to the listing of interest use the linked cross references below SR5690 Pin Listing Sorted by Ball Reference on page A 2 SR5690 Pin Listing Sorted by Pin Name on page A 9 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary Appendix A 1 585690 Pin Listing Sorted by Ball Reference 5 5690 Pin Lis
56. ck generator on the 1 REFCLKN YEDATSPEIE 7 motherboard when the General Purpose 1 link is used and can be left unconnected if the link is not used General Purpose 2 Clock Differential Pair The pair is GPP2 REFCLKP connected to an external clock generator on the GPP2 REFCLKN VSS motherboard when the General Purpose 2 link is used and can be left unconnected if the link is not used General Purpose 3 Clock Differential Pair The pair has to GPP3 REFCLKP be connected to an external clock generator on the REFCLKN MERRIER VSSE EIE motherboard whether the General Purpose 3 link is used or not 14 318MHz Reference clock input from the external clock OSCIN VDD18 VSS Disabled chip 1 8 volt signaling 2011 Advanced Micro Devices Inc Proprietary Power Management Pins 3 6 3 7 Power Management Pins Table 3 6 Power Management Pins ALLOW_LDTSTOP OD VDD18 VSS Allow LDTSTOP This signal is used by the SR5690 to communicate with the Southbridge and tell it when it can assert the LDTSTOP signal 1 LDTSTOP can be asserted 0 LDTSTOP has to be de asserted LDTSTOP VDD18 VSS HyperTransport Stop This signal is generated by the Southbridge and is used to determine when the HyperTransport link should be disconnected and go into a low power state It is a single ended signal Input from the motherboard signifying that the power to the S
57. cket to the processor complex Because the pin is used as a pin strap during the power on of the DFT_GPIOO NMI VDD18 VSS Pull Up SR5690 an external device must not drive the pin until after SYSRESET is deasserted Also the pin is not 3 3V tolerant and needs a level shifter when interfacing to a 3 3V line The pin cannot be used for general GPIO functions Output for Debug Bus or Non Fatal or Correctable Error signal to BMC The pin is not 3 3V tolerant and needs a level shifter when NON FATAL CORR VDD18 VSS Pull Up interfacing to a 3 3V line When used as a debug bus output the pins NON_FATAL_CORRz function is overridden The pin cannot be used for general GPIO functions DBG_GPIO2 Output for Debug Bus or data for PCle hot plug The pin PCIE HP SDA NERIS MES cannot be used for general GPIO functions GPIO1 Output for Debug Bus or clock for PCle hot plug The pin HP SCL Me ns PUN Up cannot be used for general GPIO functions 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 3 7 Power Pins Table 3 7 Miscellaneous Pins Output for Debug Bus or System Error or Fatal Error signal to BMC The pin is not 3 3V tolerant and needs a level shifter when VO VDD18 VSS Pull Up interfacing to a 3 3V line When used as a debug bus output the pin s SERR_FATAL function is overridden The pin cannot be us
58. ds Vin pc Input High Voltage 1 1 E V 1 Input Low Voltage z 0 7 V 1 Minimum Output High Voltage 1 4 V 2 3 VoL Maximum Output Low Voltage 8 0 4 V 2 3 lot Minimum Output Low Current V 0 1V 2 0 2 3 lou Minimum Output High Current V VDDR 0 1V 2 0 mA 2 3 Notes 1 Measured with edge rate of 1us at PAD pin 2 For detailed current voltage characteristics please refer to IBIS model 3 Measurement taken with SP SN set to default values PVT Noml Case Table 5 4 DC Characteristics for the HyperTransport 100MHz Differential Clock HT REFCLK Vit Input Low Voltage 0 2V Input High Voltage 1 4V 1 8V Vimax Maximum Input Voltage 2 1V 5 2 SR5690 Thermal Characteristics This section describes some key thermal parameters of the SR5690 For a detailed discussion on these parameters and other thermal design descriptions including package level thermal data and analysis please consult the Thermal Design and Analysis Guidelines for SR5650 5670 5690 order 44382 5 2 1 SR5690 Thermal Limits Table 5 5 SR5690 Thermal Limits 43869 SR5690 Databook 2 10 Operating Case Temperature 0 95 C 1 22 Junction u 415 2 Storage Temperature 40 60 Ambient Temperature 0 55 Thermal Design Power 18 Notes 1 The maximum operating case temperature is the d
59. e Northbridge ml AMD Logo YYWW Date Code MADE IN TAIWAN Country of Origin WXXXXX 4 Wafer Lot Number 215 0716056 4 Part Number YY Assembly Start Year WW Assembly Start Week Note Branding can be in laser ink or mixed laser and ink marking Figure 1 3 SR5690 Alternate Branding for A21 Production ASIC Lead Free Part 1 6 Conventions and Notations The following sections explain the conventions used throughout this manual 1 6 1 Pin Names Pins are identified by their pin names or ball references active low signals are identified by the suffix in their names e g SYSRESET 1 6 2 Pin Types The pins are assigned different codes according to their operational characteristics These codes are listed in Table 1 2 Table 1 2 Pin Type Codes Digital Input Digital Output Bi Directional Digital Input or Output M Multifunctional Pwr Power Gnd Ground A O Analog Output Analog Input Analog Bi Directional Input Output A Pwr Analog Power A Gnd Analog Ground Other Pin types not included in any of the categories above 1 6 3 Numeric Representation Hexadecimal numbers are appended with h whenever there is a risk of ambiguity Other numbers are in decimal Pins of identical functions but different trailing digits e g GPIOO GPIOI DFT GPIO5 are referred to collectively by specifying their digits in square brac
60. e Northbridge platform See section 2 3 Multiple Northbridge Support on page 2 4 for details Do not install a resistor for sinlge Northbridge platforms 0 Device is a secondary Northbridge 1 Device is the primary Northbridge Default Reserved PWM 4 Reserved Make provision for an external pull down resistor on this pin but do not install a resistor Reserved PWM GPIO2 Reserved Make provision for an external pull down resistor on this pin but do not install PCIE HP INT L a resistor Reserved DFT_GPIOO NMI Reserved Make provision for an external pull down resistor on this pin but not install a resistor LOAD ROM STRAPS DFT GPIO1 Selects loading of strap values from EEPROM 0 master can load strap values from EEPROM if connected or use hardware default values if not connected 1 Use hardware default values Default STRAP PCIE GPP CFG GPIO 4 2 General Purpose Link 3 Configuration See Table 3 11 below for details Reserved DFT GPIO5 Reserved Make provision for an external pull down resistor on this pin but do not install SYNCFLOODIN resistor Table 3 11 Strap Definition for STRAP_PCIE_GPP_CFG 1 Default 1 1 0 Hardware default Mode L or EEPROM strap values 1 0 1 x2 x2 x2 x4 C2 1 0 0 x2 x2 x1 x1 x4 K 0 1 1 x2 x1 x1 x1 x1 x4 E 0 1 0 x1 x1 x1 x1 x1 x1 x4 L 0 1 4 1 1 4 0 0 4 x2 x4 B
61. ed for general GPIO functions DBG_GPIO0 SERR_FATAL THERMALDIODE_P _ Diode connections to external SM Bus microcontroller for THERMALDIODE N monitoring IC thermal characteristics GPIOs GPIO6 PWM GPIO 4 3 are also parts of the test interface see section 7 2 Test Interface on page 7 GPIO 6 3 1 in VEDI M 1 PWM GPIO5 is also used as a strap see section 3 10 Strapping Options on page 3 10 PWM GPIO2 GPIO or interrupt for PCle hot plug The pin is also used as a PCIE HP INT L VDD18 VSS strap pin see section 3 10 Strapping Options on page 3 10 3 8 Power Pins Table 3 8 Power Pins L14 L16 M13 M15 N12 N14 N16 P13 P15 P17 R12 R14 R16 T13 T15 T17 U14 U16 VDD18 1 8V 5 A18 B18 C18 018 E18 Power for GPIO pads B2 C1 04 5 F6 G8 G10 H7 H9 H11 7 L8 M7 P7 T7 V7 W8 Y7 AA10 AA12 16 18 ABQ AB11 AB13 AB15 AB17 AB19 AC6 ADS 4 AG2 A12 A1 B12 B13 C12 C13 D12 D13 E12 E13 VDDA18PCIE 1 8V 21 F12 F13 G12 G13 G14 Express interface 1 8V I O power H12 H13 H14 L11 V11 V18 AA22 22 AC22 K22 AD23 AE24 AE25 AE26 VDDHT 1 1V 21 AE27 AE28 AF27 L21 HyperTransport Interface digital 1 power M22 N21 P22 R21 T22 U21 V22 W21 Y22 C24 C25 C26 C27 C28 VDDC 1 1V 18
62. erface power HT 1 1V VDDHT 1 1V 50 52 HyperTransport interface digital IO power 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Proprietary Power Rail Sequence AMD Table 4 4 Power Rail Groupings for the SR5690 1 8V VDD18 1 8V 50 52 power for GPIO pads VDDA18PCIE 1 8V S0 S2 PCI Express interface 1 8V IO and PLL power VDDA18HTPLL 1 8V S0 S2 HyperTransport interface 1 8V PLL power Note 1 Power rails from the same group are assumed to be generated by the same voltage regulator 2 Power rails from different groups but at the same voltage can either be generated by separate regulators or by the same regulators as long as they comply with the requirements specified in the SR5690 Motherboard Design Guide 4 5 1 Power Up Figure 4 1 below illustrates the power up sequencing for the various power groups and Table 4 5 explains the symbols in the figure as well as the associated requirements 1 8V T10 VDDHTTX VDDPCIE N 1 1V VDDC Figure 4 1 SR5690 Power Rail Power Up Sequence Table 4 5 SR5690 Power Power up Sequence T10 1 8V rails to VDDHTTX 1 2V VDDHTTX ramps after 1 8V rails See Note 1 T11 VDDHTTX 1 2V to VDDPCIE 1 1V VDDPCIE ramps together with or after VDDHTTX See Note 1 and 2 T12 VDDHTTX 1 2V to HT 1 1V rails 1 1V rails ramp together with or after VDDHTTX See Note 1 and 2 T13 VDDHTTX 1 2V to
63. error interrupts may be optionally redirected to an MSI generation block underneath the SB IOMMU LI so that they can be remapped by internal MSI interrupts are never remapped The PCI configuration spaces of each on board device contains a fixed HT MSI mapping capability except for Device 1 which is unused This implies that all MSI interrupts with address OxFEEx_xxxx have to be converted to HT interrupts Because of this software is required to program all MSI address registers with an address 2 4 5 Internally Generated Interrupts The SR5690 may internally generate interrupts for the following purposes e PCI Express error e PCI Express PME e error e Internal parity error e OMMU command handler e JOMMU event logger Internally generated interrupts may be in either legacy INTx or MSI format Internal MSI interrupt sources do not support per vector masking 2 46 IOMMU Interrupt Remapping When the IOMMU 15 enabled interrupts generated downstream of the IOMMU are remapped based upon the IOMMU tables The following classes of interrupts are not remapped by the IOMMU because they are generated upstream of the IOMMU e error optional e Internal parity error optional e IOMMU command handler and event logger 2 47 Interrupt Routing Architecture 2 4 7 1 Legacy Mode Primary SR5690 Legacy INTx messages are routed directly to the SB IOAPIC The SB IOAPIC generates upstream interrupt
64. errors for which signalling by FATAL is enabled Fatal errors are identified via the fatal error status bits 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 2 7 RAS Features Non fatal or correctable errors may be likewise signalled via GPIO3 NON FATAL The SERR FATAL and NON FATAL CORR pin functionalities are disabled on warm reset 2 5 3 NMI and SYNCFLOODIN The SR5690 may configure the DFT_GPIO0 NMI pin as an input pin for triggering an upstream NMI packet to the processor complex The pin should be driven by a BMC An internal sticky status bit records the use of the NMI pin Also SR5690 may configure GPIOS SYNCFLOODIN pin as an input pin for triggering a HyperTransport syncflood event The pin should driven by a BMC An internal sticky status bit records the use of the SY NCFLOODIN pin 2 5 4 Suggested Platform Level RAS Sideband Signal Connections Figure 2 7 is a logical diagram showing suggestions for RAS sideband signal connections at the platform level 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 2 8 Proprietary RAS Features DBG_GPIO0 SERR_FATAL Separate connections to debug pins and GPIO expander for each SR5690 in the system SCL SDA DBG GPIO3 NON FATAL CORR DFT GPIO5 A SYNCFLOODIN GPIOO NMI NMI only needs to be connected on
65. he HyperTransport link into the syncflood state when a fatal or non fatal error is received on the PCIe interface This is done in order to help stop data movement within the system 2 6 PCI Express 2 6 1 PCIe Ports In total there are 12 ports on the SR5690 divided into 5 groups and implemented in hardware as 5 separate cores e 2 general purpose ports 16 lanes in total Width of each port is x8 In the default configuration the 2 ports are combined to provide a 1 x16 port e PCIE GPP2 2 general purpose ports 16 lanes in total Width of each port is x8 In the default configuration the 2 ports are combined to provide a 1 x16 port e PCIE GPP3a 6 general purpose ports with 6 lanes in total They support 6 different configurations with respect to link widths 4 2 4 1 1 2 2 2 2 2 1 1 2 1 1 1 1 and 1 1 1 1 1 1 default configuration e PCIE GPP3b 1 general purpose port with 4 lanes in total Width of the port is x4 For details on the possible configurations for the GPP3 lanes see Table 2 4 below and Table 3 11 Strap Definition for STRAP PCIE GPP on page 3 10 Table 2 4 Possible Configurations for the PCI Express General Purpose Links GPP3 lane 0 x1 x2 x2 x2 gt GPP3 lane 1 x1 x4 x4 GPP3 lane 2 x1 x1 GPP3a x2 x2 gt GPP3 lane 3 x1 x1 GPP3 lane 4 x1 x1 x1 x1 x2 x2 GPP3 lane 5 x1 x1 x1 x1 GPP3 lane 6 GPP3 lane 7 GPP3b x4 x
66. ie top center temperature measured via a thermocouple based on the methodology given in the document Thermal Design and Analysis Guidelines for SR5650 5670 5690 Chapter 12 This is the temperature at which the functionality of the chip is qualified 2 The maximum absolute rated junction temperature is the junction temperature at which the device can operate without causing damage to the ASIC 3 The ambient temperature is defined as the temperature of the local intake air at the inlet to the thermal management device The maximum ambient temperature is dependent on the heat sink design and the value given here is based on AMD s reference heat sink solution for the SR5690 Refer to Chapter 6 in Thermal Design and Analysis Guidelines for SR5650 5670 5690 for heatsink and thermal design guidelines Refer to Chapter 7 for details of ambient conditions 4 Thermal Design Power TDP is defined as the highest power dissipated while running currently available worst case applications at nominal voltages The core voltage was raised to 596 above its nominal value for measuring the ASIC power Since the core power of modern ASICs using 65nm and smaller process technology can vary significantly parts specifically screened for higher core power were used for TDP measurement The TDP is intended only as a design reference and the value given here is preliminary 2011 Advanced Micro Devices Inc Proprietary SR5690 Thermal Characteristics AMD
67. in any on board memory is 4 All macros contain test circuitry for software to generate false errors on either the read or write side of the memory for verification of error handling routines Error injection circuitry only corrupts parity bits rather than real data bits to avoid data corruption Parity Protection for IOMMU Cache Memories All IOMMU cache memories are parity protected When a parity error is detected the access from the associated bank is marked as an automatic miss The cache line is marked as invalid and may later be overwritten with data from system memory which is ECC protected The error is logged in a status bit and an optional interrupt is generated either fatal non fatal or correctable parity error Parity Protection for Normal Memories normal memories are also parity protected When a parity error is detected the failure is likely to be fatal as there 15 no automatic recovery mechanism and no way for hardware to tag a specific request or operation with the error The error is logged in a status bit for later diagnosis and an optional interrupt is generated either fatal or non fatal parity error SERR_FATAL and NON FATAL CORR Pins The SR5690 implements a dedicated pin GPIOO SERR FATALZ to signal either a system or a fatal error which can be used to signal a BMC for further actions SERR FATAL may be asserted on various error conditions like HT syncflood as well as internal parity errors or fatal
68. istics and Physical Data Electrical CharacteristiC S obesse OUR PUE rb ac rads eee DN den 5 1 Skk Maximum and Minimum RAE ADM PA ME 5 1 5 1 2 9 5 UEM EROR IN DM 5 1 5 2 85690 Thermal 1 0 0 0202 020 0 0 20 00000000000 5 2 5 2 1 SR5690 Thermal OPE bump 5 2 522 Thermal Diode Characteristics 5 3 5 3 5 4 5 3 acu dot oL 5 5 5 3 2 Board Solder Reflow Process Recommendations 2 1 2 1 2 22 02 20 00 001000000002 5 6 Chapter 6 Power Management and ACPI 6 1 ACPI Power Management Implementation 6 1 Chapter 7 Testability T I Test Capability Beatutes alec Gone a lab nas 7 1 7 2 Test Interface EE T ARA 7 1 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Table of Contents 2 Proprietary 13 OI MEC RP TES 7 1 131 Brief Description of an Tree
69. it JTAG Joint Test Access Group An IEEE standard MB Mega Byte NB Northbridge PCI Peripheral Component Interface PCIe PCI Express PLL Phase Locked Loop POST Power On Self Test PD Pull down Resistor PU Pull up Resistor RAS Reliability Availability and Serviceability SB Southbridge TBA To Be Added VRM Voltage Regulation Module 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 1 5 Conventions and Notations This page is left blank intentionally 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 1 6 Proprietary Chapter 2 Functional Descriptions This chapter describes the functional operation of the major interfaces of the SR5690 system logic chip Figure 2 1 illustrates the SR5690 internal blocks and interfaces 5 HyperTransport 3 CPU 194 4 0 8 gt ATL Southbridge lt 54 v Expansion Uy Slots 20 22 Root 9 m 4 8 30 Complex c z 0 gt 55 0 E Expansion 9 4 Slots e 4 2 gt _ o 4 gt 20 4 Expansion 3 go E Slots 4 223 0 gt s Register Interface Figure 2 1 SR5690 Internal Blocks and Interfaces 2 1 HyperTransport Interface 2 1 1 Overview The SR569
70. kets and with colons 1 e GPIO 5 0 A similar short hand 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 1 4 Proprietary Conventions and Notations notation is used to indicate bit occupation in a register For example COMMAND 15 10 refers to the bit positions 10 through 15 ofthe NB COMMAND register 1 6 44 Hyperlinks Phrases or sentences in blue italic font are hyperlinks to other parts of the manual Users of the PDF version of this manual can click on the links to go directly to the referenced sections tables or figures 1 6 5 Acronyms and Abbreviations The following is a list of the acronyms and abbreviations used in this manual Table 1 3 Acronyms and Abbreviations ACPI Advanced Configuration and Power Interface ASPM Active State Power Management A Link E A Link Express interface between the Northbridge and Southbridge BGA Ball Grid Array BIOS Basic Input Output System Initialization code stored in a ROM or Flash RAM used to start up a System or expansion card BIST Built In Self Test DBI Dynamic Bus Inversion DPM Defects per Million EPROM Erasable Programmable Read Only Memory FCBGA Flip Chip Ball Grid Array FIFO First In First Out VSS Ground GPIO General Purpose Input Output HT HyperTransport interface IDDQ Direct Drain Quiescent Current IOMMU Input Output Memory Management Un
71. lity Features The SR5690 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM Defect Per Million ratio e Full scan implementation on the digital core logic which provides about 97 fault coverage through ATPG Automatic Test Pattern Generation Vectors e Dedicated test logic for the on chip custom memory macros to provide complete coverage on these modules e AJTAG test mode in order to allow board level testing of neighboring devices e tree test mode on all the digital I O s to allow for proper soldering verification at the board level e Access to the analog modules and PLLs in the SR5690 in order to allow full evaluation and characterization of these modules e DDQ mode support to allow chip evaluation through current leakage measurements e Highly advanced signal observability through the debug port These test modes can be accessed through the settings of the instruction register of the JTAG circuitry 1 2 9 Packaging e Single chip solution in 65nm 1 1 V CMOS technology e chip design in a 29mm x 29mm 692 FCBGA package 1 3 Software Features e Supports Windows Server 2003 Windows Server 2008 Red Hat Enterprise Linux SUSE Linux and Solaris e Supports corporate manageability requirements such as DMI e ACPI support e Full write combining support for maximum performance e Comprehensive OS API support e Extensive Power Management support 43869 SR5690 Databook 2 10
72. ll Pads on PCB 5 3 2 2 5 6 Warpage of the PCB and the package may cause solderjoint quality issues at the surface mount Therefore it is recommended that the stencil opening sizes be adjusted to compensate for the warpage The recommendation is for the stencil aperture of the solderballs to be kept at the same size as the pads Reflow Profile A reference reflow profile is given below Please note the following when using RoHS lead free solder SAC 105 305 405 Tin Silver Cu The final reflow temperature profile will depend on the type of solder paste and chemistry of flux used in the SMT process Modifications to the reference reflow profile may be required in order to accommodate the requirements of the other components in the application An oven with 10 heating zones or above is recommended To ensure that the reflow profile meets the target specification on both sides of the board a different profile and oven recipe for the first and second reflow may be required Mechanical stiffening can be used to minimize board warpage during reflow It is suggested to decrease temperature cooling rate to minimize board warpage This reflow profile applies only to RoHS lead free high temperature soldering process and it should not be used for Eutectic solder packages Damage may result if this condition is violated Maximum 3 reflows are allowed on the same part Table 5 7 Recommended Board Solder Reflow Profile RoHS Lead Free Solder
73. mber based upon the bridge device number The second stage is register controllable on a per bridge basis and maps the rotated INT A B C D onto INT E F G H INT A to H messages sent to the Southbridge are mapped onto the SB IOAPIC interrupt redirection table entries 16 to 23 Non SB IOAPIC Support The SR5690 supports routing legacy IOAPIC memory mapped I O addresses OXFECx to any PCI Express port to support endpoint devices with integrated IOAPIC 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 2 4 Proprietary Interrupt Handling 2 4 3 Integrated IOAPIC Support The SR5690 supports routing local INTx messages to its integrated IOAPIC The integrated IOAPIC contains a 32 entry redirection table INTx messages from endpoint devices bridges HTIU and IOMMU can be mapped onto different redirection entries under register control 2 44 MSI Interrupt Handling and MSI to HT Interrupt Conversion In MSI interrupt mode all interrupts are sent directly from the endpoint devices through the SR5690 up to the processor complex All MSI interrupts are converted into HT formatted interrupts For MSIs from PCI Express endpoint devices and internally generated PCI Express interrupts the conversion occurs in the associated IOMMU LI block For interrupts and optionally HT error interrupts and internal parity error interrupts the conversion occurs in the HTIU block HT error interrupts and internal parity
74. n Calibration for Rx and Tx Channels on Bottom Side PCE TCALRN VDDA18PCIE VSSA PCIE N Channel Driver Compensation Calibration for Rx and Tx Channels Top Side PCE TCALRP VDDA18PCIE VSSA PCIE P Channel Driver Compensation Calibration for Rx and Tx Channels on Top Side PCE RCALRN VDDA18PCIE VSSA PCIE N Channel Driver Compensation Calibration for Rx and Tx Channels on Right Side PCE RCALRP VDDA18PCIE VSSA PCIE P Channel Driver Compensation Calibration for Rx and Tx Channels on Right Side PCIE RESET PCIe Resets Except for PCIE RESET GPIOS they can also be 101511 VDDA18PCIE VSS used as GPIOs There are internal pull downs of 1 7 on these pins DBG GPIO2 VDD18 vss data for PCle hot plug or Output for Debug Bus The pin PCIE_HP_SDA cannot be used for general GPIO functions 2 DBG GPIO1 VDD18 vss I C clock for PCle hot plug or Output for Debug Bus The pin cannot PCIE HP SCL be used for general GPIO functions PWM GPIO2 interrupt for PCle hot plug or GPIO The pin is also used as a VDD18 VSS strap pin see section 3 10 Strapping Options on page 3 PCIE HP INT 10 Clock Interface Table 3 5 Clock Interface HT REFCLKP HyperTransport 100 MHz Clock Differential Pair from HT REFCLKN VEBASSHIPEK VSISACHIT Disabled external clock source General Purpose 1 Clock Differential Pair The pair is GPP1 REFCLKP connected to an external clo
75. nsport Internal Parity Error Reporting One register bit per memory macro is used to log parity errors Values for those bits are persistent across a warm reset for diagnostic purposes Interrupt Generation on Errors Internal interrupts may be generated on the following error conditions e PCI Express errors fatal non fatal or correctable e errors fatal or non fatal e OMMU events e Internal parity error fatal or non fatal e Internal parity error in the IOMMU cache fatal non fatal or correctable Poisoned Data Support The SR5690 supports the propagation of poisoned data attributes EP in PCIe and Data Error in HT between PCI Express endpoints and the processor for both host and DMA requests or responses The SR5690 cannot actively mark a transaction with a poisoned data attribute even if the transaction encounters an internal parity error Received packets containing ECRC errors are not marked as poisoned PCIe Link Disable State The SR5690 has the ability to put PCIe links into the disabled state as an error response in order to help stop data movement within the system Links which received fatal errors may be disabled Also a HyperTransport syncflood event may be used to trigger all links to enter the disabled state 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 2 11 PCI Express amp 2 5 9 Syncflood Based on PCIe Error The SR5690 has the ability to put t
76. o cache address translation These features enhance memory protection and support hardware based I O virtualization when combined with appropriate operating system or hypervisor software Combined with AMD VirtualizationTM AMD VTM technology these features are designed to provide comprehensive platform level virtualization support SR5690 Features CPU Interface e Supports 16 bit up down HyperTransport HT 3 0 interface up to 5 2 GT s e Supports 200 400 600 800 and 1000 MHz frequencies e Supports 1200 1400 1600 1800 2000 2200 2400 and 2600 MHz HT3 frequencies up to 2400 MHz only for the 980 e Supports Shanghai and subsequent series of AMD server workstation and desktop processors through sockets G34 and C32 e Supports LDTSTOP interface and CPU throttling PCI Express Interface e Supports PCIe Gen 2 version 2 0 e Optimized peer to peer and general purpose link performance e Supports 42 PCIe Gen 2 general purpose lanes and up to 11 devices on specific ports possible configurations are described in Section 2 6 PCI Express e Supports a revision 1 26 compliant IOMMU Input Output Memory Management Unit implementation for address translation and protection services Please refer to the AMD Virtualization Technology IOMMU Specification for more details e Supports PCIe hot plug function for up to eight slots firmware support required A Link Express II Inte
77. od d 3 4 3 5 341 PCI Express Interface for General Purpose External Devices 23 5 3 4 2 A Link Express II Interface to Southbridge sse 3 5 343 Miscellaneous PCI Express Signals 3 6 lock Interlace T TEL 3 6 3 6 Power Management Pits iussu ibi vu AF Fc BEER 3 7 321 MiscellancOus III HH 3 7 3 8 Power PINS me rm IET 3 8 3 9 Ground MN dd lud i di CMM Aa 3 9 3 10 Strapping ODpLGOFSa DRM ER AE RD 3 10 Chapter 4 Timing Specifications 4 1 Hyper Transport Bus PITE baeo iata teet Raab bp del rap cate led 4 1 4 2 PCI Express Differential Clock AC 4 1 4 3 HyperTransport Reference Clock Timing Parameters 4 4 OSCIN Reference Clock Timing Parameters 4 2 45 Power Rail 4 2 a Min slc e UN 4 3 5 2 Power iei oret pp eei dide esd Oia pM tp Mid 4 4 Chapter 5 Electrical Character
78. ogic 0 or 1 a logic change in any one of these pins will toggle the output pin The following is the truth table for the XOR tree shown in Figure 7 1 The XOR start signal is assumed to be logic 1 Table 7 2 Example of an XOR Tree 1 0 2 1 3 1 4 1 5 1 6 1 7 1 alalAslAlololo gt 7 3 2 Description of the XOR Tree for SR5690 The XOR start signal 15 applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree 15 obtained at the TDO Pin Refer to Section 7 3 4 for the list of the signals included on the XOR tree There is no specific order to these signals in the tree A toggle of any of these balls in the XOR tree will cause the output to toggle 7 3 3 XOR Tree Activation To activate the XOR tree and run a XOR test perform the sequence below 1 Supply a 10MHz clock to 2 CLK Test Mode Clock and a differential clock pair to the REFCLKP N REFCLKP N GPP2 REFCLKP N and GPP3 REFCLKP N pins Set POWERGOOD to 0 Set TESTMODE to 1 Set PCIE RESET GPIO2 to 0 Wait 5 or more 2 cycles 2 3 4 5 6 Load JTAG instruction register with the instruction 0001 1111 7 Load JTAG instruction register with the instruction 0010 0000 8 Load JTAG instruction register with the instruction 0000 1000 9 Go to Run Test Idle state 10 Set POWERGOOD to 1 43869 SR5690 Dat
79. or the SR5690 TOP VIEW COMPONENT KEEP OUT AREA VIEW PIN 1 CORNER UNDERFILL 1 DIE 2 22 E 2 7 E 4 l 777 00000000000 000000000 2 900000000000 3883387 000000000 o 1 B 0000000000000 ea m N D4 A D1 _ DETAIL A DETAIL B MOD 00094 03 Figure 5 2 SR5690 692 Pin FCBGA Package Outline Table 5 6 SR5690 692 Pin FCBGA Package Physical Dimensions 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc Proprietary Package Information Table 5 6 SR5690 692 Pin FCBGA Package Physical Dimensions Min mm Typical mm ddd 0 20 Note Maximum height of SMT components is 0 650 mm 2 2 00000090009000000000000 0000 Q00 Co 66666 uc 20 6 900 2 OG e 666 OOD XS 0000000 666 eo pcc Hcc eO Figure 5 3 SR5690 Ball Arrangement Bottom View OO Jenene 0009
80. r the function Hot plug signals from the PCIe slots are connected to the PCIe hot plug interface of the SR5690 through 9539 1 expanders each of which supports up to two slots Figure 2 5 illustrates the connections to the hot plug interface in the maximal eight slots configuration Figure 2 9 shows the signals that go between the PCA9539 I O expander and the PCIe hot plug slot Hot plug support is available on any PCIe slot connected to the GPP1 GPP2 or GPP3b core and up to three slots connected to the GPP3a core 1 connected through GPP3 lane 0 to lane 5 When more than three PCIe slots are connected to the GPP3a core the PCIe hot plug function is only available on the three ports on the lower lanes Table 2 5 shows the ports with hot plug support for each configuration of the GPP3a core SR5690 vas dH alod coldo 98a 10S dH 2129 01 9 98a 11 dH 3alOd cOld9 Hot plug di signals Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Figure 2 8 Hot plug Interface Connections 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 2 13 External Clock Chip PRSNTH PWRELT ATNSW EMILS PWREN lt ATNLED PWRLED EMIL lt Figure 2 9 Hot plug Signals between PCIe Slot and I O Expander Table 2 5 GPP3a Ports with PCle Hot Plug Support Shaded GPP3laneO 1
81. r Non fatal Unsupported Request Uncorrectable Fatal or Non fatal Malformed TLP Uncorrectable Fatal or Non fatal Unexpected Completion Uncorrectable Fatal or Non fatal Completer Abort Uncorrectable Fatal or Non fatal Completion Timeout Uncorrectable Fatal or Non fatal Poisoned TLP Received Uncorrectable Fatal or Non fatal Data Link Layer Protocol Error Uncorrectable Fatal or Non fatal ECRC Error Uncorrectable Fatal or Non fatal Replay Timeout Correctable REPLAY NUM Rollover Correctable Bad DLLP Correctable Bad TLP Correctable The following error classes are NOT supported Receiver Overflow Error Control Error e Surprise Down Error Receiver Error IOMMU Error Reporting The IOMMU specification defines a standard error logging facility that logs error events in system memory with register status bits or interrupt notification to system software The SR5690 fully supports the generation of logging events following this standard HyperTransport Error Reporting The HyperTransport specification defines various levels of error handling for link related errors The SR5690 supports the detection of most error classes including protocol error overflow error and response error The SR5690 also supports notification of error conditions via fatal interrupts non fatal interrupts or syncflood Table 2 3 lists the types of errors supported by the error handling capabilities of the SR5690 for H
82. r reliance damages arising from use of or reliance on this document No license whether express implied arising by estoppel or otherwise to any intellectual property rights are granted by this publication Except for AMD product purchased pursuant to AMD s Standard Terms and Conditions of Sale and then only as expressly set forth therein AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or in any other application in which the failure of AMD s product could create a situation where personal injury death or severe property or environmental damage may occur AMD reserves the right to discontinue or make changes to its products at any time without notice 2011 Advanced Micro Devices Inc rights reserved Table of Contents Chapter 1 Overview 1 1 Introducing 5600 aA tbt ADU 1 1 1 2 SR36090 ECaUltes baisses siat paesi 1 1 12 1 Interfaces dide etc c aeu 1 1 122 Express Interface ois aita bib Poe Use rael aan 1 1 1 23 A Link Express
83. ransmitter Control Differential Pair The pair is for distinguishing control TXCTL 4 0 N VDDHT VSS packets from data packets Each byte of TXCAD uses a separate control signal HT_RXCALN Other VDDHT VSS Receiver Calibration Resistor to HT_RXCALP HT_RXCALP Other VDDHT VSS Receiver Calibration Resistor to HT_RXCALN HT_TXCALP Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALN HT_TXCALN Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALP 3 4 PCI Express Interfaces 3 4 1 PCI Express Interface for General Purpose External Devices Table 3 2 PCI Express Interface for General Purpose External Devices A General Purpose 1 Transmit Data Differential Pairs VDDA48PCIE VSSA PCIE wedi Connect to connector s for general purpose external GPP1 TX 15 0 N complements device s on the motherboard General Purpose 1 Receive Data Differential Pairs GPP T RATSO VDDA18PCIE VSSA PCIE 300 between Connect to connector s for general purpose external GPP1 RX 15 0 N complements device s on the motherboard General Purpose 2 Transmit Data Differential Pairs OPPA VDDA48PCIE VSSA PCIE sbi beeen Connect to connector s for general purpose external GPP2 TX 15 0 N complements device s on the motherboard General Purpose 2 Receive Data Differential Pairs VDDA18PCIE VSSA 500 between Connect to connector s for general purpose external GPP2 RX 15 0 N complements device s on
84. rence VDD18 D18 VDDC R16 VDDHTTX G22 VDD18 E18 VDDC T13 VDDHTTX H22 VDDA18HTPLL G21 VDDC T15 VDDPCIE A3 VDDA18PCIE A12 VDDC T17 VDDPCIE AA10 VDDA18PCIE A13 VDDC U14 VDDPCIE AA12 VDDA18PCIE B12 VDDC U16 VDDPCIE AA16 VDDA18PCIE B13 VDDHT 22 VDDPCIE AA18 VDDA18PCIE C12 VDDHT AB22 VDDPCIE AAB VDDA18PCIE C13 VDDHT AC22 VDDPCIE AB11 VDDA18PCIE D12 VDDHT AD23 VDDPCIE AB13 VDDA18PCIE D13 VDDHT AE24 VDDPCIE AB15 VDDA18PCIE E12 VDDHT AE25 VDDPCIE AB17 VDDA18PCIE E13 VDDHT AE26 VDDPCIE AB19 VDDA18PCIE F12 VDDHT AE27 VDDPCIE AB7 VDDA18PCIE F13 VDDHT AE28 VDDPCIE ABO VDDA18PCIE G12 VDDHT AF27 VDDPCIE AC6 VDDA18PCIE G13 VDDHT K22 VDDPCIE AD5 VDDA18PCIE G14 VDDHT L21 VDDPCIE 4 VDDA18PCIE H12 VDDHT M22 VDDPCIE AF3 VDDA18PCIE H13 VDDHT N21 VDDPCIE AG2 VDDA18PCIE H14 VDDHT P22 VDDPCIE B2 VDDA18PCIE L11 VDDHT R21 VDDPCIE C1 VDDA18PCIE v11 VDDHT T22 VDDPCIE C3 VDDA18PCIE V18 VDDHT U21 VDDPCIE 4 VDDC L14 VDDHT 22 VDDPCIE E5 VDDC L16 VDDHT W21 VDDPCIE F6 VDDC M13 VDDHT Y22 VDDPCIE G10 VDDC M15 VDDHTTX C24 VDDPCIE G7 VDDC N12 VDDHTTX C25 VDDPCIE G8 VDDC N14 VDDHTTX C26 VDDPCIE H11 VDDC N16 VDDHTTX C27 VDDPCIE H7 VDDC P13
85. rface e One x4 A Link Express II interface for connection to an AMD Southbridge The A Link Express is a proprietary interface developed by AMD based on the PCI Express technology with additional Northbridge Southbridge messaging functionalities 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 1 1 Software Features 1 2 4 Multiple Processor Support e Supports multiple socket configurations for up to 8 processors on the same system 125 Multiple Northbridge Support e Supports multiple SR5690 5670 5650 configurations on the same system See Section 2 3 Multiple Northbridge Support for details 1 2 6 Power Management Features e Fully supports ACPI states S1 S3 54 and S5 e The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture On Standby Suspend and Off Each power state can be achieved by software control bits e Support for AMD PowerNow technology e Clocks are controlled dynamically using a mechanism that is transparent to the software The ASIC hardware detects idle blocks and turns off the clocks to those blocks in order to reduce power consumption e Supports dynamic lane reduction for the PCIe interfaces adjusting to the task the number of lanes employed 1 2 7 PC Design Guide Compliance The SR5690 complies with all relevant Windows Logo Program WLP requirements from Microsoft for WHQL certification 1 2 8 Test Capabi
86. ssible via the bridge configuration spaces 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 2 9 RAS Features 2 5 5 3 2 5 5 4 The ACS violations for ACS Source Validation and ACS Translation Blocking are recorded in the AER error log Errors due to IOMMU translation failures are not logged as ACS violations but are logged as UR or CA depending on the error type IOC may abort a non posted request with UR status 1f it determines that the request will not hit system memory Such errors are pushed back into the PCIe core for logging The IOC must abort potential peer to peer non posted requests to avoid a deadlock condition For posted requests the IOC can be configured to forward all non decoded non system memory and non peer to peer posted requests up to the processor which may abort the request and generate an MCA error log For downstream completions with abort status coming back from the processor error status is propagated to the endpoint but no AER header information is logged in the chipset For upstream completions error status is propagated up to the processor and AER information may be logged Table 2 2 lists the types of errors that are detectable by the SR5690 AER implementation For details see the PCI Express 2 0 Base Specification Table 2 2 Types of Errors Detectable by the SR5690 AER Implementation ACS Violation Uncorrectable Fatal o
87. sts containing virtual addresses are received the IOMMU looks up the page translation tables located in the system memory in order to convert the virtual addresses into physical addresses and to verify access privileges On chip caching is provided in order to speed up translation and reduce or eliminate the number of system memory accesses required Every PCIe core contains a local translation cache and SR5690 also contains a shared global translation cache The SR5690 supports up to 219 domains each of which can utilize a separate 64 bit virtual address space It supports a 52 bit physical address space Multiple Northbridge Support Multiple SR5690 5670 5650 referred to as SR56x0 below Northbridges may be implemented in the same system given enough free HyperTransport links from the processor complex However only a single Southbridge may be used The SR56x0 attached to the Southbridge 15 called the primary SR56x0 and any other instance of SR56x0 is called a secondary SR56x0 The A Link Express interface on any secondary SR56x0 must be left unconnected and it cannot be used to support any PCI Express endpoint devices The PWM GPIOS pin strap is used to indicate whether an SR56x0 is a primary or a secondary Northbridge If no pull down resistor is attached on the pin the internal pull up resistor on it will set the strap value to 1 indicating the device to be a primary Northbridge On any secondary SR56x0 the 5 pin
88. the link is independently controlled e 400MT s to 5 2GT s link speeds in increments of 400MT s up to 2GT s only for HyperTransport 1 mode e DC coupled HyperTransport mode only UnitID clumping for x16 PCI Express ports e sochronous flow control mode for Southbridge audio and IOMMU traffic e 64 bit address extension support 52 bit physical addressing e Link disconnection with tristate 1 51 and LS2 low power modes e Error retry in HyperTransport 3 mode e Full HyperTransport defined BIST support for both internal and external loopback modes 212 HyperTransport Flow Control Buffers The SR5690 HTIU implements the following flow control buffers in its receiver Table 2 1 SR5690 HyperTransport Flow Control Buffers 16 16 Advertise 63 credits Data 16 1 Advertise 63 credits ISOC Cmd 0 0 Advertise 63 credits ISOC Data 0 0 Advertise 63 credits 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary 2 3 IOMMU 2 2 23 2 4 2 4 1 2 4 2 IOMMU The SR5690 s IOMMU Input Output Memory Management Unit block provides address translation and protection services as described in version 1 26 of the AMD Virtualization Technology Specification The SR5690 also supports the PCI Express Address Translation Services 1 0 Specification which allows the supporting of endpoint devices to request and cache address translations When DMA reque
89. the primary SR5690 Interrupt line to Sys SMBUS IO EXP INTR L OPMA pin Enable signals should default to Pam 4 a logic 0 on reset powergood Enable only after S W From NMI button and trigger MCARD NMIBTN L pin OPMA pin reset This is a pin strap sampled shortly after powergood 5 5 Add option to drive SYNCFLOODIN pins on all 5856905 Enable only after in the system reset This is a pin strap sampled shortly after powergood Attach to a pin that can generate like USB 5 SYS 1 gt and NON FATAL CORR from other SR5690s These are buffered to help isolate the failing device Figure 2 7 Suggested Platform Level RAS Sideband Signal Connections 2 5 5 Error Reporting and Logging 2 5 51 PCI Error Logging The SR5690 implements all PCI standard error logging bits for all on board devices and functions including the host bridge device IOMMU and PCI Express bridges 2 5 5 2 PCIe Advanced Error Reporting The SR5690 PCIe cores implement the optional Advanced Error Reporting AER feature mechanism in the PCI Express 2 0 Base Specification Errors are logged for received packet errors such as poisoned data malformed TLP and etc within the PCIe core and are acce
90. ting Sorted by Ball Reference Table 1 585690 Pin Listing Sorted by Ball Reference GPP1 TX1P VDDPCIE A10 11 VSS A12 VDDA18PCIE A13 VDDA18PCIE A14 VSS A15 PWM GPIO4 A16 VSS A17 POWERGOOD A18 VDD18 A19 TESTMODE A20 VSS ree DBG_GPIO3 NON _FATAL_CORR A22 VSS 23 SYNCFLOODINE A24 VSS A25 DFT_GPIO1 A26 VSS A3 VDDPCIE A4 GPP1_TX6P A5 VSS A6 GPP1_TX5P A7 VSS A8 GPP1_TX3P A9 VSS AA1 VSS AA10 VDDPCIE 11 VSS AA12 VDDPCIE AA13 VSS AA14 GPP3_REFCLKN AA15 GPP3_REFCLKP AA16 VDDPCIE AA17 VSS AA18 AA19 VSS AA2 GPP2_TX7N AA20 VSS AA21 THERMALDIODE _ N AA22 VDDHT AA23 RXCAD11N AA24 HT RXCAD11P AA25 VSS AA26 HT_RXCAD3N AA27 AA28 VSS GPP2 TX7P AAA VSS AAS GPP2_RX7N 6 GPP2_RX7P AAT VSS VDDPCIE AA9 VSS AB1 GPP2_TX8N AB10 VSS AB11 VDDPCIE AB12 VSS AB13 VDDPCIE AB14 VSS AB15 VDDPCIE AB16 VSS AB17 VDDPCIE AB18 VSS AB19 VDDPCIE AB2 GPP2_TX8P AB20 VSS AB21 VSS 43869 SR5690 Databook 2 10 Appendix A 2 AB22 VDDHT AB23 VSS AB24 HT_RXCAD10N AB25 HT_RXCAD10P AB26 VSS AB27 HT_RXCAD2N AB28 HT_RXCAD2P AB3 VSS AB4 GPP2_RX8N ABS
91. vanced Micro Devices Inc Appendix B 2 Proprietary
92. vss AB20 vss AF16 vss C6 vss AB21 VSS AF18 VSS C8 vss AB23 vss AF20 vss D11 vss AB26 vss AF22 VSS D14 2011 Advanced Micro Devices Inc 43869 SR5690 Databook 2 10 Proprietary Appendix A 13 SR5690 Pin Listing Sorted by Ball Reference VSS D20 VSS D26 VSS D3 VSS 05 VSS D7 VSS 09 VSS E1 VSS E20 VSS E25 VSS E28 VSS E4 VSS F10 VSS F15 VSS F17 VSS F18 VSS F19 VSS F20 VSS F21 VSS F23 VSS F26 VSS F3 VSS F8 VSS G1 VSS G11 VSS G15 VSS G16 VSS G17 VSS G18 VSS G19 VSS G20 VSS G25 VSS G28 VSS G4 VSS G9 VSS H10 43869 SR5690 Databook 2 10 Appendix A 14 VSS H16 VSS H17 VSS H18 VSS H19 VSS H20 VSS H21 VSS H23 VSS H26 VSS H3 VSS H6 VSS J1 VSS J22 VSS J25 VSS J28 VSS J4 VSS J7 VSS K23 VSS K26 VSS K3 VSS VSS K8 VSS L1 VSS L12 VSS L13 VSS L15 VSS L17 VSS L18 VSS L22 VSS L25 VSS L28 VSS L4 VSS L7 VSS M11 VSS M12 VSS M14 VSS M17 VSS M18 VSS M21 VSS M23 VSS M26 VSS M3 VSS M6 VSS M8 VSS N1 VSS N11 VSS N13 VSS N15 VSS N17 VSS N18 VSS N22 VSS N25 VSS N28 VSS N4 VSS N7 VSS P11 VSS P12 VSS P14 VSS P16 VSS P18 VSS P21 VSS P23 VSS P26 VSS P3 VSS P
93. wnstream directions On power up the link is 8 bit wide and runs at a default speed of 400MT s in HyperTransport 1 mode After negotiation carried out by the HW and SW together the link width can be brought up to the full 16 bit width and the interface can run up to 5 2GT s in HyperTransport 3 mode In HyperTransport 1 mode the interface operates by clock forwarding while in HyperTransport 3 mode the interface operates by dynamic phase recovery with frequency information propagated over the clock pins The interface is illustrated below in Figure 2 3 SR5690 HyperTransport Interface Signals The signal name and direction for each signal is shown with respect to the SR5690 Detailed descriptions of the signals are given in Section 3 3 CPU HyperTransport Interface on page 3 4 43869 SR5690 Databook 2 10 2 2 2011 Advanced Micro Devices Inc Proprietary HyperTransport Interface HT TXCLKP HT TXCLKN 7 LUN HT 2 7 HT TXCTLN 2 DINE HT TXCADP HT TXCADN 16 vow v 069545 HT RXCLKP 5 HT RXCLKN HT RXCTLP 2 HT 2 HT RXCADP 16 RXCALN RXCALP HT 16 Figure 2 3 SR5690 HyperTransport Interface Signals The SR5690 HyperTransport interface has the following features e HyperTransport 3 0 compliant e 16 bit and 8 bit link widths supported Width for each direction of
94. yperTransport 43869 SR5690 Databook 2 10 2011 Advanced Micro Devices Inc 2 10 Proprietary RAS Features 2 5 5 5 2 5 6 2 5 7 2 5 8 Table 2 3 Types of HyperTransport Errors Supported by the 85690 Response Error Received incorrect response type such as tgtdone for read request read response for flush or size of received data did not match size of requested data Overflow Error Flow control buffer overflow in the receiver This is only mapped to a fatal or non fatal error in HT1 mode In HT3 mode this maps onto a retry in the hope that when the packet is subsequently received there is space in the FCB No interrupt will be generated in HT3 mode CRC Error Periodic CRC error Retry Error Per packet CRC error received Retry Count Rollover CRC error counter overflowed Non fatal interrupt only Protocol Error Protocol conditions detected in HT1 mode Data count not matching header Invalid command encoding Invalid CTL encoding ncomplete header Unexpected data Protocol conditions detected in HT3 mode Data count not matching header Invalid command encoding Invalid CTL encoding Incomplete header Unexpected data Unexpected CRC Missing CRC Non NOP inserted command Inserted command without inserted command CTL encoding End of chain error is not supported since the end of the chain is on PCI Express instead HyperTra
95. yperTransport Transmit Interface power VDDA18HTPLL 18 1 746 4 854 171 1 89 interface 1 8V PLL Note The voltage set point must be contained within the DC specification in order to ensure proper operation Voltage ripple and transient events outside the DC specification must remain within the AC specification at all times Transients must return to within the DC specification within 20 Table 5 2 Power Rail Current Ratings VDDC 0 62 6 56 6 56 5 94 300 VDD18 0 00048 0 00060 0 00060 0 00012 VDDPCIE 0 31 3 79 3 79 3 48 28 VDDA18PCIE 0 02 1 33 1 33 1 31 23 VDDHT 0 23 1 90 1 90 1 67 28 VDDHTTX 0 08 0 51 0 51 0 43 5 VDDA18HTPLL 0 007 0 013 0 013 0 006 DC Characteristics Table 5 1 DC Characteristics for PCle Differential Clocks GPP1_REFCLK GPP2_REFCLK and GPP3_REFCLK at 100MHz Differential Input Low Voltage 150 mV Differential Input High Voltage 150 mV VcRoss Absolute Crossing Point Voltage 250 550 mV VcRoss DELTA Variation of over all rising 140 clock edges 2011 Advanced Micro Devices Inc Proprietary 43869 SR5690 Databook 2 10 5 1 SR5690 Thermal Characteristics VRB Ring back Voltage Margin 100 100 mV VIMAX Absolute Max Input Voltage 1 15 V Absolute Min Input Voltage 0 15 V Table 5 3 DC Characteristics for 1 8V GPIO Pa

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