PHILIPS 74F195A handbook
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1. 55 Philips Semiconductors Product specification 4 bit parallel access shift register 74F195A LOGIC SYMBOL IEC IEEE SYMBOL Vec Pin 16 GND S FINE SF00758 SF00759 LOGIC DIAGRAM Q3 Voc Pin 16 GND Pin 8 SF00760 1996 Mar 12 3 Philips Semiconductors Product specification 4 bit parallel access shift register 74F195A FUNCTION TABLE OPERATING MODES Reset clear Shift set First stage Shift reset First stage Shift toggle First stage Shift retain First stage H High voltage level h High voltage level one setup time prior to Low to High clock transition L Low voltage level Low voltage level one setup time prior to Low to High clock transition X Don t care T Low to High clock transition dn qn Lower case letters indicate the state of the referenced input or output one setup time prior to the Low to High clock transition ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device Unless otherwise noted these limits are over the operating free air temperature range Supply voltage oar vg nouns i oaptdne ES EX CE T T a RECOMMENDED OPERATING CONDITIONS PTS SYMBOL PARAMETER UNIT me omm EE er RE EE CE EN EN CR NE CP EE PE NC HE fic e E A E S C EE A S CE ET PS A AE Tans E2. Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 print code Date of release 10 98 Telephone 800 234 7381 Document order number 9397 750 05096 Let make things better ee PHILIPS
3. O INTEGRATED CIRCUITS DATA SAHEET 74F195A 4 bit parallel access shift register Product specification 1996 Mar 12 IC15 Data Handbook Philips PHILIPS Semiconductors pl l LI PS Philips Semiconductors Product specification 4 bit parallel access shift register 74F195A FEATURES Shift right and parallel load capability J K D inputs to first stage Complement output from last stage Asynchronous Master Reset Diode inputs DESCRIPTION The 74F195A is a 4 Bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table This device is useful in a variety of shifting counting and storage applications It performs serial parallel serial to parallel or parallel to serial data transfers at very high speeds The 74F195A operates in two primary modes shift right Q0 Q1 and parallel load which are controlled by the state of the Parallel Enable PE input Serial data enters the first flip flop QO via the J and K inputs when the PE input is High and is shifted one bit in the direction Q0 Q1 Q2 0Q3 following each Low to High clock transition The J and K inputs provide the flexibility of the J K type input for special applications and by tying the two together the simple D type input is made for general applications The device appears as four common clocked D flip flops when the PE input is Low After the Low to High clock transition
4. T NS id CS 1996 Mar 12 4 Philips Semiconductors Product specification 4 bit parallel access shift register 74F195A DC ELECTRICAL CHARACTERISTICS Over recommended operating free air temperature range unless otherwise noted LIMITS SYMBOL PARAMETER TEST CONDITIONSNO TAG TYP UNIT NO TAG VoH VoL Vik LH liL los Vik o Input clamp voltage Vcc MIN l lik Supply current total NOTES 1 For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions for the applicable type 2 All typical values are at Voc 5V Tamp 25 C 3 Not more than one output should be shorted at a time For testing los the use of high speed test apparatus and or sample and hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values Otherwise prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests In any sequence of parameter tests los tests should be performed last AC ELECTRICAL CHARACTERISTICS LIMITS FES Vec 5V Vcc 5V 10 SYMBOL PARAMETER Tamb 25 C Tamb 0 C to 70 C CONDITION CL 50pF RL 5000 CL 50pF RL 5002 Min typ max mN max tyne Maximum clock waveform 165 180 150 ue tp Propagation delay Waveform 3 0 5 0 9 5 2 5 10 ns CP to Qn NO TAG 2 5 4 0 7 0 2 0 7 H Propagation del
5. ata sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design target or goal specifications for product development specification Specification may change in any manner without notice Preliminary Qualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently issued datasheet before initiating or completing a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of
6. ay Waveform 2 0 5 5 9 5 2 5 9 ns H CP to Q3 NO TAG 2 0 4 0 6 5 2 0 7 H H H HL L L Propagation delay MR to Qn Waveform 2 2 0 4 0 7 0 2 0 7 0 ns Propagation delay MR to 03 Waveform 2 2 5 4 5 2 0 10 0 ns 1996 Mar 12 5 Philips Semiconductors Product specification 4 bit parallel access shift register 74F195A AC SETUP REQUIREMENTS LIMITS Voc 5V Vec 5V 10 SYMBOL PARAMETER CONDITION Tamb 25 C Tamb 0 C to 70 C 50pF 5002 ED fee fat eo poe onio wama fof feof m ee daem ome ej f ded fe of e e w J deee e e de AC WAVEFORMS For all waveforms Vy 1 5V The shaded areas indicate when the input is permitted to change for predictable output performance SF00761 Waveform 1 Propagation Delay Clock Input to Output Clock Pulse Width and Maximum Clock Frequency SF00762 Waveform 3 Master Reset Pulse Width Master Reset to Output Delay and Master Reset to Clock Recovery Time SERIAL SHIFT RIGHT PARALLEL LOAD VM VM SF00763 Waveform 2 Data Setup and Hold Times n RESPONSE Qn Dn SF00764 Waveform 4 Setup and Hold Times Parallel Enable to Clock 1996 Mar 12 6 Philips Semiconductors 4 bit parallel access shift register TEST CIRCUIT AND WAVEFORMS PULSE GENERATOR Test Circuit for Totem Pole Outputs DEFINITIONS RL Load resistor see AC ELECTRICAL CHARACTERISTICS for value CL Load capacitanc
7. data on the parallel inputs DO D3 is transferred to the respective Q0 Q3 outputs Shift left operation Q3 Q2 can be achieved by tying the Qn outputs to the Dn 1 inputs and holding the PE input Low All parallel and serial data transfers are synchronous occurring after each Low to High clock transition The 74F195A utilizes edge triggering therefore there is no restriction on the activity of the INPUT AND OUTPUT LOADING AND FAN OUT TABLE J K Dn and PE inputs for logic operation other than the set up and hold time requirements A Low on the asynchronous Master Reset MR input sets all Q outputs Low independent of any other input condition PIN CONFIGURATION SF00757 TYPICAL SUPPLY CURRENT TYPE TYPICAL fmax TOTAL ORDERING INFORMATION COMMERCIAL RANGE DESCRIPTION Vec 5V 10 Tamb 0 C to 70 C 16 pin plastic DIP N74F195AN SOT 38 4 16 pin plastic SO N74F195AD SOT 109 1 74F U L LOAD VALUE HIGH LOW 74F195 1 0 0 033 20uA 20uA Data inputs 74F195A 1 0 1 0 20uA 0 6mA 74F195 1 0 0 033 20uA 20uA J K or D type serial inputs 74F195A 1 0 1 0 20uA 0 6mA 74F195 1 0 0 033 20uA 20uA Clock Pulse input active rising edge 74F195A 1 0 1 0 20uA 0 6mA 74F195 2 0 0 066 40uA 40uA Master Reset input active Low 74F195A 1 0 1 0 20uA 0 6mA 50 33 1 0mA 20mA Data outputs NOTE One 1 0 FAST unit load is defined as 20uA in the High state and 0 6mA in the Low state 1996 Mar 12 853 0024 165
8. e includes jig and probe capacitance see AC ELECTRICAL CHARACTERISTICS for value RT Termination resistance should be equal to Zour of pulse generators 1996 Mar 12 NEGATIVE PULSE POSITIVE PULSE Product specification 74F195A TH t gt tTHL tf gt tw Input Pulse Definition INPUT PULSE REQUIREMENTS amplitude rep rate tw tTLH 3 0V 1MHz 2 5ns SF00006 Philips Semiconductors Product specification 4 bit parallel access shift register 74F195A DIP16 plastic dual in line package 16 leads 300 mil SOT38 4 Le seating plane 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions A Ay A2 max min max UNIT b by b2 c pM El 1 73 0 53 1 25 0 36 19 50 6 48 10 0 1 30 0 38 0 85 0 23 18 55 6 20 8 3 0 068 0 021 0 049 0 014 0 77 0 26 0 39 inches oa 0 051 0 015 0033 0 009 0 73 024 0 33 0 01 0 254 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION 92 14 44 SOT38 4 ET 95 01 14 ISSUE DATE 1996 Mar 12 8 Philips Semiconductors Product specification 4 bit parallel access shift register 74F195A NOTES 1996 Mar 12 9 Philips Semiconductors Product specification 4 bit parallel access shift register 74F195A D
9. the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips
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PHILIPS 74F195A handbook