PHILIPS 74F193 handbook
Contents
1. 1995 Juk 17 10 Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F193 NOTES 1995 Juk 17 11 Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F193 Data sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design target or goal specifications for product development specification Specification may change in any manner without notice Preliminary Qualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently issued datasheet before initiating or completing a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maxi2. any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 print code Date of release 10 98 Telephone 800 234 7381 Document order number 9397 750 05094 45 make things beter ee amp PHILIPS
3. 0 INTEGRATED CIRCUITS DATA 1 74F193 Up down binary counter with separate up down clocks Product specification 1995 Jul 17 IC15 Data Handbook Philips PHILIPS Semiconductors DS Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F193 FEATURES Synchronous reversible 4 bit counting 9 Asynchronous parallel load capability Asynchronous reset clear Cascadable without external logic DESCRIPTION The 74F193 is a 4 bit synchronous up down counter in the binary mode Separate up down clocks CPy and CPp respectively simplify operation The outputs change state synchronously with the Low to High transition of either clock input If the CPy clock is pulsed while CPp is held High the device will count up If CPp clock is pulsed while CPy is held High the device will count down The device can be cleared at any time by the asynchronous reset pin It may also be loaded in parallel by activating the asynchronous parallel load pin Inside the device are four master slave JK flip flops with the necessary steering logic to provide the asynchronous reset asynchronous preset load and synchronous count up and count down functions Each flip flop contains JK feedback from slave to master such that a Low to High transition on the CPp input will decrease the count by one while a similar transition on the CPy input will advance the count by one
4. CTERISTICS Tamb 25 C Tamb 0 C to 70 C Voc 5 0V Voc 5 0V 10 C 50pF 5000 C 50pF 5000 Ed Apo d delay to TCy i p L 5 5 5 0 5 5 8 5 4 0 9 5 6 5 8 5 7 oa 8 oa ooj f 00 2 5 3 0 2 5 5 0 2 0 6 0 4 5 5 5 5 0 5 0 7 H Propagation delay MR to TCp Waveform 5 Propagation delay PL to TCy or Waveform 3 Propagation delay Dn to TCy or TCp Waveform 4 H 2d ansloo H H H s Tamb 0 C to 70 TEST CONDITIONS 5 0V 5 0V 10 C 5 5002 50pF R 5000 i ine width CP or CPp Pulse width ine at AR lt v vja a EA 3 1 5 5 0 0 0 4 0 1995 Jul 17 6 Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F 193 AC WAVEFORMS For all waveforms Vm 1 5V VM SF00753 SF00750 Waveform 2 Propagation Delay Clock to Terminal Count Waveform 1 Propagation Delay Clock Input to Output Clock Pulse Width and Maximum Clock Frequency TCy TCp Qn TCy TCp Vu SF00754 TCy TCp Qn Waveform 4 Propagation Delay Data to Flip Flop Outputs Terminal Count Up and Down Outputs SF00751 Waveform 3 Parallel Pulse Width Parallel Load to Output Delays and Parallel Load to Clock Recovery Time The shaded ar
5. One clock should be held High while counting with the other because the circuit will either count by twos or not at all depending on the state of the first JK flip flop which cannot toggle as long as either clock input is Low Applications requiring reversible operation must make the reversing decision while the activating clock is High to avoid erroneous counts The Terminal Count Up TCy and Terminal Count Down TCp outputs are normally High When the circuit has reached the maximum count state of 15 the next High to Low transition of CPy will cause TCy to go Low TCy will stay Low until CPy goes High again duplicating the count up clock although delayed by two gate delays Likewise the TCp output will go Low when the circuit is in the zero state and the CPp goes Low The TC outputs can be used as the clock input signals to the next higher order circuit in a multistage counter since they duplicate the clock waveforms INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F U L Multistage counters will not be fully synchronous since there is a two gate delay time difference added for each stage that is added The counter may be preset by the asynchronous parallel load capability of the circuit Information present on the parallel Data inputs DO D3 is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs when the Parallel Load PL input is Low A High level on the Master Reset MR input w
6. eas indicate when the input is permitted to change for predictable output performance SF00755 Waveform 6 Data Setup and Hold Times E ipu Vi lt lt ipu Nw SF00752 Waveform 5 Master Reset Pulse Width Master Reset to Output Delay and Master Reset to Clock Recovery Time 1995 Jul 17 7 Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F193 Timing Diagram Typical clear load and count sequence CLEAR LOAD COUNT UP COUNT DOWN OUTPUTS SEQUENCE 14 15 0 1 2 1 0 15 14 13 co COUNT UP COUNT DOWN NOTES G 1 Clear overrides load data and count inputs 2 When counting up count down input must be High when counting down count up input must be High SF00756 Binary Counter TEST CIRCUIT AND WAVEFORMS NEGATIVE PULSE PULSE UT GENERATOR tr 79 f gt POSITIVE PULSE Test Circuit for Totem Pole Outputs w DEFINITIONS Input Pulse Definition RL Load resistor see AC ELECTRICAL CHARACTERISTICS for value INPUT PULSE REQUIREMENTS CL Load capacitance includes jig and probe capacitance see AC ELECTRICAL CHARACTERISTICS for value amplitude Vm rep rate tTLH RT Termination resistance should be equal to Zour of pulse generators 3 0V 1MHz 2 5ns SF00006 1995 Jul 17 8 Philips Semiconductors Pr
7. fication 74F193 SF00747 Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F 193 LOGIC DIAGRAM MR Bott Voc 16 Q0 ONL png SF00749 INPUTS OPERATING MODE E Reset clear L H L H Parallel load H H FUNCTION TABLE MR PE cru CPo bo D2 D3 H X X L X X X X H X X H X X X X E L X L L L L L L X H L L L L L L L X H H H H B L H X H H H H H High voltage level NOTES L Low voltage level TCy CPy at terminal count up HHHH X Don tcare TCp CPp at terminal count down LLLL T Low to High clock transition 1995 Jul 17 4 Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F 193 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device Unless otherwise noted these limits are over the operating free air temperature range RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER Suppi votes unius Low level input voltage Input clamp current High level output current Low level output current Operating free air temperature ra
8. ill disable the parallel load gates override both clock inputs and set all Q outputs Low If one of the clock inputs is Low during and after a reset or load operation the next Low to High transition of the clock will be interpreted as a legitimate signal and will be counted TYPICAL SUPPLY CURRENT TOTAL ORDERING INFORMATION COMMERCIAL RANGE 5V 10 Tamb 0 C to 70 C 16 pin plastic DIP N74F193N SOT38 4 16 pin plastic SO N74F193D SOT109 1 PIN CONFIGURATION TYPE TYPICAL fmax DESCRIPTION LOAD VALUE HIGH LOW Count up clock input active rising edge 1 0 3 0 Count down clock input active rising edge 1 0 3 0 20uA 1 8mA 20nA 0 6mA Asynchronous master reset input 1 0 1 0 Q0 Q3 Flip flop outputs 50 33 Asynchronous parallel load control input active Low 1 0 1 0 Terminal count up carry output active Low 50 33 TCp Terminal count down borrow output active Low 50 33 1 0mA 20mA NOTE One 1 0 FAST Unit Load U L is defined as 20 in the High state and 0 6mA in the Low state 1995 Jul 17 853 0353 15459 Philips Semiconductors Up down binary counter with separate up down clocks LOGIC SYMBOL LOGIC SYMBOL IEEE IEC CTR DIV 16 1CT 15 2CT 0 Voc Pin 16 SND Ring SF00746 COUNT UP COUNT DOWN TCy Q0 Q1 Q2 Q3 CP TCp Q0 Q1 Q2 Q3 CP Logic Equations for Terminal Count SF00748 1995 Jul 17 3 Product speci
9. mum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under
10. nge DC ELECTRICAL CHARACTERISTICS Over recommended operating free air temperature range unless otherwise noted SYMBOL PARAMETER TEST CONDITIONSNO TAG TYP UNIT NO TAG Low levalicuiputvallage Vo MIN Vi MAX 10 Vcc 035 oso v n Input current at maximum _ _ input voltage Vcc MAX 7 0V i High level input current Cae MAX 2 7V EM EE E level i UI we rz EIE 3 Short circuit output TAG Vcc MAX Supply current total 4 Voc MAX haan For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions for the applicable type All typical values are at Voc 5V Tamb 25 3 Not more than one output should be shorted at a time For testing los the use of high speed test apparatus and or sample and hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values Otherwise prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests In any sequence of parameter tests los tests should be performed last 4 Measure lcc with parallel load and Master reset inputs grounded all other inputs at 4 5V and all outputs open 1995 Jul 17 5 Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F 193 AC ELECTRICAL CHARA
11. oduct specification Up down binary counter with separate up down clocks 74F193 DIP16 plastic dual in line package 16 leads 300 mil SOT38 4 lt seating plane 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions A Ay 2 UNIT b by b2 c p eM 1 73 0 53 1 25 0 36 19 50 6 48 10 0 1 30 0 38 0 85 0 23 18 55 6 20 8 3 0 068 0 021 0 049 0 014 0 77 0 26 0 39 inches Bate 0 051 0 015 0 033 0009 073 024 0 33 901 0 254 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION 92 H Y SOT38 4 E Q 95 01 14 ISSUE DATE 1995 Juk 17 9 Philips Semiconductors Product specification Up down binary counter with separate up down clocks 74F193 S016 plastic small outline package 16 leads body width 3 9 mm SOT109 1 detail X 25 scale DIMENSIONS inch dimensions are derived from the original mm dimensions A UNIT nax At ED e Lp Q 0 25 10 0 4 0 1 0 0 7 1 73 0 19 9 8 3 8 Wer 0 4 0 6 0 0100 0 39 0 16 0 038 0 028 inches 0 069 0 0075 0 38 0 15 090 0 016 0 020 Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN ISSUE DATE
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PHILIPS 74F193 handbook