PHILIPS 74F173 handbook
Contents
1. ov SF00297 Waveform 2 Master reset pulse width master reset to output delay and master reset to clock recovery time SF00296 Waveform 3 Data and enable setup time and hold times Notes to AC waveforms 1 For all waveforms Vyp 1 5V Waveform 4 3 state output enable time to high level output disable time from high level and transition time to high level VM VM 3 5V BS VoL 0 3V SF00298 Waveform 5 3 state output enable time to low level output disable time from low level and transition time to low level 2 The shaded areas indicate when the input is permitted to change for predictable output performance TEST CIRCUIT AND WAVEFORMS PULSE GENERATOR A o AL i il Test Circuit for Open Collector Outputs SWITCH POSITION TEST SWITCH tpLz closed tpzi closed All other open DEFINITIONS RL Load resistor see AC electrical characteristics for value Load capacitance includes jig and probe capacitance see AC electrical characteristics for value Termination resistance should be equal to Zout of pulse generators RT August 31 1990 NEGATIVE PULSE POSITIVE PULSE 90 tTLH tr gt tTHL t I Input Pulse Definition INPUT PULSE REQUIREMENTS Vm amplitude rep rate tw ttLy ttHL 2 5ns 2 5ns 3 0V 1MHz SF00128 Philips Semiconductors2. 5 0V Vcc 5 0V 10 CONDITION C 50pF R 5002 C 50pF R 5009 aan te wax win WAX a Waximum cock reaueney Waveiomm 100 ves 20 __ we PLH Propagation delay 4 5 6 5 9 0 4 0 10 0 ie ees ee em a ee Ie tpzH Output enable time Waveform 4 5 0 8 0 2 5 8 5 tPZL to high or low level Waveform 5 7 0 10 0 4 5 1 0 s tpuz Output disable time Waveform 4 i 35 7 0 1 0 8 0 tPpLZz from high or low level Waveform 5 3 5 0 8 5 2 5 9 0 trHL Transition time Waveform 5 2 5 0 8 0 2 0 8 5 is TLH 10 to 90 90 to 10 Waveform 4 4 Wine 10 0 4 0 11 0 AC SETUP REQUIREMENTS Tamb 25 C Tamb 0 C to 70 C SYMBOL PARAMETER TEST Vece 5 0V Vcc 5 0V 10 CONDITION C 50pF RL 5000 C 50pF R 5002 TYP tsu H Setup time high or low level 2 5 tsu L Dn to CP Waveform3 25 th H Hold time high or low level tn b Dn to CP Waveform 3 tsu H Setup time high or low level 4 5 teu L E to CP Waveform3 75 th H Hold time high or low level tnb E to CP Waveform 3 i 3 0 6 0 tw H CP Pulse width tw L high or low Waveform 1 tw H MR Pulse width high Recovery time MR to CP AC WAVEFORMS SF00294 Waveform 1 Propagation delay for clock input to output clock pulse widths and maximum clock frequency August 31 1990 6 Philips Semiconductors Quad D type flip flop 3 State Product specification 74F173 VM VM SF00295 ER VOH 0 3V
3. Over recommended operating free air temperature range unless otherwise noted Voc MIN Vi MAX Vin MIN lop MAX Voc MIN Vi MAX Low level output voltage Voc MIN Vit MAX f 10 Vcc 4 0 35 oso v a e ER oa a acm uA Off state output current high level voltage applied Voc MAX Vo 2 7V Li Off state output current low level voltage applied Voc MAX Vo 0 5V aa dh Short circuit output current3 Vcc MAX ie Supply current total Voc MAX mA has to DC electrical characteristics For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions for the applicable type All typical values are at Voc 5V Tamb 25 C 3 Not more than one output should be shorted at a time For testing los the use of high speed test apparatus and or sample and hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests In any sequence of parameter tests los tests should be performed last NINJ gt WNI wo e S go 3 gt gt August 31 1990 5 Philips Semiconductors Product specification Quad D type flip flop 3 State 74F173 AC ELECTRICAL CHARACTERISTICS Tamb 25 C Tamb 0 C to 70 C SYMBOL PARAMETER TEST Vcc
4. Product specification Quad D type flip flop 3 State 74F173 DIP16 plastic dual in line package 16 leads 300 mil SOT38 4 lt seating plane 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions A Ay Ao max min max UNIT b by b2 c pM eM 1 73 0 53 1 25 0 36 19 50 6 48 10 0 1 30 0 38 0 85 0 23 18 55 6 20 8 3 0 068 0 021 0 049 0 014 0 77 0 26 0 39 inches oa 0 051 0 015 0 033 0 009 0 73 o24 0 33 201 0 254 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION 92 14 44 SOT38 4 95 01 14 ISSUE DATE 1990 Aug 31 8 Philips Semiconductors Product specification Quad D type flip flop 3 State 74F 173 S016 plastic small outline package 16 leads body width 3 9 mm SOT109 1 detail X 25 scale DIMENSIONS inch dimensions are derived from the original mm dimensions A UNIT nax At Ao c D ED e Lp Q 0 25 10 0 4 0 1 0 0 7 1 73 0 19 9 8 3 8 ner 0 4 0 6 0 0100 0 39 0 16 0 038 0 028 inches 0 069 0 0075 0 38 0 15 0 016 0 020 Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN ISSUE DATE 1990 Aug 31 9 Philips Semiconductors Product
5. clock transition Lower case letters indicate the state of the referenced input or output on setup time prior to the low to high clock transition Don t care Low to high clock transition on 7x2 rs T August 31 1990 3 Philips Semiconductors Product specification Quad D type flip flop 3 State 74F173 FUNCTION TABLE INPUTS OUTPUTS OUTPUTS Qn wa Disabled Notes to function table H High voltage level L Low voltage level X Don tcare Z High impedance off state LOGIC DIAGRAM Vcc Pin 16 GND Pin 8 SF00293 ABSOLUTE MAXIMUM RATINGS Operation beyond the limit set forth in this table may impair the useful life of the device Unless otherwise noted these limits are over the operating free air temperature range Voltage applied to output in high output state 0 5 to Voc Current applied to output in low output state ee ee Operating free air temperature range 0 to 70 Storage temperature range 65 to 150 August 31 1990 4 Philips Semiconductors Product specification Quad D type flip flop 3 State 74F173 RECOMMENDED OPERATING CONDITIONS LIMITS UNIT Supply voltage Vv High level input voltage Vv Low level input voltage Vv Input clamp current mA High level output current mA Ee Ea Low level output current Operating free air temperature range DC ELECTRICAL CHARACTERISTICS
6. 0 INTEGRATED CIRCUITS DATA SAHEET 74F173 Quad D type flip flop 3 State Product specification 1990 Aug 31 IC15 Data Handbook Philips PHILIPS Semiconductors FA l LI PS Philips Semiconductors Product specification Quad D type flip flop 3 State 74F173 FEATURES Edge triggered D type register Gated clock enable for hold do nothing mode 3 state output buffers Gated output enable control Speed upgrade of N8T10 and current sink upgrade Controlled output edges to minimize ground bounces 48mA sinking capability DESCRIPTION The 74F173 is a high speed 4 bit parallel load register with clock enable control 3 state buffered outputs and master reset MR When the two clock enable E0 and E1 inputs are low the data on the D inputs is loaded into the register simultaneously with low to high clock CP transition When one or both enable inputs are high one setup time before the low to high clock transition the register retains the previous Data inputs and clock enable inputs are fully edge triggered and must be stable only one setup time before the low to high clock transition The master reset MR is an active high asynchronous input When the MR is high all four flip flops are reset cleared independently of any other input condition The 3 state output buffers are controlled by a 2 input NOR gate When both output enable OE0 and OE1 inputs are low the data in the
7. ditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwi
8. register is presented at the Q output When one or both OE inputs are high the outputs are forced to a high impedance off state The 3 state output buffers are completely independent of the register operation the OE transition does not affect the clock and reset operations TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT TOTAL ORDERING INFORMATION ORDER CODE COMMERCIAL RANGE Vec 5V 10 Tamb 0 C to 70 DESCRIPTION 16 pin plastic DIP N74F173N SOT38 4 16 pin plastic SO INPUT AND OUTPUT LOADING AND FAN OUT TABLE N74F173D SOT109 1 DESCRIPTION 74F U L HIGH LOAD VALUE LOW HIGH LOW DO D3 Data inputs 1 0 1 0 20uA 0 6mA CP Clock input 1 0 1 0 20uA 0 6mA E0 E1 Clock enable inputs 1 0 1 0 20uA 0 6mA OE OE1 Output enable inputs 1 0 1 0 20uA 0 6mMA Note to input and output loading and fan out table 1 One 1 0 FAST unit load is defined as 20uA in the high state and 0 6mA in the low state August 31 1990 853 1160 00286 Philips Semiconductors Product specification Quad D type flip flop 3 State 74F173 PIN CONFIGURATION IEC IEEE SYMBOL SF00290 SF00292 LOGIC SYMBOL 14 13 12 11 Vcc Pin 16 GND Pin 8 SF00291 FUNCTION TABLE R a a aa a aan D E a E E S E a CC ee Notes to function table High voltage level High state one setup time before the low to high clock transition Low voltage level Low state one setup time before the low to high
9. se specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 print code Date of release 10 98 Telephone 800 234 7381 Document order number 9397 750 05088 Lett make things beter ee PHILIPS
10. specification Quad D type flip flop 3 State 74F 173 Data sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design target or goal specifications for product development specification Specification may change in any manner without notice Preliminary Qualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently issued datasheet before initiating or completing a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other con
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PHILIPS 74F173 handbook