SEMTECH SC1164/5 handbook
Contents
1. S9 59 310081 4noos APPLICATION CIRCUIT 652 MITCHELL ROAD NEWBURY PARK CA 91320 1999 SEMTECH CORP PROGRAMMABLE SYNCHRONOUS DC DC 5 SEIMIT EC HI converter DUAL LOW DROPOUT SC1164 5 pn T US REGULATOR CONTROLLER October 25 1999 MATERIALS LIST Reference Part Description Vendor C1 C5 C13 C 0 1uF Ceramic Various 18 C2 C3 C14 1500 6 3 SANYO MV GX or equiv Low ESR C17 C9 C12 330UF 6 3V Various C21 C22 L1 4uH 8 Turns 16AWG on MICROMETALS T50 52D core Q1 Q2 Q3 See notes See notes FET selection requires trade off between efficiency and Q4 cost Absolute maximum Rosow 22 MQ for Q1 Q2 R4 5mQ IRC OAR 1 Series R5 2 32kQ 1 1 8W Various R6 1kQ 196 1 8W Various R1 100 5 1 8W Various R12 1 1 8W Various See Table Below Not required for SC1164 R13 1 1 8W Various See Table Below Not required for SC1164 R14 1 1 8W Various See Table Below Not required for SC1164 R15 1 1 8W Various See Table Below Not required for SC1164 R17 R18 100kO 596 1 8W Various Required if Voltage is applied to the linear FET s without 12V applied to SC1164 5 U1 SC1164 5CSW SEMTECH SETTING LDO OUTPUT VOLTAGE VOUT LDO1 LDO2 12 814 13 R15 1 265 R Vour 4 leg Ra B Where leg Fee2. i E NORTON 0 B 2914 29927 40 DAT C 394 419 0 00 10 64 DETAIL A D 050 BSC 1 27 BSC E 015 020 33 51 F FJ liii 004 0 118 10 30 0926 1043 2 35 2 64 _ J 0091 0125 23 32 7 o 3 o 38 L 016 050 41 1 27 zi s JEDEC MS 013AD E F SEE DETAIL A B17104B 2 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTUSIONS CONTROLLING DIMENSION MILLIMETERS ECN 99 667 12 1999 SEMTECH CORP 652 MITCHELL ROAD NEWBURY PARK CA 91320
3. Scuer nr PROGRAMMABLE SYNCHRONOUS DC DC CONVERTER DUAL LOW DROPOUT REGULATOR CONTROLLER Today s Results Tomorrow s SEMTECH P October 25 1999 DESCRIPTION The SC1164 5 combines a synchronous voltage mode controller with two low dropout linear regulators providing most of the circuitry necessary to implement three DC DC converters for powering advanced microprocessors such as Pentium Il The SC1164 5 switching section features an integrated 5 bit D A converter pulse by pulse current limiting integrated power good signaling and logic compatible shutdown The SC1164 5 switching section operates at a fixed frequency of 200kHz providing an optimum compromise between size efficiency and cost in the intended application areas The integrated D A con verter provides programmability of output voltage from 2 0V to 3 5V in 100mV increments and 1 30V to 2 05V in 50mV increments with no external components The SC1164 5 linear sections are low dropout regula tors The SC1164 supplies 1 5V for GTL bus and 2 5V for non GTL I O For the SC1165 both LDO s are adjustable PIN CONFIGURATION Top View MD4 o VID2 5 1164 5 TEL 805 498 2111 FAX 805 498 3804 WEB http www semtech com FEATURES Synchronous design enables no heatsink solution 95 efficiency switching section 5 bit DAC for output programmability On chip power good function Designed for Intel Pentium II requirements 1 5V 2 5V or
4. Adj 196 for linear section APPLICATIONS Pentium Il or Deschutes microprocessor supplies Flexible motherboards 1 3V to 3 5V microprocessor supplies Programmable triple power supplies ORDERING INFORMATION Linear Temp Voltage Range T Part Number Package 50 24 1 5V 2 5V 0 to 125 C SO 24 Adj 0 to 125 C Note 1 Add suffix TR for tape and reel BLOCK DIAGRAM vec CS CS CURRENT LIMIT LEVEL SHIFT AND HIGH SIDE MOSFET DRIVE 2 LDOV VIDO VID1 VID2 VID3 VIDA VOSENSE AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD VOSENSE 0 PWRGOOD 00120 In 10 11 12 DUTT 24 Pin SOIC 1999 SEMTECH CORP OSCILLATOR SHOOT THRU CONTROL ERROR SYNCHRONOUS MOSFET DRIVER GATE2 10052 AGND Pentium is a registered trademark of Intel Corporation 1 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC DC 5 SEIMIT EC converter DUAL LOW DROPOUT SC1164 5 ee USUS REGULATOR CONTROLLER October 25 1999 ABSOLUTE MAXIMUM RATINGS Parameter Maximum VCC to GND 0 3 to 7 PGND to GND 1 BST to GND 0 3 to 15 Operatin
5. ERATECH converter DUAL Low DROPOUT REGULATOR CONTROLLER Today s Results Tomorrow s Vision October 25 1999 COMPONENT SELECTION SWITCHING SECTION OUTPUT CAPACITORS Selection begins with the most critical component Because of fast transient load current requirements in modern microprocessor core supplies the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level Output capacitor ESR is therefore one of the most important criteria The maximum ESR can be simply calculated from V lt I Where V Maximum transient voltage excursion Transient current step For example to meet a 100mV transient limit with a 10A load step the output capacitor ESR must be less than 10mQ To meet this kind of ESR level there are three available capacitor technologies Each Capacitor Technology C ESR 330 60 330 25 1500 44 Low ESR Tantalum OS CON Low ESR Aluminum The choice of which to use is simply a cost perfor mance issue with Low ESR Aluminum being the cheapest but taking up the most space INDUCTOR Having decided on a suitable type and value of output capacitor the maximum allowable value of inductor can be calculated Too large an in ductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the tran sient load current for lo
6. HRONOUS DC DC 5 SERNATECH CONVERTER DUAL LOW DROPOUT SC1164 5 REGULATOR CONTROLLER October 25 1999 PIN DESCRIPTION Pin Function Small Signal Analog and Digital Ground Pin Name AGND GATE1 Top View Gate Drive Output LDO1 LDOS1 Sense Input for LDO1 LDOS2 Sense Input for LDO2 VCC Input Voltage OVP High Signal out if Vo gt setpoint 20 PWRGOOD Open collector logic output high if Vo within 1096 of setpoint CS Current Sense Input negative CS Current Sense Input positive PGNDH Power Ground for High Side Switch DH High Side Driver Output PGNDL Power Ground for Low Side Switch DL Low Side Driver Output BSTL Supply for Low Side Driver BSTH Supply for High Side Driver EN Logic low shuts down the converter High or open for normal operation VOSENSE Top end of internal feedback chain Programming Input MSB Programming Input Programming Input Programming Input Programming Input LSB 12V for LDO section Gate Drive Output LDO2 1999 SEMTECH CORP AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD Note gt 10 11 12 DUTT 24 Pin SOIC GATE2 LDOV VIDO VID1 VID2 VID3 VIDA VOSENSE 1 All logic level inputs and outputs are open collector TTL compatib
7. ce or copper region It should be as short as practical Since this connection has fast voltage transitions keeping this connection short will minimize EMI The connection be tween the output inductor and the sense resistor should be a wide trace or copper area there are no fast volt age or current transitions in this connection and length is not so important however adding unnecessary impedance will reduce efficiency AGND GATE1 LDOS1 LDOS2 VCC OVP PWRGOOD CS CS PGNDH DH PGNDL 561164 5 2 LDVO gt VIDO VID1 VID2 VID3 VID4 m 1 VOSENSE EN BSTH BSTL DL Heavy lines indicate high current paths Vo Lin1 posu Cout Lint For SC1164 RA1 RA2 RB1 and RB2 are not required LDOS1 connects to Vo Lin1 LDOS2 connects to Vo Lin2 Vo Lin2 Cout Lin2 Layout diagram for the SC1164 5 1999 SEMTECH CORP NA 8 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC DC 5 SERATECH converter DUAL LOW DROPOUT Today s Results Tomorrow s Vision October 25 1999 4 The Output Capacitor s Cout should be located as close to the load as possible fast transient load currents are supplied by Cout only and connecti
8. dback pin bias current R4 Top feedback resistor Rs Bottom feedback resistor See layout diagram for clarification 1000 1210 R andR must be low enough so 1000 97 60 that the l g R4 term does not cause 1000 18 70 significant error 1050 1820 1050 1690 1020 1470 1000 1300 6 1999 SEMTECH CORP 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC DC SC1164 5 5 SERATECH converter DUAL LOW DROPOUT REGULATOR CONTROLLER October 25 1999 Efficiency Efficiency 3 5V Std 2 8V Std 3 5V Sync 2 8V Sync 3 5V Sync Lo Rds 95 4 2 8V Sync Lo Rds 8 8 lo Amps lo Amps Typical Efficiency at Vo 3 5V Typical Efficiency at Vo22 8V Efficiency Efficiency 2 0V Std 2 0V Sync 9 2 0V Sync Lo Rds 2 5V Std 2 5V Sync 2 5 Sync Lo Rds 8 lo Amps Typical Efficiency at Vo 2 5V Typical Efficiency at Vo 2 0V lo Amps Tek 20 5 5 Tek Run 200kS s 7 5 250 5 Chi J 45 2mV Zim M 2 3 s Chl 9 2 MA 20mv 250 Typical Ripple Vo 2 8V lo 10A Transient Response Vo 2 8V lo 300mA to 10A 7 1999 SEMTECH CORP 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC DC P SERATECH conv
9. erter DUAL Low DROPOUT REGULATOR CONTROLLER Today s Results lemerrow s Vision October 25 1999 LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1164 5 PWM controller High currents switching at 200kHz are pre sent in the application and their effect on ground plane voltage differentials must be understood and mini mized 1 The high power parts of the circuit should be laid out first A ground plane should be used the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane in tegrity Isolated or semi isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas for example the in put capacitor and bottom FET ground 2 The loop formed by the Input Capacitor s Cin the Top FET Q1 and the Bottom FET Q2 must be kept 12V IN o 5 1164 5 as small as possible This loop contains all the high cur rent fast transition switching Connections should be as wide and as short as possible to minimize loop induc tance Minimizing this loop area will a reduce EMI b lower ground injection currents resulting in electrically cleaner grounds for the rest of the system and c mini mize source ringing resulting in more reliable gate switching signals 3 The connection between the junction of Q1 Q2 and the output inductor should be a wide tra
10. g Temperature Range 0 to 70 Junction Temperature Range to 125 Storage Temperature Range 65 to 150 Lead Temperature Soldering 10 seconds 300 Thermal Impedance Junction to Ambient 80 Thermal Impedance Junction to Case 25 ELECTRICAL CHARACTERISTICS Unless specified VCC 4 75V to 5 25V GND PGND OV VOSENSE Vo OmV lt CS CS lt 60mV LDOV 11 4V to 12 6V 25 C PARAMETER CONDITIONS MIN TYP Switching Section Output Voltage lo 2 Supply Voltage VCC 4 5 Supply Current VCC 5 0V Load Regulation lo 0 8A to 15A Line Regulation Current Limit Voltage Oscillator Frequency Oscillator Max Duty Cycle Peak DH Sink Source Current BSTH DH 4 5V DH PGNDH 3V Peak DL Sink Source Current BSTL DL 4 5V DL PGNDL 3V Output Voltage Tempco Gain Ao VOSENSE to Vo OVP threshold voltage OVP source current 3 0V Power good threshold voltage Dead time Linear Sections Quiescent current LDOV 12V Output Voltage LDO1 SC1164 Output Voltage LDO2 SC1164 Reference Voltage SC1165 Feedback Pin Bias Current SC1165 Gain Ao LDOS 1 2 to GATE 1 2 Load Regulation 0 to 8A Line Regulation Output Impedance Notes 1 See Output Voltage table 2 In application circuit 1999 SEMTECH CORP 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNC
11. k used For the sur face mount packages on double sided FR4 2 oz printed circuit board material thermal impedances of 40 C W for the D PAK and 80 C W for the SO 8 are readily achievable The corresponding temperature rise is de tailed below Temperature rise C Top FET Bottom FET 49 6 39 0 31 6 24 8 122 4 96 1 With 20 C W Heatsink It is apparent that single SO 8 Si4410 are not adequate for this application but by using parallel pairs in each posi tion power dissipation will be approximately halved and temperature rise reduced by a factor of 4 1999 SEMTECH CORP PROGRAMMABLE SYNCHRONOUS DC DC SERATECH converter DUAL Low DROPOUT REGULATOR CONTROLLER 5 1164 5 CAPACITORS since the RMS ripple current in the input capacitors may be as high as 50 of the out put current suitable capacitors must be chosen ac cordingly Also during fast load transients there may be restrictions on input di dt These restrictions require useable energy storage within the converter circuitry either as extra output capacitance or more usually additional input capacitors Choosing low ESR input capacitors will help maximize ripple rating for a given size 11 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC DC eC4464 5 P SENTECH converter DUAL LOW DROPOUT REGULATOR CONTROLLER October 25 1999 OUTLINE DRAWING SO 24 A
12. le 3 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC DC SC1164 5 5 SERATECH converter DUAL LOW DROPOUT REGULATOR CONTROLLER October 25 1999 OUTPUT VOLTAGE Unless specified VCC 5 00V GND PGND VOSENSE Vo lt CS CS lt 60mV 25 C CONDITIONS 2A in Application Circuit 4 1999 SEMTECH CORP 652 MITCHELL ROAD NEWBURY PARK CA 91320 5 1164 5 PROGRAMMABLE SYNCHRONOUS DC DC SERATECH converter DUAL Low DROPOUT REGULATOR CONTROLLER Today s Results lomerrow s Vision 4 25 1999 1N3Sdud 1 38 NYO NIINIA dl GAYINOAY 218 s 371971 sADVLIOA LNdLNO ONILLAS 336 AS L 31VH3N39 OL ZNITA OL A1193HIG PNId 25041 LOANNOO 2 AS2 31VH3N39 OL INITA OL ATLOSUIG ENId 15007 LOANNOO GSYINOAY LON ANY ELH ZLH 991106 HOS ALON jnoee 77 222 Jnoee Jno ATIVINHON NIA euo HO 9SSxng8 595 91125 Anoost Anoost 3 gssyna posa co 3HOO ISNAS OA
13. nger leading to an output volt age sag below the ESR excursion calculated above The maximum inductor value may be calculated from lt Resa C t Vin Vo The calculated maximum inductor value assumes 100 duty cycle so some allowance must be made Choosing an inductor value of 50 to 75 of the calculated maxi mum will guarantee that the inductor current will ramp 1999 SEMTECH CORP 5 1164 5 fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags hence en suring a good recovery from transient with no additional excursions We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10 of maximum output current as ripple current Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capac itor ESR Ripple current can be calculated from Vin LRIPPLE 4 L fosc Ripple current allowance will define the minimum permit ted inductor value POWER FETS The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability TOP FET The power dissipation in the top FET is a combination of conduction losses switching losses and bottom FET body diode recovery losses a Conduction losses are simply calculated as Poon b Roson where 6 duty cycle Ao Vin b Switching los
14. ons between Cout and the load must be short wide cop per areas to minimize inductance and resistance 5 The SC1164 5 is best placed over a quiet ground plane area avoid pulse currents in the Cin Q1 Q2 loop flowing in this area PGNDH and PGNDL should be returned to the ground plane close to the package The AGND pin should be connected to the ground side of one of the output capacitor s If this is not possible the AGND pin may be connected to the ground path between the Output Capacitor s and the Cin Q1 Q2 loop Under no circumstances should AGND be returned to a ground inside the Cin Q1 Q2 loop 6 Vcc for the SC1164 5 should be supplied from the 5 1164 5 REGULATOR CONTROLLER supply through a 100 resistor the Vcc pin should be decoupled directly to AGND by a 0 1uF ceramic capacitor trace lengths should be as short as possi ble 7 The Current Sense resistor and the divider across it should form as small a loop as possible the traces running back to CS and CS on the SC1164 5 should run parallel and close to each other The 0 1uF ca pacitor should be mounted as close to the CS and CS pins as possible 8 Ideally the grounds for the two LDO sections should be returned to the ground side of one of the output capacitor s Vout Currents in various parts of the power section 1999 SEMTECH CORP 9 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC DC P S
15. ses can be estimated by assuming a switching time if we assume 100ns then Paw lo Vy dg or more generally lo t ty fosc 4 Psw d c Body diode recovery losses are more difficult to esti mate but to a first approximation it is reasonable to as sume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on The resulting power dissipation in the top FET will be Pag Qaa gt fosc To a first order approximation it is convenient to only consider conduction losses to determine FET suitability For a 5V in 2 8V out at 14 2A requirement typical FET losses would be 10 652 MITCHELL ROAD NEWBURY PARK CA 91320 p Today s Results Tomorrow s Vision October 25 1999 Package Rosjon MQ 22 7 0 13 5 TO220 D PAK SO 8 BOTTOM FET Bottom FET losses are almost entirely due to conduction The body diode is forced into conduc tion at the beginning and end of the bottom switch con duction period so when the FET turns on and off there is very little voltage across it resulting in low switching losses Conduction losses for the FET can be deter mined by lo Rog 1 8 For the example above Package TO220 D PAK SO 8 Each of the package types has a characteristic thermal impedance for the TO 220 package thermal impedance is mostly determined by the heatsin
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SEMTECH SC1164/5 handbook