SEMTECH SC1112 handbook
Contents
1. Temp nei Part Number Package Range T 5VSTBY 1 GND SC1112STR PWRGD 2 VTTIN SO 16 0 to 125 C DELAY 3 VTTGATE SC1112ASTR ess SC1112TSTR AGPSEL 5 Ge TSSOP 16 0 to 125 C ADJGATE 6 AGPSEN SC1112ATSTR ADJSEN 7 FC CAP 8 CAP SC1112EVB Evaluation Board Note 16 Pin SOIC or TSSOP 1 Only available in tape and reel packaging A reel contains 2500 devices 2 Part Number SO 16 SC1112STR 1 25V and SC1112ASTR 1 2V we Part Number TSSOP 16 SC1112TSTR 1 25V and Pin Descriptions SC1112ATSTR 1 2V Pin Name Pin Function 5VSTBY 5V Standby input supplies power for Ref Charge Pump Oscillator and FET controllers PWRGD Open collector Power Good Flag for VTT output A capacitor from this pin to GND will program the delay for the Power Good Flag of VTT output and the glitch immunity time TTL signal that programs the VTT output voltage VTTSEL LOW VTT 1 2XV VTTSEL HIGH VTT 1 5V AGPSEL TTL signal that programs the AGP output voltage AGPSEL LOW AGP 1 5V AGPSEL HIGH AGP 3 3V ADJGATE Gate drive output for AGP ADJSEN Sense input for ADJ CAP Negative connection to boost capacitor CAP Positive connection to boost capacitor FC Filter capacitor for the internal charge pump should be connected from this pin to GN2. 800 270 z 3 2 250 3 g 750 E a a S 3 230 700 210 190 650 170 180 600 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C 2001 Semtech Corp 12 www semtech com SC1112 pi d SEMTECH POWER MANAGEMENT Typical Characteristics Cont I 5V Stby vs Ta Output Select Threshold vs Ta 7 50 1 60 TTSEL 730 4 AGPSEL 1 55 740 150 6 90 B em S 145 2 G E B 650 s 140 a 2 6 30 s amp 135 s 8 6 10 1 30 5 90 SV Siby 5 25V N 5V Stby 5 00V e 5V Sty 475V 125 5 70 5 50 120 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C Line Regulation VTTIN 3 13V to 3 47V lo 2A vs Ta Load Regulation VTTIN 3 3V lo 0 to 2A vs Ta 160 0E 3 180 0E 3 140 0E 3 170 0E 3 120 0E 3 160 0E 3 g 103 g 150 0E 3 2 s 800E3 3 140 0E 3 Z g 3 2 60 0E3 130 0E 3 40 0E 3 120 0E 3 VTT 1 25V VTT 125V 4 AGP 1 25V 4 AGP 1 25V 20 0E 3 110 0E 3 000 0E 0 100 0E 3 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C Charge Pump Output Voltage vs Ta Charge Pump Frequency vs Ta 9 32 375 V Charge Pump 9 31 4 Charge Pump Frequency
3. Ta C VTT 1 25V Output Voltage lo OA vs Ta RV Stby 5 25V RRV Stby 5 00V KRN Stby 4 75V 10 20 30 40 50 60 70 Ta C VTT Input Supply Threshold vs Ta e EN Stby 4 75V NI 5V Stby 5 00V sv Stby 5 25V Ta C 2001 Semtech Corp VTT AW VTT 2 V 1 5035 1 5030 1 5025 1 5020 VTT 1 5V Output Voltage lo 2A vs Ta 1 5015 1 5010 1 5005 5V Stby 5 25V m 5V Stby 5 00V dec BN Stby 4 75V 1 5000 1 4995 0 10 20 30 40 50 60 70 Ta C VTT 1 5V Output Voltage lo 2A vs Ta 1 2465 1 2460 1 2455 1 2450 1 2445 1 2440 1 2435 SN Stby 5 25V E 5V Stby 5 00V 4 5V Stby 4 75V 1 2430 1 2425 0 10 20 30 40 50 60 70 Ta C VTT Sense Bias current vs Ta 116 sV Stby 5 25V REM Siby 5 00V k 5V Siby 4 75V 114 112 lt z a 110 E oO g 108 106 104 0 10 20 30 40 50 60 70 www semtech com SC1112 ran p SEMTECH Typical Characteristics Cont VTT Gate Current Vgate 3V 5V Stby 4 75V vs Ta VTT Short circuit Delay source current vs Ta 800 23 60 5V Stby 5 25V ir Source current IMI 5V Stby 5 0
4. POWER MANAGEMENT Absolute Maximum Ratings Parameter Maximum 5VSTBY to GND 0 3 to 7 VTTSEN to GND 0 3 to 5 AGPSEN to GND 0 3 to 5 ADJSEN to GND 0 3 to 5 Operating Temperature Range T 0 to 70 Junction Temperature Range T 0 to 125 Storage Temperature Range 65 to 150 Lead Temperature Soldering 10 Sec 300 Thermal Resistance Junction to Ambient 0 130 Thermal Impedance Junction to Case 30 ESD Rating Human Body Model 2 Electrical Characteristics Unless specified 5VSTBY 4 75V to 5 25V VTTIN 3 3V T 25 C Parameter Symbol Conditions Supply 5VSTBY Supply Voltage 5VSTBY Supply Current L 5VSTBY 5V VTT Short Circuit Protection VTT Short Circuit Delay Timer Threshold 1 5 VTT Short Circuit Delay Time Cdelay SC l VTT Short Circuit Delay Source Current 22 VTT Short Circuit Threshold 700 VTT Power Good PWRGD Delay Timer Threshold PG 1 500 Delay TH PWRGD Threashold PG 1 085 TH_1 2 PWRGD Threashold PG 1 350 TH_1 5 PWRGD Delay Time PG Cdelay PG td_1 2 THA BI PWRGD Delay Time PO i5 Cdelay PG PWRGD Source Current 22 Linear Sections TH 1 PL VTT Input Supply Threshold Tracking Difference 09 2001 Semtech Corp 2 www semtech com SC1112 ra p SEMTECH Electrical Characteristics Cont Unless specified 5VSTBY 4 75V to 5 25V
5. 9 30 370 9 29 E E 365 _ 9 28 s 2 a E 9 27 H a 9 360 o Qa 8 9 26 E lt 2 o a 7 925 S 355 o 9 24 9 23 350 9 22 9 21 345 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C 2001 Semtech Corp 13 www semtech com F P SEMTECH Typical Gain amp Phase Margin POWER MANAGEMENT C1112 Gain Phase VTT 1 25V 2A 60 200 Gain Phase d 50 E se ee FT 60 Gain m E 160 140 30 X Phase 120 amp 20 N KJ X 100 s 10 80 0 60 i 40 20 20 30 0 10 100 1000 10000 100000 1000000 Freq Hz SC1112 Gain Phase ADJ 1 2V 2A 50 200 Gain L PPhase deg 180 40 MR Gain ge 30 140 20 N 120 a Phase e 10 100 s 6 H 80 0 60 10 40 20 20 30 0 10 100 1000 10000 100000 1000000 Freq Hz 2001 Semtech Corp Phase deg Phase deg 14 Gain dB Gain dB SC1112 SC1
6. H MM INCHES MIN MAX Ka 193 1 201 169 1 177 252 BSC 026 BSC 007 012 002 006 047 Aejommpomp 004 008 0 8 DIR S 9 L 1 018 030 JEDEC MO 153AB www semtech com 2001 Semtech Corp ra P SEMTECH SC1112 POWER MANAGEMENT Outline Drawing SO 16 mmm A fe SS TE a SK DETAIL A re N Z SEE DETAIL A DI DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTUSIONS Land Pattern SO 16 GRID PLACEME COURTYARD DIMENSIONS INCHES M MIN GRID PLACEMENT COURTYARD IS 22 X 16 11mm X 8mm IN ACCORDANCE WITH TH ELEMENTS E INTERNATIONAL GRID DETAILED IN IEC PUBLICATION 97 Contact Information Semtech Corporation Power Management Products Division 652 Mitchell Rd Newbury Park CA 91320 Phone 805 498 2111 FAX 805 498 3804 2001 Semtech Corp 21 www semtech com
7. VTTGATE initially turns on hard and is latched off when DELAY DELAY reaches 1 5V and VTT is below 0 7V PWRGD VTTGATE 2001 Semtech Corp 4 www semtech com SC1112 ran p SEMTECH Diagrams Co SHORT CIRCUIT DURING NORMAL OPERATION VTT Once VTT drops out of VTT 0 7V regulation VTTGATE turns on VTTEIOEV 7 harder to try and raise VTT When VTT drops below 1 08V the delay capacitor is l discharged and PWRGD goes low When VTT drops below DELAY 0 7V the delay capacitor begins charging DELAY 1 5V If VTT is still below 0 7V when DELAY reaches 1 5V 4 VTTGATE is latched off PWRGD VTTGATE RCUIT AND RECOVERY ING NORMAL OPERATION VTTIN Once VTT drops out of regulation VTTGATE turns on VTT harder to try and raise VTT l I l I f 4 I l I l I When VTT drops below 1 08V VTT 1 08V VTT 0 7V VTT 1 08V the delay capacitor is discharged I and PWRGD goes low When d 1 T I I I I I I I I I VTT drops below 0 7V the delay capacitor begins charging If VTT recovers above 0 7V before DELAY reaches 1 5V DELAY DELAY is again discharged If VTT reaches 1 08V the delay capacitor begins charging and normal operation continues PWRGD I I I I 4 4 4 2001 Semtech Corp 5 www semtech com SC1112 m P SEMTECH POWER MANAGEMENT Pin Configuration Ordering Information
8. 1 5V Power Good Delay Time vs Ta 1 361 8 40 g A 8 10 5 x E 2 E 2 a amp 8004 7 90 te 5V Siby 4 75V I 5V Stby 5 00V 5V Sby 5 25V 7 80 1 350 7 70 10 20 30 40 50 60 70 0 10 20 30 50 60 70 Ta C Ta C VTT Power Good Source current vs Ta 23 60 be DN Stby 5 25V E 5V Stby 5 00V Sa sVStby 475V 23 20 23 00 22 80 22 60 lt 3 2240 22 20 22 00 21 80 21 60 21 40 T T 10 20 30 50 60 70 Ta C www semtech com SC1112 lt p SEMTECH Typical Characteristics Cont AGP 1 5V Output Voltage lo OA vs Ta AGP 1 5V Output Voltage lo 2A vs Ta 1 5055 1 5035 1 5050 1 5045 1 5040 1 5035 1 5030 C a n E lt 1 5025 1 5020 15015 5V Siby 525V 14995 5V Siby 525V i 5V Stby 5 00V E 5V Stby 5 00V t DN Stby 4 75V dr 5V Stby 4 75V 1 5010 1 4990 1 5005 1 4985 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C AGP 3 3V Output Voltage lo OA vs Ta AGP 3 3V Output Voltage lo 2A vs Ta 3 2900 32900 3 2890 32890 3 2880 32880 3 2870 3 2870 s s d 3 2860 2 32860 S lt 3 28
9. VTTIN 3 3V T 25 C Parameter Symbol Conditions i Typ Linear Sections Cont Output Voltage VTT SC1112A 0 to 2A VITSEL LOW 1 200 VIS SC1112 0 to 2A VITSEL LOW 1 250 VII VTT 0 to 2A VTTSEL HIGH 1 500 Output Voltage AGP AGP 0 to 2A AGPSEL LOW 1 500 AGP 0 to 2A AGPSEL HIGH 3 300 Output Voltage ADJ ADJ 0 to 2A 1 2 1 RA RB VTTSEN Bias Current bias sen 120 SC1112 VTTSEN Bias Current bias rsen SC1112A AGPSEN Bias Current bias cpsen ADJSEN Bias Current IDiaS o igen VTT Gate Current ISOUICE 9VSTBY 4 75V Vgate 3 0V ISINK ate AGP Gate Current Fouen SVSTBY 4 75V Vgate 3 0V Isi H ADJ Gate Current Source je OVSTBY 4 75V Vgate 3 0V KH NK bugate Load Regulation LOAD VTTIN 3 30V 0 to 2A Line Regulation LINE peg VTTIN 3 13V to 3 47V lo 2A Gain AOL GAIN po LDOS Output to GATE Notes 1 All electrical characteristics are for the application circuit on page 19 2 Guaranteed by design 3 Tracking Difference is defined as the delta between 3 3V Vin and the VTT AGP ADJ output voltages during the linear ramp up until regulation is achieved The Tracking Voltage difference might vary depending on MOSFETs Rdson and Load Conditions 4 During power up an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTIN 1 5V During the glit
10. VTTSEL pin AGP output can also be prgorammed via AGPSEL pin to a 1 50V or a 3 30V The SC1112 also provides an Adjustable output which utilizes a resistive voltage divider The 5VSTBY supply will power the internal Reference Charge Pump Oscillator and the Fet controllers After the 5VSTBy has been established LDO outputs will track the VTTIN 3 30V supply as it is applied An external capaitor connected to the Delay pin will pro gram the VTT short circuit delay time SC and the PWRGD delay time PG During power up an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTIN 1 5V During the glitch timer immunity time determined by the Delay capacitor Delay time is approximately equal to Cdelay SCTH ISC the short circuit protection is disabled to allow VTT output to rise above the trip threashold O 7V If the VTT output has not risen above the trip threashold after the immunity time has elapsed the VTT output is latched off and will only be enabled again if either the VTT input voltage or the 5VSTBY is cycled PWRGD pin is kept low during the power up until the VTT output has reached its PG or PG level At that time the PWRGD source current I 20uA is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin Once the capacitor is charged above the PG 1 5V the PWRGD pin is released from ground A detailed timing diagram
11. is shown on pages 4 to 5 2001 Semtech Corp Also included is an overcurrent protection circuit that moni tors the VTT voltage If the output voltage drops below 700mV as would occur during an overcurrent or short condition the device will pull the drive pin low and latch off the output Fixed Output Voltage Options VTT AGP Please refer to the Application Circuit on Page 1 The VTT and the AGP fixed output voltage can be programed from a Control logic signal Table below shows the possible Volt ages VTTSEL AGPSEL AGP 1 50V pw Once the VTTSEL or the AGPSEL signal is established an internal resistive divider is used to compare the bandgap reference voltage with the feed back output voltage The drive pin voltage is then adjusted to maintain the output voltage set by the internal resistor divider Referring to the block diagram on page 7 3 30V Ls pope It is possible to adjust the output voltage of the VTT or AGP by applying an external resistor divider to the sense pin please referto Figure 1 on Page 11 Since the sense pin sinks a nominal 3100pgA the resistor values should be selected to allow 10mA to flow through the divider This will ensure that variations in this current do not adversely affect output voltage regulation Thus a target value for R2 maximum can be calculated R2 V aur FIXED 10mA The output voltage can only be adjusted upwards from the fixed output voltage and can be
12. 0V Sink current 23 40 5V Stby 4 75V 750 23 20 700 23 00 650 22 80 E 600 22 60 E 22 40 550 22 20 500 22 00 450 21 80 400 21 60 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C VTT Short circuit Delay Time Cdelay 0 1uF vs Ta 8 40 8 20 8 10 no 8 00 7 90 4 DN Stby 4 75V I 5V Stby 5 00V 5V Stby 5 25V 7 80 7 70 0 10 20 30 40 50 60 70 Ta C VTT Short circuit Delay Timer Threshold vs Ta 1 515 amp 5V Stby 4 75V I 5V Stby 5 00V 5V Stby 5 25V Ta C 2001 Semtech Corp 9 www semtech com SC1112 a P SEMTECH POWER MANAGEMENT Typical Characteristics Cont 1 098 VTT 1 25V Power Good Threshold vs Ta 2001 Semtech Corp 10 VTT 1 25V Power Good Delay Time vs Ta 8 30 8 20 8 40 B 8 30 1 094 8 20 1 092 S 1 090 g 8 10 1 088 3 amp 8 00 1 086 NN 7 90 1 084 ae 5V Siby 4 75V i 5V Stby 5 25V E 5V Stby 5 00V EB 5V Stby 5 00V 5V Stby 5 25V ABN Stby 4 75V 7 80 1 082 1 080 7 70 T T T T T 10 20 30 40 50 60 70 0 10 20 30 50 60 70 Ta C Ta C VTT 1 5V Power Good Threshold vs Ta VTT
13. 112 Gain Phase VTT 1 5V 2A 60 200 Gain gd Phase deg LC 180 Gain 160 40 L 140 30 120 20 Phase 100 10 80 0 60 e 40 20 20 30 r r 0 10 100 1000 10000 100000 1000000 Freq Hz SC1112 Gain Phase AGP 1 5V 2A 50 r4 200 Gain M OTAR Phase deg L 180 40 In Ga 160 30 L 140 120 20 Phase L 100 10 T 80 0 60 40 10 L 20 20 r r 0 10 100 1000 10000 100000 1000000 Freq Hz Phase deg Phase deg www semtech com a P SEMTECH SC1112 POWER MANAGEMENT Applications Infomation Theory Of Operation The SC1112 was designed for the latest high speed mother boards requiring a controled power up sequencing of the Outputs and a programable delay for the Power good sig nal Three Linear controllers have been incorperated into the SC1112 The VTT output can be programmed to either a 1 250V or a 1 500V by applying a LOW or a HIGH control signal to the
14. 50 32850 3 2840 5V Stby 5 25V 32840 ES SE RBU Siby 5 00V I 5V Stby 5 00V 3 2830 FR SV SIUE UON Ge svby 475V 3 2820 3 2820 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C AGP Sense Bias current vs Ta AGP Gate Current Vgate 3V 5V Stby 4 75 vs Ta M 5V Siby 5 25V CH lt Sink current E 5V Siby 5 00V 140 t 5V Stby 4 75V Source current 850 138 800 lt z 136 z 750 3 S 134 E 2 700 132 130 E 128 T T T T T T 600 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C 2001 Semtech Corp 11 www semtech com SC1112 a P SEMTECH POWER MANAGEMENT Typical Characteristics Cont ADJ 1 2V Output Voltage lo OA vs Ta ADJ 1 2V Output Voltage lo 2A vs Ta 1 2020 1 1955 4 2010 1 1950 1 1945 1 2000 1 1940 1 1990 1 1935 1 1980 1 1930 1 1970 ADJ 2 V ADJ V 5V Stby 5 25V ss m sV Stby 5 00V i 9 5V Stby 5 25V 5V Stby 4 75V m 5V Stby 5 00V 1 1960 de EN Stby 4 75V 1 1920 1 1950 14915 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Ta C Ta C ADJ Sense Bias current vs Ta ADJ Gate Current Vgate 3V BV Stby 4 75V vs Ta 950 a 5V Sby 4 75V 900 it 5V Stby 5 00V Sink current 55 EBU Siby 525V Source current 850
15. D AGPSEN Sense input for AGP AGPGATE Gate drive output for AGP VTTSEN Sense input for VTT VTTGATE Gate drive output for VTT VTTIN Short circuit sense line connected to the 3 3Vin GND Ground NOTE 1 Alllogic levelinputs and outputs are open collector T TL compatible 2001 Semtech Corp 6 www semtech com SC1112 ra P SEMTECH POWER MANAGEMENT Block Diagram 5VSTBY VTTSEL Bandgap VITGATE Reference i e Disablet 5 VTTSEN 1 2V O Disable1 2 C AGPGATE Disable1 5 AGPSEN 0 7V Disable3 3 LO Oscillator VTTSEN O ChargePump Pwrgd Threshold L 7 ADJGATE AGPSEL CAP CAP 2001 Semtech Corp 7 www semtech com a P SEMTECH POWER MANAGEMENT SC1112 Typical Characteristics 1 5055 1 5050 1 5045 1 5040 1 5035 VT V 1 5030 1 5025 1 5020 1 2485 1 2480 1 2475 1 2470 1 2465 YT AV 1 2460 1 2455 1 2450 1 2445 1 498 1 497 1 496 1 495 VTTINrH V 1 494 1 493 1 492 1 491 VTT 1 5V Output Voltage lo OA vs Ta EBU Stby 5 25V m sV Stby 5 00V amp 5V Stby 4 75V
16. Jnoeg L 4ni0 GE NOZIH3HI Ee O 6107F 897 69 gi 31V90dOV 13849Y Le 27 gp NASLLA TaSLLA L nyo l anoce gi 30Y911A AV130 L 19 39 WIDE gt ib sr MALA g9uMd gr 0M9 ABLSAS L D STTS I ai Or PAN anne u3MOd TT 29F v9 anyo 9 D i i t ABISAS www semtech com 19 2001 Semtech Corp ra p SESMTECH SC1112 POWER MANAGEMENT Evaluation Board Bill of Materials Reference Foot Print C1 10uF 1206 C2 06 C8 C12 014 C16 C18 C 19 330uF CPCYUD 2 75 LS 100 031 C3 C4 C7 C9 C11 013 C15 C17 0 1uF 0805 22nF 0805 1uF 0805 TP2 VIA 2P 5VSTBY ED5052 J2 J5 J7 J10 J12 J16 J17 J20 J21 GND ED5052 NM O O GO ND J3 J4 3 3V ED5052 e Power Good ED5052 ch VTT ED5052 D ADJ ED5052 zech Co J14 VTT SELECT Signal ED5052 A J15 AGP SELECT Signal ED5052 Ln J18 J19 AGP ED5052 c Q1 Q2 Q3 IRFR120N DPAKFET N R1 RA RB 1k 0805 CO R2 R3 100k 0805 ak cO U1 A ed III KD CONTROLLING DIMENSIONS MILLIMETERS e SEE DETAIL ENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSIONS SC1112STR SO 16 DIMENSIONS
17. Vall Ce CO SEMTECH P SC1112 Triple Low Dropout Regulator Controllers POWER MANAGEMENT The SC1112 was designed for the latest high speed motherboards It includes three low dropout regulator con trollers The controllers provide the power for the system AGTL bus Termination Voltage Chipset and clock circuitry An adjustable controller with a 1 2V reference is available while two selectable outputs are provided for the VTT 1 25 V or 1 5V SC1112 or 1 2V or 1 5V SC1112A and the AGP 1 5V or 3 3V The SC1112 low dropout regulators are designed to track the 3 3V power supply as the VTTIN supply is cycled On and Off A latched short circuit protection is also available for the VTT output Other features include an integrated charge pump that provides adequate gate drives for the external Mosfets and a capacitive programable delay for the power good signal Typical Application Circuit Revision 7 October 2001 Features Triple linear controllers Selectable and Adjustable Output Voltages LDOs track input voltage within 200mV Function of the Mosfets used until regulation Integrated Charge Pump Programmable Power Good delay Signal Latched Over Current Protection VTT 060 99 Applications Pentium III Motherboards Triple power supplies o 5V STBY C19 C8 330u T 330u 0 1u T AGP SELECT Signal www semtech com SC1112 tm P SEIVIT ECH
18. calculated using the following equation R1 Vour ADJUSTED Vour xp az Ris100uA Volts 15 www semtech com SC1112 ran p SEMTECH Applications Infomation Cont e o 3 3V I o 5V STBY C1 I 10u SC1112 amp 5VSTBY GND as c ADJGATE AGPGATE Le 330u ADJSEN AGPSEN e o GP car 2 C18 1 SA Ke eil 330u C16 C17 CAP VTTSEN He 0 1u H Ki FC AGPSEL ov DELAY VTTSEL zx C19 C8 C9 ue UR m 3300 ru F R1 VTT SELECT Signal AGP SELECT Signal Figure 1 Adjusting The Output Voltage of VTT or AGP Adjustable Output Voltage Option The adjustable output voltage option does not have an internal resistor divider The adjust pin connects directly to the inverting input of the error amplifier and the output voltage is set using external resistors please refer to Figure 2 In this case the adjust pin sources a nominal O SyA so the resistor values should be selected VTT to allow SOA to flow through the divider Again a target S value for RB maximum can be 1K calculated R1 POWER GOOD S 5VSTBY RB lt 1 200 V ADJGATE BOpBA ADJSEN The output voltage can be calculated as follows Vout 1 200 al 0 5uA RA RB The maximum output voltage that can be obtained from the adjustable option is determined by the input supply voltage and the Rss and
19. ch timer immunity time determined by the Delay capacitor Delay time is approximately equal to Cdelay SCTH ISC the short circuit protection is disabled to allow VTT output to rise above the trip threshold 0 7V If the VTT output has not risen above the trip threshold after the immunity time has elapsed the VTT output is latched off and will only be enabled again if either the VTT input voltage or the 5VSTBY is cycled 5 PWRGD pin is kept low during the power up until the VTT output has reached its PG Or PG s level At that time the PWRGD source current I 20UA is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin Once the capacitor is charged above the PG 1 5V the PWRGD pin is released from ground Delay TH 2001 Semtech Corp 3 www semtech com SC1112 a P SEMTECH POWER MANAGEMENT Timing Diagrams NORMAL STARTUP CONDITION VTTIN VTTIN 1 5V VTT The delay capacitor does not begin charging until VTTIN has reached 1 5V and VTT is above the powergood threshold of 1 08V Once DELAY reaches 1 5V the PWRGD signal goes high DELAY VTTGATE initially turns on hard until VTT reaches regulation Then VTTGATE drops to its normal regulating level 4 4 SHORT CIRCUIT STARTUP VTTIN VTTIN 1 5V VTT The delay capacitor does not begin charging until VTTIN has reached 1 5V and VTT is below the short circuit threshold of 0 7V
20. d from a 3 3V 596 rail the maximum allowable Ro gon WOuld be _ 0 95 3 3 1 5 1 025 R os oN max 4 400 m Q To allow for temperature effects 200mQ would be a suitable room temperature maximum allowing a peak short circuit current of approximately 15A for a short time before shutdown Capacitor Selection Output Capacitors low ESR aluminum electrolytic or tan talum capacitors are recommended for bulk capacitance with ceramic bypass capacitors for decoupling high frequency transients Input Capacitors placement of low ESR aluminum electrolytic or tantalum capacitors at the input to the MOSFET VTTIN will help to hold up the power supply during fast load changes thus improving overall transient response The 5VSTBY supply should be bypassed with a 10yF ceramic capacitor 2001 Semtech Corp Layout Guidelines One of the advantages of using the SC1112 to drive an external MOSFET is that the bandgap reference and control circuitry do not need to be located right next to the power device thus a very accurate output voltage can be obtained since heating effects will be minimal The O 1uF bypass capacitor should be located close to the 5VSTBY supply pin and connected directly to the ground plane The ground pin of the device should also be con nected directly to the ground plane The sense or adjust pin does not need to be close to the output voltage plane but should be routed to avoid noisy traces if at al
21. gate threshold voltage of the external MOSFET Assuming that the MOSFET gate threshold voltage is sufficiently low for the output voltage chosen and a worst case drive voltage of 9V V is given by Figure 2 OUT MAX VOUT MAX VTTIN mn lout max Rps oN MAX 2001 Semtech Corp 16 www semtech com LS P SEMTECH SC1112 POWER MANAGEMENT Applications Infomation Cont Short Circuit Protection The VTT short circuit protection feature of the SC1112 is implemented by using the R of the MOSFET As the output current increases the regulation loop maintains the output voltage by turning the FET on more and more Eventually as the Rs limit is reached the MOSFET will be unable to turn on any further and the output voltage will start to fall When the VTT output voltage falls to approximately 700mV the LDO controller is latched off setting output voltage to OV Power must be cycled to re set the latch To prevent false latching due to capacitor inrush currents or low supply rails the current limit latch is initially disabled It is enabled once the short circuit delay time has elapsed Timing diagram on pages 4 to 5 will show a detailed operation of the Short circuit protection circuitry should not be To be most effective the MOSFET R son selected artificially low The MOSFET should be chosen so that at maximum required current it is almost fully turned on If for example a supply of 1 5V at 4A is require
22. l pos sible Power dissipation within the device is practically negligible requiring no special consideration during layout 17 www semtech com tm P SEIVIT ECH SC1112 POWER MANAGEMENT Evaluation Board Gerbers J1 d J4 JS J5 SVSTBY GND 3 5V d rm co J14 QNIT SELECT J15 Quer SELECT ne m J 9 1760 2001 Semtech Corp ZA p 5 e e N a Board Layout Assembly Top SC1112 Evaluation Board Revision la SEMTECH 2001 httpi www sentech cosa Board Layout Top Board Layout Assembly Bottom Board Layout Bottom 18 www semtech com SC1112 Va P SEIVIT ECH POWER MANAGEMENT E D is o 0 D e m c 2 gt DI QN9 ler QN9 oer dov 6r d SIT QN9 zir QN9 opf 11A 6f LIA 8f QNO Ar QNO or Age bP Age EI QNO zr AGLSAS LP ASI dOV lHOHS dr A ZX A A d9 V N3dO df ASZL7 LLA LYOHS Id pem Fate 919 His AG L 1LA N3dO Idf ee A T Zdr ie Ldr I O Ir aN9 be O 9ir QNO WIDE OR gu 0 s jnogg L 4npo lOF eu Ann 19 jeubis 193138 d9V Ljnpg L 3noe au vu i z 1 rav Dee 819 Troun O leuis 109313S LLA vu an dV9 dv9 La SS Oeir rav J wo L 04 nasrav ray O H ray Angee
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SEMTECH SC1112 handbook