National LMX2522/LMX2532 handbook
Contents
1. D Register IF_FREQ 1 0 IF Frequency Selection 00 170 76 MHz LMX2532LQ0967 01 367 20 MHz LMX2532LQ1065 10 440 76 MHz LMX2522LQ1635 OSC_FREQ Reference Frequency Selection 0 19 20 MHz 1 19 68 MHz SPUR_RDT 1 0 Spur Reduction Scheme 00 No spur reduction 01 Not Used 10 Continuous tracking of variation Recommended 11 One time optimization OB_CRL 1 0 RF Output Power Control 00 Minimum Output Power 01 10 11 Maximum Output Power RF Enable 0 RF Off 1 RF On IF_EN IF Enable 0 IF Off 1 IF On 13 www national com CEGCXINT ZZSZXNT LMX2522 LMX2532 Programming Description Continued R2 REGISTER The R2 Register address bits R2 1 0 are 10 The IF_CUR 1 0 bits program the IF charge pump current Considering the external IF VCO and loop filter the user can select the amount of IF charge pump current to be 100A 200A 300HA or 800A R2 REGISTER SHIFT REGISTER BIT LOCATION Register R2 IF_ Default CUR 1 0 16 15 14 13 Data Field 12 11 10 9 8 7 6 5 Address Field Name IF_CUR 1 0 Functions IF Charge Pump Current 00 100 pA 01 200 pA 10 300 pA 11 800 pA www national com Programming Description Continued R3 REGISTER The2. Programming Description continued R1 REGISTER The R1 register address bits R1 1 0 are 01 The IF_FREQ bits selects the default IF frequency applicable to the specific CDMA system For the LMX2522 the default IF frequency is 440 76 MHz and for the LMX2532 the default IF frequencies are 367 20 MHz and 170 76 MHz depending on variant Reference Frequency Selection bit OSC_FREQ selects either 19 20 MHz or 19 68 MHz for the reference oscillator frequency The internal spurious reduction scheme is controlled by the SPUR_RDT 1 0 bits There are two different spur reduction schemes a continuous tracking mode and a single optimization mode The continuous tracking mode will adjust for variations in voltage and temperature The single optimization mode fixes the internal compensation parameters only when the PLL goes into the locked state The spur reduction can also be disabled but it is recommended that the continuous mode be used for normal operation The OB_CRL 1 0 bits determine the power level of the RF output buffer The power level is set according to the system requirement The two bits RF_EN and IF_EN logically select the active state of the RF GPS synthesizer system and the IF PLL respectively The entire IC can be placed in a power down state by using the CE control pin pin 20 R1 REGISTER SHIFT REGISTER BIT LOCATION LSB 16 15 14 13 12 11 10 9 8 7 6 0 Data Field Address Field
3. FIGURE 1 Lock Detect Timing Diagram Waveform Note 9 LD output becomes low when the phase error is larger than two Note 10 LD output becomes high when the phase error is less than ty for four or more consecutive cycles Note 11 Phase Error is measured on leading edge Only errors greater than tw1 and two are labeled Note 12 ty and tw2 are equal to 10 ns Note 13 The lock detect comparison occurs with every 64th cycle of fg and fy www national com Functional Description Continued MICROWIRE INTERFACE The programmable register set MICROWIRE serial interface The interface comprises three signal pins CLK DATA and LE Serial data DATA is LD HIGH i Phase Error gt ty FIGURE 2 Lock Detect Flow Diagram is accessed via the START LD LOW Not Locked 7 Phase Error lt ty 7 Phase Error lt ty 7 Phase Error lt ty Phase E 20067206 clock CLK The last bits decode the internal control register clocked into the 24 bit shift register on the rising edge of the address When the Latch Enable LE transitions from LOW to HIGH data stored in the shift registers is loaded into the corresponding control register www national com CEGCXINT ZZSZXNT LMX2522 LMX2532 Programming Description CONTROL REGISTER CONTENT MAP The serial interface has a 24 bit shift register to store the incoming data bits temporarily The incoming Data is loaded into th
4. www national com Functional Description GENERAL DESCRIPTION LMX2522 32 is a highly integrated frequency synthesizer system that generates LO signals for PCS Cellular CDMA and GPS systems These devices include all of the func tional blocks of a PLL RF VCO prescaler RF phase detec tor and loop filter The need for external components is limited to a few passive elements for matching the output impedance and bypass elements for power line stabilization In addition to the RF circuitry the IC also includes IF fre quency dividers and an IF phase detector to complete the IF synthesis with an external VCO and loop filter Table 4 summarizes the counter values to generate the default IF frequencies Using a low spurious fractional N synthesizer based on a delta sigma modulator the circuit can support 10 kHz chan nel spacing for PCS Cellular CDMA and GPS systems The fractional N synthesizer enables faster lock time which reduces power consumption and system set up time Addi tionally the loop filter occupies a smaller area as opposed to the integer N architecture This allows the loop filter to be embedded into the circuit minimizing the external noise coupling and total form factor The delta sigma architecture delivers very low spurious which can be a significant prob lem for other PLL solutions The circuit also supports commonly used reference frequen cies of 19 20 MHz and 19 68 MHz FREQUENCY GENERATION RF
5. 800 HA DIGITAL INTERFACE DATA CLK LE LD CE Vin High Level Input Voltage Vop V Voc V Vit Low Level Input Voltage 0 2 Vop V 0 2 Voc V la High Level Input Current 10 yA liv Low Level Input Current 10 yA Input Capacitance 3 pF Vou High Level Output Voltage V V Voi Low Level Output Voltage 0 1 Vbo V 0 1 Voc V Output Capacitance 5 pF www national com CEGCXINT ZZSZXNT LMX2522 LMX2532 Electrical Characteristics Vcc Voo 2 8 V T 25 C unless otherwise noted Continued Symbol Parameter Conditions Min Typ Max Units MICROWIRE INTERFACE TIMING tes Data to Clock Set Up Time ns tes Clock to Latch Enable Set Up Time ns tew Latch Enable Pulse Width 50 ns Note 4 In power down mode set DATA CLK and LE pins to 0 V GND Note 5 The reference frequency must also be programmed using the OSC_FREQ control bit For other reference frequencies please contact National Semiconductor Note 6 For other frequency ranges please contact National Semiconductor Note 7 Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within 1 kHz of the final frequency Note 8 Frequencies other that the default value can be programmed using Words R4 and R5 See Programming Description for details Serial Data Input Timing DATA MSB X LSB CLK towL LE _ M tes tes teH towH tew 20067204
6. MHz MHz Marking Supplied As LMX2522LQX1635 1619 62 1649 62 1635 440 76 1355 04 25221635 4500 units on tape and reel 1000 units on tape and reel LMX2522LQ1635 1619 62 1649 62 1355 04 25221635 LMX2532LQX0967 954 42 979 35 1490 04 25320967 4500 units on tape and reel LMX2532LQ0967 954 42 979 35 1490 04 25320967 1000 units on tape and reel LMX2532LQX1065 1052 64 1077 57 367 20 1391 82 25321065 4500 units on tape and reel LMX2532LQ1065 1052 64 1077 57 1065 367 20 1391 82 25321065 1000 units on tape and reel Part Number Description LMX2522 LQ X 1635 L 1635 RF Center LMX2522 Root Part Frequency approx LQ Leadless Leadframe Package LLP X 4500 units supplied on Tape and Reel 20067203 www national com CEGCXINT ZZSZXNT LMX2522 LMX2532 Absolute Maximum Ratings notes 1 2 3 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Symbol Ratings Units Voc Vpp 0 3 to 3 6 V Parameter Supply Voltage Voltage on any pin to GND Storage Temperature Tstg Range Vi 0 3 to Vpp 0 3 0 3 to Vcc 0 3 65 to 150 C Recommended Operating Conditions Parameter Symbol Min Typ Max Units Supply Votage to GND Veo Vool27 33 v Note 1 Absolute Maximum Ratings indicate limits beyond wh
7. PLL Section The divide ratio can be calculated using the following equa tion LMX2522 PCS CDMA fvco 8 x RF_B RF_A RF_FN fosc x 107 x fosc where RF_A lt RF_B LMX2532 Cellular CDMA fvco 6 x RF_B RF_A RF_FN fosc x 104 x fosc where RF_A lt RF_B where fyco Output frequency of voltage controlled oscillator VCO RF_B Preset divide ratio of binary 4 bit programmable counter 2 lt RF_B lt 15 RF_A Preset divide ratio of binary 3 bit swallow counter 0 lt RF_A lt 7 for LMX2522 or 0 lt RF_A lt 5 for LMX2532 RF_FN Preset numerator of binary 11 bit modulus counter 0 lt RF_FN lt 1920 for fosc 19 20 MHz or 0 lt RF_FN lt 1968 for fosc 19 68 MHz fosc Reference oscillator frequency GPS PLL SECTION The divide ratio can be calculated using the following equa tion LMX2522 PCS CDMA fyco 6 x RF_B RF_A RF FN fosc X 107 X fosc where RF_A lt RF_B LMX2532 Cellular CDMA fyco 8 x RF_B RF_A RF FN fosc x 107 x fosc where RF_A lt RF_B where fvco Output frequency of voltage controlled oscillator VCO RF_B Preset divide ratio of binary 4 bit programmable counter 2 lt RF_B lt 15 RF_A Preset divide ratio of binary 3 bit swallow counter 0 lt RF_A lt 5 for LMX2522 or 0 lt RF_A lt 7 for LMX2532 RF_FN Preset numerator of binary 11 bit modulus counter 0 lt RF_FN lt 1920 for fosc 19 20 MHz or 0 lt RF_
8. 0 0 LMX25221 0 O National Semiconductor LMX2522 LMX2532 PLLatinum Frequency Synthesizer System with Integrated VCOs General Description LMX2522 and LMX2532 are highly integrated high perfor mance low power frequency synthesizer systems optimized for Korean PCS K PCS with GPS and Korean Cellular K Cellular with GPS CDMA 1xRTT IS 95 mobile hand sets Using a proprietary digital phase locked loop tech nique LMX2522 and LMX2532 generate very stable low noise local oscillator signals for up and down conversion in wireless communications devices LMX2522 and LMX2532 include a RF voltage controlled oscillator VCO a GPS VCO a loop filter and a fractional N RF PLL based on a delta sigma modulator In concert these blocks form a closed loop RF and GPS synthesizer system LMX2522 supports the Korean PCS band with GPS and LMX2532 supports the Korean Cellular band with GPS LMX2522 and LMX2532 include an Integer N IF PLL also For more flexible loop filter designs the IF PLL includes a 4 level programmable charge pump Together with an exter nal VCO and loop filter LMX2522 and LMX2532 make a complete closed loop IF synthesizer system Serial data is transferred to the device via a three wire MICROWIRE interface DATA LE CLK Operating supply voltage ranges from 2 7 V to 3 3 V LMX2502 and LMX2512 feature low current consumption 17 mA at 2 8 V LMX2522 and LMX2532 are available in a 28 pin leadless leadframe
9. FN lt 1968 for fosc 19 68 MHz fosc Reference oscillator frequency PCS CDMA applications using the LMX2522 if the GPS frequency is 1355 04 MHz Table 1 provides the proper register settings TABLE 1 Settings for GPS 1355 04 MHz in LMX2522 PCS CDMA application Reference Frequency RFB RFA RF_FN Cellular CDMA applications using the LMX2532 in which the GPS frequency is 1490 04 MHz then Table 2 provides the proper register settings TABLE 2 Settings for GPS 1490 04 MHz in LMX2532 Cellular CDMA application Reference Frequency 19 20 MHz 19 68 MHz Cellular CDMA applications using the LMX2532 in which the GPS frequency is 1391 82 MHz then Table 3 provides the proper register settings TABLE 3 Settings for GPS 1391 82 MHz in LMX2532 Cellular CDMA application Reference Frequency RF_B RF_A RF_FN C nam o 0 om C oeme e 6 1422 IF PLL SECTION fvco 16 x IF_B IF_A x fosc IF_R where IF_A lt IF_B where fvco Output frequency of the voltage controlled oscillator VCO IF_B Preset divide ratio of the binary 9 bit programmable counter 1 lt IF_B lt 511 IF_A Preset divide ratio of the binary 4 bit swallow counter 0 lt IF_A lt 15 fosc Reference oscillator frequency IF_R Preset divide ratio of the binary 9 bit programmable reference counter 2 lt IF_R lt 511 From the above equation the LMX2522 32 generates the fixed
10. IF frequencies as summarized in Table 4 www national com CEGCXINT ZZSZXNT LMX2522 LMX2532 Functional Description Continued TABLE 4 IF Frequencies Device Type fvco IF_B IF_A fosc IF_R MHz kHz LMX2522LQ1635 440 76 229 9 120 LMX2532LQ0967 170 67 88 15 120 LMX2532LQ1065 367 20 191 4 120 VCO FREQUENCY TUNING The center frequency of the RF VCO is mainly determined by the resonant frequency of the tank circuit This tank circuit is implemented on chip and requires no external inductor The LMX2522 32 actively tunes the tank circuit to the re quired frequency with the built in tracking algorithm BANDWIDTH CONTROL AND FREQUENCY LOCK During the frequency acquisition period the loop bandwidth is significantly extended to achieve frequency lock Once frequency lock occurs the PLL will return to a steady state condition with the loop bandwidth set to its nominal value The transition between acquisition and lock modes occurs seamlessly and extremely fast thereby meeting the strin gent requirements associated with lock time and phase noise Several controls BW_DUR BW_CRL and BW_EN are used to optimize the lock time performance SPURIOUS REDUCTION To improve the spurious performance of the device one of two types of spurious reduction schemes can be selected e A continuous optimization scheme which tracks the en vironmental and voltage variations giving the best spur
11. R3 register address bits R3 2 0 are O11 Register R3 contains the controls for the phase lock bandwidth controls BW_DUR BW_CRL and BW_EN The duration of the digital controller portion of the bandwidth control is set by BW_DUR 1 0 The minimum time set with 00 and increasing durations to the maximum value set with 11 BW_CRL 1 0 sets the phase offset criterion for the bandwidth controller Once the phase offset between the reference clock and the divided VCO signal are within the set criterion the bandwidth control stops The maximum phase offset is set with 00 and decreases to the minimum value set with 11 BW_EN enables the bandwidth control in the locking state The VCO dynamic current is also controlled in register R3 with VCO_CUR 1 0 The minimum value corresponds to 00 and increases to a maximum value set at 11 R3 REGISTER MSB SHIFT REGISTER BIT LOCATION LSB 23 22 21 20 19 18 17 16 14 13 12 11 10 9 2 1 0 o 2 2 o a a Field Address Name Functions BW_DUR 1 0 Bandwidth Duration 00 Minimum value Recommended 01 10 11 Maximum value BW_CRL 1 0 Bandwidth Control 00 Maximum phase offset Recommended 01 10 11 Minimum phase offset BW_EN Bandwidth Enable 0 Disable 1 Enable Recommended VCO_CUR 1 0 VCO Dynamic Current 00 Minimum value 01 10 11 Max
12. X2532LQ1065 25 MHz Band for RF us PLL a 7 RMS Prase Enor AF PL maisaa OoOo degrees LMX2522LQ1635 100 kHz offset dBc Hz 1 25 MHz offset dBc Hz LMX2532LQ0967 100 kHz offset dBc Hz 900 kHz offset dBc Hz LMX2532LQ1065 100 kHz offset dBc Hz aBolHz 2nd Harmonic Suppression i dBc dBc 3rd Harmonic Suppression www national com Electrical Characteristics Voc Vpp 2 8 V Ta 25 C unless otherwise noted Continued Symbol Parameter Conditions Min Typ Max Units GPS VCO RFout Operating Frequency LMX2522LQ1635 GPS VCO 1355 04 MHz Toa MHz P 1398 82 MHz PREout Output Power 1 4 dBm OB_CRL 1 0 10 5 2 1 dBm OB_CRL 1 0 01 7 4 1 dBm OB_CRL 1 0 00 9 6 3 dBm Lock Time Note 7 From RF to GPS PLL 600 800 uS Reference Spurs 75 dBc RMS Phase Error RF PLL in all band 1 3 degrees L f Phase Noise 100 kHz offset 112 dBo Hz e125 Miz offset a3 136 dorz 2nd Harmonic Suppression o e SE 25 dBc 3rd Harmonic Suppression 20 dBc IF PLL fkin Operating Frequency LMX2522LQ1635 IF_FREQ 1 0 10 440 76 MHz Note 8 Default Value LMX2532LQ0967 IF_FREQ 1 0 00 170 76 MHz Default Value LMX2532LQ1065 IF_FREQ 1 0 01 367 20 MHz PEin IF Input Sensitivity 0 dBm four Phase Detector Frequency 120 kHz lopout Charge Pump Current IF_CUR 1 0 00 100 yA IF_CUR 1 0 01 200 yA IF_CUR 1 0 10 300 yA
13. _A lt 7 for LMX2522 0 lt RF_A lt 5 for LMX2532 RF_FN 10 0 RF Fractional Numerator Counter 11 bit programmable counter 0 lt RF_FN lt 1920 for fosc 19 20 MHz 0 lt RF_FN lt 1968 for fosc 19 68 MHz TABLE 8 RF_SEL Configuration Device Type RF_SEL 0 RF_SEL 1 LMX2522 GPS K PCS 11 www national com CEGCXINT ZZSZXNT LMX2522 LMX2532 Programming Description Continued RF N Counter Setting Function Counter Name Symbol Modulus Counter RF_FN RF N Divider Programmable RF_B N Prescaler x RF_B RF_A RF_FN fosc 104 Counter Swallow Counter RF_A Pulse Swallow Function f Prescaler x RF_B RF_A RF_FN fosc x 104 x fosc where RF_A lt RF_B where fyco Output frequency of voltage controlled oscillator VCO Prescaler Values Device Type RF Prescaler GPS Prescaler LMX2532 C e N B O RF_B Preset divide ratio of binary 4 bit programmable counter 2 lt RF_B lt 15 RF_A Preset divide ratio of binary 3 bit swallow counter 0 lt RF_A lt 7 for prescaler of 8 or 0 lt RF_A lt 5 for prescaler of 6 RF_FN Preset numerator of binary 11 bit modulus counter 0 lt RF_FN lt 1920 for fosc 19 20 MHz 0 lt RF_FN lt 1968 for fosc 19 68 MHz fosc Reference oscillator frequency NOTE For the use of reference frequencies other than those specified please contact National Semiconductor www national com 12
14. e IF_R divider if the default value is not desired This register is only active if the SPI_DEF bit in register RO is 0 R5 REGISTER SHIFT REGISTER BIT LOCATION 22 21 20 19 18 16 15 14 13 12 11 3 2 1 Data Field Address Field Register Po o ame nets SS S S IF_R 8 0 IF R Counter 9 bit programmable counter 2 lt IFR lt 511 www national com 16 Programming Description Continued R6 REGISTER The R6 register address bits R6 5 0 are 011111 Register R6 is used for internal testing of the device and is not intended for customer use This register is only active if the SPI_DEF bit in register RO is 0 R6 REGISTER Ezi SHIFT REGISTER BIT LOCATION aS 22 21 16 13 10 9 8 7 6 5 41 3 2 Data Field E Am jo o o o o o o o o o o o o 17 www national com CEGCXINT ZZSZXNT Physical Dimensions inches millimeters unless otherwise noted 3 8 ooomooo oOo oO a 0 2 0 2378 05 co oOo 0 25 D co 0 25 28X 0 5 OOggoo0 DETAIL A j calle 1 ot 28X 0 25 DIMENSIONS ARE IN MILLIMETERS H 24X 0 5 RECOMMENDED LAND PATTERN 1 1 RATION WITH PKG SOLDER PADS PIN 4 INDEX AREA 0 1 MAX aii LEADS C O O O O O O O A L a x lt 28X 0 50 05 28X 0 25 0 05 Le o 1 cla 8 LQA28A Rev B 28 Pin Leadless Leadframe Package LLP NS Pac
15. e shift register from MSB to LSB The Data is shifted at the rising edge of the Clock signal When the Latch Enable signal transitions from LOW to HIGH the data stored in the shift register is transferred to the proper register depending on the address bit settings The selection of the particular register is determined by the control bits indicated in boldface text At initial start up the MICROWIRE loading requires 4 default words registers R3 loaded first to RO loaded last After the device has been initially programmed the RF VCO frequency can be changed using a single register RO If an IF frequency other than the default value for the device is desired the SPI_DEF bit should be set to 0 the desired values for IF_A IF_B and IF_R entered and words R6 to RO should be sent The control register content map describes how the bits within each control register are allocated to the specific control functions Complete Register Map S MSB SHIFT REGISTER BIT LOCATION LSB v 0 a RO 0 R1 1 Default R2 a 0 Default CUR 1 0 R3 BW_ 1 Default DUR 1 0 1 1 NOTE Bold numbers represent the address bits www national com Programming Description Continued RO REGISTER The RO register address bits RO 1 0 are OO The SPI_DEF bit selects between using the default IF counter values and user programmable values The use of the default count
16. er values requires that only words RO to R3 registers R3 loaded first to RO loaded last be sent after initial power up The RF_LD bit activates the lock detect output of the LD pin pin 19 The lock detect mode shows the lock status of the RF PLL The waveform of the lock detect mode is shown in Figure 1 in the Functional Description section on LOCK DETECT The SPUR_CRL bit is set to 1 only in the GPS mode with the LMX2532LQ1065 when a 19 68 MHz reference oscillator is used The RF N counter consists of the 4 bit programmable counter RF_B counter the 3 bit swallow counter RF_A counter and the 11 bit delta sigma modulator RF_FN counter The equations for calculating the counter values are presented below RO REGISTER SHIFT REGISTER BIT LOCATION E N gt Data Field Address oc Field RO SPI_ RF_ RF_ SP RF_B RF_A RF_FN 0 o Default DEF SEL LD UR_ 8 0 2 0 10 0 CRL Name Functions SPI_DEF Default Register Selection 0 OFF Use values set in RO to R6 1 ON Use default values set in RO to R3 RF_SEL RF Select Configuration See Table 8 RF_SEL Configuration below RF_LD RF Lock Detect 0 Hard zero GND 1 Lock detect SPUR_CRL Spur Control 1 LMX2532LQ1065 in GPS mode with 19 68 MHz reference oscillator only 0 All other options RF_B 3 0 RF_B Counter 4 bit programmable counter 2 lt RF_B lt 15 RF_A 2 0 RF_A Counter 3 bit swallow counter 0 lt RF
17. i ous performance over changing conditions e Aone time optimization scheme which sets the internal compensation values only when the PLL goes into a locked state The spurious reduction can also be disabled but it is recom mended that the continuous optimization mode be used for normal operation POWER DOWN MODE The LMX2522 and LMX2532 include a power down mode to reduce the power consumption The LMX2522 32 enters into the power down mode either by taking the CE pin LOW or by setting the power down bits in Register R1 Table 5 summa rizes the power down function If CE is set LOW the circuit is powered down regardless of the register values When CE is HIGH the IF and RF circuitry are individually powered down by setting the register bits TABLE 5 Power Down Configuration CE Pin RF_EN IF_EN RF Circuitry IF Circuitry OFF OFF X X 0 0 0 1 1 0 1 1 X Don t care LOCK DETECT The LD output can be used to indicate the lock status of the RF PLL Bit 21 in Register RO determines the signal that appears on the LD pin When the RF PLL is not locked the LD pin remains LOW After obtaining phase lock the LD pin will have a logical HIGH level The output can also be programmed to be ground at all times TABLE 6 Lock Detect Modes LD Bit Disable GND Enable TABLE 7 Lock Detect Logic Table RF PLL Section LD Output Locked HIGH Not Locked LOW 20067205
18. ich damage to the device may occur Recommended Operating Conditions indicate condi tions for which the device is intended to be functional but do not guarantee specific performance limits For guaranteed specifications and test condi tions refer to the Electrical Characteristics section The guaranteed specifi cations apply only for the conditions listed Note 2 This device is a high performance RF integrated circuit with an ESD rating lt 2 kV and is ESD sensitive Handling and assembly of this device should be done at ESD protected work stations Note 3 GND 0 V Electrical Characteristics vec Vop 2 8 V Ta 25 C unless otherwise noted Symbol Parameter lcc PARAMETERS Conditions Min Typ loc lbp Total Supply Current OB_CRL 1 0 00 mA loc RF PLL Total Supply Current OB_CRL 1 0 00 mA lop RF lpp Power Down Current Note 4 CE Low or pA RF_EN 0 IF_EN 0 REFERENCE OSCILLATOR foscin Reference Oscillator Input Frequency 19 20 MHz and 19 68 MHz Voscin Reference Oscillator Input sensitivity 0 2 Voc Vp p RF VCO farout Frequency Range LMX2522LQ1635 RF VCO 1619 62 1649 62 MHz Note 6 LMX2532LQ0967 954 42 979 35 MHz LMX2532LQ1065 1052 64 1077 57 MHz Daron RF Output Power dBm OB_CRL 1 0 00 Lock Time Note 7 Reference Spurs 1 z 6 3 dBm LMX2522LQ1635 30 MHz Band for RF 500 800 us PLL LMX2532LQ0967 25 MHz Band for RF 500 800 us PLL LM
19. imum value Recommended 15 www national com CEGCXINT ZZSZXNT LMX2522 LMX2532 Programming Description Continued R4 REGISTER The R4 register address bits R3 3 0 are 0111 Register R4 is used to set the IF N counters if the default value is not desired This register is only active if the SPI_DEF bit in register RO is 0 The IF N counter consists of the 9 bit programmable counter IF_B counter and the 4 bit swallow counter IF_A counter The equations for calculating the counter values are presented below R4 REGISTER MSB SHIFT REGISTER BIT LOCATION LSB S 23 Data Field Address ra Field R4 0 o o 1 o o o IF_A IF_B 0 1 11 3 0 8 0 Name Functions IF_A 3 0 IF A Counter 4 bit swallow counter O lt IF_A lt 15 IF_B 8 0 IF B Counter 9 bit programmable counter 1 lt IF_B lt 511 IF Frequency Setting fyco 16 x IF_B IF_A x fosc R where IF_A lt IF_B where fyco Output frequency of IF voltage controlled oscillator IF VCO IF_B Preset divide ratio of binary 9 bit programmable counter 1 lt IF_B lt 511 IF_A Preset divide ratio of binary 4 bit swallow counter 0 lt IF_A lt 15 IF_R Preset divide ratio of binary 9 bit programmable reference counter 2 lt IF_R lt 511 fosc Reference oscillator frequency R5 REGISTER The R5 register address bits R5 4 0 are 01111 Register R5 is used to set th
20. kage Number LQA28A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user N LMX2522 LMX2532 PLLatinum Dual Frequency Synthesizer System with Integrated VCOs National Semiconductor Europe Customer Support Center Fax 49 0 180 530 85 86 Email europe support nsc com National Semiconductor Americas Customer Support Center Email new feedback nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 English Tel 44 0 870 24 0 2171 www national com Fran ais Tel 33 0 1 41 91 8790 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Japan Customer Support Center Fax 81 3 5639 7507 Email jpn feedback nsc com Tel 81 3 5639 7560 National Semiconductor Asia Pacific Customer Supp
21. ort Center Email ap support nsc com National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
22. package LLP June 2003 Features m Small Size Small 5 0 mm x 5 0 mm x 0 75 mm 28 Pin LLP Package m RF GPS Synthesizer System Integrated RF VCO Integrated GPS VCO Integrated Loop Filter Low Spurious Low Phase Noise Fractional N RF PLL Based on 11 bit Delta Sigma Modulator 10 kHz Frequency Resolution m F Synthesizer System Integer N IF PLL Programmable Charge Pump Current Levels Programmable Frequencies m Supports Various Reference Oscillator Frequencies 19 20 19 68 MHz m Fast Lock Time 500 us m Low Current Consumption 17 mA at 2 8 V m 2 7 V to 3 3 V Operation m Digital Filtered Lock Detect Output m Hardware and Software Power Down Control Applications m Korean PCS CDMA Systems with GPS m Korean Cellular CDMA Systems with GPS Functional Block Diagram OSCin RF Phase Detector Power CE Down Control ii Serial ix Interface E IFR Divider PLLatinum is a trademark of National Semiconductor Corporation Loop Filter N N 1 Divider Delta Sigma Control RFout CPout Detector IF N Divider Fin 20067201 2003 National Semiconductor Corporation DS200672 www national com SODA peyesBbaju YM Wayshs JezisayjUAS Aouenbasy jeng wnune 1d ZESZXNT ZZSZXNT LMX2522 LMX2532 Connection Diagram 28 Pin LLP LQ Package o is NC S o O 8 zZz 8 gt oO gt a k gt L gt 20067202 NOTE Analog ground connected through exposed die attached pad Pin Descrip
23. tions Pin Number Name 1 0 Description 1 CPout O IF PLL charge pump output pooo 2 mno Do not connect to any node on printed circuit board a ee looo omno Do not connect to any node on printed circuit board Co a O vo _ Supply vortage for IF analog circuitry LE MICROWIRE Latch Enable Wy N CLK MICROWIRE Clock MICROWIRE Data ao lN o oa a Supply voltage for VCOs Do not connect to any node on printed circuit board Do not connect to any node on printed circuit board Do not connect to any node on printed circuit board Supply voltage for VCOs 14 Supply voltage for VCOs output buffer 15 Buffered VCO output 16 Voc Supply voltage for RF prescaler COo o T e Oooo ao oo omno Do not connect to any node on printed circuit board Pe e o 17 Vec Supply voltage for charge pump P18 ve o Supply voltage for RF digital circuitry C i Chip Enable contol pin Ground for digital circuitry Reference frequency input Supply voltage for reference input buffer Ground for digital circuitry Supply voltage for IF digital circuitry IF buffer prescaler input 27 Vec Supply voltage for IF buffer prescaler 28 NC Do not connect to any node on printed circuit board N www national com Ordering Information Part Number RF Min RF Max RF Center IF GPS Package MHz MHz MHz
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National LMX2522/LMX2532 handbook