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National LMX2430/LMX2433/LMX2434 handbook

1. 2 Source Current IF CPG Bit 0 Note 6 2 IF CPG Bit 1 Note 6 IF Charge Pump Output Sink Current 2 Sink IF CPG Bit 0 Note 6 Vcpouur 2 CPG Bit 1 Note 6 www national com VevexiN TeevexiN Yoev eX LMX2430 LMX2433 LMX2434 Electrical Characteristics continued EN 2 5V 40 C TA 85 C unless otherwise specified Value 1 Symbol Parameter Conditions Units Min Typ Max IF SYNTHESIZER PARAMETERS lePoutuF IF Charge Pump Output TRI STATE 0 5 lt Vee 0 5V 2 5 2 5 nA TRI Current Note 6 lcPouuF IF Charge Pump Output Sink Current Vcc 2 3 10 MIS Vs Charge Pump Output Source Note 7 Current Mismatch lcPoutiF IF Charge Pump Output Current 0 5V 0 5V 5 15 Magnitude Variation Vs Charge Pump Note 7 Output Voltage IF Charge Pump Output Current Vcpouur 2 2 Magnitude Variation Vs Temperature 7 OSCILLATOR PARAMETERS foscin Oscillator Operating Frequency 1 256 MHz Voscin Oscillator Sensitivity Note 8 0 5 Vpp loscin Oscillator Input Current Voscin Vcc 100 Voscin 0V 100 DIGITAL INTERFACE DATA CLK LE EN ENosc Ftest LD FLoutRF OSCout FLoutlF Vin High
2. 2 7 2 CPP IF Synthesizer Phase Detector Polarity R3 18 The IF CPP bit is used to control the IF synthesizer s phase frequency detector polarity based on the VCO tuning characteristics Control Bit Register Location Description Function IF CPP R3 18 IF Phase Frequency IF VCO Negative IF VCO Positive Detector Polarity Tuning Tuning Characteristics Characteristics IF VCO Characteristics IF_CPP 1 IF VCO OUTPUT FREQUENCY IF_CPP 0 IF VCO INPUT VOLTAGE 20053568 43 www national com VevecxiN TeevexiN VOEPCXINT LMX2430 LMX2433 LMX2434 2 0 Programming Description continued 2 7 3 IF CPG IF Synthesizer Charge Pump Current Gain R3 19 The CPG bit controls the IF synthesizer s charge pump gain Two gain levels are available 1 IF CPG R3 19 IF Charge Pump LOW HIGH am 2 7 4 IF CPT IF Synthesizer Charge Pump TRI STATE R3 20 The IF CPT bit allows the charge pump to be switched between a normal operating mode and a high impedance output state This happens asynchronously with the change in the bit Furthermore the IF CPT bit operates in conjuction with the IF PD bit to set a synchronous or an asynchronous powerdown mode Refer to Section 2 8 4 for more details on how to program the IF PD bit Control Bit Register Location Description Function 0 1 IF CPT R3 20 IF Charge Pump IF Charge Pump IF Charge Pump TRI
3. LCS o 1 c 2X 20 Pin Ultra Thin Chip Scale Package UTCSP NS Package Number SLE20A 4X 0 520 1 20X 0 320 05 0 16 SLE20A Rev A www national com 48 Physical Dimensions inches millimeters unless otherwise noted Continued 8 05494 10 Jeziseuju s 3 9 5944 v rzXIWT EEveXIWT 0 t2XIW 4 16 YP 1 12 1 440 1 D Lx 0 2 CJB A 20X 0 miss 1 10 ALL LEAD TIPS 18 0 65 PIN 1 IDENT LAND PATTERN RECOMENDATION atts SEE DETAIL A LEAD TIPS m 0 9 3 2 1 gem 0 65 AGE PLANE 20X 0 19 0 30 E 25 ARNAR DIMENSIONS ARE IN MILLIMETERS BEN I PLANE DETAL A MTC20 Rev E 20 Pin Thin Shrink Small Outine Package TSSOP NS Package Number MTC20 LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for
4. x 100 il 5 T 25 C 20053565 www national com Typical Performance Characteristics Sensitivity INPUT POWER dBm INPUT POWER dBm 1 1 1 40 50 1 1 40 50 LMX2430 FinRF Input Power Vs Frequency EN 2 25V T 859C 5000 500 1000 1500 2000 2500 3000 3500 4000 4500 fringe MHz 20053592 LMX2430 FinRF Input Power Vs Frequency Vcc EN 2 75V T 25 C Ty 859 Ty 259C Ty 409C S 500 1000 1500 2000 2500 3000 3500 4000 4500 fringe MHz 5000 20053593 www national com VevecxiN VEEVCXIN 08v cXIN 1 LMX2430 LMX2433 LMX2434 Typical Performance Characteristics Sensitivity Continued LMX2433 FinRF Input Power Vs Frequency Vcc EN 2 25V 1 INPUT POWER dBm 1 Ww 40 50 0 500 2000 2500 35000 5500 4000 fringe MHz LMX2433 FinRF Input Power Vs Frequency Vcc EN 2 75V 5500 20053594 1 INPUT POWER dBm 1 1 e 40 50 0 500 2000 2500 3000 3500 4000 fringe MHz 5500 20053595 www national com Typical Performance Characteristics Sensitivity Continued INPUT POWER dBm INPUT POWER
5. IF FASTLOCK FLoutlF OSCout 6 7 IF 18 BIT IF PRESCALER N COUNTER CHARGE CPoutlF 4 5 PUMP 15 BIT IF R COUNTER Ftest LD 9 10 O 15 BIT RF R COUNTER 2 5 7 8 05 14 15 FinRFO RF 19 BIT RF CPoutRF 12 13 15 16 FinRF PRESCALER COUNTER RF 19 20 CLK FASTLOCK FLoutRF 10 11 18 19 DATA MICROWIRE 17 18 LEO INTERFACE 3 4 EN 5 6 ENosc LMX2430 LMX2433 LMX2434 GND GND GND 1 2 11 12 13 14 20053501 Note 1 2 refers to Pin 1 of the 20 Pin UTCSP and Pin 2 of the 20 Pin TSSOP www national com 2 Connection Diagrams Ultra Thin Chip Scale Package SLE Top View Thin Shrink Small Outline Package TM Top View CPoutlF ENosc OSCout FLoutlF OSCin Voc Pin Descriptions DATA B d Ftest LD FLoutRF CLK LE LE GND FinlF EN CPoutlF ENosc OSCout FLoutlF OSCin o FinRF FinRF GND CPoutRF GND FLoutRF FinRF FinRF GND 2 3 4 5 6 7 8 9 CPoutRF Ftest LD GND 20053583 20053539 Pin No UTCSP 1 Pin No TSSOP Pin Name GND yo Description Ground for the IF PLL analog and digital circuits MICROWIRE Ftest LD and oscillator circuits IF PLL prescaler input Small signal input from the VCO Chip Enable input High Impedance CMOS input When this pin is set HIGH the RF and I
6. Im ZFinRF Q IZFinRFI 9 8 63 334 27 339 55 476 48 10 72 265 44 313 48 410 77 346 46 287 93 240 60 204 37 175 88 153 09 134 72 119 59 106 86 95 86 86 19 77 82 70 24 63 33 57 09 51 25 45 83 41 23 37 05 33 34 30 17 27 06 24 22 21 07 18 26 15 49 12 85 10 61 8 79 7 46 6 57 6 19 6 37 7 08 8 16 9 49 10 86 12 24 13 62 14 91 15 95 16 80 17 52 18 21 18 67 19 05 www national VevecxiN TeevexiN Yoevexi1 LMX2430 LMX2433 LMX2434 LMX243x UTCSP FinRF Input Impedance Table continued EN 2 50V 25 C frinRF MHz Iri Angle e Re ZFinRF Q Im ZFinRF Q IZFinRFl 9 4900 0 84 137 79 4 84 18 85 19 46 5000 0 84 136 82 4 92 19 79 20 39 5100 0 84 135 77 4 88 18 89 19 51 5200 5300 5400 5500 5600 0 84 134 64 4 99 20 44 21 04 5700 5800 5900 6000 www national com 22 LMX243x TSSOP FinRF Input Impedance Table 2 50V 25 C Angle Re ZFinRF Im ZFinRF IZFinRFl 0 0 0 12 47 214 61 314 33 380 61 15 35 166 75 270 14 317 46 157 50
7. counter The maximum error is one prescaler cycle Control Bit Register Location Description Function 0 RF RST RO 21 RF Counter Reset RF_A RF_B and RF_A RF_B and RF_R RF_R Normal Operation Reset 2 5 R1 REGISTER The R1 register contains the RF B RF P and RF PD control words The RF_A and RF B control words are used to setup the programmable feedback divider The detailed descriptions and programming information for each control word is discussed in the following sections 22 21 19 te iz ie 16 4 iS 12 1 110 9 8 7 6 8 4 31211 ADDRESS 2 0 FIELD DATA 20 0 FIELD Ri LMX2430 33 LMX2430 33 PD RF B 14 0 RF A 3 0 Ri LMX2434 LMX2434 1 0 RF B 13 0 RF A 4 0 2 5 1 LMX243x RF Synthesizer Swallow Counter 2 5 1 1 RF A 3 0 LMX2430 33 RF Synthesizer Swallow Counter A Counter R1 6 3 The RF A control word is used to setup the RF synthesizer s A counter For both the LMX2430 and 2433 the A counter is 4 bit swallow counter used in the programmable feedback divider The RF A control word can be programmed to values ranging from 0 to 15 LMX2430 33 RF A 3 0 Divide Ratio www national com 40 2 0 Programming Description continued 2 5 1 2 RF A 4 0 LMX2434 RF Synthesizer Swallow Counter A Counter R1 7 3
8. solder 4 s 260 C Note 2 This device is a high performance RF integrated circuit with an ESD rating lt 2 kV and is ESD sensitive Handling and assembly of this device should only be done at ESD protected work stations Note 3 GND 0V Electrical Characteristics Vcc EN 2 5V 40 C T lt 85 C unless otherwise specified Value Symbol Parameter Conditions Units Min Typ Max PARAMETERS Power Supply LMX2430 CLK DATA and LE OV 5 3 6 Current RF OSCin GND Synthesizer LMX2433 RF_PD Bit 0 4 4 mA LMX2434 IF E 62 RF P Bit 0 Ice Power Supply LMX2430 CLK DATA and LE OV 2 0 Current OSCin GND Synthesizer LMX2433 PD Bit 1 2 8 mA LMX2434 9 35 IF P Bit 0 Powerdown Current EN ENosc CLK DATA 10 and LE OV SYNTHESIZER PARAMETERS RF Operating LMX2430 RF P Bit 0 250 2500 MHz Frequency RF P Bit 1 250 3000 MHz LMX2433 RF P Bit 0 500 3000 MHz RF P Bit 1 50 3600 MHz LMX2434 RF P Bit 0 or 1 1000 5000 Nar N Divider Range P 8 9 24 262151 Note 4 P 16 17 48 524287 Note 4 P 32 33 96 524287 Note 4 Rear RF R Divider Range 3 32767 RF Phase Detector Frequency 10 2 PFinRE RF Input Sensitivity LMX2430 33 15 0 dBm 2 25V lt lt 2 75V Note 5 LMX2434 12 0 dBm 2 35V lt Vcc lt 2 75V
9. 138 30 122 35 108 47 96 28 58 42 51 45 45 29 39 94 2 35 19 21 74 18 97 16 36 13 40 8 i 10 42 8 94 11 09 13 75 16 85 20 27 23 96 39 69 43 44 47 20 50 95 i 2 54 32 4700 0 76 70 66 19 89 66 66 69 56 4800 0 75 66 05 22 50 72 05 75 48 23 www nationa 9 LMX2430 LMX2433 LMX2434 LMX243x TSSOP FinRF Input Impedance Table continued EN 2 50V 25 C frinRF MHz Iri Angle e Re ZFinRF Q Im ZFinRF Q IZFinRFl 9 4900 0 75 61 68 25 37 77 73 81 77 5000 0 75 57 35 28 56 84 19 88 90 5100 0 76 53 11 31 70 91 39 96 73 5200 5300 5400 5500 5600 0 77 48 79 34 78 100 34 106 20 5700 5800 5900 6000 www national com 24 LMX243x UTCSP FinlF Input Impedance Table EN 2 50V 25 C Angle Re 2 ZFinlF IZFinlFI 0 0 0 6 19 446 34 341 41 561 94 8 10 353 77 328 44 482 73 234 03 201 91 176 17 155 83 140 05 97 20 69 15 2 11 75 71 68 63 2200 0 71 100 18 14 07 40 46 42 84 2300 0 69 107 33 13 94 35 79 38 41 2400 0 68 114 48 13 37 31 55 34 27 2500 0 68 118 42 12 71 28 62 31 32 w
10. High impedance CMOS input When LE transitions HIGH DATA stored in the shift register is loaded into one of 6 internal control registers 18 MICROWIRE Clock input High impedance CMOS input DATA is clocked into the 24 bit shift register on the rising edge of CLK 19 20 DATA MICROWIRE Data input High impedance CMOS input Binary serial data The MSB of DATA is shifted in first The two last bits are the control bits 20 1 Power supply bias for the IF PLL analog and digital circuits MICROWIRE Ftest LD circuits Vcc may range from 2 25V to 2 75V Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane www national com Ordering Information Model LMX2430TM LMX2430TMX Temperature Range 40 C to 85 C 40 C to 85 C Package Description Thin Shrink Small Outline Package TSSOP Thin Shrink Small Outline Package TSSOP Tape and Reel Packing 73 Units Per Rail 2500 Units Per Reel NS Package Number MTC20 MTC20 LMX2430SLEX LMX2433TM 40 C to 85 C 40 C to 85 C Ultra Thin Chip Scale Package UTCSP Tape and Reel Thin Shrink Small Outline Package TSSOP 2500 Units Per Reel 73 Units Per Rail SLE20A MTC20 LMX2433TMX 40 C to 85 C Thin Shrink Small Outline Package TSSOP Tape and Reel 2500 Units Per Reel MTC20 LMX2433SLEX LMX2434TM 40 to 485 40 C
11. MHz Voscin 1 Vpp RF_CPG Bit 1 IF PD Bit 1 TA 25 C Note 11 dBc Hz LMX2434 fringe 4700 MHz f 10 kHz offset fcompre 1 MHz Loop Bandwidth 100 kHz Npr 4700 foscin 10 MHz Voscin 1 Vpp RF CPG Bit 1 IF PD Bit 1 Ta 25 C Note 11 dBc Hz Note 4 Some of the values in this range are illegal divide ratios B A To obtain continuous legal division the Minimum Divide Ratio must be calculated Use N gt P P 1 where P is the value of the prescaler selected Note 5 Refer to the LMX243x FinRF Sensitivity Test Setup section Note 6 Refer to the LMX243x Charge Pump Test Setup section Note 7 Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made Note 8 Refer to the LMX243x OSCin Sensitivity Test Setup section Note 9 Refer to the LMX243x Serial Data Input Timing section Note 10 Normalized Phase Noise Contribution is defined Ly f 20 log 10 log fcomp where L f is defined as the single side band phase noise measured at an offset frequency f in a 1 Hz bandwidth The offset frequency f must be chosen sufficiently smaller than the PLL s loop bandwidth yet large enough to avoid substantial phase noise contribution from the reference source N is the value selected for the feedback divider and is the RF IF phase frequency detector comparison frequency Note 11 The synthesiz
12. MULTI FUNCTION OUTPUTS The LMX243x device s Ftest LD output pin is a multi function output that can be configured as a general purpose CMOS TRI STATE output push pull analog lock detect output open drain analog lock detect output digital filtered lock detect output or used to monitor the output of the various reference divider R counter or feedback divider N counter circuits The Ftest LD control word is used to select the desired output function When the PLL is in powerdown mode the Ftest LD output is disabled and is in a high impedance state complete programming description of the multi function output is provided in Section 2 10 The diagram assumes positive VCO characteristics i e RF_CPP or IF_CPP 1 fp is the PFD input from the programmable feedback divder N counter 1 8 1 Push Pull Analog Lock Detect Output An analog lock detect status generated from the phase detector is available on the Ftest LD output pin if selected A push pull configuration can be selected for the lock detect output signal With this configuration the lock detect output goes HIGH when the charge pump is inactive It goes LOW when the charge pump is active during a comparison cycle Narrow low going pulses are observed when the charge pump turns on There are three separate push pull analog lock detect sig nals that are routed to the multiplexer Two of these monitor the lock status of the individual synthesizers The third de tects the
13. Note 5 www national com 6 Electrical Characteristics continued Vcc EN 2 5V 40 lt 85 C unless otherwise specified Symbol Parameter Conditions Units Min Typ Max RF SYNTHESIZER PARAMETERS RF Charge Pump Output Source 2 1 0 mA RF CPG Bit 0 Note 6 2 RF CPG Bit 1 Note 6 RF Charge Pump Output Sink Current Vcc 2 Sink RF CPG Bit 0 Note 6 Source Current 2 RF CPG Bit 1 Note 6 TRI RF Charge Pump Output Sink Current Vcc 2 Vs Charge Pump Output Source Note 7 Current Mismatch 5 RF Charge Pump Output Current 0 5V lt Vee 0 5V Magnitude Variation Vs Charge Pump Note 7 Output Voltage lcPoutRF cPoutRF RF Charge Pump Output Current VCC 2 lcPoutRF Magnitude Variation Vs Temperature 7 IF SYNTHESIZER PARAMETERS IF Operating LMX2430 IF P Bit O or 1 Frequency LMX2433 IF P Bit 0 or 1 1700 LMX2434 IF P Bit 0 or 1 2500 NiF IF N Divider Range P 8 9 131079 Note 4 P 16 17 262143 Note 4 PriniF IF Input Sensitivity 2 25V lt Vcc lt 2 75V Note 5 leeoutiE IF Charge Pump Output Source
14. Performance Characteristics Sensitivity Continued LMX2433 Input Power Vs Frequency Vcc EN 2 25V 1 INPUT POWER dBm 1 40 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 82 200535 0 LMX2433 Input Power Vs Frequency Vcc EN 2 75V 1 INPUT POWER dBm 1 1 40 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 feine MHz 200535A1 15 www national com VevecxiN VEEVCXIN 08v cXIN 1 LMX2430 LMX2433 LMX2434 Typical Performance Characteristics Sensitivity Continued LMX2434 Input Power Vs Frequency Vcc EN 2 25V _ 710 5 e 5 20 50 40 50 0 500 1000 1500 2000 2500 5000 5500 4000 4500 MHz 200535 2 LMX2434 Input Power Vs Frequency Vcc EN 2 75V 10 0 710 5 a 20 LM z 30 40 50 0 500 1000 1500 2000 2500 3000 3500 4000 4500 MHz 200535A3 www national com 16 Typical Performance Characteristics Sensitivity Continued INPUT VOLTAGE Vpp INPUT VOLTAGE Vpp LMX243x OSCin Input Voltage Vs Frequency Vcc EN 2 25V 0 10
15. STATE Normal Operation Output in High Impedance State 2 7 5 IF RST IF Synthesizer Counter Reset R3 21 The IF RST bit resets of the IF A IF B and IF counters After removing the reset the IF and IF counters resume counting in close alignment with the IF counter The maximum error is one prescaler cycle Control Bit Register Location Description Function 0 IF RST R3 21 IF Counter Reset IF A IF B and IF IF A IF B and IF R Normal Operation Reset 2 8 R4 REGISTER The R4 register contains the IF B IF P and IF PD control words The IF A and IF B control words are used to setup the programmable feedback divider The detailed descriptions and programming information for each control word is discussed in the following sections R4 21 is always set to 0 1 ADDRESS 2 0 FIELD DATA 20 0 FIELD IF_B 13 0 IF_A 3 0 2 8 1 IF_A 3 0 IF Synthesizer Swallow Counter A Counter R4 6 3 The IF_A control word is used to setup the IF synthesizer s A counter The A counter is a 4 bit swallow counter used in the programmable feedback divider The control word can be programmed to values ranging from 0 to 15 Divide Ratio IF_A 3 0 0 0 1 15 1 1 1 1 www national com 44 2 0 Programming Description continued 2 8 2 IF B 13 0 IF Synthesizer Programmable Binary Counter B
16. The LMX2434 A counter is a 5 bit swallow counter used in the programmable feedback divider The RF A control word can be programmed to values ranging from O to 31 Divide Ratio LMX2434 RF A 4 0 4 3 2 1 0 0 0 0 0 0 0 1 2 5 2 LMX243x RF Synthesizer Programmable Binary Counter 2 5 2 1 B 14 0 LMX2430 33 RF Synthesizer Programmable Binary Counter B Counter R1 21 7 The RF B control word is used to setup the RF synthesizer s B counter For both the LMX2430 and LMX2433 the B counter is a 15 bit programmable binary counter used in the programmable feedback divider The RF B control word can be programmed to values ranging from 3 to 32767 Divide ratios less than 3 are prohibited LMX2430 33 8 14 0 Ratio 2 5 2 2 B 13 0 LMX2434 RF Synthesizer Programmable Binary Counter B Counter R1 21 8 The LMX2434 B counter is a 14 bit programmable binary counter used in the programmable feedback divider The RF B control word can be programmed to values ranging from 3 to 16383 Divide ratios less than 3 are prohibited LMX2434 RF B 13 0 Divide Ratio 2 5 3 LMX243x RF Synthesizer Prescaler Select 2 5 3 1 P LMX2430 33 RF Synthesizer Prescaler Select R1 22 Both the LMX2430 and LMX2433 RF synthesizers utilize a selectable dual modulus prescaler An 8 9 or a 16 17 prescale ratio c
17. appropriate matching networks to match the PLL to The desired operating frequency is then set The typical the VCO or in more critical situations to the characteristic frequency range selected for the LMX243x device s RF syn impedance of the printed circuit board PCB trace to pre thesizer is from 100 MHz to 6000 MHz vent undesired transmission line effects The FinlF input The Network Analyzer calculates the calibration coefficients impedance is evaluated in the same way based on the measured S parameters With this all done Before the actual measurements are taken the Network calibration is now complete Analyzer needs to be calibrated i e the error coefficients The PLL chip is then placed on the PCB A power supply is need to be calculated The Network Analyzer s calibration then connected to Vcc The EN ENosc and OSCin pins are standard is used to calculate these coefficients The calibra all tied to Vcc Alternatively the OSCin pin can be tied to tion standard includes an open short and a matched load A ground In this setup the complementary input FinRF is 1 port calibration is implemented here AC coupled to ground With the Network Analyzer still con To calculate the coefficients the PLL chip is first removed nected to the semi rigid coaxial cable the measured FinRF from the PCB A piece of semi rigid coaxial cable is then impedance is displayed soldered to the pad on the PCB which is equivalent to the The OSCin input imped
18. condition when both the RF and IF synthesizers are in a locked state External circuitry is required to provide a steady DC signal to indicate when the PLL is in a locked state Refer to Section 2 10 for details on how to program the different push pull analog lock detect options 1 8 2 Open Drain Analog Lock Detect Output The lock detect output can be an open drain configuration In this configuration the lock detect output goes to a high impedance state when the charge pump is inactive It goes LOW when the charge pump is active during a comparison cycle When a pull up resistor is used narrow low going pulses are observed when the charge pump turns on Similarly three separate open drain analog lock detect sig nals are routed to the multiplexer Two of these monitor the lock status of the individual synthesizers The third detects the condition when both the RF and IF synthesizers are in a locked state External circuitry is required to provide a steady DC signal to indicate when the PLL is in a locked state Refer to Section 2 10 for details on how to program the different open drain analog lock detect options 35 www national com VevcxiN TeevexiN 08v cXIN 1 LMX2430 LMX2433 LMX2434 1 0 Functional Description continued 1 8 3 Digital Filtered Lock Detect Output A digital filtered lock detect status generated from the phase detector is also available on the Ftest LD output pin if se lected The lock detect digita
19. configured for asynchronous powerdown the part will go into powerdown mode immediately EN Pin RF CPT RF PD Operating Mode IF CPT Bit IF PD Bit 0 X X Asynchronous Powerdown 1 0 0 PLL Active Normal Operation 1 1 0 PLL Active Charge Pump Output in High Impedance State 1 0 1 Synchronous Powerdown 1 1 1 Asynchronous Powerdown Note X refers to a don t care condition 37 www national com VevcxiN TeevexiN VOEPCXINT LMX2430 LMX2433 LMX2434 2 0 Programming Description 2 1 MICROWIRE INTERFACE The 24 bit shift register is loaded via the MICROWIRE interface The shift register consists of a 21 bit DATA 20 0 FIELD and a 3 bit ADDRESS 2 0 FIELD as shown below The ADDRESS FIELD is used to decode the internal control register address When LE transitions HIGH DATA stored in the shift register is loaded into one of 6 control registers depending on the state of the ADDRESS bits The MSB of DATA is loaded into the shift register first The DATA FIELD assignments are shown in Section 2 3 CONTROL REGISTER CONTENT MAP MSB LSB DATA 20 0 ADDRESS 2 0 2 2 CONTROL REGISTER LOCATION The ADDRESS 2 0 bits decode the internal register address The table below shows how the ADDRESS bits are mapped into the target control register ADDRESS 2 0 Target FIELD Register 0 0 RO 2 3 CONTROL REGISTER CONTENT MAP The control register content map describes how the bits within each control regi
20. of a phase frequency detector and compared with the feedback signal fp which was obtained by dividing the VCO frequency down by way of the feedback divider The phase frequency detector measures the phase error between the f and f signals and outputs control signals that are directly proportional to the phase error The charge pump then pumps charge into or out of the loop filter based on the magnitude and direction of the phase error The loop filter converts the charge into a stable control voltage for the VCO The phase frequency detector s function is to adjust the voltage presented to the VCO until the feedback signal s frequency and phase match that of the reference signal When this Phase Locked condition exists the VCO fre quency will be times that of the comparison frequency where N is the feedback divider ratio 1 1 REFERENCE OSCILLATOR INPUT The reference oscillator frequency for both the RF and IF PLLs is provided from an external reference via the OSCin pin The reference buffer circuit supports input frequencies from 5 to 40 MHz with a minimum input sensitivity of 0 5 Vpp The reference buffer circuit has an approximate Vcc 2 input threshold and can be driven from an external AC coupled Source Typically the OSCin pin is connected to the output of a crystal oscillator 1 2 REFERENCE DIVIDERS R COUNTERS The reference dividers divide the reference input signal OSCin by a factor of The output of the refe
21. to 85 C Ultra Thin Chip Scale Package UTCSP Tape and Reel Thin Shrink Small Outline Package TSSOP 2500 Units Per Reel 73 Units Per Rail SLE20A MTC20 LMX2434TMX LMX2434SLEX 40 C to 85 C 40 to 485 Thin Shrink Small Outline Package TSSOP Tape and Reel Ultra Thin Chip Scale Package UTCSP Tape and Reel 2500 Units Per Reel 2500 Units Per Reel MTC20 SLE20A www national com VevecxiN VEEVeXIN YO8evcXIN 1 LMX2430 LMX2433 LMX2434 Absolute Maximum Ratings Notes 1 Recommended Operating 2 3 Conditions 1 If Military Aerospace specified devices are required 1 Power Supply Voltage please contact the National Semiconductor Sales Office Distributors for availability and specifications Vcc to GND 2 25V to 2 75V Operating Temperature T4 40 C to 85 C Power Supply Voltage Vcc to GND 0 3V to 43 25V Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Recommended Operating Conditions indicate condi Voltage on any pin to GND Vj tions for which the device is intended to be functional but do not guarantee specific performance limits For guaranteed specifications and test condi V must be lt 3 25V 0 3 to Veo 0 3V ions to the Electrical Sein The guaranteed specifi Storage Temperature Range 65 C to 150 C cations apply only for the conditions listed Lead Temperature
22. 0 LM X2439 00 2003 National id Semiconductor LMX2430 LMX2433 LMX2434 PLLatinum Dual High Frequency Synthesizer for RF Personal Communications LMX2430 3 0 GHz 0 8 GHz LMX2433 3 6 GHz 1 7 GHz LMX2434 5 0 GHz 2 5 GHz General Description Features The LMX243x devices are high performance frequency syn Low Current Consumption thesizers with integrated dual modulus prescalers The 2 25V to 2 75V Operation LMX243x devices are designed for use as RF and IF local Selectable Synchronous or Asynchronous Powerdown oscillators for dual conversion radio transceivers Mode 32 33 or a 16 17 prescale ratio can be selected forthe 5 0 Selectable Dual Modulus Prescaler GHz LMX2434 RF synthesizer An 8 9 or a 16 17 prescale LMX2430 RF 8 9 or 16 17 ratio can be selected for both the LMX2430 and LMX2433 LMX2433 RF 8 9 or 16 17 RF synthesizers The IF circuitry contains an 8 9 or a 16 17 LMX2434 RF 16 17 or 32 33 prescaler Using a proprietary digital phase locked loop tech LMX243x IF 8 9 or 16 17 nique the LMX243x devices generate very stable low noise Programmable Charge Pump Current Levels control signals for RF and IF voltage controlled oscillators RF and IF 1 or 4 mA Both the RF and IF synthesizers include a two level pro m Fastlock Technology with Integrated Timeout Counters grammable charge pump Both the RF and IF synthesizers m Digital Filtered Lock Detect Output have dedicated Fastlock circ
23. 0 200 300 400 500 600 700 800 900 1000 foscin MHz 200535A4 LMX243x OSCin Input Voltage Vs Frequency Vcc EN 2 75V 0 100 200 300 400 500 600 700 800 900 1000 foscin MHz 200535A5 17 www national com VevecxiN VEEVCXIN 08v cXIN 1 LMX2430 LMX2433 LMX2434 Typical Performance Characteristics Charge Pump LMX243x RF Charge Pump Sweeps Vcc EN 2 50V 40 C lt TA x 85 C 4 5 4 0 3 5 RF_CPG Bit 1 3 0 2 5 2 0 1 5 _ 1 0 lt 0 5 Bi 0 0 2 0 5 1 0 1 5 2 0 2 5 3 0 RF CPG Bit 1 3 5 4 0 4 5 0 00 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 2 25 2 50 Vepoutrr 200535 6 LMX243x IF Charge Pump Sweeps Vcc EN 2 50V 40 C lt T lt 85 C 4 5 4 0 3 0 2 5 2 0 1 5 1 0 2 95 IF CPG Bit 0 oo 5 0 5 5 1 0 1 5 2 0 2 5 3 0 IF_CPG Bit 1 3 5 4 0 4 5 5 0 0 00 0 25 0 50 0 75 1 00 1 25 1 50 1 75 2 00 2 25 2 50 V 200535A7 www national com 18 Typical Performance Characteristics Input Impedance LMX243x UTCSP FinRF Input Impedance EN 2 50V 25 C LMX243x TSSOP FinRF Input Impedance EN 2 50V 25 C Marker 1 900 MHz Marker 2 19
24. 00 MHz Marker 3 2500 MHz Marker 4 5000 MHz 200535A8 LMX243x UTCSP FinlF Input Impedance EN 2 50V 25 C Marker 1 900 MHz Marker 2 1900 MHz Marker 3 2500 MHz Marker 4 5000 MHz 200535A9 LMX243x TSSOP FinlF Input Impedance EN 2 50V 25 C Marker 1 100 MHz Marker 2 900 MHz Marker 3 1900 MHz Marker 4 2500 MHz 200535B0 Marker 1 100 MHz Marker 2 900 MHz Marker 3 1900 MHz Marker 4 2500 MHz 200535B1 19 www national com VevecxiN VEEVCXIN 0e v cXIN T LMX2430 LMX2433 LMX2434 Typical Performance Characteristics Input Impedance Continued Z0SCin Izoscin LMX243x UTCSP OSCin Input Impedance Vs Frequency EN 2 50V 14000 25 12000 10000 8000 OSCin POWERED DOWN 6000 4000 OSCin POWERED UP 2000 17 5 20 0 22 5 25 0 27 5 30 0 32 5 35 0 57 5 40 0 foscin MHz 200535B2 LMX233xU TSSOP OSCin Input Impedance Vs Frequency 2 50V 10000 25 8000 6000 4000 OSCin POWERED DOWN 2000 OSCin POWER 17 5 20 0 22 5 25 0 27 5 30 0 52 5 55 0 37 5 40 0 foscin MHz 200535B3 www national com 20 LMX243x UTCSP FinRF Input Impedance Table EN 2 50V 25 C Angle Re ZFinRF 0
25. B counters The following equations are useful in determining and program ming a particular value of N N PxB A Fin x Definitions RF or IF phase detector comparison frequency Fin RF or IF input frequency A RF_A or IF_A counter value B RF_B or IF_B counter value P Preset modulus of the dual modulus prescaler LMX2430 RF synthesizer P 8 or 16 LMX2433 RF synthesizer P 8 or 16 LMX2434 RF synthesizer P 16 or 32 LMX248x IF synthesizer P 8 or 16 1 5 PHASE FREQUENCY DETECTORS The RF and IF phase frequency detectors PFD are driven from their respective N and R counter outputs The maxi mum frequency for both the RF and IF phase detector inputs is 10 MHz The PFD outputs control the respective charge pumps The polarity of the pump up or pump down control signals are programmed using the RF_CPP or IF_CPP con trol bits depending on whether the RF or IF VCO character istics are positive or negative Refer to Sections 2 4 2 and 2 7 2 for more details The PFDs have a detection range of 2 to 27 The PFDs also receive a feedback signal from the charge pump in order to eliminate dead zone www national com 34 1 0 Functional Description continued 1 5 1 Phase Comparator and Internal Charge Pump Characteristics 101 ET 3 1 Notes 20053511 1 The minimum width of the pump up and pump down current pulses occur at the CPoutRF or CPoutlF
26. COUNTERS The programmable feedback dividers operate in concert with the prescalers to divide the input signal Fin by a factor of N The output of the programmable reference divider is pro vided to the feedback input of the phase detector circuit The divide ratio should be chosen such that the maximum phase comparison frequency OF fcompir of 10 MHz is not exceeded The programmable feedback divider circuit is comprised of an A counter swallow counter and a B counter program mble binary counter For both the LMX2430 and LMX2433 the RF A counter is a 4 bit swallow counter programmable from 0 to 15 The LMX2434 RF counter is a 5 bit swallow counter programmable from 0 to 31 The LMX243x IF counter is a 4 bit swallow counter programmable from to 15 For both the LMX2430 and LMX2433 the RF B counter is a 15 bit binary counter programmable from 3 to 32767 The LMX2434 RF B counter is a 14 bit binary counter programmable from 3 to 16383 The LMX243x IF B is a 14 bit binary counter programmable from 3 to 16383 A continuous integer divide ratio is achieved if N gt P 1 where P is the value of the prescaler selected Divide ratios less than the minimum continuous divide ratio are achiev able as long as the binary programmable counter value is greater than the swallow counter value B 2 A Refer to Sections 2 5 1 1 2 5 1 2 2 5 2 1 2 5 2 2 2 8 1 and 2 8 2 for details on how to program the A and
27. Counter R4 20 7 The IF B control word is used to setup the IF synthesizers B counter The B counter is a 14 bit programmable binary counter used in the programmable feedback divider The B control word be programmed to values ranging from 3 to 16383 Divide ratios less than 3 are prohibited Divide IF B 13 0 Ratio 2 1 0 3 0 1 1 4 1 0 0 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 8 3 IF P IF Synthesizer Prescaler Select R4 22 The LMX243x IF synthesizer utilizes a selectable dual modulus prescaler An 8 9 or a 16 17 prescale ratio can be selected Control Bit IF P Register Location R4 22 Description IF Prescaler Select 8 9 Prescaler Selected Function 16 17 Prescaler Selected 2 8 4 IF PD IF Synthesizer Powerdown R4 23 The PD bit is used to switch the IF PLL between a powered up and powered down mode Furthermore the IF PD bit operates in conjuction with the bit to set a synchronous or an asynchronous powerdown mode Refer to Section 2 7 4 for more details on how to program the CPT bit Control Bit Register Location Description 0 Function 1 IF PD R4 23 IF Powerdown IF PLL Active IF PLL Powerdown 45 www national com VevecxiN TeevexiN Yoev eX LMX2430 LMX2433 LMX2434 2 0 Programming Description continued 2 9 R5 REGISTER The R5 Register cont
28. E output or as a Fastlock output by programming the TOC appropriately When the TOC is programmed from 0 to 3 Automatic Fastlock is disabled and the FLoutRF pin is either configured a general purpose CMOS TRI STATE output or Manual Fastlock is enabled When the RF TOC is programmed to 0 the FLoutRF pin will be in TRI STATE high impedance mode The charge pump current is then the value specified by RF CPG RO 19 When the RF TOC is programmed to 1 the FLoutRF pin is pulled to a LOW state The charge pump current is then set to a HIGH gain state CPG bit 1 This condition is known as the Manual Fastlock When the RF TOC is programmed to 2 the FLout RF pin will again be pulled to a LOW state but this time the charge pump current is the value specified by CPG RO 19 When the RF TOC is programmed to 3 the FLoutRF pin is pulled to a HIGH state Again the charge pump current is the value specified by RF CPG RO 19 When the TOC is programmed from 4 to 4095 Fastlock is enabled and the FLoutRF pin is pulled to a LOW state Fastlock will time out after the specified number of PFD events At this time the FLoutRF pin will switch to TRI STATE high impedance mode The value programmed into RF TOC represents the number of PFD events that the RF synthesizer will spend in the Fastlock state Note that any write to the TOC requires a PFD event on the RF synthesizer to latch the contents This means that writes to the RF
29. EVeXIN Yoev eX LMX2430 LMX2433 LMX2434 LMX243x TSSOP OSCin Input Impedance Table EN 2 50V 25 C foscin ENosc 1 ENosc 0 MHz Re ZOSCin Im ZOSCin IZOSCinl Re ZOSCin Im ZOSCin IZOSCinl Q Q Q Q Q Q 5 0 1111 30 4814 09 4940 69 654 13 7449 33 7477 99 75 52881 10 0 355 99 15 0 203 53 1801 24 1812 70 2597 16 2601 63 17 5 134 32 1548 50 1554 32 2222 34 2223 86 20 0 109 85 1343 30 1347 78 1956 99 1957 94 22 5 80 56 1192 73 1195 45 1730 53 1731 18 25 0 69 37 1063 72 1065 98 1553 43 1554 15 27 5 60 10 973 84 975 70 37 83 1414 54 1415 04 30 0 50 30 890 31 891 73 34 80 1290 03 1290 50 32 5 45 52 816 01 817 28 29 72 1188 88 1189 25 35 0 41 55 758 24 759 38 31 50 1096 89 1097 35 37 5 37 73 707 57 708 57 23 04 1024 88 1025 14 40 0 36 09 661 87 662 86 22 61 963 11 963 38 www national com 28 LMX243x Charge Pump Test Setup DC POWER SUPPLY LMX243xSLE PLL CPoutlF ENosc OSCout FLoutlF OSCin Ftest LD 100 pF The block diagram above illustrates the setup required to measure the LMX243x device s RF charge pump sink cur rent The same setup is used for the LMX2430TM Evaluation Board The purpose of this test is to assess the functionality of the RF charge pump The IF charge pump is evaluated in the same way This setup uses an open loop configuration A power supply is conne
30. F PLLs are powered up Powerdown is then controlled through the MICROWIRE When this pin is set LOW the device is asynchronously powered down and the charge pump output is forced to a high impedance state TRI STATE IF PLL charge pump output The output is connected to the external loop filter which drives the input of the IF VCO Oscillator Enable input High impedance CMOS input When this pin is set HIGH the oscillator buffer is always powered up independent of the state of the EN pin When this pin is set LOW the OSCout FLoutlF pin functions as an IF Fastlock output which connects a resistor in parallel to R2 of the external loop filter OSCout FLoutlF Oscillator output IF PLL Fastlock output The output configuration is dependent on the state of the ENosc pin When ENosc is set LOW the pin functions as an IF Fastlock output which connects a resistor in parallel to R2 of the external loop filter This configuration also functions as a general purpose CMOS TRI STATE output When ENosc is set HIGH the pin functions as an oscillator output so that an external crystal can be used Reference oscillator input The input has an approximate Vcc 2 threshold and is driven by an external AC coupled source 10 Ftest LD Power supply bias for the RF PLL digital circuits and oscillator circuits Vcc may range from 2 25V to 2 75V Bypass capacitors should be placed as close as possible to this pin and be connected dir
31. Frequency Detector Tuning Tuning Polarity Characteristics Characteristics RF VCO Characteristics RF_CPP 1 RF VCO OUTPUT FREQUENCY RF_CPP 0 RF VCO INPUT VOLTAGE 20053567 39 www national com VevecxiN VEEVeXIN VOEVCXINI LMX2430 LMX2433 LMX2434 2 0 Programming Description continued 2 4 3 RF CPG RF Synthesizer Charge Pump Current Gain 0 19 The RF CPG bit controls the RF synthesizer s charge pump gain Two gain levels are available RF CPG 0 19 RF Charge Pump LOW HIGH omm om oam 2 4 4 CPT RF Synthesizer Charge Pump TRI STATE RO 20 The RF CPT bit allows the charge pump to be switched between a normal operating mode and a high impedance output state This happens asynchronously with the change in the RF CPT bit Furthermore the bit operates in conjuction with the RF bit to set a synchronous or an asynchronous powerdown mode Refer to Section 2 5 4 for more details on how to program the RF PD bit Description Control Bit Register Location Ead Function 0 1 RF Charge Pump RF Charge Pump Normal Operation Output in High Impedance State Control Bit Register Location Description RF CPT RO 20 RF Charge Pump TRI STATE 2 4 5 RF_RST RF Synthesizer Counter Reset RO 21 The RF RST bit resets the RF A B and RF R counters After removing the reset the RF A and RF B counters resume counting in close alignment with the
32. Level Input Voltage 1 6 Vu Low Level Input Voltage 0 4 V High Level Input Current Vin 1 0 li Low Level Input Current Vit OV Vou High Level Output Voltage 500 V VoL Low Level Output Voltage lo 500 pA 0 4 V MICROWIRE INTERFACE tcs DATA to CLK Set Up Time Note 9 50 ns tcu DATA to CLK Hold Time Note 9 10 ns town CLK Pulse Width HIGH Note 9 50 ns tow CLK Pulse Width LOW Note 9 50 ns tes CLK to LE Set Up Time Note 9 50 ns tew LE Pulse Width Note 9 50 ns www national com Electrical Characteristics continued Vcc EN 2 5V 40 TA lt 85 C unless otherwise specified Symbol Parameter Conditions Min Value Typ Units Max PHASE NOISE CHARACTERISTICS Line Noise Contribution Note 10 Lyir f Noise Contribution Note 10 Lpe f RF Synthesizer Single Side Band Phase Noise Measured RF Synthesizer Normalized Phase IF Synthesizer Normalized Phase LMX2430 TCXO Reference Source RF_CPG Bit 1 IF_PD Bit 1 TCXO Reference Source IF_CPG Bit 1 RF_PD Bit 1 ffingr 2750 MHz f 10 kHz offset fcompre 1 MHz Loop Bandwidth 100 kHz Nar 2750 foscin 10 MHz Voscin 1 Vpp RF CPG Bit 1 IF PD Bit 1 Ta 25 C Note 11 219 0 dBc Hz dBc Hz dBc Hz LMX2433 fringe 3200 MHz f 10 kHz offset fcompre 1 MHz Loop Bandwidth 100 kHz 3200 foscin 10
33. Programming Description continued 2 10 MUX 3 0 MULTIFUNCTION OUTPUT SELECT R3 23 22 R0 23 22 The MUX control word is used to determine which signal is routed to the Ftest LD pin MUX 3 0 MUX Output State 0 0 0 0 High Impedance TRI STATE State Output 0 0 0 1 0 0 0 0 0 1 1 RF PLL and IF PLL Digital Lock Detect Open Drain Output 0 1 0 0 PLL Digital Lock Detect Open Drain Output 0 1 0 1 IF PLL Digital Lock Detect Open Drain Output 0 1 1 0 PLL and IF PLL Analog Lock Detect Open Drain Output 0 1 1 1 RF PLL Analog Lock Detect Open Drain Output 1 0 0 0 IF PLL Analog Lock Detect Open Drain Output 1 0 0 1 RF PLL and IF PLL Analog Lock Detect Push Pull Output 1 0 1 0 RF PLL Analog Lock Detect Push Pull Output 1 0 1 1 IF PLL Analog Lock Detect Push Pull Output 1 1 0 0 R 2 Frequency 1 1 0 1 N 2 Frequency 1 1 1 0 RF R 2 Frequency 1 1 1 1 RF N 2 Frequency Notes 1 N B RF P RF A 2 IF_N IF B IF P IF A 47 www national com VevecxiN VEEVeXIN YoevcXIN 1 LMX2430 LMX2433 LMX2434 Physical Dimensions inches millimeters unless otherwise noted 20X o 0 00o 20X O E3 4 2 5 16 0 5 C C LJ Li o D n DIMENSIONS ARE IN MILLIMETERS RECOMMENDED LAND PATTERN 1 1 RATIO WITH PACKAGE SOLDER PADS PIN 1 INDEX AREA 47 2X 3 2 11 16X
34. TOC take effect synchronously with the next PFD event RF TOC 11 0 FastLock Mode FLoutRF Pin Functionality State Fastlock Period PFD Events Magnitude Automatic Fastlock Enabled Automatic Fastlock 4095 Logic LOW State Switches to High Impedance after 4 PFD events FastLock Logic LOW State Switches to High Impedance after 4095 PFD events 0 Disabled N A General Purpose magnitude High Impedance State controlled by RO 19 1 Enabled N A General Purpose 4 mA Manual Fastlock Logic LOW State Logic LOW State controlled by RO 19 3 Disabled General Purpose magnitude 4 Enabled FastLock 4 MA Switches to 1 mA after 4 PFD events 4 Switches to 1 mA after 4095 PFD events www national com 42 2 0 Programming Description 2 7 R3 REGISTER Continued The R register contains the IF R IF CPP IF CPG IF CPT and IF RST control words in addition to two of the four bits that compose the MUX control word The detailed descriptions and programming information for each control word is discussed in the following sections 2 7 1 IF R 14 0 IF Synthesizer Programmable Reference Divider R Counter R3 17 3 The IF reference divider can be programmed to support divide ratios from to 32767 Divide ratios less than 3 are prohibited IF R 14 0
35. ains the IF TOC control word The IF TOC is used to setup the IF syhnthesizer s Fastlock circuitry The IF TOC is a 12 bit binary counter programmable from 0 to 4095 23 22 21 20 19 18 17 16 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 20 0 FIELD R5 01010 0 0 olo IF 11 0 1 0 1 2 9 1 IF TOC 0 11 IF Synthesizer Timeout Counter R5 14 3 The OSCout FLoutlF pin can be configured as a general purpose CMOS TRI STATE output or as a Fastlock output by programming the IF appropriately When the IF TOC is programmed from 0 to 3 Automatic Fastlock is disabled and the OSCout FLoutlF pin is configured as a general purpose CMOS TRI STATE output or Manual Fastlock is enabled When the IF TOC is programmed to 0 the OSCout FLoutlF pin will be in TRI STATE high impedance mode The charge pump current is then the value specified by IF CPG R3 19 When the IF TOC is programmed to 1 the OSCout FLoutlF pin is pulled to a LOW state The charge pump current is then set to a HIGH gain state IF CPG bit 1 This condition is known as the Manual Fastlock When the IF TOC is programmed to 2 the OSCout FLout IF pin will again be pulled to a LOW state but this time the charge pump current is the value specified by IF CPG R3 19 When the IF TOC is programmed to 3 the OSCout FLoutlF pin is pulled to a HIGH state Again the charge pump current is the value specified b
36. an be selected Control Bit Register Location Description R1 22 LMX2430 33 8 9 Prescaler 16 17 Prescaler BIENNIUM lt _ 2 5 3 2 P LMX2434 RF Synthesizer Prescaler Select R1 22 The LMX2434 RF synthesizer utilizes a selectable dual modulus prescaler A 16 17 or a 32 33 prescale ratio can be selected Control Bit Register Location Description Function R1 22 LMX2434 16 17 Prescaler 32 33 Prescaler RF Prescaler Select Selected Selected 41 www national com VevecxiN TeevexiN YO8evcXIN 1 LMX2430 LMX2433 LMX2434 2 0 Programming Description continued 2 5 4 PD RF Synthesizer Powerdown R1 23 The RF PD bit is used to switch the RF PLL between a powered up and powered down mode Furthermore the RF PD bit operates in conjuction with the RF CPT bit to set a synchronous or an asynchronous powerdown mode Refer to Section 2 4 4 for more details on how to program the bit Control Bit Function Register Location Description 2 6 R2 REGISTER The R2 Register contains the RF TOC control word The RF TOC is used to setup the RF syhnthesizer s Fastlock circuitry The TOC is a 12 bit binary counter programmable from 0 to 4095 DATA 20 0 FIELD 2 0 R2 0 0 0 olo 0 RF_TOC 11 0 0 2 6 1 RF TOC 0 11 RF Synthesizer Timeout Counter R2 14 3 The FLoutRF pin can be configured as a general purpose CMOS TRI STAT
37. ance is measured in the same way FinRF pin on the PLL chip Proper grounding near the ex The impedance is measured when the oscillator buffer is posed tip of the semi rigid coaxial cable is required for powered up ENosc is set HIGH and when the oscillator accurate results Note that the DC blocking capacitor is buffer is powered down ENosc pin is set LOW removed for this test The Network Analyzer port is then connected to the other end of the semi rigid coaxial cable In www national com 32 LMX243x Serial Data Input Timing DATA MSB LSB CLK LE ae tes tes teH tew 20053510 Notes 1 DATA is clocked into the 24 bit shift register on the rising edge of CLK 2 The MSB of DATA is shifted in first 33 www national com VevecxiN VEEVCXIN 08v cXIN 1 LMX2430 LMX2433 LMX2434 1 0 Functional Description The basic phase lock loop PLL configuration consists of a high stability crystal reference oscillator a frequency synthe sizer such as the National Semiconductor LMX243x a volt age controlled oscillator VCO and a passive loop filter The frequency synthesizer includes a phase detector current mode charge pump programmable reference R and feed back N frequency dividers The VCO frequency is estab lished by dividing the crystal reference signal down via the reference divider to obtain a comparison reference fre quency This reference signal f is then presented to the input
38. cted to Vcc By means of a signal generator 10 MHz signal is typically applied to the FinRF pin The signal is one of two inputs to the phase frequency detector PFD The 3 dB pad provides a 500 match between the PLL and the signal generator The OSCin pin is tied to Vcc This establishes the other input to the PFD Alternatively this input can be tied directly to the ground plane The EN and ENosc pins are also both tied to Vcc A Semiconductor Parameter Analyzer is connected to the CPoutRF pin and used to measure the sink source and TRI STATE leakage currents Let F represent the frequency of the signal applied to the OSCin pin which is simply zero in this case DC and let represent the frequency of the signal applied to the FinRF CODELOADER LMX2430SLEEBPCB EVALUATION BOARD LEVEL SHIFT BUFFER SEMICONDUCTOR PARAMETER ANALYZER pin The PFD is sensitive to the rising edges of F and Assuming positive VCO characteristics CPP bit 1 the charge pump turns ON and sinks current when the first rising edge of F is detected Since F has no rising edge the charge pump continues to sink current indefinitely In order to measure the RF charge pump source current the RF CPP bit is simply set to negative VCO characteristics in CodeLoader Similarly in order to measure the TRI STATE leakage current the RF CPT bit is set to 1 The measurements are typically taken over supply vol
39. ctive prescaler phase detector and charge pump circuit is dis abled The CPoutRF CPoutlF FinRF FinlF and FinRF pins are all forced to a high impedance state The reference divider and feedback divider circuits are held at the load point during powerdown The oscillator buffer is disabled when the ENosc pin is set LOW The OSCin pin is forced to a HIGH state through an approximate 100 resistance when this condition exists When either synthesizer is acti vated the respective prescaler phase detector charge pump circuit and the oscillator buffer are all powered up The feedback divider and reference divider are held at their load point This allows the reference oscillator feedback divider reference divider and prescaler circuitry to reach proper bias levels After a finite delay the feedback and reference dividers are enabled and they resume counting in close alignment the maximum error is one prescaler cycle The MICROWIRE control register remains active and ca pable of loading and latching data while in powerdown mode 1 11 1 Synchronous Powerdown Mode In this mode the powerdown function is gated by the charge pump When the device is configured for synchronous pow erdown the device will enter the powerdown mode upon completion of the next charge pump pulse event 1 11 2 Asynchronous Powerdown Mode In this mode the powerdown function is NOT gated by the completion of a charge pump pulse event When the device is
40. dBm 1 1 40 50 1 1 1 40 50 LMX2434 FinRF Input Power Vs Frequency Vcc EN 2 35V T 859C 0 500 1000 1500 2000 2500 3000 3500 40 fringe M 00 4500 5000 5500 6000 6500 7000 7500 Hz 20053596 LMX2434 FinRF Input Power Vs Frequency Vcc EN 2 75V 0 500 1000 1500 2000 2500 3000 3500 40 fringe M 00 4500 5000 5500 6000 6500 7000 7500 Hz 20053597 13 www national com VevecxiN VEEVCXIN 08v cXIN 1 LMX2430 LMX2433 LMX2434 Typical Performance Characteristics Sensitivity Continued LMX2430 Input Power Vs Frequency Vcc EN 2 25V 1200 1200 10 1 Jy o o Ty 25 C TA 409C TA 859C a 710 55 x 5 720 5 Ty 25 C 30 2 m 50 0 100 200 300 400 500 600 700 800 900 1000 1100 MHz 20053598 LMX2430 Input Power Vs Frequency Vcc EN 2 75V 10 T T AT AT AT 710 5 20 L z 22 Ty 859 Ty 425 C E gt lt 40 T 409 50 0 100 200 300 400 500 600 700 800 900 1000 1100 MHz 20053599 www national com 14 Typical
41. e timeout counter register RF TOC IF with the appro priate number of phase comparison cycles that the RF IF synthesizer will spend in the Fastlock state Refer to Sec tions 2 6 and 2 9 for details on how to configure the FLoutRF or OSCout FLoutlF output to an open drain Fast lock output 1 10 COUNTER RESET When the RF RST IF bit is enabled both the feed back divider N and reference divider RF R are held at their load point When the device is pro grammed to normal operation both the feedback divider and reference divder are enabled and resume counting in close alignment to each other Refer to Sections 2 4 5 and 2 7 5 for more details 1 11 POWER CONTROL The LMX243x device can be asynchronously powered down when the EN pin is set LOW independent of the state of the powerdown bits Note that the OSCout FLoutlF pin can still be enabled if the ENosc pin is set HIGH independent of the state of the EN pin This capability allows the oscillator buffer to be used as a crystal oscillator When EN is set HIGH powerdown is controlled through the MICROWIRE The powerdown word is comprised of the PD IF PD bit in conjuction with the CPT IF CPT bit The powerdown control word is used to set the operating mode of the device Refer to Sections 2 4 4 2 5 4 2 7 4 and 2 8 4 for details on how to program the RF or IF powerdown bits When either synthesizer is powered down the respe
42. ectly to the ground plane Programmable multiplexed output Functions as a general purpose CMOS TRI STATE output N and R divider output RF IF PLL push pull analog lock detect output RF IF PLL open drain analog lock detect output or RF IF PLL digital filtered lock detect output 3 www national com VevecxiN TeevexiN 08v cXIN 1 LMX2430 LMX2433 LMX2434 Pin Descriptions continued Pin No UTCSP TSSOP Pin Name 1 0 Description 10 FLoutRF 11 12 GND 12 CPoutRF RF PLL Fastlock output This pin connects resistor in parallel to R2 of the external loop filter This pin can also function as a general purpose CMOS TRI STATE output Ground for the RF PLL digital circuits RF PLL charge pump output The output is connected to the external loop filter which drives the input of the RF VCO 13 GND Ground for the RF PLL analog circuits 14 FinRF PLL prescaler input Small signal input from the VCO 15 FinRF RF PLL prescaler complementary input For single ended operation this pin should be AC grounded through a 100 pF capacitor The LMX243x can be driven differentially when the AC coupled capacitor is omitted 16 Power supply bias for the RF PLL analog circuits Vcc may range from 2 25V to 2 75 Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane 17 MICROWIRE Latch Enable input
43. electing the RF N 2 Fre limits this can introduce spurs or cause degradation to the quency word MUX 3 0 word 15 in CodeLoader Uni phase noise When the power level gets even closer to these versal Counter is connected to the Ftest LD pin and used to limits or exceeds it then the RF PLL loses lock monitor the output frequency of the feedback divider The www national com 30 LMX243x OSCin Sensitivity Test Setup DC POWER SUPPLY LMX243xSLE PLL CPoutlF ENosc 1000 pF OSCout FLoutlF SIGNAL GENERATOR OSCin 8 0 01 uF 100 pF The block diagram above illustrates the setup required to measure the LMX243x device s OSCin buffer sensitivity level The same setup is used for the LMX2430TM Evalua tion Board This setup is similar to the FinRF sensitivity setup except that the signal generator is now connected to the OSCin and both Fin pins are tied to Vcc The 510 shunt resistor matches the OSCin input to the signal generator The counter is typically set to 1000 i e RF word 1000 or IF R word 1000 The reference divider output is routed to the Ftest LD pin by selecting the RF R 2 Frequency word MUX 3 0 word 14 or the IF R 2 Frequency word MUX 3 0 word 12 in CodeLoader A Universal Counter is connected to the Ftest LD pin and is used to monitor the UNIVERSAL COUNTER CODELOADER LMX2430SLEEBPCB EVALUATION BOARD LEVEL SHIFT BUFFER 20053590 output f
44. er phase noise is measured with the LMX2430TM LMX2430SLE Evaluation boards and the HP8566B Spectrum Analyzer www national com VevecxiN VEEVCXIN VOEPCXIN LMX2430 LMX2433 LMX2434 1 0V Charge Pump Current Specification Definitions VOLTAGE OFFSET IcPout MA Vcc 20053537 11 Charge Pump Sink Current at AV 12 Charge Pump Sink Current at Vcc 2 Charge Pump Sink Current at AV 14 Charge Pump Source Current at AV 15 Charge Pump Source Current at Vcc 2 16 Charge Pump Source Current at AV AV Voltage offset from the positive and negative rails Dependent on the VCO tuning range relative to Vcc and GND Typical values are between 0 5V and refers to either OF VCPoutlF Icpou refers to either OF Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage Qut 3 IcPout VS x 100 11 5 14 16 x 141416 20053563 100 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch 112 15 lepout Sink Vs Source 00 X 1 121515 20053564 Charge Pump Output Current Magnitude Variation Vs Temperature _ 896 100 2 25 C hsi Ils 5 25 C
45. est LD word This is essential when performing OSCin or Fin sensitivity measure ments Refer to the LMX243x FinRF Sensitivity Test Setup or LMX243x OSCin Sensitivity Test Setup sections for more details Note the R and N outputs that are routed to the Ftest LD are R 2 and N 2 respectively The internal 2 circuit is used to provide a 5096 duty cycle Refer to Section 2 10 for more details on how to route the appropriate divider output to the Ftest LD pin 1 9 FASTLOCK OUTPUT The LMX243x Fastlock feature allows a faster loop response time during lock aquisition The loop response time lock time can be approximately halved if the loop bandwidth is doubled In order to achieve this the same gain phase relationship should be maintained when the loop bandwidth is doubled When the FLoutRF or OSCout FLoutlF pins are configured as FastLock outputs an open drain device is enabled The open drain device switches in a resistor paral lel and of equal value to R2 of the external loop filter The loop bandwidth is effectively doubled and stability is main tained Once locked to the correct frequency the PLL will return to a steady state condition The LMX243x offers two methods to achieve Fastlock manual and automatic Manual Fastlock is achieved by increasing the charge pump current from 1 mA RF CPG IF CPG Bit 0 in the steady state mode to 4 mA RF CPG IF CPG Bit 1 Fastlock mode Automatic Fastlock is achieved by programming th
46. l filter compares the difference bewteen the phases of the inputs to the PFD to an RC generated delay of approximately 15 ns If the phase error is less than the 15 ns RC delay for 5 consecutive reference Phase Phase Err Error lt 15 ns Phase Phase Error lt 15 ns Error lt 15 ns Lock HIGH Locked State Phase Error gt 30 ns Similarly three separate digital filtered lock detect signals are routed to the multiplexer Two of these monitor the lock status of the individual synthesizers The third detects the condition when both the RF and IF synthesizers are in a E or X 15 ns cycles the PLL enters a locked state HIGH Once in lock the RC delay is changed to approximately 30 ns Once the phase error becomes greater than the 30 ns RC delay the PLL falls out of lock LOW When the PLL is in powerdown mode the Ftest LD output is forced LOW A flow chart of the digital filtered lock detect output is shown below Lock LOW Not Locked No No 20053503 locked state External circuitry is not required when the digital filtered lock detect option is selected Refer to Section 2 10 for details on how to program the different digital filtered lock detect options www national com 36 1 0 Functional Description continued 1 8 4 Reference Divider and Feedback Divider Output The outputs of the various N and R dividers can be moni tored by selecting the appropriate Ft
47. of the PLL chip Outside the 50 duty cycle acceptable signal range the feedback divider begins to di Sensitivity is typically measured over frequency supply volt vide incorrectly and miscount the frequency The FinlF sen age and temperature In order to perform the measurement sitivity is evaluated in the same way the temperature frequency and supply voltage is set to a The setup uses an open loop configuration A power supply fixed value and the power level of the signal at FinRF is is connected to Vcc The IF PLL is powered down IF PD bit varied Sensitivity is reached when the frequency error of the 1 By means of a signal generator an RF signal is applied divided RF input is greater than or equal to 1 Hz The power to the FinRF pin The dB pad provides a 500 match attenuation from the cable and the 3 dB pad must be ac between the PLL and the signal generator The EN ENosc counted for The feedback divider will actually miscount if too and OSCin pins are all tied to Vcc The value is typically much or too little power is applied to the FinRF input There set to 10000 in CodeLoader i e RF B word 156 and fore the allowed input power level will be bounded by the A word 16 for RF P bit 0 LMX2434 or RF P bit upper and lower sensitivity limits In a typical application if 1 LMX2430 and LMX2433 The feedback divider output is the power level to the FinRF input approaches the sensitivity routed to the Ftest LD pin by s
48. pins when the loop is phase locked fr is the PFD input from the reference divider counter CPout refers to either the RF or IF charge pump output 1 6 CHARGE PUMPS The charge pump directs charge into or out of an external loop filter The loop filter converts the charge into a stable control voltage which is applied to the tuning input of the VCO The charge pump steers the VCO control voltage towards Vcc during pump up events and towards GND dur ing pump down events When locked CPoutRF or CPoutlF are primarily in a TRI STATE mode with small corrections occuring at the phase comparator rate The charge pump output current magnitude can be selected by toggling the RF CPG or IF CPG control bits 1 7 MICROWIRE SERIAL INTERFACE The programmable register set is accessed via the MI CROWIRE serial interface A low voltage logic interface allows direct connection to 1 8V devices The interface is comprised of three signal pins CLK DATA and LE Serial data is clocked into the 24 bit shift register on the rising edge of CLK The last two bits decode the internal control register address When LE transitions HIGH DATA stored in the shift register is loaded into one of four control registers depending on the state of the address bits The MSB of DATA is loaded in first The synthesizers can be programmed even in power down mode A complete programming description is pro vided in Section 2 0 Programming Description 1 8
49. rence divider circuits feeds the reference input of the phase detector This reference input to the phase detector is often referred to as the comparison frequency The divide ratio should be chosen such that the maximum phase comparison frequency PRF Of fcompir Of 10 MHz is not exceeded The RF and IF reference dividers are each comprised of 15 bit CMOS binary counters that support a continuous in teger divide ratio from 3 to 32767 The RF and IF reference divider circuits are clocked by the output of the reference buffer circuit which is common to both Refer to Sections 2 4 1 and 2 7 1 for details on how to program the RF and IF R counters 1 3 PRESCALERS The FinRF and FinlF input pins drive the input of a differential pair amplifier The output of the differential pair amplifier drives a chain of D type flip flops in a dual modulus configuration The output of the prescaler is used to clock the subsequent feedback dividers The RF PLL complementary inputs can be driven differentially or the negative input can be AC coupled to ground through an external capacitor for single ended configuration A 16 17 or a 32 33 prescale ratio can be selected for the 5 0 GHz LMX2434 RF synthesizer An 8 9 or a 16 17 prescale ratio can be selected for both the LMX2430 and LMX2433 RF synthesizers The IF PLL is single ended An 8 9 or a 16 17 prescale ratio can be se lected for the IF synthesizer 1 4 PROGRAMMABLE FEEDBACK DIVIDERS N
50. requency of the reference divider The expected frequency should be the signal generator frequency divided by twice the corresponding counter value i e 2000 The factor of two comes in because the LMX243x device has an internal 2 circuit which is used to provide a 5096 duty cycle In a similar way sensitivity is typically measured over fre quency supply voltage and temperature In order to perform the measurement the temperature frequency and supply voltage is set to a fixed value and the power level voltage level of the signal at OSCin is varied Sensitivity is reached when the frequency error of the divided input signal is greater than or equal to 1 Hz 31 www national com VevecxiN VEEVeXIN Yo8evcXIN 1 LMX2430 LMX2433 LMX2434 LMX243x FinRF Input Impedance Test Setup CODELOADER LMX2430SLEEBPCB EVALUATION BOARD DC POWER SUPPLY LEVEL SHIFT BUFFER LMX243xSLE PLL CPoutlF ENosc OSCout FLoutlF OSCin 0 01 uF 100 pF 20053591 The block diagram above illustrates the setup required to this way the semi rigid coaxial cable acts as a transmission measure the LMX243x device s RF input impedance The line This transmission line adds electrical length and pro same setup is used for the LMX2430TM Evaluation Board duces an offset from the reference plane of the Network Measuring the device s input impedance facilitates the de Analyzer therefore it must be included in the calibration sign of
51. ster are allocated to specific control functions The bits that are marked should be programmed as such to ensure proper device operation DATA 20 0 FIELD BF_ RF 855 LMX2430 33 LMX2430 33 RF B 14 0 RF A 3 0 LMX2434 LMX2434 B 13 0 RF A 4 0 RF TOC 11 0 R1 R3 R 14 0 1 RST CPT CPG E IF 8 3 0 IF_A 3 0 0 www national com 38 2 0 Programming Description continued 2 4 RO REGISTER The RO register contains the RF RF CPP RF CPG RF and RST control words in addition to two of the four bits that compose the MUX control word The detailed descriptions and programming information for each control word is discussed in the following sections 2 4 1 RF R 14 0 RF Synthesizer Programmable Reference Divider Counter 80 17 3 The RF reference divider can be programmed to support divide ratios from 3 to 32767 Divide ratios less than 3 prohibited RF R 14 0 2 4 2 CPP RF Synthesizer Phase Detector Polarity RO 18 The RF CPP bit is used to control the RF synthesizer s phase frequency detector polarity based on the VCO tuning characteristics Control Bit Register Location Description Function 0 1 CPP RO 18 RF Phase RF VCO Negative RF VCO Positive
52. surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Americas Customer Europe Customer Support Center Asia Pacific Customer Japan Customer Support Center Support Center Fax 49 0 180 530 85 86 Support Center Fax 81 3 5639 7507 Email new feedback 9 nsc com Email europe support nsc com Email ap support nsc com Email jpn feedback 9 nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 Tel 61 3 5639 7560 English Tel 44 0 870 24 0 2171 www national com Francais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
53. tage and temperature The measurements are also typically taken at the HIGH and LOW charge pump current gains The charge pump current gain can be controlled by the RF CPG bit in CodeLoader Once the charge pump currents are determined the i charge pump output current magnitude variation versus charge pump output voltage ii charge pump output sink current versus charge pump output source current mismatch and iii charge pump output current mag nitude versus tempeature can be calculated Refer to the Charge Pump Current Specifications Definition for more details 20053588 29 www national com VevcxiN VEEVeXIN YO8evcXIN 1 LMX2430 LMX2433 LMX2434 LMX243x FinRF Sensitivity Test Setup CODELOADER LMX2430SLEEBPCB EVALUATION BOARD DC POWER SUPPLY LEVEL SHIFT BUFFER LMX243xSLE PLL CPoutlF ENosc OSCout FLoutlF OSCin 58 SIGNAL GENERATOR 10 MHz REF OUT 0 01 uF 100 pF UNIVERSAL COUNTER 20053589 The block diagram above illustrates the setup required to expected frequency should be the signal generator fre measure the LMX243x device s RF input sensitivity level quency divided by twice the corresponding counter value The same setup is used for the LMX2430TM Evaluation i e 20000 The factor of two comes in because the LMX43x Board The purpose of this test is to measure the acceptable device has an internal 2 circuit which is used to provide a signal level to the FinRF input
54. uitry with integrated timeout counters Furthermore only a single word write is required to power up and tune the synthesizers to a new frequency Serial data is transferred to the devices via a three wire interface DATA LE CLK A low voltage logic interface allows direct connection to 1 8V devices Supply voltages from 2 25V to 2 75V are supported The LMX243x family Applications features low current consumption m Mobile Handsets LMX2430 3 0 GHz 0 8 GHz 2 8 1 4 mA LMX2433 GSM GPRS W CDMA CDMA PCS AMPS PDC 3 6 GHz 1 7 GHz 3 2 mA 2 0 mA LMX2434 5 0 GHz DCS m Analog Lock Detect Output supports both Push Pull and Open Drain configurations m 1 8V MICROWIRE Logic Interface m Available in 20 Pin TSSOP and 20 Pin UTCSP 2 5 GHz 4 6 mA 2 4 mA at 2 50V m Cordless Handsets The LMX243x devices are available in 20 Pin TSSOP and DECT DCT 20 Pin UTCSP surface mount plastic packages m Wireless Data Cable TV Tuners Thin Shrink Small Outline Package MTC20 Ultra Thin Chip Scale Package SLE20A 20053580 20053581 PLLatinum is a trademark of National Semiconductor Corporation 2003 National Semiconductor Corporation DS200535 www national com suoneoiunululo 8 05494 10 1eziseuju s 3 9 5944 v rzXIWT EEveXIW1 0 teXIW 1 LMX2430 LMX2433 LMX2434 Functional Block Diagram 9 16 17 20 1
55. ww national com VevecxiN VEEVeXIN YoevcXIN 1 LMX2430 LMX2433 LMX2434 LMX243x TSSOP FinlF Input Impedance Table EN 2 50V 25 C frinir MHz Angle 0 ZFinlF 0 Im ZFinlF Q IZFinIFI 9 100 7 11 400 44 348 14 530 62 200 300 400 500 600 9 92 288 69 318 81 430 10 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 www national com LMX243x UTCSP OSCin Input Impedance Table EN 2 50V 25 C ENosc 1 ENosc 0 Re ZOSCin Im ZOSCin IZOSCinl Re ZOSCin Im ZOSCin IZOSCinl 9 9 9 9 9 9 5032 01 10120 58 11302 53 2641 63 13293 58 13553 50 7803 46 1108 82 8932 61 9001 17 5866 06 526 74 6461 11 6482 55 5041 60 330 16 5452 11 5462 10 4099 58 4160 72 233 66 4455 98 4462 10 3584 60 3625 92 212 67 3822 33 3828 24 3125 21 3156 35 192 16 3306 06 3311 64 2806 10 2823 63 112 07 2963 67 2965 79 2518 94 2538 75 143 65 2657 93 2661 81 2290 95 84 09 2405 34 2406 81 2114 30 40 38 2196 07 2196 45 1950 35 77 29 2044 88 2046 34 35 0 158 95 1816 83 1823 77 67 31 1898 92 1900 12 37 5 137 80 1701 59 1707 16 51 11 1775 84 1776 58 40 0 114 20 1573 28 1577 42 50 39 1652 06 1652 83 27 www national com VevecxiN VE
56. y IF CPG R3 19 When the IF TOC is programmed from 4 to 4095 Fastlock is enabled and the OSCout FLoutlF pin is pulled to a LOW state Fastlock will time out after the specified number of PFD events At this time the OSCout FLoutlF pin will switch to TRI STATE high impedance mode The value programmed into represents the number of PFD events that the IF synthesizer will spend in the Fastlock state Note that any write to the IF TOC requires a PFD event on the IF synthesizer to latch the contents This means that writes to the IF TOC take effect synchronously with the next PFD event IF TOC 11 0 FastLock Mode Fastlock Period OSCout FLoutlF Pin Magnitude PFD Events Functionality State 0 Disabled N A General Purpose lopoutie Magnitude High Impedance State controlled by R3 19 1 Enabled N A General Purpose lepouur 4 mA Manual Fastlock Logic LOW State 2 Disabled General Purpose lcPoutir magnitude Logic LOW State controlled by R3 19 3 Disabled General Purpose lcPoutir magnitude Logic HIGH State controlled by R3 19 4 Enabled FastLock lcPoutir 4 mA Automatic Fastlock Logic LOW State Switches to 1 mA after Switches to High 4 PFD events Impedance after 4 PFD events 4095 Enabled 4095 FastLock lcPoutir 4 mA Automatic Fastlock Logic LOW State Switches to 1 mA after Switches to High 4095 PFD events Impedance after 4095 PFD events www national com 46 2 0

National LMX2430/LMX2433/LMX2434 handbook

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