National LMX2364 handbook
Contents
1. 20X 2 TH SLE24A Rev A Ultra Thin Chip Scale Package SLE For Tape and Reel 2500 Units per Reel Order Number LMX2364SLEX NS Package Number SLE24A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user N National Semiconductor Europe Customer Support Center 49 0 180 530 85 86 National Semiconductor Americas Customer Support Center Fax Email new feedback nsc com Email europe support nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 English Tel 44 0 870 24 O 2171 www national com Fran ais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to ca2. The RF CPF 1 0 word is used to control the charge pump gain for the RF synthesizer when FastLock is enabled and engaged Four different CP gains are supported ranging from 1 to 16 mA Note that when RF FastLock mode is disengaged or disabled the charge pump gain is controlled by RF CP 1 0 Pa TT Am S 2 8 3 RF OM 1 0 RF Synthesizer Operating Mode RF OM 1 0 controls the operating mode of the RF synthesizer The various operating modes are described below RF Synthesizer Operating Mode Descriptions arom Fecneriep Operating Mode Operating Mode Description 5 o f meo RF synthesizer avays operates as an lnteger NPL Note that the Fractional Enable Bit FE R6 16 needs to be set appropriately Enabling the fractional compensation in Integer mode always degrades performance It is generally recommended to enable it in fractional mode although there may be some rare exceptions that it may be set to 0 2 8 4 RF CSR 1 0 Cycle Slip Reduction Control RF Synthesizer RF CSR 1 0 controls the operation of the cycle slip reduction circuitry This circuit can be used eliminate the occurrence of phase detector cycle slips when operating in Fractional Mode RF OM 1 When operating in integer mode the cycle slip reduction circuitry should be disabled by setting RF CSR 0 RF CSR CSR State Sample Rate Reduction Factor www national com 32 Programming Description Continued 2 9 R6 REGISTER 25 22 er
3. 20 log N 10log fcomp where L f is defined as the single side band phase noise measured at an offset frequency f in a 1 Hz Bandwidth The offset frequency f must be chosen sufficiently smaller than the PLL s loop bandwidth yet large enough to avoid substantial phase noise contribution from the reference source www national com Serial Data Input Timing Data DATA 23 MSB K DATA 22 DATA N 1 CTL 0 LSB Clock LE OR LE 20050603 Note Data is shifted MSB first into the MICROWIRE shift register on the rising edge of the Clock signal When a rising edge is seen on the LE pulse these values are actually loaded into the PLL target registers Since the data is clocked in on the rising edge of the LE pulse the programming time of one register can be eliminated by sending the Data and Clock signals in advance and delaying the LE pulse until it is desired that the values are to be loaded Note The Serial Data Input Timing is tested using a symmetrical waveform around Vgc 2 The test waveform has an edge rate of 0 6 V ns with amplitudes of 2 2V Vcc 2 7V and 2 6V Vcc 3 3V 7 www national com 79EcXINT LMX2364 Typical Performance Characteristics PN1Hz dBc Hz PN1Hz dBc Hz www national com RF PLL 1 Hz Normalized Phase Noise Fractional Mode 202 204 206 208 210 7 za Zia H Hi pi L COMPARISON FREQUENCY KHz 20050672 IF PLL 1 Hz Normalized Phase Noise 200 2
4. K Fcomp is the ratio of the FastLock comparison frequency to the steady state comparison frequency If this ratio is less than one this implies that the CSR is being used When K is greater than one is necessary to switch a Fast Lock resistor R2 in parallel with R2 in order to keep the loop filter optimized and maintain the same phase margin After the PLL has achieved a freguency that is sufficiently close to the desired freguency the resistor R2 is disengaged and the charge pump current is and comparison freguency are returned to normal Of special concern is the glitch that is caused when the resistor R2 is disengaged This glitch can take up a significant portion of the lock time The LMX2364 has enhanced switching circuitry to minimize this gliteh and therefore improve the lock time The change in loop bandwidth is dependent upon the loop gain multiplier K The theoretical improvement in lock time is given below but the actual improvement will be less than this due to the glitch that is caused by disengaging FastLock The theoretical improvement is given to show an upper bound on what improvement is possible with FastLock In the case that K lt 1 this implies the CSR is being engaged FastLock Loop Bandwidth Steady State Loop Loop Gain Multiplier K R2 Value 20050640 and that the theoretical lock time will be degraded However since this mode reduces or eliminates cycle slipping the actual lock time may be
5. general designs with higher comparison frequencies tend to be less succeptible to degradations in lock time due to capacitor dielectric effects Capacitor dielectrics have very little impact on phase noise or spurs Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances allowing a larger footprint for the loop filter capacitors using a lower charge pump current and reducing the fractional modulus are all ways to reduce ca pacitor values www national com 79EcXINT LMX2364 Physical Dimensions inches millimeters Unless otherwise noted MNO Hini 24X ran L Am ke 22x 0 65 S N 1 I I lM ALL LEAD TIPS PIN 1 ID LAND PATTERN RECOMENDATION 1 1 MAX TYP 0 9 SEE DETAIL A Pg Ng TE 0 20 xj Si Lu 05 TYP 22x 8 0 1 ABO CO ee aan 0 8 DIMENSIONS ARE IN MILLIMETERS SEATING PLANE DETAIL A TYPICAL MTC24 Rev E Thin Shrink Small Outline TSSOP Package Order Number LMX2364TM Rail Order Number LMX2364TMX Tape and Reel NS Package Number MTC24 www national com 38 Physical Dimensions inches millimeters unless otherwise noted Continued EN de L aile CO 24X osni JE CO L o 20X 0 5 O O o ODD RECOMMENDED LAND PATTERN 1 1 RATIO WITH PACKAGE SOLDER PADS PIN 1 INDEX AREA CD 0 08c DIMENSIONS ARE IN MILLIMETERS 4X 0 520 1 LU LI UI 10 24X 0 25 0 01
6. 2003 National Semiconductor Corporation U U LMX23641 1 National Semiconductor LMX2364 July 2003 2 6 GHz PLLatinum Fractional RF Freguency Synthesizer with 850 MHz Integer IF Freguency Synthesizer General Description The LMX2364 integrates a high performance 2 6 GHz frac tional frequency synthesizer with a 850 MHz low power Integer N frequency synthesizer Designed for use in a local oscillator subsystem of a radio transceiver the LMX2364 generates very stable low noise control signals for UHF and VHF voltage controlled oscillators It is fabricated using Na tional s high performance BiCMOS process The RF Synthesizer supports both fractional and integer modes The N counter contains a selectable guadruple modulus prescaler and can support fractional denominators from 1 to 128 A flexible 4 level programmable charge pump supplies output current magnitudes ranging from 1 mA to 16 mA Only a single word write is reguired to power up and tune the synthesizer to a new freguency High performance FastLock technology makes the LMX2364 an excellent choice for applications reguiring ag gressive lock time while maintaining excellent phase noise and spurious performance The combination of the improved FastLock circuitry the enhanced fractional compensation engine and the programmable charge pump architecture gives the designer maximum freedom to optimize the perfor mance of the synthesizer for the target application
7. Sinbo a POE Value mga O tara OSCILLATOR PARAMETERS fosc Oscillator Operating Frequency Vosc losc Oscillator Input Current Units Oscillator Sensitivity OSCinRF OSCinlF V HA o WA DIGITAL INTERFACE DATA CLK LE ENIF ENRF Ftest LD FLoutRF FLoutlF VH High Level Input Voltage Lowtevel Output Votage la soma _ oa VoL MICROWIRE INTERFACE TIMING PHASE NOISE Lr i f RF RF Synthesizer s Normalized Phase Noise Contribution Fractional Mode Note 4 RF Synthesizer s Normalized Phase Noise Contribution Integer Mode Note 4 Lun IF IF Synthesizer s Normalized Phase Noise Contribution Note 4 22 Wess 2 NE ATEN 82 Data to Clock Set Up Time See Data input Timing 80 _ w Data to Clock Hold Time See Data Input Timing 10 ns REN EN ee ns Clock to Load Enable Set See Data Input Timing na Up Time Load Enable Pulse Width See Data Input Timing ns RF_OM 1 Fractional Mode f 3 KHz TCXO Reference Source RF_CP 1 4 mA Venir LOW RF OM 0 Integer Mode f 3 KHz TCXO Reference Source RF_CP 2 4 mA Venir LOW f 3 KHz TCXO Reference Source IF_CP 1 800 mA Venap LOW dBc Hz dBc Hz dBc Hz Note 3 Some reference divider ratios between the minimum and maximum are not realizable See the section on R divider programming for more details Note 4 Normalized Phase Noise Contribution is defined as Lg41Hz f L f
8. 00 o v s a e 468 75 5 C a 896 rn 428 a 0 71 3m 15 www national com V9EcXINT1 LMX2364 Typical Performance Characteristics Ice mA no U1 CURRENT uA www national com Total Current Consumption RF_OM 1 3 75 4 25 Vec V Powerdown Current Venre Venir OV 20050660 20050661 Typical Performance Characteristics continued RF Charge Pump Current VvepRF 3 0V CHARGE PUMP CURRENT mA CHARGE PUMP VOLTAGE V RF Charge Pump Current VvepRF 5 0V CHARGE PUMP CURRENT mA CHARGE PUMP VOLTAGE V 17 20050667 20050668 www national com 79EcXINT LMX2364 Typical Performance Characteristics continued IF Charge Pump Current VvepiF 3 0V CHARGE PUMP CURRENT mA CHARGE PUMP VOLTAGE V IF Charge Pump Current VvepiF 5 0V CHARGE PUMP CURRENT mA CHARGE PUMP VOLTAGE V www national com 18 20050665 20050666 Typical Performance Characteristics continued LEAKAGE nA LEAKAGE nA Charge Pump Leakage RF PLL 4 00 3 00 2 00 1 00 0 00 1 00 0 0 1 0 2 0 3 0 4 0 5 0 CHARGE PUMP VOLTAGE V 20050664 Charge Pump Leakage IF PLL 0 30 0 20 0 00 0 10 0 20 0 0 1 0 2 0 3 0 4 0 5 0 CHARGE PUMP VOLTAGE V 20050663 19 www national com V9EcXINT1 LMX2364 Test Setup Procedures Sensitivity SMA Cable SMA Cable Frequency Coun
9. 2 6 6 RF_RST Counter Reset RF Synthesizer The RF Counter Reset enable bit when activated RF RST 1 allows the reset of both the RF N and RF R dividers Upon powering up the N counter resumes counting in close alignment with the R counter The maximum error is one prescaler cycle 29 www national com 79EcXINT LMX2364 Programming Description Continued 2 7 R4 REGISTER This register is used to setup the N divider for the RF Synthesizer A single word write to this register is all that is required to power up and tune the RF synthesizer to the desired freguency 8 2 a e 6 7 6 6 6 n 0 o 6 7lel5l410 2 Ra RE RF N 12 0 RF FN 6 0 ilo 0 2 7 1 RF FN Fractional Numerator RF Synthesizer In the case that the PLL is operating in fractional mode RF OM 1 RF FN 6 0 specifies the fractional numerator of the complete N counter value of the RF PLL In the case that the PLL is operating in integer mode RF OM 0 RF FN adds to the total value of the N counter Reg Operating Mode RF N Divider Value Calculation Fractional Mode RF OM 1 RF N RF FN RF FD Integer Mode RF OM 0 RF N x RF_FD RF EN 2 7 2 RF N 12 0 N Divider Ratio RF Synthesizer RF N 12 0 specifies an integer value that is used in calculating the N divider ratio for the RF synthesizer In the case the part is operating in fractional mode it value is the N divider ratio In the case the part is operating in integer mode this numb
10. 20 19 18 17 16 18 14 12 n RHH R KN sl EN EN RH E RON PP Fb ee eee bp IA una 2 9 1 MUX 3 0 Coltrol Word for the Ftest LD Pin The MUX 3 0 control word is used to determine the function of the Ftest LD output pin The pin can be setup as a general purpose CMOS TRI STATE I O pin a digital filtered lock detect pin an analog lock detect pin push pull or open drain output or used to view the output of the various R amp N dividers 1 General Purpose I O Logic LOW Output Push Pull 1 1 RF 8 IF Analog Lock Detect Width of Open Drain narrow low pulses determines lock 1 RF Analog Lock Detect Width of narrow Open Drain low pulses determines lock 1 1 IF Analog Lock Detect Width of narrow Open Drain low pulses determines m IF Digital Lock Detect Push Pull 1 1 RF amp IF Analog Lock Detect Width of Push Pull narrow low pulses determines lock RF Analog Lock Detect Width of narrow Push Pull low pulses determines lock IF Analog Lock Detect Width of narrow Push Pull low pulses determines lock IF R Divider 2 Output is divided by 2 to Push Pull simplify testing IF N Divider 2 Output is divided by 2 to Push Pull simplify testing RF R Divider 2 Output is divided by 2 to Push Pull simplify testing RF N Divider 2 Output is divided by 2 to Push Pull simplify testing 2 9 2 OSC Single Resonator Mode The OSC bit selects whether the oscillator input pins OSCinIF and OSCinRF drive the IF and RF R divi
11. Inte grated timeout counters greatly simplify the programming aspects of FastLock These timeout counters reduce the demands on the microcontroller by automatically disengag ing FastLock after a perscribed number of reference cycles of the phase detector The IF synthesizer includes a fixed 8 9 dual modulus pres caler a two level programmable charge pump and dedi cated FastLock circuitry with an integrated timeout counter The LMX2364 offers many performance enhancements over the LMX2354 Improvements in the fractional compensation make the spurs on the LMX2364 approximately 6 dB better in a typical application The higher and more flexible frac tional modulus combined with the higher charge pump cur rents result in phase noise improvements on the order of 10 dB The cycle slip reduction circuitry of the LMX2364 is both easy to use and effective in reducing cycle slipping and allows one to use very high phase detector freguencies without degrading lock times Serial data is transferred to the device via a three wire interface DATA LE CLK The low voltage logic interface FastLock is a trademark of National Semiconductor Corporation TRI STATE is a registered trademark of National Semiconductor Corporation DS200506 allows direct connection to 1 8 Volt and 3 0 Volt devices Supply voltages from 2 7V to 5 5V are supported Indepen dent charge pump supplies for each synthesizer allows the designer to optimize the bias level
12. R Integer Mode RF Rx RF FD Since RF R can take on integer values between 1 511 and RF FD can take on integer values between 1 128 this value can range from 1 65408 although prime values between 512 and 65 408 can not be realized RF R 8 0 RF R Value www national com 28 Programming Description Continued 2 6 3 RF CP 1 0 Charge Pump Gain RF Synthesizer The RF CP word is used to control the charge pump gain for the RF synthesizer Four different CP gains are supported ranging from 1 to 16 mA Note that when RF FastLock mode is enabled and the synthesizer is operating in the FastLock state the charge pump gain is controlled by the RF CPF 1 0 control word Higher charge pump currents yield slightly better phase noise but lead to larger loop filter capacitors and slightly higher current consumption in cases where the comparison freguency is very high RF CP 1 0 Charge Pump Current 2 6 4 RF CPP Phase Detector Polarity RF Synthesizer This bit controls the polarity of phase detector for the RF synthesizer It should be set to one when the chosen RF VCO has positive tuning gain and zero when the tuning gain is negative 2 6 5 RF P Prescaler RF Synthesizer The RF synthesizer utilizes a selectable guadruple modulus prescaler RF P selects between the 8 9 12 13 prescaler and the 16 17 20 21 prescaler as described in the table below RF P 1 0 Selected Prescaler Eo Z CAE 8 16 16 17 20 21
13. Synthesizer power down bit results in the disabling of the respective N divider and de biasing of its respective Fin inputs to a high impedance state The respective R divider functionality also becomes disabled when the power down bit is activated The OSCinIF pin reverts to a high impedance state when both RF and IF power down bits are asserted Power down forces the respective charge pump and phase comparator logic to a TRI STATE condition The MICROWIRE control register remains active and capable of loading and latching in data during all of the power down modes Both synchronous and asynchronous power down modes are supported The power down mode bit R6 8 is used to select between synchronous and asynchronous power down The MICROWIRE control register remains active and capable of loading and latching in data in either power down mode Synchronous Power Down Mode The IF synthesizer can be synchronously powered down by first setting the power down mode bit HIGH R6 8 1 and then asserting its power down bit R1 23 1 The power down function is gated by the charge pump Once the power down bit is loaded the part will go into power down mode upon the completion of a charge pump pulse event Asynchronous Power Down Mode The IF synthesizer can be asynchronously powered down by first setting the power down mode bit LOW R6 8 0 and then asserting its power down bit R1 23 1 The power down function is NOT gated by the charge pump Once t
14. VvopRF 2 RF_CP 2 VcPoutRF VvcpRE 2 RF_CP 3 H 16 VCPoutRF VVcpRF 2 lcpoutrr T RI RF Charge Pump 0 5 lt Vcpoutr S VvepRE 0 5 ABO 10 0 TRI STATE Current lcpoutrr MIS RF CP Sink VS CP Source VcPoutRF VVcpRF 2 o 3 5 Mismatch Tas25C lcpoutrr V RF CP Current vs CP 0 5 lt Vcpoutr lt VvepRE 0 5 TA 25 C RF_CP 0 1 or 2 lepoutre TEMP RF CP Current VS VP cPoutRF VvepRF 12 10 Temperature IF SYNTHESIZER PARAMETERS N IF Continuous N Divider 262 143 Range R IF R Divider Range fcomp Phase Detector Frequency PFinlF IF Input Sensitivity 2 7 ZN lt SAV Voltage 32 767 3 mm do lcPoutr RCE IF Charge Pump Source IE CP 0 Current V cpoutiF Vvepir 2 IF_CP 1 VepoutiF V cplF 2 lcpoutirSINK IF Charge Pump Sink IF CD 0 Current Vopoutit Vycpir 2 IF_CP 1 V epoutiF VvcpiF l2 Icpout TRI IF Charge Pump 0 5 2 Vopout S Vvcpir 0 5 TRI STATE Current lcPouir MIS IF CP Sink vs CP Source Vepoutir Vvepir 2 Mismatch T 25 C lcPouir V IF CP Current vs CP 05 lt Verse Veje 0 5 Voltage TA 225CC l epoui r TEMP IF CP Current VS V cpoutiF VvepiF 12 Temperature N O N o di O1 O h RR lt o o 5 www national com Units MHz MHz dBm gt T gt uA uA nA V9EcXINT1 LMX2364 Electrical Characteristics Vvce Vvep 3 0V 40 C lt Ta lt 85 C except as specified Continued Value
15. easier to find physically smaller components and components with better dielectric properties 2 Allows a larger loop bandwidth multiplier for phase noise benefit will be realized FastLock or a higher cycle slip reduction factor HE OPE The only reason not to always choose this to 16 mA is to make it such that no FastLock resistor is reguired for FastLock For 3rd and 4th order filters it is not possible to keep the filter perfectly optimized by simply switching in a resistor for FastLock bandwidth of the system will be slightly worse for lower charge pump currents If the charge pump gain is at least 4 mA most of the This allows the maximum possible benefit for FastLock RF CSR Do not choose this any larger than necessary This will eliminate cycle slips better to eliminate cycle slipping Keeping this small allows a larger loop bandwidth multiplier for FastLock 3 6 CAPACITOR DIELECTRIC CONSIDERATIONS The LMX2364 has a high fractional modulus and high charge pump gain for the lowest possible phase noise One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop filter to become larger in value For larger capacitor values it is common to have a trade off between capacitor dielectric quality and physical size Using film capacitors or NP0 CGO capacitors yields the best possible lock times where as using X7R or Z5R capacitors can increase lock time by O 50096 In 37
16. for the selected VCO The LMX2364 consumes 5 0 mA typical of current in integer mode and 7 2 mA typical in fractional mode The LMX2364 is available in a 24 Pin Ultra Thin CSP package and 24 Pin TSSOP Package Features m RF Synthesizer supports both Fractional and Integer Operating Modes Pin Compatible upgrade for LMX2354 2 7N to 5 5V operation Pin and programmable power down Fractional N divider supports fractional denominators ranging from 1 through 128 Supports Integer Mode Operation Programmable charge pump current levels RF 4 level 1 16 mA IF 2 level 100 800 uA FastLock Technology with integrated timeout counters Digital filtered amp analog lock detect output FastLock Glitch Reduction Technology Enhanced Low Noise Fractional Compensation Engine Low voltage programming interface allows direct connection to 1 8V logic Applications Digital Cellular GPRS IS 136 GAIT PDC EDGE CDMA Zero blind slot TDMA systems Cable TV Tuners CATV www national com yuAs Aouenbel 41 N 1069JUI ZHIN 058 YUM JazisayjuAs Aduanbal JH eUon92e14 UNUNETId ZH 9 Z v9EZXIN1T1 A9ZIS9 LMX2364 Functional Block Diagram IF N Divider 8 9 or 16 17 Prescaler IF R Divider RF R Divider RF N Divider FinlF FinlF OSCinlF OSCinRF FinRF 8 9 12 13 Or FinRF 16 17 20 21 Prescaler Se MICROWIRE DATA Interface LE ENRF ENIF Connection Diagrams 24 Pin TSSOP TM Package FLoutRF VccRF Vcp
17. in parallel Note that no DC blocking capacitor is used for this test procedure This is done with the PLL removed from the PCB This requires the use of a clamp down fixture that may not always be generally available If no clamp down fixture is available then this procedure can be done by calibrating up to the point where the DC blocking www national com L Frequency Input Pin Evaluation Board S 22 20050676 capacitor usually is and then adding a O ohm resistor back for the actual measurement Once that the network analyzer is calibrated it is necessary to ensure that the PLL is powered up This can be done by toggling the power down bits RF_PD and IF_PD and ob serving that the current consumption indeed increases when the bit is disabled Sometimes it may be necessary to apply a signal to the OSCiniF pin in order to program the part If this is necessary disconnect the signal once it is established that the part is powered up It is useful to know the input impedance of the PLL for the purposes of debugging RF problems and designing match ing networks Another use of knowing this parameter is make the trace width on the PCB such that the input impedance of this trace matches the real part of the input impedance of the PLL frequency of operation In general it is good practice to keep trace lengths short and make designs that are relatively resistant to variations in the input impedance of the PLL Functi
18. 00 pF is a typical value 3 2 FASTLOCK AND CYCLE SLIP REDUCTION CIRCUITRY OPERATION The LMX2364 has enhanced features for FastLock opera tion When the PLL is switching frequencies the charge pump current and comparison freguencies may be adjusted The purpose of increasing the charge pump current is to increase the loop bandwidth The purpose of reducing the comparison frequency is to combat cycle slipping If these two parameters are not changed by the same ratio then it is necessary to switch in a resistor in order to keep the loop filter optimized Furthermore it may be difficult in this case to keep loop filters of higher than second order well optimized during FastLock in these cases The timeout counter con trols how long the change in charge pump current and or comparison freguency is active One also needs to realize that there is a frequency glitch that is caused when any sort of FastLock or Cycle Slip Reduction is disengaged This frequency glitch is application specific In this case the table below shows all the possible permutations for using the FastLock and cycle slip reduction circuitry Keep Comparison Freguency Decrease Comparison Freguency the Same RF Side Only Increase Charge Pump Classical Fastlock Current Keep Charge Pump Current the Same using fastlock at all This mode allows the loop bandwidth to be increased during FastLock and then switched back to normal after FastLock is disengaged Operatio
19. 02 204 206 PP 208 210 212 COMPARISON FREQUENCY KHz 20050673 Typical Performance Characteristics continued RF N Counter Sensitivity Ta 25 C 20 0 10 0 0 0 10 0 20 0 INPUT POWER dBm 30 0 40 0 FREQUENCY MHz RF N Counter Sensitivity Vcc 3 0V 20 0 10 0 0 0 10 0 20 0 INPUT POWER dBm 30 0 40 0 0 500 1000 1500 FREQUENCY MHz 2000 2500 3000 20050645 3000 20050646 www national com V9EcXINT1 LMX2364 Typical Performance Characteristics continued IF N Counter Sensitivity Ta lt 25C T T lo yop Cd TY IU JU 0 0 ae Vec 2 7V 3 0V and 5 5V 10 0 20 0 30 0 INPUT POWER dBm 40 0 50 0 0 200 400 600 800 1000 FREQUENCY MHz IF N Counter Sensitivity Vcc 3 0V 20 0 10 0 0 0 10 0 20 0 INPUT POWER dBm 30 0 40 0 50 0 0 200 400 600 800 1000 FREQUENCY MHz www national com 10 1200 20050647 1200 20050648 Typical Performance Characteristics continued OSCinRF Counter Sensitivity Ta 25 C INPUT POWER dBm FREQUENCY MHz OSCinRF Counter Sensitivity Vcc 3 0V 20 0 10 0 0 0 1 400C 25 C and 85 C 10 0 20 0 INPUT POWER dBm 30 0 40 0 FREQUENCY MHz 11 120 20050649 120 20050650 www national com V9EcXINT1 LMX2364 Typical Performance Characteristics c
20. 12 11 10 9 8 7 6 5 4 3 2 1 o DATA 20 0 D e et IF IF IF ro o o o er 6 e paka KE na of oo Zz CUE PG ojojol ojojojoj IF_TOC 13 0 ofifo RF TRE RF SE XI ras EN EN E R4 RF N 12 0 RF FN 6 0 ijo 0 RF_ RF_ RF_ as i CSR T 0 OM i 0 CPFIT 0 RF_TOC 18 0 HE 1 aloe sla o JE OSEO MNE Reg www national com 24 Programming Description Continued 2 3 RO REGISTER 25 22 er 20 19 18 17 16 18 14 12 n RHH R KN EN EN ENENENK IF IF IF o o o o er Se r mo GE 2 3 1 IF_R 14 0 R Divider Ratio IF Synthesizer The RO control word is used to configure the 15 Bit R Divider for the IF Synthesizer Divide ratios ranging from 3 to 32 767 are paga Reg IF R 14 0 KG 2 3 2 IF CPP Charge Pump Polarity IF Synthesizer This bit controls the polarity of phase detector for the IF synthesizer It should be set to 1 when the IF VCO has positive tuning gain and O when the tuning gain is negative 2 3 3 IF CP Charge Pump Gain IF Synthesizer This bit controls the charge pump gain for the IF Synthesizer Set this bit to O for low gain mode 100 uA and a 1 for high gain mode 800 uA When FastLock mode is enabled the charge pump gain is controlled by the FastLock circuit 2 3 4 IF RST Counter Reset IF Synthesizer The IF Counter Reset enable bit when activated IF RST 1 allows the reset of both the IF N and R dividers and sets the IF charge pump to a TR
21. 9 32 34 36 38 Legal Divide Ratios in Integer Mode All these values are legal in integer mode www national com 30 Programming Description Continued 2 7 3 RF_PD RF Synthesizer Power Down Activation of the RF Synthesizer power down bit results in the disabling of the respective N divider and de biasing of its respective Fin inputs to a high impedance state The respective R divider functionality also becomes disabled when the power down bit is activated The OSCinRF pin reverts to a high impedance state when both RF and IF power down bits are asserted Power down forces the respective charge pump and phase comparator logic to a TRI STATE condition The MICROWIRE control register remains active and capable of loading and latching in data during all of the power down modes Both synchronous and asynchronous power down modes are available with the LMX2364 in order to adapt to different types of applications The power down mode bit R6 8 is used to select between synchronous and asynchronous power down The MICROWIRE control register remains active and capable of loading and latching in data in either power down mode Synchronous Power down Mode The RF synthesizer can be synchronously powered down by first setting the power down mode bit HIGH R6 8 1 and then asserting its power down bit R4 23 1 The power down function is gated by the charge pump Once the power down bit is loaded the part will go into power down mode upon the co
22. ESD sensitive Handling and assembly of this device should only be done at ESD free workstations Electrical Characteristics v Vve 3 0V 40 C lt T lt 485 C except as specified lcc PARAMETERS locRF Power Supply Current RF Synthesizer Integer Mode Power Supply Current RF Synthesizer Fractional Mode Power Supply Current IF Synthesizer loc IF Io lF PD Power Down Current RF SYNTHESIZER PARAMETERS fFinRE Operating Frequency N Continuous N Divider Continuous N Divider R R Divider Range R Divider Range Integer Mode Note 3 PFinRF RF Input Sensitivity www national com Value a Parameter Gondions ae Typ Venr Vouk Voara VLE LOW Venrev HIGH FE 0 Venir V crk Vpara VLE 0 V Venre HIGH FE 1 Venre VcLk Vpata VLE LOW Venir HIGH Venre Venr LOW a Votk Vpata Vie LOW Presar zeon so o pesa 16 17 20 21____ 1200 2600 _ Prescaler 8 9 12 13 40 anos ao sw RE RE HAH mA mA mA uA MHz MHz Electrical Characteristics Vvcc Vvep 3 0V 40 C lt Ta lt 85 C except as specified Continued Value E bol ee nm Value Parameter amass gt gt T T e RF SYNTHESIZER PARAMETERS lcpoutrrSRCE RF Charge Pump Source RF_CP 0 4 Current VopoutRr Vvepre 2 V opoutRF VvcpRF 2 RF_CP 2 VopoutRr VvcpRF 2 RF_CP CP 3 16 V cpoutRE VvcpRE 2 lopoutrrSINK RF Charge Pump Sink RE CP 0 4 Current V cpoutF Vvcprr 2 VopoutRr
23. I STATE condition Upon powering up the N counter resumes counting in close alignment with the R counter The maximum error is one prescaler cycle 25 www national com 79EcXINT LMX2364 Programming Description Continued 2 4 R1 REGISTER This register is used to configure the N divider for the IF synthesizer A single word write to this register is all that is required to power up and tune the synthesizer to the desired frequency aaa 0 DATA 20 0 Cr c HEE nia OO 2 4 1 IF N 16 0 N Divider Ratio IF Synthesizer The IF N 16 0 word is used to setup up the N Divider Ratio for the IF synthesizer The IF N counter is actually a combination of an IF A counter IF B counter and an IF 8 9 prescaler The relationship between IF N IF B and IF A is shown below IF N 8 xIF B4IF A Although the IF N counter value can created by programming the IF B and IF A values it is easier to simply convert the IF N counter value into binary and program the entire IF N 16 0 word in this manner The fact that the IF N counter has a prescaler is what puts restrictions on IF N values less than 56 Reg IF N 16 0 IF B 13 0 IF A 2 0 Ooo o OA pte 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 o o Divide ratios of less than 24 are notallowed Divide ratios of less than 24 are not allowed Legal divide ratios in this range are 24 27 32 36 40 45 and 48 54 2 4 2 IF PD Power Down IF Synthesizer Activation of the IF
24. RF CPoutRF GND FinRF FinRF GND OSCinRF OSCinlF Ftest LD ENRF www national com Fractional Compensation FLoutIF VcclF VcplF CPoutlF GND FinlF FinlF GND LE DATA CLK ENIF 20050602 IF FLoutlF VcplF CPoutlF Ftest LD VccRF VcclF VcpRF CPoutRF RF Fastlock FLoutRF GND GND GND GND 20050601 Ultra Thin 24 Pin CSP SLE Package L LL LL gt VccRF VcplF VcpRF O CPoutlF CPoutRF GND GND FinlF FinRF FinlF FinRF 6 GND GND LE OSCinRF DATA oscinlF 9 13 CLK 20050622 Pin Descriptions Pin Number TSSOP ao Hs 10 OSCiniF 11 Na Ftest LD i H m l 7 l E 20 21 CPoutlF 24 FLoutlF Description RF PLL power supply voltage input Must be equal to V je May range from 2 7V to 5 5V Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane Power supply for RF charge pump Must be gt Vy Re and VycoiF RF charge pump output Ground for RF PLL digital circuitry RF prescaler input Small signal input from the VCO RF prescaler complementary input For single ended operation a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane Ground for RF PLL analog circuitry RF R counter input Has a V 2 input threshold when configured as an input and can be driven from an external CMOS or TTL
25. acitors of very different sizes for the best filtering 0 1 uF and 100 pF are typical values The charge pump supply pins in particular are vulnerable to power supply noise High Frequency Input Pins FinRF and FinlF The signal path from the VCO to the PLL is sensitive to matching and layout therefore creating unigue challenges fro board lay out It is generally recommended that the VCO output go through a resistive pad and then through a DC blocking capacitor before it gets to these high frequency input pins If the trace length is sufficiently short lt 1 10th of a wave length then the pad may not be necessary however a series resistor of about 39 ohms is still recommended to isolate the PLL from the VCO The DC blocking capacitor should be chosen at least to be 100 pF It may turn out that the freguency in this trace is above the self resonant fre guency of the capacitor but since the input impedance of the PLL tends to be capacitive it actually be a benefit to exceed the self resonant freguency The pad and the DC blocking capacitor should be placed as close to the PLL as possible Complimentary High Frequency Pins FinRF and FinlF These outputs may be used to drive the PLL differentially but it is very common to drive the PLL in a single ended fashion These capacitors should be chosen such that the impedance including the ESR of the capacitor is as close to an AC short as possible at the operating freguency of the PLL 1
26. actional Integer n77 E at Ph improvement Degradation Enabled Illegal State 20 dB 33 www national com 79EcXINT LMX2364 Supplemental Information 3 0 USE OF THE DIGITAL LOCK DETECT FUNCTION The Lock Detect Digital Filler compares the difference be tween the phase of the inputs of the phase detector to a RC generated delay of approximately 15nS To enter the locked state Lock HIGH the phase error must be less than the START 15nS RC delay for 5 consecutive reference cycles Once in lock Lock HIGH the RC delay is changed to approxi mately 30nS To exit the locked state Lock LOW the phase error must become greater than the 30nS RC delay When the PLL is in the power down mode Lock is forced LOW A flow chart of the digital filter is shown below Lock LOW Not Locked Phase Error lt 15 ns No Yes Lock HIGH Locked State www national com Error lt 15 ns Phase Error gt 30 ns 34 No Yes 20050604 Supplemental Information continued 3 1 PCB LAYOUT CONSIDERATIONS Power Supply Pins For these pins it is recommended that these be filtered by taking a series 18 ohm resistor and then placing two capacitors shunt to ground thus creating a lowpass filter Although theoretically it makes sense to make these capacitors as large as possible the ESR Equivalent Series Resistance is greater for larger capacitors It is therefore recommended to provide two cap
27. better in cases where the loop bandwidth is small relative to the comparison freguency Realize that the theoretical lock time multiplier does not account for the FastLock CSR disengagement glitch which is most severe for larger values of K Theoretical Lock Time Multiplier x 1 000 R2 0 41 x 0 707 SK 1 These modes of operation are generally not recommended 3 4 USING FASTLOCK AND CSR TO AVOID CYCLE SLIPPING In the case that the comparison freguency is very large ie 70 x of the loop bandwidth cycle slipping may occur when an instantaneous phase error is presented to the phase www national com 36 detector This can be reduced by increasing the loop band width during freguency aguisition decreasing the compari son freguency during freguency acguisition or some combi nation of the these If increasing the loop bandwidth during freguency acguisition is not sufficient to reduce cycle slip ping the LMX2364 also has a routine to decrease the com parison frequency Supplemental Information continued 3 5 RF PLL FASTLOCK REFERENCE TABLE The table below shows most of the trade offs involved in choosing a steady state charge pump current RF_CP the FastLock charge pump current RF CPF 1 0 and the Cycle Slip Reduction Factor CSR Advantages to Choosing Smaller Advantages to Choosing Larger RF CP 1 Allows capacitors in loop filter to be smaller Phase noise especially within the loop values making it
28. ders separately or by a common input signal path When OSC is set to O the OSCinIF pin drives the IF R divider while the OSCinRF pin drives the RF R divider When the OSC bit is set to 1 the OSCinIF pin drives both the RF R and IF R counters Note that setting the OSC mode to 1 does not allow the use of a crystal This part does not include the inverter for use in construction of a crystal oscillator Reg 2 9 3 PD_M Power Down Mode This bit determines if a power down event for either synthesizer will be handled synchronously or asynchronously with respect to a charge pump event Synchronous powerdown means that the PLL does not power down until the charge pump turns off Asynchronous powerdown means that the PLL powers down regardless of the charge pump state When set to one synchronous mode is enabled When set to 0 asynchronous mode is enabled The setting of this bit applies to both the RF amp IF synthesizers 2 9 4 FE Fractional Compensation Enable For integer mode RF OM 0 mode this bit should always be set to O For fractional mode RF OM 1 this bit should be set to 1 for the best fractional spurs However there may be applications using fractional mode where it would be beneficial to set this bit to O Disabling this bit will drastically degrade the fractional spurs but will also result in a small improvement in phase noise which may be practical for some applications FractionalMode Mode Fr
29. er is used in conjunction with the RF FD and RF FN values to calculate the N divider value The range of values supported is dependant on the selected prescaler When the 8 9 12 13 prescaler is selected RF N value can range from 40 to 4095 When the 16 17 20 21 prescaler is selected the RF N value can range from 80 to 8191 The following tables describe how to program a specific value of RF N for a given prescaler The RF N value is actually created using a prescaler C counter B counter and an A counter If RF P 16 then the RF N 12 0 word is just the binary representation of the desired value If RF P 8 then the case is similiar except that the third LSB is disregarded in all calculations The relationship between RF N RF P RF A RF B and RF C is shown below RF_N RF_PxRF_C 4xRF_B RF_A RF N 12 0 Programming with RF P 16 2 Tu Te sle T7 Tels Pt 5 2 1 0 Values from 0 47 are not allowed Some of these N values are allowed others are illegal divide ratios and not allowed Legal Divide Ratios in Fractional Mode 48 49 52 53 64 66 68 70 72 74 76 78 Legal Divide Ratios in Integer Mode All these values are legal in integer mode 86 o o o o ojo i1 o 1 o a o o 81 0 o 06 6 0 059 1 56 1 6 o o 1 RF N 12 0 a Na 000 _ T o 7 S TS JS LE TS Some of these N values are allowed others are illegal divide ratios and not allowed Legal Divide Ratios in Fractional Mode 24 25 28 2
30. he case that both R counters are to be driven with the same frequency this bit needs to be set to one This PLL does not support the use of a crystal in any mode www national com 79EcXINT LMX2364 Programming Description 2 0 INPUT DATA REGISTER The 24 bit input data register is loaded through the MICROWIRE Interface The input data register is used to program the control registers The data format of the 24 bit data register is shown below The control bits CTL 2 0 decode the internal register address and the data bits DATA 21 0 are used to program various control words for the synthesizer On the rising edge of LE data stored in the input date register is loaded into one of the 8 appropriate latches selected by control bits Data is shifted in MSB first 2 1 REGISTER LOCATION TRUTH TABLE The control bits CTL 2 0 decode the internal register address The table below shows how the control bits are mapped to the target control register This address is invalid 2 2 CONTROL REGISTER CONTENT MAP The control register content map describes how the bits within each control register are allocated to specific control functions The bits that are marked 0 should be programmed as such to insure proper device operation It is important to note that some control words are dual mapped and take one a different control function depending on the operating mode of the device 23 22 21 20 19 18 17 16 15 14 18
31. he power down bit is loaded the part will go into power down mode immediately www national com 26 Programming Description Continued 2 5 R2 REGISTER The R2 Register is used to setup the FastLock circuitry for the IF synthesizer Reg 1 1 9 8 0 DATA 20 0 Co R2 ojojojojojoj roms a 2 5 1 IF TOC 13 0 FastLock Timeout Counter IF Synthesizer The IF TOC 13 0 word controls the operation of the IF FastLock circuitry as well as the function of the FLoutIF output pin When IF TOC is set to a value between 0 and 3 the IF timeout counter is disabled and the FLoutlF pin operates as a general purpose I O pin When IF TOC is set to a value between 4 and 16383 the IF FastLock mode is enabled and FLoutlF is utilized as the IF FastLock output pin The value programmed into IF TOC represents the number of phase comparison cycles that the IF synthesizer will spend in the FastLock state FastLock Period IF TOC 13 0 FastLock Mode o lig FLoutiF Pin Functionality CP Events Co ogabeg mwa Hohimpedance _ SS 2 Manual MA Logo LOW State Force IF Charge Pump o 800 uA HH Festo 27 www national com 79EcXINT LMX2364 Programming Description Continued 2 6 R3 REGISTER The R3 register is used to setup the RF R Divider ratio as well as several other control functions related to the RF synthesizer Reg 11 NA 0 DATA 20 0 RF_ RF ETES E m CORN E 2 6 1 RF FD 6 0 Fractional Denomina
32. itivity limits The temperature freguency and voltage can be varied in order to produce a family of sensitivity curves Since this is an open loop test the charge pump is set to TRI STATE and the unused side of the PLL RF or IF is powered down when not being tested For this part there are actually four freguency input pins although there is only one freguency test pin Ftest LD The conditions specific to each pin are show above Charge Pump Currents SMA Cable Signal Generator Semiconductor SMA Cable Parameter Analyzer Power Supply The above block diagram shows the test procedure for test ing the RF and IF charge pumps These tests include abso lute current level mismatch and leakage In order to mea sure the charge pump currents a signal is applied to the high frequency input pins The reason for this is to guarantee that the phase detector gets enough transitions in order to be able to change states If no signal is applied it is possible that the charge pump current reading will be low due to the fact that the duty cycle is not 100 The OSCinlF Pin is tied to the supply The charge pump currents can be measured by simply programming the phase detector to the necessary polarity For instance in order to measure the RF charge DC Blocking Capacitor Frequency Input Pin CPout Pin OSCinlF Pin 20050675 Evaluation Board pump current a 10 MHz signal is applied to
33. itry IF charge pump output Power supply for IF charge pump Must be gt Vy ge and V asip IF power supply voltage input Must be equal to Vvecrr Input may range from 2 7V to 5 5V Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane IF FastLock Output Also functions as Programmable TRI STATE CMOS output RF FastLock Output Also functions as Programmable TRI STATE CMOS output 3 www national com 79EcXINT LMX2364 Absolute Maximum Ratings Parameter Power Supply Voltage Voltage on any pin with GND 0V Storage Temperature Range Lead Temperature Solder 4 sec Notes 1 2 aa Te Ves m3 we 33 Ves a a io JU uso 260 Recommended Operating Conditions Parameter Power Supply Voltage VVcpRF V venir Operating Temperature Value Typ m ss METE NI NR TN Symbol VveciF VVccRF 5 5 Co J Ta C Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is intended to be functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Note 2 This Device is a high performance RF integrated circuit with an ESD rating lt 2 kV and is
34. logic gate Oscillator input which can be configured to drive both the IF and RF R counter inputs or only the IF R counter depending on the state of the OSC programming bit Programmable multiplexed output pin Can function as general purpose CMOS TRI STATE I O analog lock detect output digital filtered lock detect output or N 4 R divider output RF PLL Enable Powers down RF N and R counters prescaler and TRI STATE charge pump output when LOW regardless of the state RF PD bit Bringing ENRF high powers up RF PLL depending on the state of RF PD control bit IF PLL Enable Powers down IF N and R counters prescaler and will TRI STATE the charge pump output when LOW regardless of the state IF PD bit Bringing ENIF high powers up IF PLL depending on the state of IF PD control bit High impedance CMOS Clock input Data for the control registers is clocked into the 24 bit shift register on the rising edge Binary serial data input Data entered MSB first The last three bits are the control bits High impedance CMOS input Latch enable High impedance CMOS input Data stored in the shift register is loaded into one of the 7 internal latches when LE goes HIGH Ground for IF analog circuitry IF prescaler complementary input For single ended operation a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground IF prescaler input Small signal input from the VCO Ground for IF digital circu
35. mpletion of a charge pump pulse event Asynchronous Power down Mode The RF synthesizer can be asynchronously powered down by first setting the power down mode bit LOW R6 8 0 and then asserting its power down bit R4 23 1 The power down function is NOT gated by the charge pump Once the power down bit is loaded the part will go into power down mode immediately 31 www national com 79EcXINT LMX2364 Programming Description Continued 2 8 R5 REGISTER The R5 Register is used to setup and control the FastLock circuitry for the RF synthesizer T o TS TTS Telo RE RE RF RS KI CSR 1 0 OMf1 0 CPF 1 0 RF TOC 13 0 ijo 1 2 8 1 RF TOC 13 0 FastLock Timeout Counter RF Synthesizer The RF TOC 13 0 word controls the operation of the RF FastLock circuitry as well as the function of the FLoutRF output pin When RF TOC is set to a value between 0 and 3 the RF timeout counter is disabled and the FLoutRF pin operates as a general purpose I O pin When RF TOC is set to a value between 4 and 16383 the RF FastLock mode is enabled and FLoutRF is utilized as the RF FastLock output pin The value programmed into RF TOC represents the number of phase comparison cycles that the RF synthesizer will spend in the FastLock state RF 0 FastLock Mode FAP Events FLoutRF Pin Functionality based EE ET SE C oswa Na io LOW Ste Ta a 2 8 2 RF CPF 1 0 FastLock Charge Pump Gain RF Synthesizer
36. n Without Fastlock This mode is essentially not CSR Fastlock Combination This is the recommended way to use CSR If the charge pump gain is used to balance the change in loop gain due to the lower comparision freguency no fastlock resistor is necessary CSR Only In general this mode is not recommended but it may be practical in some rare situations Decrease Charge Pump Illegal Mode Current This mode degrades performance and should never be used Note If the charge pump current and cycle slip reduction circuitry are engaged in the same proportion then it is not necessary to switch in a FastLock resistor and the loop filter will be optimized for both normal mode and FastLocking 35 mode For third and fourth order filters which have problems with cycle slipping this may prove to be the optimal choice of settings www national com 79EcXINT LMX2364 Supplemental Information continued 3 3 DETERMINING THE THEORETICAL LOCK TIME IMPROVEMENT AND FASTLOCK RESISTOR R2 The loop bandwidth multiplier K is necessary in order to determine the theoretical impact of FastLock CSR on the loop bandwidth and also which resistor should be switched in parallel with the loop filter resistor R2 K K_Kphi x K_Fcomp where K is the loop gain multiplier K_Kphi and K_Fcomp are the ratio of the FastLock currents and com parison frequencies to their steady state conditions Note that this should always be greater than or equal to one
37. onal Description 1 0 GENERAL The basic phase lock loop PLL configuration consists of a high stability crystal reference oscillator a frequency synthe sizer such as the National Semiconductor LMX2364 a volt age controlled oscillator VCO and a passive loop filter The frequency synthesizer includes a phase detector charge pump and programmable frequency dividers These divid ers are the reference R and feedback N frequency divid ers The VCO frequency is established by dividing the crystal reference signal down via the R counter to obtain a fre quency in order to establish the comparison frequency This comparison frequency fcomp is input to the phase detector which compares this signal to another signal fy the feed back signal fy is the result of dividing the VCO frequency down by way of the N counter and fractional circuitry The phase frequency detector s charge pump outputs a current into the loop filter which is then converted into the VCO s control voltage The phase frequency comparator s function is to adjust the voltage presented to the VCO until the feedback signal s frequency and phase match that of the reference signal When this phase locked condition exists the VCO s frequency will be N F times that of the compari son frequency where N is the integer component of the divide ratio and F is the fractional component Fractional synthesis allows the phase detector frequency to be in creased
38. ontinued INPUT POWER dBm INPUT POWER dBm www national com OSCinlF Counter Sensitivity Ta 25 C 20 0 10 0 0 0 10 0 20 0 30 0 40 0 50 0 FREQUENCY MHz 20050651 OSCinIF Counter Sensitivity Vcc 3 0V 20 0 10 0 O O l o O 20 0 30 0 FREQUENCY MHz 20050652 12 Input Impedance FinRF Pin CSP Package TSSOP Package Marker 1 500 MHz Marker 1 500 MHz Marker 2 1GHz Marker 2 1GHz Marker 3 2 GHz Marker 3 2 GHz Marker 4 3 GHz Marker 4 3 GHz 20050653 20050656 FinRF Input Impedance Ohms Frequency MHz CSP Package TSSOP Package ai T V m ee HR 13 www national com 79EcXINT LMX2364 Input Impedance FinlF Pin CSP Package TSSOP Package Marker 1 110 MHz Marker 1 50 MHz Marker 2 500 MHz Marker 2 500 MHz Marker 3 900 MHz Marker 3 900 MHz Marker 4 1 5 GHz Marker 4 1 2 GHz 20050657 20050654 TSSOP Package imaginary www national com 14 Input Impedance OSCinlF Pin CSP Package TSSOP Package Marker 1 10 MHz Marker 2 50 MHz Marker 3 100 MHz Marker 4 200 MHz 20050655 Marker 1 10 MHz Marker 2 50 MHz Marker 3 100 MHz Marker 4 200 MHz 20050658 OSCinlF Input Impedance ohms Frequency CSP Package TSSOP Package MHz Powered Up Powered Up Powered Down Real imaginary Real Imaginary Rea Imaginary heal Imaginary Mas o os 92 2o 112 0 84
39. ter Power Supply bo a o p LL Matching Network Frequency Input Pin DC Blocking Capacitor Ftest LD Pin Evaluation Board 20050674 Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz or more of its expected value It is typically measured over frequency voltage and temperature In order to test sensitivity the MUX 3 0 word is programmed to the appropriate value The counter value isthen programmed to a fixed value and a freguency counter is set to monitor the freguency of this pin The expected freguency at the Ftest LD pin should be the signal generator freguency divided by twice the correspond ing counter value The factor of two comes in because the LMX2364 has a flip flop which divides this freguency by two to make the duty cycle 50 in order to make it easier to read with the freguency counter The freguency counter input impedance should be set to high impedance In order to perform the measurement the temperature fre guency and voltage is set to a fixed value and the power www national com 20 level of the signal is varied Note that the power level at the part is assumed to be 4 dB less than the signal generator power level This accounts for 1 dB for cable losses and 3 dB for the pad The power level range where the freguency is correct at the Ftest LD pin to within 1 Hz accuracy is re corded for the sens
40. the FinRF pin The source current can be measured by setting the RF PLL phase detector to a positive polarity and the sink current can be measured by setting the phase detector to a negative polarity The IF PLL currents can be measured in a similar way Note that the magnitude of the RF and IF PLL charge pump currents are also controlled by the RF CP and IF CP bits Once the charge pump currents are known the mis match can be calculated as well In order to measure leak age currents the charge pump current is set to a TRI STATE mode by enabling the counter reset bits This is RF RST for the RF PLL and IF RST for the IF PLL 21 www national com V9EcXINT1 LMX2364 Input Impedance Network Analyzer Power Supply The above block diagram shows the test procedure measur ing the input impedance for the LMX2364 This applies to the FinRF FinlF OSCinRF and OSCinIF pins The input imped ance of the CSP and the TSSOP package should always be assumed to be different until proven otherwise The basic test procedure is to calibrate the network analyzer ensure that the part is powered up and then measure the input impedance The network analyzer can be calibrated by using either calibration standards or by soldering resistors directly to the evaluation board An open can be implemented by putting no resistor a short can be implemented by using a 0 ohm resistor and a short can be implemented by using two 100 ohm resistors
41. tor RF Synthesizer In Fractional Mode RF FD 6 0 is used to specify the fractional denominator of the fractional part of the N counter value Note that in this mode values below 32 are not supported If a fractional denominator between 2 and 32 is desired the same N counter value can be achieved by multiplying the fractional numerator and denominator by some constant factor For instance 1 16 can be expressed as 5 80 In integer mode the value represented by this bit multiplies both the RF N and RF R counter values If both of these counter sizes are sufficiently large it is recommended to set this bit to one If the counter sizes are too small this bit can be used to extend the counter range Integer Mode Fractional Mode O or po m pos 7 a H Not Supported Use Integer Mode Instead _ Not Supported Use a higher value RF FD Value RF FD 6 0 Fractional Mode Integer Mode See R divider programming section 2 6 2 and N divider programming Section 2 7 2 for more detailed programming information 2 6 2 RF R 8 0 R Divider Ratio RF Synthesizer RF R 8 0 is used to specify an integer value from 1 to 511 that is used in calculating the R divider ratio for the RF synthesizer In the case that the PLL is operating in fractional mode the R counter value is simply the value represented by RF R However in integer mode the R counter value is calculated by multiplying RF R by the fractional denominator value
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43. while maintaining the same frequency step size for channel selection The division value N is thereby reduced giving a lower phase noise referred to the phase detector input and the comparison frequency is increased allowing faster switching times 23 1 1 OPERATING MODES The LMX2364 RF PLL is a capable of operating as both a Fractional N synthesizer and an Integer N synthesizer Op erating in Fractional mode is likely to yield the best phase noise but Integer mode often yields the lowest spur levels The operating mode is determined by the RF OM 1 0 word It is possible to cause this PLL to behave as an integer PLL in fractional mode by setting the fractional numerator RF_FN to zero and disabling the fractional compensation that is controlled by the FE bit However by actually setting the part to Integer mode allows the range of the counters to be extended 1 2 POWER DOWN The LMX2364 can be powered down via the two software bits and the two enable pins The RF PLL is only powered up when the ENRF pin is high and the RF PD bit R4 23 is low In a similar manner the IF PLL is powered up only when the ENIF pin is high and the IF PD bit R1 23 is low 1 3 OSCILLATOR The OSCinRF and OSCinlFpins are used to drive the R dividers for the RF and IF PLLs In the case that the OSC Bit R6 7 is set to 0 the RF R counter is driven by the OSCinRF pin and the IF R counter is driven independently of this by the OSCinIF pin In t
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