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National LMX2330L/LMX2331L/LMX2332L handbook

1. 15 BIT IF R COUNTER fiy RF RF 18 BIT RF Prescaler N zlii 22 BIT DATA REGISTER TRI STATE is a registered trademark of National Semiconductor Corporation 15 BIT RF R mal Features m Ultra low current consumption m 2 7V to 5 5V operation m Selectable synchronous or asynchronous powerdown mode loc 1 pA typical at 3V m Dual modulus prescaler LMX2330L RF 32 33 or 64 65 LMX2331L 32L RF 64 65 or 128 129 LMX2330L 31L 32L IF 8 9 or 16 17 m Selectable charge pump TRI STATE9 mode m Selectable charge pump current levels m Selectable Fastlock mode m Upgrade and compatible to LMX233XA family Applications m Portable Wireless Communications PCS PCN cordless m Cordless and cellular telephone systems m Wireless Local Area Networks WLANs m Cable TV tuners CATV m Other wireless communication systems CHARGE PUMP Da Tr four Lock Detect Fastlock MUX PHASE CHARGE x COMP PUMP D RE FASTLOCK DS012806 1 Fastlock MICROWIRE and PLLatinum are trademarks of National Semiconductor Corporation 1999 National Semiconductor Corporation DS012806 www national com suomneoiunululo euosJad Ju 104 Jeziseuju g Aouenbej4 ununeTid TZEE SXINT TLEETXINT TOEESXINA Connection Diagrams Chip Scale Package SLB Top Vi op ew Thin Shrink Small Outline Package TM o uw Top View gt gt gt ob 23 22 N
2. Charge Pump Current vs D Voltage HIGH 0 Current 0 05 1 15 2 25 3 35 4 45 5 55 D Voltage V DS012806 23 Charge Pump Current Variation See Note 6 under Charge Pump Current Specification Definitions Variation 25 20 15 10 0 0 0 5 05 0 5 1 125 15 175 2 225 25 Voltage Offset V DS012806 25 Charge Pump Current vs D Voltage lop LOW Mismatch 0 Current mA 20 15 0 5 15 2 25 3 35 4 45 5 55 D Voltage V DS012806 24 Sink vs Source Mismatch See Note 7 under Charge Pump Current Specification Definitions Vp 3 0V Vp 5 0V 0 5 15 2 25 3 35 4 45 5 D Voltage V DS012806 26 www national com Typical Performance Characteristics continued RF Input Impedance IF Input Impedance 2 7V to 5 5V fin 50 MHz to 3 GHz Vec 2 7V to 5 5V f n 50 MHz to 1000 MHz 1 Marker 1 1 GHz 125 Imaginary 141 Marker 1 100 MHz Real 443 Imaginary 249 Marker 2 2 GHz Real 39 Imaginary 52 Marker 2 200 MHz Real 248 Imaginary 214 Marker 5 5 GHz Real 21 Imaginary 3 Marker 3 300 MHz Real 297 Imaginary 208 Marker 4 500 MHz Real 237 Imaginary 185 Marker 4 500 MHz Real 222 Imaginary
3. LMX233xL ck ok R 0 011 18 Voc Vp IN 1000 p Crystal Osc 199p ax Input 0 01 2d 100p 0 014 vco I RF out C1 R1 10p 05012806 12 Operational Notes VCO is assumed AC coupled Rm increases impedance so that VCO output power is provided to the load rather than the PLL Typical values are 100 to 2000 depending on the VCO power level fiy RF impedance ranges from 400 to 1000 fiy IF impedances are higher Adding RC filters to the Vcc lines is recommended to reduce loop to loop noise coupling 100 ko OSC DS012806 13 Application Hints Proper use of grounds and bypass capacitors is essential to achieve a high level of performance Crosstalk between pins can be reduced by careful board layout This is an electrostatic sensitive device It should be handled only at static free work stations 17 www national com Application Information A block diagram of the basic phase locked loop is shown in Figure 1 PHASE DETECTOR REFERENCE fp CRYSTAL DIVIDER REFERENCE reference frequency Frequency Synthesizer L CHARGE PUMP 05012806 14 FIGURE 1 Basic Charge Pump Phase Locked Loop LOOP GAIN EQUATIONS A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 2 The open loop gain is the product of the phase comparator gain Ko the VCO gain Kyco s and the loop filter gain Z s divided by the gain of
4. AR 2 e Top View 2 3 4 5 6 7 8 9 pers DS012806 2 Order Number LMX2330LTM LMX2331LTM or LMX2332LTM NS Package Number MTC20 B Te 7 10 19 TN v Jory Ja N 13 a o Clock DS012806 39 Order Number LMX2330LSLB LMX2331LSLB or LMX2332LSLB NS Package Number SLB24A Pin Descriptions Pin No Pin No LMX233XLSLB LMX233XLTM Pin UO Description 24 pinCSP 20 pin TSSOP Name Package Package 24 1 Veci Power supply voltage input for RF analog and RF digital circuits Input may range from 2 7V to 5 5V Voc1 must equal 2 Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane Power Supply for RF charge pump Must be 2 Voc Internal charge pump output For connection to a loop filter for driving the input of an external VCO Ground for RF digital circuitry RF prescaler input Small signal input from the VCO 70 Co 2 0 gt i 3 Q 2 12 DIS a 6 6 fin RF RF prescaler complementary input A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane Capacitor is optional with some loss of sensitivity 7 7 GND Ground for RF analog circuitry Oscillator input The input has a V 2 input threshold and can be driven from an external CMOS or TTL logic gate 10 9
5. LMX2331LSLB or LMX2332LSLB For Tape and Reel 2500 Units per Reel Order Number LMX2330LSLBX LMX2331LSLBX or LMX2332LSLBX NS Package Number SLB24A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd Americas Fax 49 0 1 80 530 85 86 Response Group Tel 81 3 5639 7560 Tel 1 800 272 9959 Email europe support nsc com Tel 65 2544466 Fax 81 3 5639 7507 Fax 1 800 737 7018 Deutsch Tel 49 0 1 80 530 85 85 Fax 65 2504466 Email support nsc com English Tel 49 0 1 80 532 78 32 Email sea support nsc com Frangais Tel 49 0 1 80 532 93
6. PROGRAMMABLE DIVIDER N COUNTER The N counter consists of the 7 bit swallow counter A counter and the 11 bit programmable counter B counter If the Control Bits are 10 or 11 10 for IF counter and 11 for RF counter data is transferred from the 22 bit shift register into a 4 bit or 7 bit latch which sets the Swallow A Counter and an 11 bit latch which sets the 11 bit programmable B Counter MSB first Serial data format is shown below For the IF N counter bits 5 6 and 7 are don t care bits The RF N counter does not have don t care bits LSB MSB t bivide ratio of the reference divider n rro Control bits DS012806 8 7 BIT SWALLOW COUNTER DIVIDE RATIO A COUNTER Divide N Ratio 6 EE E a 1 Notes Divide ratio O to 127 X DON T CARE condition BA 11 BIT PROGRAMMABLE COUNTER DIVIDE RATIO B COUNTER Note Divide ratio 3 to 2047 BA Divide ratios less than 3 are prohibited PULSE SWALLOW FUNCTION fvco P x B A x fosc R fuco Output frequency of external voltage controlled oscillator VCO B Preset divide ratio of binary 11 bit programmable counter 3 to 2047 A Preset divide ratio of binary 7 bit swallow counter 0 lt lt 127 RF 0 lt lt 15 IF A lt B fosc Output frequency of the external reference frequency oscillator R Preset divide ratio of binary 15 bit programmable reference counter 3 to 32767 P Preset modulus of dual modulus
7. 198 Marker 5 1 GHz Real 128 Imaginary 144 DS012806 28 Marker 6 2 GHz Real 38 Imaginary 64 Marker 7 3 GHz Real 24 Imaginary 18 Marker 8 500 MHz Real 207 Imaginary 184 DS012806 27 LMX2330L RF Sensitivity vs Frequency LMX2331L RF Sensitivity vs Frequency 5 5 10 10 15 g 715 20 Vee 5 5V EZ 25 SS gt gt 25 30 e o 30 35 Vec 2 7V 40 35 45 40 1000 1400 1800 2200 2600 5000 500 900 1300 1700 2100 2500 1200 1600 2000 2400 2800 700 1100 1500 1900 2300 Frequency MHz Frequency MHz DS012806 29 DS012806 30 www national com 10 Typical Performance Characteristics continued LMX2332L RF Sensitivity vs Frequency IF Input Sensitivity vs Frequency 5 Sensitivity dBm Sensitivity dBm 40 50 150 250 350 100 300 500 700 900 1100 1300 1500 100 200 300 400 500 600 Frequency MHz Frequency MHz DS012806 31 DS012806 32 Oscillator Input Sensitivity vs Frequency 10 2 000 1 125 0 633 0 356 0 200 0 113 0 063 0 036 0 020 0 011 0 006 0 5 10 15 20 25 30 35 40 45 50 Sensitivity dBm Sensitivity Vpp Frequency MHz DS012806 33 11 www national com Functional Description The simplif
8. Current Sink vs Source Mismatch I2 5 112 I5 100 Note 8 lp vs TA Charge Pump Output Current magnitude variation vs Temperature 12 amp temp 2 25 12 25 100 and 15 temp I5 25 C I5 25 C 100 7 www national com RF Sensitivity Test Block Diagram Parallel PC Port HP5385A IN Frequency Counter Note 1 N 10 000 50 LMX233XL Evaluation Board 2 7V 5 0V 64 Note 2 Sensitivity limit is reached when the error of the divided RF output FoLD is 2 1 Hz Typical Performance Characteristics 13 dB ATTN RF 500 SMHU 835 8011 52 Signal Generator 10 MHz EXT REF OUT 05012806 38 lec VS Vec loc VS Vee LMX2330L LMX2331L 7 6 5 6 5 6 6 T 85 C xr 5 5 c lt lt E i E 9 9 5 259C 4 T 40 C 3 5 3 2 5 3 3 5 4 4 5 5 5 5 2 5 3 5 4 4 5 5 5 5 Vec v Vec v DS012806 19 DS012806 20 lcc VS Vec lbo TRI STATE LMX2332L vs D Voltage 5 5 1500 5 1250 4 5 T 85 C 1000 90 4 X 750 lt S amp 3 5 z 500 T s T 70 C gt 3 250 T 2500 250 2 5 0 409C 2 250 1 5 500 2 5 3 3 5 4 4 5 5 5 5 0 2 3 4 5 6 Vcc V 0 VOLTAGE V DS012806 21 www national com DS012806 22 Typical Performance Characteristics continued
9. GND _ Ground for IF digital MICROWIRE F LD and oscillator circuits 11 10 F LD Multiplexed output of the RF IF programmable or reference dividers RF IF lock detect signals and Fastlock mode CMOS output see Programmable Modes 12 11 Clock High impedance CMOS Clock input Data for the various counters is clocked in on the rising edge into the 22 bit shift register 14 12 Binary serial data input Data entered MSB first The last two bits are the control bits High impedance CMOS input 40 3 www national com 2 Pin Descriptions continued Pin No Pin No LMX233XLSLB LMX233XLTM VO Description 24 pinCSP 20 pin TSSOP Package Package 15 13 LE Load enable high impedance CMOS input When LE goes HIGH data stored in the shift registers is loaded into one of the 4 appropriate latches control bit dependent 16 4 Ground for IF analog circuitry 17 15 fin IF IF prescaler complementary input A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane Capacitor is optional with some loss of sensitivity 18 fin IF IF prescaler input Small signal input from the VCO 19 GND Ground for IF digital MICROWIRE and oscillator circuits 20 18 D IF IF charge pump output For connection to a loop filter for driving the input of an external VCO 22 39 Power Supply for IF charge pump Must be gt Voc 23
10. prescaler for IF P 8 or 16 for RF LMX2330L P 32 or 64 LMX2331L 32L P 64 or 128 13 www national com Functional Description continued PROGRAMMABLE MODES Several modes of operation can be programmed with bits R16 R20 including the phase detector polarity charge pump TRI STATE and the output of the F LD pin The prescaler and powerdown modes are selected with bits N19 and N20 The pro grammable modes are shown in Table 1 Truth table for the programmable modes F LD output are shown in Table 2 and Table 3 TABLE 1 Programmable Modes pcr c2 Ri6 Ri7 ms mo IF Phase IF lopo IF D IF LD Tm rm um RF Phase RF lopo RF D RF LD 7 2 P rer e we wo 1 0 iF Prescaler TABLE 2 Mode Select Truth Table Phase Detector D TRI STATE lcPo 2330L RF 2331L 32L RF Pwdn m moeone Tessie Homa Gpoaion tow Note 9 Refer to POWERDOWN OPERATION in Functional Description Note 10 The LOW current state 1 4 x HIGH current Note 11 PHASE DETECTOR POLARITY Depending upon VCO characteristics R16 bit should be set accordingly see figure right When VCO characteristics are positive like 1 R16 should be set HIGH When VCO characteristics are negative like 2 R16 should be set LOW VCO Characteristics 1 OUTPUT FREQUENCY 2 VCO INPUT VOL
11. the feedback counter modulus N The passive loop filter configuration used is displayed in Figure 3 while the complex impedance of the filter is given in Equation 1 05012806 15 vco H I DS012806 16 FIGURE 3 Passive Loop Filter H s G s KoZ s Kyco Ns _ s C2 R2 1 Z s B s2 C2eR2 sC1 sC2 1 The time constants which determine the pole and zero fre quencies of the filter transfer function can be defined as Open loop gain C1eC2 T1 R2e T ES 2 and 2 R2 C2 3 The 3rd order PLL Open Loop Gain can be calculated in terms of frequency o the filter time constants T1 and T2 and the design constants Ky Kyco and www national com 18 5 jea 000 077 o C1eN 1 1 4 From Equations 2 3 we can see that the phase term will be dependent on the single pole and zero such that the phase margin is determined in Equation 5 tan 7 o T2 tan o 1 180 5 A plot of the magnitude and phase of G s H s for a stable loop is shown in Figure 4 with a solid trace The parameter p shows the amount of phase margin that exists at the point the gain drops below zero the cutoff frequency wp of the loop In a critically damped system the amount of phase margin would be approximately 45 degrees If we were now to redefine the cut off frequency wp as double the frequency which gave us our original loop band wid
12. 0 C lt lt 85 C except as specified Symbol Units Ibo SOURCE Charge Pump Output Vp 2 lcpg HIGH Note 5 mA Ibo SINK Current E Vp 2 lcpg HIGH Note 5 j mA Ibo SOURCE Vbo Vp 2 LOW Note 5 mA Ibo SINK Vbo Vp 2 lcro LOW Note 5 mA Ibo TRI Charge Pump 0 5V lt Vp lt Vp 0 5V s ak TRI STATE Current 40 C lt Ta lt 85 C IDbo SINK vs CP Sink vs Vp 2 lbo SOURCE Source Mismatch Note 7 TA 25 C VS Vpo CP Current vs Voltage 0 5 lt nis lt Vp 0 5V 96 lbo VS op vs Vy2 96 Temperature Note 8 bon lt Ta lt 85 Note 5 See PROGRAMMABLE MODES for description www national com 6 Charge Pump Current Specification Definitions VOLTAGE OFFSET AV Current mA 0 AV Vp 2 Vp AV Vp Do Voltage DS012806 37 11 CP sink current at Vpo Vp AV 12 CP sink current at Vpo Vp 2 1 CP sink current at AV 14 CP source current at Vp Vp AV 15 CP source current at Vpo Vp 2 l6 CP source current at Vpo AV AV Voltage offset from positive and negative rails Dependent on VCO tuning range relative to Voc and ground Typical values are between 0 5V 1 0V Note 6 IDo vs Vpy Charge Pump Output Current magnitude variation vs Voltage qi ISA 1 100 14 141 I6 1141 I6 100 Note 7 lpo sink VS Charge Pump Output
13. 20 2 Power supply voltage input for IF analog IF digital MICROWIRE FLD and oscillator circuits Input may range from 2 7V to 5 5V Vcc2 must equal Vcc1 Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane 1 9 13 21 X NC No connect 3 www national com Block Diagram Fout _20 Vand Lock Detect ce RF Fastlock IF Lock Multiplexer Lock Detect Detect 19 IF 15 Bit N Latch 1 Bit P2 1 Bit IF Latch PWDN 14 GND RF 1 Bit RF i Bit p1 7 RF 18 814 N Latch 5 Bit Mode Latch FI 15 Bit R1 Latch Programmable 15 Bit i R1 Reference Counter GND RF IF Phase Phase 18 Detector Detector Dy IF 17 GND fo RF 5 Programmable Programmable IF Prescaler 16 fu IF IN gt RF Prescaler 18 Bit RF 15 Bit IF 8 9 or IN N Counter N Counter 16 17 Latch Decode uc LE 8 0S6 gt GND 3 Programmable 15 Bit R2 Reference Counter 20 Bit Shift Register 12 ets 5 Bit Mode Latch 15 Bit R2 Latch p 11 Clock DS012806 3 Note The RF prescaler for the LMX2331L 32L is either 64 65 or 128 129 while the prescaler for the LMX2330L is 32 33 or 64 65 Note Vcc1 supplies power to the RF prescaler N counter R counter and phase detector 2 supplies power to the IF prescaler N counter phase detector R counter along with the OSCin buffer MICROWIRE and F LD Vcc1 and 2 are clamped t
14. 58 www national com Italiano Tel 49 0 1 80 534 16 80 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications suomneoiunululo euosJad 104 Jeziseuju g Aouenbej4 ununeTid TZEESXINT TLEETXINT TOEESXINTA
15. Fo fm RF Operating LMX2330L ER EN LMX2332L Power Supply Current uA Frequency fin IF Operating a 0 MHz f DEI NNNM Phase Detector MHz Frequency PI RF RF Input Sensiiviy 9 Vecs o Pf IF IF Input Sensitivity EPIS to55V 0 o dBm Vu High Level input Voltage neg Vi Low Level nputVotage Weng vef Note 4 Note 4 in OsWaormpuCuem Weve 0 M lu Oscillator Input Current v QV Vec 5 5V High Level Output Voltage lon 500 pA gt V for F LD pin number 10 VoL Low Level Output Voltage for ee lE V FLD pin number 10 tss to Clock Set Up Time See Data mpu Timing 50 tow Data to Glock Hold Time Data Timing 10 town Clock Pulse Width Hion Data Input Timing 50 tom Clock Pulse WidthLow rs 5 www national com Electrical Characteristics continued Voc 3 0V Vp 3 0V 40 C lt TA lt 85 except as specified vau Parameter Conditions Units Parameter Tre T Clock to Load Enable Set Up Time See Data Input Timing 50 ns Load Enable Pulse Width See Data Input Timing 50 ns Note 3 Clock Data and LE GND or Vec Note 4 Clock Data and LE does not include fiy RF fiy IF and OSCyy Charge Pump Characteristics Voc 3 0V Vp 3 0V 4
16. O LMX2330L9 June 1999 National Semiconductor LMX2330L LMX2331L LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal Communications LMX2330L 2 5 GHz 510 MHz LMX2331L 2 0 GHz 510 MHz LMX2332L 1 2 GHz 510 MHz General Description The LMX233XL family of monolithic integrated dual fre quency synthesizers including prescalers is to be used asa local oscillator for RF and first IF of a dual conversion trans ceiver It is fabricated using National s 0 5 ABiC V silicon BiCMOS process The LMX233XL contains dual modulus prescalers A 64 65 or a 128 129 prescaler 32 33 or 64 65 in the 2 5 GHz LMX2330L can be selected for the RF synthesizer and a 8 9 or a 16 17 prescaler can be selected for the IF synthesizer LMX233XL which employs a digital phase locked loop tech nique combined with a high quality reference oscillator pro vides the tuning voltages for voltage controlled oscillators to generate very stable low noise signals for RF and IF local oscillators Serial data is transferred into the LMX233XL via a three wire interface Data Enable Clock Supply voltage can range from 2 7V to 5 5V The LMX233XL family features very low current consumption LMX2330L 5 0 mA at 3V LMX2331L 4 0 mA at LMX2332L 3 0 mA at 3V The LMX233XL are available in a TSSOP 20 pin and CSP 24 pin surface mount plastic package Functional Block Diagram IF 15 BIT IF Prescaler N COUNTER fiy IF
17. TAGE DS012806 9 www national com 14 Functional Description continued TABLE 3 The F LD Pin 10 Output Truth Table RF R 19 IF R 19 RF R 20 IF R 20 F Output State RF LD IF LD RF F IF 0 o J 9 9 12 Fastlock Note 14 IF Counter Reset Note 15 RF Counter Reset Note 15 IF and RF Counter Reset Note 15 Note 12 When the FLD output is disabled it is actively pulled to a low logic state X don t care condition Note 13 Lock detect output provided to indicate when the VCO frequency is in lock When the loop is locked and a lock detect mode is selected the pins output is HIGH with narrow pulses LOW In the RF IF lock detect mode a locked condition is indicated when RF and IF are both locked Note 14 The Fastlock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation Activation of Fastlock occurs whenever the RF loop s Icpo magnitude bit 17 is selected HIGH while the 19 and 20 mode bits are set for Fastlock Note 15 The IF Counter Reset mode resets IF PLL s R and N counters and brings IF charge pump output to a TRI STATE condition The RF Counter Reset mode resets RF PLL s R and N counters and brings RF charge pump output to a TRI STATE condition The IF and RF Counter Reset mode resets all counters and brings both charge pump outputs to a TRI STATE condition Upon removal of the Reset bits then N counter resumes
18. counting in close alignment with the R counter The maximum error is one prescaler cycle POWERDOWN OPERATION Powerdown Mode Select Table Synchronous and asynchronous powerdown modes are PowerdownStatus both available by MICROWIRE selection Synchronously 18 N20 Stalts In the synchronous powerdown mode the powerdown func tion is gated by the charge pump to prevent unwanted fre quency jumps Once the powerdown program bit N20 is loaded the part will go into powerdown mode when the charge pump reaches a TRI STATE condition In the asynchronous powerdown mode the device powers down immediately after the LE pin latches in a HI condition on the powerdown bit N20 Activation of either the IF or RF PLL powerdown conditions in either synchronous or asynchronous modes forces the re spective loop s R and N dividers to their load state condition and debiasing of its respective f n input to a high impedance state The oscillator circuitry function does not become dis abled until both IF and RF powerdown bits are activated The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown modes The device returns to an actively powered up condition in ei ther synchronous or asynchronous modes immediately upon LE latching LOW data into bit N20 powerdown occurs if the respective loop s R18 bit Do 0 0 PLL Active TRI STATE is LOW when its N20 bit Pwdn beco
19. ied block diagram below shows the 22 bit data register two 15 bit R Counters and the 15 and 18 bit N Counters in termediate latches are not shown The data stream is clocked on the rising edge of Clock into the DATA register MSB first The data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE The last two bits are the Con trol Bits The DATA is transferred into the counters as follows Control Bits DATA Location fiy IF IF Prescaler 05 in PHASE COMP RF Prescaler N 22 BIT DATA REGISTER FASTLOCK PROGRAMMABLE REFERENCE DIVIDERS IF AND RF R COUNTERS If the Control Bits are 00 or 01 00 for IF and 01 for RF data is transferred from the 22 bit shift register into a latch which sets the 15 bit R Counter Serial data format is shown below CLOCK DATA LE DS012806 6 LSB MSB C1 C2 R R RI R R R RIR R RJ R 27 3 4 5 7 12113114115 16117 19 20 divide ratio of the reference divider R gt Program Modes gt Control bits DS012806 7 15 BIT PROGRAMMABLE REFERENCE DIVIDER RATIO R COUNTER Divide RR Ratio 7 6 3 1 o o Notes Divide ratios less than 3 are prohibited Divide ratio 3 to 32767 R1 to R15 These bits select the divide ratio of the programmable reference divider Data is shifted in MSB first www national com 12 Functional Description continued
20. mes HI 1 0 PLL Active Asynchronous powerdown occurs if the loop s R18 bit is HI Charge Pump Output TRI STATE when its N20 bit becomes HI 0 1 Synchronous Powerdown Initiated 1 1 Asynchronous Powerdown Initiated 15 www national com Functional Description continued SERIAL DATA INPUT TIMING DATA N20 MSB C2 C1 LSB R8 R20 MSB C2 LSB CLOCK LE OR DS012806 10 Note 1 Parenthesis data indicates programmable reference divider data Data shifted into register on clock rising edge Data is shifted in MSB first Note 2 tp Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High towL Clock Pulse Width Low tes Clock to Load Enable Set Up Time tew Load Enable Pulse Width Test Conditions The Serial Data Input Timing is tested using a symmetrical waveform around 2 The test waveform has an edge rate of 0 6 V ns with amplitudes of 2 2V 9 Vcc 2 7V and 2 6V Vcc 5 5V PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS LET LE La Lea oT IT fe gt fp f fy f f fe lt fp f lt fp DS012806 11 Notes Phase difference detection range 2x to 27 The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked R16 HIGH www national com 16 Typical Application Example Les Vp 0 014 100p 100p From Controller fin IF fiy IF LE Data Clock
21. nous with the charge pump output This creates a nearly seamless change be tween Fastlock and standard mode MAIN DIVIDER PHASE DETECTOR REFERENCE CRYSTAL DIVIDER REFERENCE CHARGE PUMP RF out DS012806 18 FIGURE 5 Fastlock PLL Architecture www national com Physical Dimensions inches millimeters unless otherwise noted BEN DODODODODI ml LAND PATTERN RECOMMENDATION GAGE PLANE m NO SEATING PLANE MER 0 6 0 1 DETAIL A e 0 2 c 8 4 TYPICAL ALL LEAD TIPS fo DETAIL D 090 7 2 1 i ALL LEAD TIPS 1 1 MAX a e N a 0 10 0 05 TYP 0 09 0 20 0 TYP 0 13 A B C 20 Lead 0 173 Wide Thin Shrink Small Outline Package TM Order Number LMX2330LTM LMX2331LTM or LMX2332LTM For Tape and Reel 2500 units per reel Order Number LMX2330LTMX LMX2331LTMX or LMX2332LTMX NS Package Number MTC20 www national com 20 Physical Dimensions inches millimeters unless otherwise noted Continued 24X 0 45 7 i 2 5 7 P OO 24X X r3 Er 3 5 E r3 r3 20x 0 5 r3 DIMENSIONS ARE IN MILLIMETERS r3 r3 r3 Qo eme RECOMMENDED LAND PATTERN 1 1 RATIO WITH PACKAGE SOLDER PADS 110 1 24X 0 45 PIN 1 INDEX AREA 0 36 0 06 PIN 1 ID M AX 0 50 1 13 2X 21 1 te 24x 0 2540 0 05 2x 317 ip 2X SLB24A REV C 24 Pin Chip Scale Package Order Number LMX2330LSLB
22. o each other by diodes and must be run at the same voltage level Note Vp1 and Vp2 can be run separately as long as Vp Vcc www national com 4 Absolute Maximum Ratings Notes 1 2 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Power Supply Voltage 0 3V to 6 5V 0 3V to 6 5V Voc Vp Voltage on Any Pin Recommended Operating Conditions Power Supply Voltage Ve 2 7V to 5 5V Vp Voc to 5 5V Operating Temperature T4 40 C to 85 C Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Recommended Operating Conditions indicate condi tions for which the device is intended to be functional but do not guarantee specific performance limits For guaranteed specifications and test condi with GND OV Vj Storage Temperature Range Ts Lead Temperature solder 4 sec T 0 3V to 0 65 C to 150 C 260 C tions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Note 2 This device is a high performance RF integrated circuit with an ESD rating lt 2 keV and is ESD sensitive Handling and assembly of this device should only be done at ESD protected work stations Electrical Characteristics Voc 3 0V Vp 3 0V 40 C lt Ta lt 85 C except as specified Voc 2 7V to 5 5V
23. ract the w term present in the denominator of Equa tion 2 and Equation 3 The term was chosen to com plete the transformation because it can readily be switched Application Information continued between 1X and 4X values This is accomplished by increas ing the charge pump output current from 1 mA in the stan dard mode to 4 mA in Fastlock Gain 6 5 H s O dB Frequency Phase 4 G s H s 90 180 05012806 17 FIGURE 4 Open Loop Response Bode Plot FASTLOCK CIRCUIT IMPLEMENTATION A diagram of the Fastlock scheme as implemented in Na tional Semiconductors LMX233XL PLL is shown in Figure 5 When a new frequency is loaded and the RF lcp bit is set high the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error while an open drain NMOS on chip device switches in a second R2 resistor element to ground The user calculates the loop filter compo nent values for the normal steady state considerations The device configuration ensures that as long as a second iden tical damping resistor is wired in appropriately the loop will lock faster without any additional stability considerations to account for Once locked on the correct frequency the user can return the PLL to standard low noise operation by send ing a MICROWIRE instruction with the RF Icp bit set low This transition does not affect the charge on the loop filter capacitors and is enacted synchro
24. th wp the loop response time would be approximately halved Because the filter attenuation at the comparison fre quency also diminishes the spurs would have increased by approximately 6 dB In the proposed Fastlock scheme the higher spur levels and wider loop filter conditions would exist only during the initial lock on phase just long enough to reap the benefits of locking faster The objective would be to open up the loop bandwidth but not introduce any additional complications or compromises related to our original design criteria We would ideally like to momentarily shift the curve of Figure 4 over to a different cutoff frequency illustrated by the dotted line without affecting the relative open loop gain and phase relationships To maintain the same gain phase relationship at twice the original cutoff frequency other terms in the gain and phase Equation 4 and Equation 5 will have to compensate by the corresponding 1 w or 1 w factor Examination of equations Equations 2 3 and Equation 5 indicates the damping resistor variable R2 could be chosen to compensate the w terms for the phase margin This im plies that another resistor of equal value to R2 will need to be switched in parallel with R2 during the initial lock period We must also insure that the magnitude of the open loop gain H s G s is equal to zero at wp 2wp Ko N or the net product of these terms can be changed by a factor of 4 to counte

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