National LMX2314/LMX2315 handbook
Contents
1. C1 1000 pF R2 3 3 kQ C2 10 nF R3 22 kQ C3 100 pF Note 1 See related equation for Kd in Charge Pump Current Specification Definitions For this example Vp 5 0V The value of Kd can then be approximated using the curves in the Typical Peformance Char acteristics for Charge Pump Current vs Do Voltage The units for Kd are in mA You may also use K 5 mA 2r rad but in this case you must convert Kyco to rad V multiplying by 27 22k 1000 pF 3 3k 10 nF TEE FIGURE 4 20 kHz Loop Filter TL W 11766 20 16 Application Information continued MEASUREMENT RESULTS MKR 200 0 kHz REF 0 9dBm ATTEN 1 OdB 74 7 0dB 10 d8 SAMPLE MARKER 2 00 OkHz 74 7 0 dB VID AVG 1 00 CENTER 9 00 000MHz SPAN 5 00 kHz RES BW 1 OkHz VBW 3 OkHz SWP 30 0 msec TL W 11766 21 FIGURE 5 PLL Reference Spurs The reference spurious level is lt 74 dBc due to the loop filter attenuation and the low spurious noise level of the LMX2315 MKR 1 0 0 kHz REF 0 9 dBm ATTEN 1 OdB 50 6 0 dB 10 dB T T T MARKER 1 0 0 kHz SAMPLE 50 6 0 dB VID AVG 1 00 SPAN 1 00 kHz SWP 3 00 msec TL W 11766 23 FIGURE 6 PLL Phase Noise 10 kHz Offset The phase noise level at 10 kHz offset is 80 dBc Hz CENTER 9 00 000MHz RES BW 1kHz VBW 3 kHz MKR 1 00 kHz REF 0 7dBm ATTEN 1 OdB2. Divide ratio of swallow Divide ratio of programmable counter counter TL W 11766 7 Note S8 to S18 Programmable counter divide ratio control bits 3 to 2047 7 BIT SWALLOW COUNTER DIVIDE RATIO 11 BIT PROGRAMMABLE COUNTER DIVIDE RATIO A COUNTER B COUNTER els siss ss s mme sis SPSS SS S sss Pu 7 6 5 4 3 2 1 PN 18 17 16 15 14 13 12 11 10 9 8 o lolololololo o 3 lololo ololo olololala 1 olololo lolol 4 0 0 0 0 0 0 0 0 1 0 0 e e e e e e e e e e e e e 127 1 1 151 1 1 1 2047 11 1 111 1 5151 311 1 Note Divide ratio O to 127 Note Divide ratio 3 to 2047 Divide ratios less than 3 are prohibited BEA BEA PULSE SWALLOW FUNCTION fyco P x B A x fosc R fyco Output frequency of external voltage controlled oscil lator VCO B Preset divide ratio of binary 11 bit programmable counter 3 to 2047 A Preset divide ratio of binary 7 bit swallow counter 0 A x 127 A lt B fosc Output frequency of the external reference frequency oscillator R Preset divide ratio of binary 14 bit programmable ref erence counter 3 to 16383 P Preset modulus of dual modulus prescaler 64 or 128 10 Functional Description Continued SERIAL DATA INPUT TIMING DATA N18 MSB N17 N10 NO N1 CONTROL BIT LSB R15 MSB R14 R8 RD R6 R1 CONTROL AIT
3. 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Japan Ltd Tel 81 043 299 2309 Fax 81 043 299 2408 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd National Semiconductor National Semiconductor Corporation Europe 1111 West Bardin Road Fax 49 0 180 530 85 86 Arlington TX 76017 Email cnjwge tevm2 nsc com N Tel 1 800 272 9959 Deutsch Tel 49 0 180 530 85 85 Tsimshatsui Kowloon Fax 1 800 737 7018 English Tel 49 0 180 532 78 32 Hong Kong Fran ais Tel 49 0 180 532 93 58 Tel 852 2737 1600 Italiano Tel 49 0 180 534 16 80 Fax 852 2736 9960 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
4. 59 6 0dB 10 dB SAMPLE VID AVG 50 CENTER 9 00 000 OMHz RES BW 1 00Hz VBW 3 00Hz SPAN 1 0 O kHz SWP 3 00 sec TL W 11766 22 FIGURE 7 PLL Phase Noise 1 kHz Offset The phase noise level at 1 kHz offset is 79 5 dBc Hz 915 002500 MHz 915 000000 MHz 914 997500 MHz 500 us 2 000 ms 4 500 ms 500 0 us div T T 1724 4 us 2478 4s Q502 us TL W 11766 24 FIGURE 8 Frequency Jump Lock Time Of concern in any PLL loop filter design is the time it takes to lock in to a new frequency when switching channels Fig ure 8 shows the switching waveforms for a frequency jump of 865 MHz to 915 MHz By narrowing the frequency span of the HP53310A Modulation Domain Analyzer enables evaluation of the frequency lock time to within 500 Hz The lock time is seen to be less than 500 us for a frequency jump of 50 MHz 17 Application Information Continueo EXTERNAL CHARGE PUMP The LMX PLLatimum series of frequency synthesizers are equipped with an internal balanced charge pump as well as outputs for driving an external charge pump Although the superior performance of NSC s on board charge pump elim inates the need for an external charge pump in most appli cations certain system requirements are more stringent In these cases using an external charge pump allows the de signer to take direct control of such parameters as charge pump voltage sw
5. X 16 BISW Oo Analog switch output When LE is HIGH the analog switch is ON routing the internal charge pump output through BISW as well as through Do 18 17 fouT Oo Monitor pin of phase comparator input CMOS output 14 18 p Oo Output for external charge pump p is an open drain N channel transistor and requires a pull up resistor 15 19 PWDN I Power Down with internal pull up resistor PWDN HIGH for normal operation PWDN LOW for power saving Power down function is gated by the return of the charge pump to a TRI STATE condition 16 20 or Oo Output for external charge pump is a CMOS logic output X 2 9 12 NC No connect Functional Block Diagram 1 1 PROGRAMMABLE 14 BIT T x 2 CRYSTAL REFERENCE OSCILLATOR R 2 3 COUNTER 3 4 14 BIT LATCH 4 5 Vec 5 6 D 19 BIT SHIFT REGISTER TL 6 7 GND 7 8 LD x 9 NC BINARY 7 BIT BINARY 11 BIT SWALLOW PROGRAMMABLE 8 10 PRESCALER 4 8 fin 64 65 OR COUNTER COUNTER 128 129 SWALLOW CONTROL PHASE COMPARATOR E DIVIDER d OUTPUT fr fp MUX CHARGE PUMP LMX2314 Pin 1 p LMX2315 Pin 8 10 Pin Name 3 fi X signifies a function not bonded out to a pin ANALOG SWITCH 16 20 r 15 19 PWDN Note 1 u 14 18 13 17 Fout X 16 BISW 12 15 FC 11 14 LE 10 13 DATA x 12 NC 9 11 CLOCK TL W 11766 4 Note 1 The power down function is gated by the charge pum
6. 0 004 0 010 0010 0020 0254 0505 798 te 10302 0 254 8 MAX TYP Se s ALL LEADS E er Y C 3 Va EE L BZHELH Y sew f B I f I PLANE 0 008 0 010 ER 0 050 0 014 0 020 0 016 0 050 TYP 0 203 0 254 0061 270 0 338 1 270 7 0 356 0 508 TYP 0 008 TYP ALL LEADS 0 004 TYP ALL LEADS 0 102 ALL LEAD TIPS JEDEC 16 Lead 0 150 Wide Small Outline Molded Package M Order Number LMX2314M For Tape and Reel Order Number LMX2314MX 2500 Units per Reel NS Package Number M16A 0 203 z M16A REV H Synthesizer for RF Personal Communications LMX2314 LMX2315 PLLatinum 1 2 GHz Frequency Physical Dimensions nilimeters Continued i t ov DUBIO JR LAND PATTERN RECOMMENDATION GAGE PLANE i SEATING PLANE 0 6 0 1 DETAIL A 1 10 a 0 2 c 8 4 TYPICAL ALL LEAD TIPS ne DETAIL D ee Tea co E 90 4 KS Ste y NT P4 ae 0 10 0 05 TYP 0 19 0 30 TYP NS Package Number MTC20 20 Lead 0 173 Wide Thin Shrink Small Outline Package TM Order Number LMX2315TM For Tape and Reel Order Number LMX2315TMX 2500 Units per Reel 0 09 0 20 Ki MTC20 REV C LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein
7. 129 Serial data format is shown below Control bit LSB Divide ratio of prescaler control bit MSB s s 11 12 15 14 15 L Divide ratio of the programmable reference divider TL W 11766 6 14 BIT PROGRAMMABLE REFERENCE DIVIDER RATIO 1 BIT PRESCALER SELECT R COUNTER S LATCH ee s s s s sisisisisisisisls s Bh s m 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ea 15 3 olololololololololo ololila 428 129 0 4 olololololololololololilolo 64 65 1 e e e e e 16888 43 1 1 1 1 13 1 1 1 1 1 1 1 4 Notes Divide ratios less than 3 are prohibited Divide ratio 3 to 16383 S1 to S14 These bits select the divide ratio of the programmable reference divider C Control bit set to HIGH level to load R counter and S Latch Data is shifted in MSB first Functional Description continued PROGRAMMABLE DIVIDER N COUNTER The N counter consists of the 7 bit swallow counter A counter and the 11 bit programmable counter B counter If the Control Bit last bit shifted into the Data Register is LOW data is transferred from the 19 bit shift register into a 7 bit latch which sets the 7 bit Swallow A Counter and an 11 bit latch which sets the 11 bit programmable B Counter Serial data format is shown below 7 Control bit LSB MSB 7 s s s s 12 135 14 15 16 17 18
8. 5 5V fi 100 MHz to 1 600 MHz TL W 11766 40 TL W 11766 39 Marker 1 500 MHz Real 67 Imag 317 Marker 1 500 MHz Real 69 Imag 330 Marker 2 900 MHz Real 24 Imag 150 Marker 2 900 MHz Real 36 Imag 193 Marker 3 1 GHz Real 19 Imag 126 Marker 3 1 GHz Real 35 Imag 172 Marker 4 1 500 MHz Real 9 Imag 63 Marker 4 1 500 MHz Real 30 Imag 106 Charge Pump Current Specification Definitions T t VOLTAGE 2 OFFSET 5 AV O 0 AV Vp 2 Vp AV Vp Dg Voltage TL W 11766 41 11 CP sink current at Vp Vp AV 14 CP source current at Vp Vp AV 12 CP sink current at Vp Vp 2 I5 CP source current at Vp Vp 2 I3 CP sink current at Vp AV l6 CP source current at Vp AV AV Voltage offset from positive and negative rails Dependent on VCO tuning range relative to Vcc and ground Typical values are between 0 5V and 1 0V 1 Ip vs Vp Charge Pump Output Current magnitude variation vs Voltage m H lisim i 100 and t4 l4 helli tlia l6 100 2 IDo sink V9 Do source Charge Pump Output Current Sink vs Source Mismatch iie 151171 l2 15 100 3 Ip vs TA Charge Pump Output Current magnitude variation vs Temperature l2 temp l2 e 25 C l2 e 25 C 100 and I5 temp I5 e 25 C I5 e 25 C 100 4 Kb Phase detector
9. H s lt G s H s C1 R2 op 0 dB pum C2 90 TL W 11766 17 s C2 R2 1 Z s s2 C1 e C2 R2 sC1 sC2 180 FIGURE 2 2nd Order Passive Filter Frequency Define the time constants which determine the pole and zero frequencies of the filter transfer function by letting TL W 11766 19 FIGURE 3 Open Loop Transfer Function Thus we can calculate the 3rd order PLL Open Loop Gain in T2 R2 C2 1a terms of frequency and j Ko Kyco 1 jo T2 T1 G s H S ls j T T1 Roe C1 C2 9 H S s je v w2C1eN 1 joeT1 T2 2 C1 C2 1b From equation 2 we can see that the phase term will be The PLL linear model control circuit is shown along with the dependent on the single pole and zero such that open loop transfer function in Figure 3 Using the phase tan 1 w T2 tan p T1 180 3 detector and VCO gain constants Kd and Kyco and the Oe Ao Nee 3 loop filter transfer function Z s the open loop Bode plot By setting can be calculated The loop bandwidth is shown on the do T2 T1 0 Bode plot cp as the point of unity gain The phase margin do 14 w T2 2 1 weT1 2 4 is shown to be the difference between the phase at the unity gain point and 180 we find the frequency point corresponding to the phase in flection point in terms of the filter time constants T1 and T2 This relationship is given in equation 5 wp 1AT2 T1 5 For the loop to be stable the
10. Pump Output Current 40 C lt T lt 85 C Magnitude Variation vs Temperature VDo Vp 2 10 Note 3 VoH High Level Output Voltage lou 1 0 mA Voc 0 8 V VoL Low Level Output Voltage loy 1 0 mA 0 4 V VoH High Level Output Voltage OSCouT lou 200 pA Vcc 0 8 V VoL Low Level Output Voltage OSCoyT lo 200 pA 0 4 V loL Open Drain Output Current p Voc 5 0V VoL 0 4V 1 0 mA loH Open Drain Output Current p VoH 5 5V 100 pA Ron Analog Switch ON Resistance 2315 100 a tcs Data to Clock Set Up Time See Data Input Timing 50 ns tcu Data to Clock Hold Time See Data Input Timing 10 ns tcwH Clock Pulse Width High See Data Input Timing 50 ns tcwL Clock Pulse Width Low See Data Input Timing 50 ns tes Clock to Enable Set Up Time See Data Input Timing 50 ns tew Enable Pulse Width See Data Input Timing 50 ns Except OSCouT Notes 1 2 3 See related equations in Charge Pump Current Specification Definitions Typical Performance Characteristics lcc vs Vcc 8 T 259 T 85 C log m4 4 T 40 C 2 2 5 3 3 5 4 45 5 5 5 Veo Y TL W 11766 29 Charge Pump Current vs Do Voltage 7 5 CURRENT mA e 0 1 2 3 4 5 Dg VOLTAGE V TL W 11766 31 Charge Pump Current Variation 25 SINK SOURCE 20 VARIATION
11. charge pump gain constant y l2 lish RF Sensitivity Test Block Diagram 13 dB ATTN LMX2314 15 Evaluation Board RF 500 SMHU 835 8011 52 Signal Generator 10 MHz EXT REF OUT HP5385A Frequency Counter 2 7V 75 0V TL W 11766 42 Note 1 N 10 000 R 50 P 64 Note 2 Sensitivity limit is reached when the error of the divided RF output four is greater than or equal to 1 Hz Functional Description The simplified block diagram below shows the 19 bit data register the 14 bit R Counter and the S Latch and the 18 bit N Counter intermediate latches are not shown The data stream is clocked on the rising edge into the DATA input MSB first If the Control Bit last bit input is HIGH the DATA is transferred into the R Counter programmable reference divider and the S Latch prescaler select 64 65 or 128 129 If the Control Bit LSB is LOW the DATA is transferred into the N Counter programmable divider 14 BIT R COUNTER 19 BIT 1 BIT DATA REGISTER S LATCH DATA PRESCALER E fin 64 65 OR eel 128 129 N COUNTER OSCiy OSCour CHARGE PUMP TL W 11766 5 PROGRAMMABLE REFERENCE DIVIDER R COUNTER AND PRESCALER SELECT S LATCH If the Control Bit last bit shifted into the Data Register is HIGH data is transferred from the 19 bit shift register into a 14 bit latch which sets the 14 bit R Counter and the 1 bit S Latch S15 which sets the prescaler 64 65 or 128
12. determine the loop filter component values channel spacing in equations 15 17 we is slightly less than Op therefore the frequency jump lock time will increase dated cc T1 T3 15 5 tano T1 T3 IN _ T1 T9 T1 T3 1 9 T1 T92 T1 T3 tano T1 T3 16 ci 11 Kb Kvco 1 ac e T22 li T2 oc 2 N 1 ac T12 1 wc2 T32 17 15 Application Information continued Consider the following application example Example 1 Kyco 20 MHz V Kd 5 mA Note 1 RF opt 900 MHz Fret 200 kHz N PF opt fret 4500 wp 27 20 kHz 1 256e5 dbp 45 ATTEN 20 dB sechp tandp Op 10 20 20 1 T3 2 387e 6 27 200e3 2 3 29e 6 2 387e 6 T1 3 29e 6 c 1 3 29e 6 2 387e 6 2 3 29e 6 2 3876 6 N y 6296 6 2 38766 3296 6 2 3876 6 3 29e 6 2 387e 6 2 7 04564 i 3 549e 5 7 045e4 2 e 3 296 6 2 3876 6 o1 3299 9 5e 9 2066 1 7 045e4 2 e 3 549e 5 2 ig 3 5496 5 7 045e4 2e 4500 1 7 04564 3 296 6 2 1 7 04564 e 2 3876 6 2 1 085 nF 8 55e 5 C2 1 085 nF e 1 10 6 nF 8 296 6 3 55e 5 R2 229 _ 9 95 ka 10 6e 9 2 34e 6 if we choose R3 22k then C3 106 pF 22e3 Converting to standard component values gives the follow ing filter values which are shown in Figure 4
13. unity gain point must occur before the phase reaches 180 degrees We therefore want the phase margin to be at a maximum when the magni tude of the open loop gain equals 1 Equation 2 then gives K Kyco Tc jap ra op N T2 1 jop T1 TL W 11766 18 Open Loop Gain 0j 0 amp H s G s C1 Ko Z s Kyco Ns Closed Loop Gain 65 6 G s 1 H s G s 6 14 Application Information Continued Therefore if we specify the loop bandwidth Op and the phase margin p Equations 1 through 6 allow us to calcu late the two time constants T1 and T2 as shown in equa tions 7 and 8 A common rule of thumb is to begin your design with a 45 phase margin _ sechp tandp Op 7 1 ap T1 8 From the time constants T1 and T2 and the loop band width Op the values for C1 R2 and C2 are obtained in equations 9 to 11 Y 2 c1 _ I1 K Kvco 1 op T2 T1 T2 T2 eg2 N V1 wp T1 9 T2 C2 C1 1 T1 10 R2 12 C2 11 Kyco MHz V Voltage Controlled Oscillator VCO Tuning Voltage constant The fre quency vs voltage tuning ratio Ko mA Phase detector charge pump gain constant The ratio of the current out put to the input phase differential N Main divider ratio Equal to RF opt fret In choosing the loop filter components a trade off must be made between lock time noise stability and reference spurs The greater the loop bandwidth the
14. 0 0 25 0 5 0 75 1 1 25 1 5 1 75 2 2 25 2 5 VOLTAGE OFFSET V TL W 11766 33 CURRENT ma SENSITIVITY dBm IDo 7 Tg pA Ip TRI STATE vs D Voltage Dp VOLTAGE V TL W 11766 30 Charge Pump Current vs Do Voltage 4 3 2 Vp 3 3 1 Vp 2 7V Vp 5 0V 0 1 2 3 4 Ece Se a es o 0 5 1 5 2 2 5 3 3 5 Do VOLTAGE V TL W 11766 32 Oscillator Input Sensitivity 0 0 63 5 0 35 10 0 2 15 T 0 11 SENSITIVITY Vpp 1 5 10 15 20 25 30 35 40 45 50 FREQUENCY MHz TL W 11766 34 Typical Performance Characteristics continued Input Sensitivity vs Frequency Input Sensitivity vs Frequency Veo A Veg 3 3V 100 300 500 700 900 1100 1300 1500 100 300 500 700 900 1100 1300 1500 FREQUENCY MHz FREQUENCY MHz TL W 11766 35 TL W 11766 36 Input Sensitivity at Temperature Input Sensitivity at Temperature Variation Vcc 5V Variation Vcc 3V 100 300 500 700 900 1100 1300 1500 100 300 500 700 900 1100 1300 1500 FREQUENCY MHz FREQUENCY MHz TL W 11766 37 TL W 11766 38 LMX2314 Input Impedance vs Frequency LMX2315 Input Impedance vs Frequency Voc 2 7V to 5 5V fi 100 MHz to 1 600 MHz Voc 2 7V to
15. 14 i VCO is assumed AC coupled Ri increases impedance so that VCO output power is provided to the load rather than the PLL Typical values are 10 to 2009 depending on the VCO power level fin RF impedance ranges from 400 to 1002 500 termination is often used on test boards to allow use of external reference oscillator For most typical products a CMOS clock is used and no terminating resistor is required OSCiN may be AC or DC coupled AC coupling is recommended because the input circuit provides its own bias See Figure below 100k0 osc SCout TL W 11766 15 Proper use of grounds and bypass capacitors is essential to achieve a high level of performance Crosstalk between pins can be reduced by careful board layout This is a static sensitive device It should be handled only at static free work stations 13 Application Information LOOP FILTER DESIGN A block diagram of the basic phase locked loop is shown A N 1 CHARGE 1 1 PUMP 1 1 1 1 1 1 1 1 PHASE l DETECTOR I i i REFERENCE I O four CRYSIAL DIVIDER P REFERENCE 1 I i 1 I I I 1 i 1 I 1 i I n PS reference I Frequency frequency I 1 l Synthesizer 1 p t 4 fet I MAIN DIVIDER 1 1 l s 4 mcr EE EE TL W 11766 16 FIGURE 1 Basic Charge Pump Phase Locked Loop An example of a passive loop filter configuration including the transfer function of the loop filter is shown in Figure 2 Gain Phase le s
16. 50 wide 2314 or TSSOP 0 173 wide 2315 package Cellular telephone systems GSM IS 54 IS 95 RCR 27 Portable wireless communications DECT ISM902 928 CT 2 Other wireless communication systems Block Diagram OSCiy 14 BIT R COUNIER 19 BIT DATA REGISTER PRESCALER ls fin 64 65 OR ieee ll 128 129 N COUNTER OSCgur TRI STATE is a registered trademark of National Semiconductor Corporation MICROWIRE and PLLatinum are trademarks of National Semiconductor Corporation LU CHARGE D PUMP p Vp TL W 11766 1 91995 National Semiconductor Corporation TL W 11766 RRD B30M115 Printed in U S A suomneoiunuluo jeuosJed JH 40 Jeziseuju S ouenbaJ4 zH5 2 unnuneTad SLECXWT v LEZXWT Connection Diagrams LMX2314 LMX2315 O O oQ Aa Top View TOP VIEW 1 2 3 4 5 6 7 8 5 6 7 8 9 1 TL W 11766 2 JEDEC 16 Lead 0 150 Wide Small Outline Molded Package M Order Number LMX2314M or LMX2314MX 20 Lead 0 173 Wide Thin Shrink See NS Package Number M16A Small Outline Package TM Order Number LMX2315TM or LMX2315TMX See NS Package Number MTC20 TL W 11766 3 Pin Descriptions Pin No Pin No Pin Name on 1 0 Description 2314 2315 2314 2315 1 1 OSCin Oscillator input A CMOS inverting gate input intended for connection to a crystal resonator for operation as an oscill
17. LSB CLOCK j l j l j l j l tewL LE m e tes tes teH H town tew TL W 11766 8 Notes Parenthesis data indicates programmable reference divider data Data shifted into register on clock rising edge Data is shifted in MSB first Test Conditions The Serial Data Input Timing is tested using a symmetrical waveform around Vcc 2 The test waveform has an edge rate of 0 6 V ns with amplitudes of 2 2V 9 Vcc 2 7V and 2 6V Vcc 5 5V Phase Characteristics In normal operation the FC pin is used to reverse the polari VCO Characteristics ty of the phase detector Both the internal and any external charge pump are affected 1 Depending upon VCO characteristics FC pin should be set accordingly vco When VCO characteristics are like 1 FC should be set OUTPUT HIGH or OPEN CIRCUIT FREQUENGY When VCO characteristics are like 2 FC should be set LOW 2 When FC is set HIGH or OPEN CIRCUIT the monitor pin of VCO INPUT VOLTAGE the phase comparator input fout is set to the reference TL W 11766 9 divider output f When FC is set LOW fout is set to the programmable divider output fp PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS LD H I I f 2f f f f f f f lt 4 r r r r F i r n e TL W 11766 10 Notes Phase difference detection range 2a to 27 The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked FC HIGH 11 A
18. O LMX2314 0 O QN vationat Semiconductor LMX2314 LMX2315 PLLatinum 1 2 GHz Frequency Synthesizer for RF Personal Communications General Description The LMX2314 and the LMX2315 are high performance fre quency synthesizers with integrated prescalers designed for RF operation up to 1 2 GHz They are fabricated using Na tional s ABiC IV BiCMOS process The LMX2314 and the LMX2315 contain dual modulus pre scalers which can select either a 64 65 or a 128 129 divide ratio at input frequencies of up to 1 2 GHz Using a proprie tary digital phase locked loop technique the LMX2314 15 s linear phase detector characteristics can generate very sta ble low noise local oscillator signals Serial data is transferred into the LMX2314 and the LMX2315 via a three line MICROWIRE interface Data Enable Clock Supply voltage can range from 2 7V to 5 5V The LMX2314 and the LMX2315 feature very low current consumption typically 6 mA at 3V The LMX2314 is available in a JEDEC 16 pin surface mount plastic package The LMX2315 is available in a TSSOP 20 pin surface mount plastic package Features Applications March 1995 RF operation up to 1 2 GHz 2 7V to 5 5V operation Low current consumption Icc 6 mA typ at Voc 3V Dual modulus prescaler 64 65 or 128 129 Internal balanced low leakage charge pump Power down feature for sleep mode lcc 30 pA typ at Vcc 3V Small outline plastic surface mount JEDEC 0 1
19. ator The input has a Vcc 2 input threshold and can be driven from an external CMOS or TTL logic gate May also be used asa buffer for an externally provided reference oscillator 2 3 OSCour Oo Oscillator output Vp Power supply for charge pump Must be Vcc 5 Voc Power supply voltage input Input may range from 2 7V to 5 5V Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane 5 6 Do Oo Internal charge pump output For connection to a loop filter for driving the input of an external VCO 6 7 GND Ground 7 8 LD Oo Lock detect Output provided to indicate when the VCO frequency is in lock When the loop is locked the pin s output is HIGH with narrow low pulses 8 10 fiN I Prescaler input Small signal input from the VCO 9 11 CLOCK I High impedance CMOS Clock input Data is clocked in on the rising edge into the various counters and registers 10 13 DATA I Binary serial data input Data entered MSB first LSB is control bit High impedance CMOS input 11 14 LE I Load enable input with internal pull up resistor When LE transitions HIGH data stored in the shift registers is loaded into the appropriate latch control bit dependent Clock must be low when LE toggles high or low See Serial Data Input Timing Diagram 12 15 FC Phase control select with internal pull up resistor When FC is LOW the polarity of the phase comparator and charge pump combination is reversed
20. faster the lock time will be but a large loop bandwidth could result in higher reference spurs Wider loop bandwidths generally improve close in phase noise but may increase integrated phase noise depending on the reference input VCO and division ratios used The reference spurs can be reduced by reduc ing the loop bandwidth or by adding more low pass filter stages but the lock time will increase and stability will de crease as a result THIRD ORDER FILTER A low pass filter section may be needed for some applica tions that require additional rejection of the reference side bands or spurs This configuration is given in Figure 4 In order to compensate for the added low pass section the component values are recalculated using the new open loop unity gain frequency The degradation of phase margin caused by the added low pass is then mitigated by slightly increasing C1 and C2 while slightly decreasing R2 The added attenuation from the low pass filter is ATTEN 20 log 27rfre R3 e C3 2 1 12 Defining the additional time constant as T3 R3 C3 13 Then in terms of the attenuation of the reference spurs add ed by the low pass pole we have RF opt MHz Radio Frequency output of the VCO at dg Oa 14 which the loop filter is optimized 27 fref fref kHz Frequency of the phase detector in We then use the calculated value for loop bandwidth cg in puts Usually equivalent to the RF equation 11 to
21. ing current magnitude TRI STATE leak age and temperature compensation One possible architecture for an external charge pump cur rent source is shown in Figure 9 The signals pp and in the diagram correspond to the phase detector outputs of the LMX2314 2315 frequency synthesizers These logic signals are converted into current pulses using the circuitry shown in Figure 9 to enable either charging or discharging of the loop filter components to control the output frequency of the PLL Referring to Figure 9 the design goal is to generate a 5 mA current which is relatively constant to within 5V of the power supply rail To accomplish this it is important to establish as large of a voltage drop across R5 R8 as possible without saturating Q2 Q4 A voltage of approximately 300 mV pro vides a good compromise This allows the current source reference being generated to be relatively repeatable in the absence of good Q1 Q2 Q3 Q4 matching Matched tran sistor pairs is recommended The pp and 4r outputs are rated for a maximum output load current of 1 mA while 5 mA current sources are desired The voltages developed across R4 9 will consequently be approximately 258 mV or 42 mV RB 5 due to the current density differences 0 026 1n 5 mA 1 mA through the Q1 Q2 Q3 Q4 pairs In order to calculate the value of R7 it is necessary to first estimate the forward base to emitter voltage drop Vfn p of the transistors used the VoL d
22. nalog Switch 2315 only The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode The purpose of the analog switch is to decrease the loop filter time constant allowing the VCO to adjust to its new frequency in a shorter amount of time This is achieved by adding another filter stage in parallel The output of the charge pump is normally through the Do pin but when LE is set HIGH the charge pump output also becomes available at BISW A typical circuit is shown below The second filter stage LPF 2 is effective only when the switch is closed in the scanning mode CHARGE PUMP ANALOG SWITCH CONTROL SIGNAL LE TL W 11766 11 Typical Crystal Oscillator Circuit Typical Lock Detect Circuit A typical circuit which can be used to implement a crystal A lock detect circuit is needed in order to provide a steady oscillator is shown below LOW signal when the PLL is in the locked state A typical circuit is shown below OSGy OSCgyr H 4 tT C1 TL W 11766 12 LD MMBT200 TL W 11766 13 12 Typical Application Example External Charge Pump Circuit optional see text FROM CONTROLLER pwon four aisw Fc LE DATA NC CLOCK 16 20 15 19 14 18 13 17 X 16 12 15 11 14 10 13 X 12 9 11 LMX2314 2315 1000p 510 100p 0 15 0 12 100p LOCK DETECT CRYSTAL OSC C4 E CIRCUIT INPUT SEE TEXT Operational Notes TL W 11766
23. p to prevent any unwanted frequency jumps Once the power down pin is brought low the part will go into power down mode when the charge pump reaches a TRI STATE condition Absolute Maximum Ratings note 1 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Power Supply Voltage Voc 0 3V to 6 5V Vp 0 3V to 6 5V Voltage on Any Pin with GND OV Vj Storage Temperature Range Ts 0 3V to 6 5V 65 C to 150 C Recommended Operating Conditions Power Supply Voltage Voc 2 7V to 5 5V Vp Voc to 5 5V Operating Temperature TA 40 C to 85 C Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is intended to be functional but do not guarantee specific perform ance limits For guaranteed specifications and test conditions see the Elec trical Characteristics The guaranteed specifications apply only for the test Lead Temperature TL solder 4 sec 260 C conditions listed Electrical Characteristics voc sov Vp 5 0V 40 C lt T4 lt 85 C except as specified Symbol Parameter Conditions Min Typ Max Units loc Power Supply Current Voc 3 0V 6 0 8 0 mA Voc 5 0V 6 5 8 5 mA ICC PWDN Power Down Curren
24. rop of pp and the Voy drop of prs under 1 mA loads fp s VoL lt 0 1V and ors Vou lt 0 1V Knowing these parameters along with the desired current allow us to design a simple external charge pump Separat ing the pump up and pump down circuits facilitates the no dal analysis and give the following equations i Vas Vr in soues i Ry p max Ilsource Vas Vr m 25 Ro In max isink Vrs Bp 1 Rs ip max Bp 1 isource Re Vrs Bn 1 ir max Bn 1 isink Re Vp VvoLap Vns Vfp lp max Ry Vp VvoHer Vna Vfn Imax EXAMPLE Typical Device Parameters Bn 100 Bp 50 Typical System Parameters Vp 5 0V Vent 0 5V 4 5V Vop 0 0V Vor 5 0V lsiNK IsouRCE 5 0 mA Vin Vt 0 8V lrmax lpmax 1 mA Vag Vns 0 3V VoL p VoHor 100 mV Design Parameters Loo Filter TL W 11766 43 FIGURE 9 Therefore select Hus Po 0 3V 0 026 meo mA 1 0 mA 5160 Rs 0 3V e 50 1 3320 1 0 mA e 50 1 5 0 mA 0 3V e 100 1 Re 315 60 1 0 mA e 100 1 5 0 mA 5V 0 1V 0 3V 0 8V Re R7 NOTE 3 8 kQ Physical Dimensions inches millimeters 0 386 0 394 9 804 10 00 16 19 14 13 12 m 10 9 0 228 0 244 30 5 791 6 198 TYP LEAD NO 1 IDENT 0 010 Max 0 254 0 150 0 157 3 810 3 988 0 053 0 069
25. t Voc 3 0V 30 180 pA Voc 5 0V 60 350 uA fin Maximum Operating Frequency 1 2 GHz fosc Maximum Oscillator Frequency 20 MHz No Load on OSC Out 40 MHz fo Maximum Phase Detector Frequency 10 MHz Pfin Input Sensitivity Voc 2 7V to 3 3V 15 6 dBm Voc 3 3V to 5 5V 10 6 Vosc Oscillator Sensitivity OSCin 0 5 Vpp VIH High Level Input Voltage t 0 7 Voc V VIL Low Level Input Voltage 0 3 Voc V liH High Level Input Current Clock Data Vin Voc 5 5V 1 0 1 0 pA lit Low Level Input Current Clock Data Vit OV Vcc 5 5V 1 0 1 0 pA liH Oscillator Input Current Vin Voc 5 5V 100 pA lit Vit OV Voc 5 5V 100 pA lin High Level Input Current LE FC Vin Voc 5 5V 1 0 1 0 pA lit Low Level Input Current LE FC Vip OV Vcc 5 5V 100 1 0 pA Except fin and OSCiy Electrical Characteristics vcc sov Vp 5 0V 40 C lt Ta lt 85 C except as specified Continued Symbol Parameter Conditions Min Typ Max Units IDo source Charge Pump Output Current VDo Vp 2 5 0 mA IDo sink Vpg Vp 2 5 0 mA IDo Tri Charge Pump TRI STATE Current 0 5V lt VDo lt Vp 0 5V 25 25 nA T 85 C Ing vs VDo Charge Pump Output Current 0 5V lt VDo lt Vp 0 5V Magnitude Variation vs Voltage T 25 C 15 Note 1 IDo sink vs Charge Pump Output Current VDo Vp 2 IDo source Sink vs Source Mismatch T 25 C 10 Note 2 Ip vs T Charge
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National LMX2314/LMX2315 handbook