National LMX2310U/LMX2311U/LMX2312U/LMX2313U handbook
Contents
1. 2003 National Semiconductor Corporation 0 O LMX2310 0 National Semiconductor December 2003 LMX2310U LMX2311U LMX2312U LMX2313U PLLatinum Ultra Low Power Frequency Synthesizer for RF Personal Communications LMX2310U 2 5 GHz LMX2312U 1 2 GHz General Description The LMX2310 1 2 3U are high performance frequency syn thesizers The LMX2310 1 2U use a selectable dual modu lus 32 33 and 16 17 prescaler The LMX2313U uses a se lectable dual modulus 16 17 and 8 9 prescaler The device when combined with a high quality reference oscillator and a voltage controlled oscillator generates very stable low noise local oscillator signals for up and down conversion in wire less communication devices Serial data is transferred into LMX2310 1 2 3U via a three wire interface Data Enable Clock that can be directly interfaced with low voltage baseband processors Supply voltage can range from 2 7V to 5 5V LMX2310U features very low current consumption typically 2 3 mA at 3 0V The LMX2310 1 2 3U are manufactured using National s 0 5u ABiC V silicon BiCMOS process and is available in 20 pin CSP packages Functional Block Diagram Reference N Divider Microwire Interface LMX2311U 2 0 GHz LMX2313U 600 MHz Features RF operation up to 2 5 GHz 2 7V to 5 5V operation Ultra Low Current Consumption Low prescaler values LMX2310 1 2U 32 33 or 16 17 LMX2313U 16 17 or 8 9 Excellent Phase Noise Internal balanced2. Address Data Field Field T JojlololofolojJojroep2 TOM tt OO 3 4 1 FoLD2 FoLD Output P O Output Truth Table T 14 See Section 3 2 5 for FoLD Output Truth Table details 3 4 2 TO CNTR 11 0 Timeout Counter Table T 13 2 When the Fastlock Timeout counter TO_CNTR is loaded with O Fastlock is off the FL pin will be in TRI STATE mode and the charge pump current will be the value specified by the Charge Pump Magnitude bit R 18 When the Timeout counter is loaded with 1 the FL pin is O pulled low and the charge pump current will be at the 4X state When the Timeout counter is loaded with 2 the FL pin will again be set to O pulled low but the charge pump current will be controlled by R 18 When the Timeout counter is loaded with 3 the FL pin is 1 pulled high with the charge pump current will be controlled by R 18 When loaded with 4 through 4095 Fastlock is active and will time out after the specified number of phase detector events Count TO CNTR 11 0 Notes FL Pin Forced TRI STATE olololololololololololo Cp current controlled by R 18 FL Pin Forced Low olololololololololololi Cp 4 mA manual Fastlock mode FL Pin Forced Low olololololololololol1lo Cp current controlled by R 18 KI 0 FL Pin Forced High rofofofofo Min Count 2 rofofofofo ccc fol 1 1 Cp current controlled by R 18 ololo 0J0 0l0 o o Cp Current set to 4 mA switches to 1 mA ele ele when count reaches O ajajaja Max Count 4095 alala
3. driven from an external CMOS or TTL logic gate OSCIN NI no NoComest SSS OSCoyr Oscillator output The OSC low noise Vec ti buffer drives an independent oscillator sa buffer Its output is connected to the OSCour pin It can be used as a buffer to SSCs provide the reference oscillator frequency to other circuitry or as a crystal oscillator FoLD Multi function CMOS output pin that Vac y provides multiplexed access to digital lock a detect open drain analog lock detect as well as the outputs of the R and N FoLD counters The FoLD pin is internally referenced to V c 10 Clock High impedance CMOS Clock input Data Vat for the counters is clocked in on the rising Vuc edge into the 22 bit shift register The Clock is internally referenced to Vc Clock 3 www national com Co CO NELECXINT NCLECXIN TUN LLE XIN TI NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Pin Descriptions Continued Nc Noo High impedance CMOS Data input Serial Data is entered MSB first The last two bits are the address for the target registers The Data is internally referenced to Vuc High impedance CMOS LE input When Latch Enable goes HIGH data stored in the 22 bit shift register is loaded into one the 3 control registers based on the address field The Latch Enable is internally referenced to V High impedance CMOS Chip Enable input Provides logical power down control of the device Pull u
4. low leakage charge pump Selectable Charge Pump Current Levels Selectable Fastlock mode with Time Out Counter Low Voltage MICROWIRE interface 1 72V to Voc Digital and Analog Lock Detect Small 20 pad Thin Chip Scale Package Applications Cellular DCS PCS WCDMA telephone systems Wireless Local Area Networks WLAN Global Positioning Systems GPS Other wireless communications systems CPo FoLD Timeout ie Powerdown Control PLLatinum is a trademark of National Semiconductor Corporation DS200438 20043822 www national com SUONEJIUNWWO9 EUOSJ9d JH 10J y u4g Aouanba14 Jamod MOT LIUN LUNUNET ld NELEZXN NE LEZXN UN LLEZXIN NO LEZXINT J9Z1S9 LMX2310U LMX2311U LMX2312U LMX2313U Connection Diagram www national com N QI N NI KI KI NEN KI KI KI Le KE OSCouT FoLD Clock 20 Pin Thin Chip Scale Package NS Package Number SLD20A Data 20043823 Pin Descriptions CE 2 CP Charge Pump output For connection to a Vp loop filter for driving the voltage control input of an external VCO CEK ann ar around RF prescaler input Small signal input Vec from the VCO KR Oo Fin 5 RF prescaler complementary input For single ended operation this pin should be AC grounded The LMX2310 1 2 3U can be driven differentially when a bypass capacitor is omitted FINB 6 Oscillator input An input to a CMOS low Vec noise inverting buffer The input can be eo
5. of a high stability crystal reference oscillator a frequency synthe sizer such as the National Semiconductor LMX2310 1 2 3U a voltage controlled oscillator VCO and a passive loop filter The frequency synthesizer includes a phase detector a current mode charge pump as well as a programmable reference divider and feedback frequency divider The VCO frequency is established by dividing the crystal reference signal down via the reference divider to obtain a frequency that sets the comparison frequency This reference signal f is then presented to the input of a phase frequency detector and compared with another signal f which was obtained by Phase Detector Charge Pump I REFERENCE CRYSTAL DIVIDER REFERENCE i I P m wa q i Frequency 1 Synthesizer I A b m m m m mmm C N Main Divider 1 1 REFERENCE OSCILLATOR The reference oscillator frequency for the RF PLL is provided from the external source via the OSC pin The low noise reference buffer circuit supports frequencies from 2 MHz to 50 MHz with a minimum input sensitivity of 0 5 Vpp The input can be driven from an external CMOS or TTL logic gate The output of this buffer drives the R COUNTER The output of the buffer also connects to an oscillator buffer circuit Its output connects to the OSC pin The oscillator buffer cir cuit can be used as a buffer to provide the reference fre quency to other circuitry It can also be us
6. signal is routed to FoLD pin ma 21 R20 0 POEs Disabled TRISTATE FoLD 0 O o li Lock Detect Analog Push Pull Reference to V 0 o 1t 0 ee Lock Detect Analog Open Drain 0 Reset R and N Dividers and TRI STATE Charge Pump 1 O Go o Lock Detect Digital Push Pull Reference to Vuc 1 1 R COUNTER Output Push Pull Reference to Vic 1 Pt eo N Counter Output Push Pull Reference to Vic 1 Reserved Do Not Use 3 3 N REGISTER The N register contains the PWDN Power Down P Prescaler NA_CNTR and NB_CNTR control words The detailed descriptions and programming information for each control word is discussed in the following sections Register Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Address Data Field Field m Pp e CNT O aa o 3 3 1 PWDN Power Down N 21 The PWDN control bit along with CP TRI control bit is used to power down the PLL The LMX2310 1 2 3U can be synchronous or asynchronous powered down by first setting the CP TRI bit and then setting the PWDN bit To power up from the synchronous Power Down mode the CP TRI bit will have to be reset to 0 O Lo 0 Normal Operation OO T O j Power down Synchronous Power down Asynchronous 3 3 2 P Prescaler N 20 The LMX2310 1 2 3U contains two dual modulus prescalers The P control bit is used to set the pres
7. 0043848 www national com NELECXINT NCLECXIN TUN LLE XIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Typical Performance Characteristics Continued LMX2311U F Sensitivity vs Frequency at 5 5V INPUT POWER dBm I o l NI O 0 500 1000 1500 INPUT POWER dBm www national com 12 2000 2500 20043849 20043850 Typical Performance Characteristics Continued LMX2312U F Sensitivity vs Frequency at 5 5V INPUT POWER dBm INPUT POWER dBm 20043851 20043852 www national com NELECXINT NCLECXIN TUN LLECXIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Typical Performance Characteristics Continued INPUT POWER dBm INPUT VOLTAGE Vpp www national com LMX2313U F Sensitivity vs Frequency at 5 5V 20043853 10 000 1 000 0 100 0 010 20043854 Typical Performance Characteristics Continued INPUT VOLTAGE Vpp Zosc N 0 LMX231XU OSC Sensitivity vs Frequency at 5 5V 10 000 1 000 0 100 0 010 OSC MHz 20043855 LMX231xU OSC Input Impedance vs Frequency 40000 55000 30000 25000 20000 15000 10000 5000 a 5 5V OSC Normal Operation as nn IN o aaa 20043858 15 www national com NELECXINT NCLECXIN TUN LLE XIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Typical Performance Characteristics Continued LMX231xUSLD OSC IMPEDANCE Vee 3 0V Ta 25 C Voc 5
8. 3 0V 40 C lt Ta lt 85 C unless specified otherwise lec CC LMX2312U L ee _ Power Supply 7 5V Note 4 Clock Data and LE GND lcc PWDN Power Down Current CE GND RF PRESCALER waa o e g las Gr l ng wa os o an i EEE oe PHASE DETECTOR Fo Phase Detector Frequency o 0 Mez REFERENCE OSCILLATOR Operating Freguency F 2 MH baa Reference Oscillator Input a a Input Sensitivity V Not V ON Reference Oscillator Input e ii he OSCn Input Current Vin bilim 5 5V Pf 100 Voscoyt OSCoyr Bias Level OSCin Gren OSC 20 MHZ 0 5 Vp p D OSC Duty Cycle OSCin Duty Cycle 50 OSC 20 MHz 0 5 Vp p Voscaur OSCoyr Level OSCoyr Load 10 pF 10 k 2 6 Vp p Ohm 5 www national com NELECXINT NCLECXIN UN LLE XIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Electrical Characteristics Continued Voc Vp Nye 3 0V 40 C lt Ta lt 85 C unless specified otherwise Symbol CHARGE PUMP POS sinde ICPO sink ICP ss ICPO sink ICPo ICPO gink VS IOP O owe GPa Vp 1CPo ax z0 ose Charge Pump Output VCPo Vp 2 1CPo 4x z0 08 Current Note 7 VCPo Vp 2 ICPo 4X 1 Current CP Sink vs Source VCPo Vp 2 Mismatch Ta 250C Note 8 ICPo vs VCPo CP Current vs Voltage 0 5V lt VCPo lt Vp 0 5V ICPo vs Ta CP Current vs VCPo Vp 2V Note 7 Temperature DIGITAL INTERFACE Data Clock LE CE Vol Low
9. 5V Ta 25 C OSC BUFFER OSC BUFFER OSC BUFFER OSC BUFFER NORMAL OPERATION POWERED DOWN MODE NORMAL OPERATION POWERED DOWN MODE IZOSC N IZOSC N 9 IZOSC N 8 O O O z Q O O g Q O O 8 Q Ol O O O O a9 280 1300 1300 800 www national com 16 Typical Performance Characteristics Continued LMX231xU F Input Impedance vs Frequency Vcc 3 0V Ta 25 C Marker 1 100 MHz Marker 2 1 GHz Marker 3 2 GHz Marker 4 2 5 GHz 20043856 LMX231xU F Input Impedance vs Frequency Vec 5 5V Ta 25 C Marker 1 100 MHz Marker 2 1 GHz Marker 3 2 GHz Marker 4 2 5 GHz 20043857 17 www national com NELECXINT NCLECXIN TUN LLECXIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Typical Performance Characteristics Continued LMX231xUSLD F n IMPEDANCE Fw oe IN MHz o 100 200 305 300 400 500 600 120 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 www national com Vec 3 0V Ta 25 C POWERED UP B OI CT aja EOl OJ M OJO 1 AIA 2 R POWERED DOWN Imaginary ZFin IZF in 554 408 330 243 209 185 163 144 134 123 ek a a Sla 2 Ol Klklklalalklalalelilil amp e o 0J olololwlolola 18 Fin POWERED UP Real ZFin 9 KE 161 o 65 5 49 3 44 6 41
10. B CLOCK LE m tes ie tew LE 20043810 Notes 1 Data shifted into register on Clock rising edge 2 Data is shifted in MSB first Fin Sensitivity Test Setup POWER SUPPLY 00pF 10 01 pF CPU 0 01 uF Ju uWire GPIB RS 232 a 4 t t C LEVEL SHIFT BUFFER Ko MHz Ref h Hig HP 53132 Counter HP83620A SIG GEN XXXX 000000 MHz OUT 8 20043830 Notes 1 LMX2310 1 2U Test Conditions NA CNTR 16 NB CNTR 312 P 1 FoLD2 1 FoLD1 1 FoLDO O PWDN 0 2 LMX2313U Test Conditions NA_CNTR 0 NB_CNTR 625 P 1 FoLD2 1 FoLD1 1 FoLDO 0 PWDN 0 3 Sensitivity limit is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz www national com 20 OSC n Sensitivity Test Setup PD 20208 PWR CPU 4 Wire GPIB RS 232 100 pF gt gt 1000 pF LEVEL SHIFT BUFFER 50 0 a Ref XX 000 kHz sgh 2 3 TT PE HP 53132 Counter GE HP83620A SIG GEN m 3 dB ATTENUATOR FRONT LL XX 000000 MHz 20043831 Notes 1 Test Conditions R CNTR 1000 FoLD2 1 FoLD1 0 FoLDO 1 PWDN 0 2 Sensitivity limit is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz 21 www national com NELESXINT NZ LESXIN V NLLECXIN I NOLECXIN LMX2310U LMX2311U LMX2312U LMX2313U 1 0 Functional Description The basic phase lock loop PLL configuration consists
11. D output pin is referenced to the V supply The FoLDO FoLD1 and FoLD2 bits are used to select the desired output function A complete programming description of the FoLD output pin is in Section 3 2 5 1 8 1 Analog Lock Detect When programmed for analog lock detect the analog lock detect status is available on the FoLD output pin When the charge pump is inactive the lock detect output goes to a high impedance in the open drain configuration and to a V source in a push pull configuration It goes low when the charge pump is active during a comparison cycle The ana log lock detect status can be programmed in either an open drain or push pull configuration The push pull output is ref erenced to Vic 1 8 2 Digital Lock Detect When programmed for digital lock detect the digital lock detect status is available on the FoLD pin The digital lock detect filter compares the phase difference of the inputs from the phase detector to a RC generated delay of approxi mately 15 ns To enter the locked state LD High the phase error must be less than the 15 ns RC delay for 5 consecutive reference cycles Once in lock the RC delay is changed to approximately 30 ns To exit the locked state the phase error must be greater than the 30 ns RC delay When a PLL is in power down mode the respective lock detect output is always low A flow chart of the digital lock detect filter follows www national com NELECXINT NCLECXIN VN LLECXIN T
12. Lae 2 35 3 35 138 136 5 32 EEA 6 25 20 Vec 5 5V Ta 25 C Imaginary ZFin Q IZF in Q Fin POWERED DOWN Real ZF in 9 Imaginary ZFin Q 1 190 221 291 eo 221 az ea 131 118 112 102 IZF in Q 555 416 340 291 253 219 193 169 152 138 130 116 106 100 89 81 73 66 61 61 61 58 54 49 45 Charge Pump Measurement Definitions VOLTAGE OFFSET GP 11 CP sink current at VCP Vp AV l2 CP sink current at VCP Vp 2 13 CP sink current at VCP AV 14 CP source current at VCP Vp AV I5 CP source current at VCP Vp 2 l6 CP source current at VCP AV AV 0 5V Vp 2 Vp AV Vp Voltage 20043837 Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage gt 1 ma ICP Vs VCP ral 1 aN 11 I3 11 13 14 16 x 100 14 16 20043863 Charge Pump Output Current Sink Vs Charge Pump Output Current Source Mismatch ICP SINK Vs ICP SOURCE 12 15 ii aT 1007 1 12 151 20043864 Charge Pump Output Current Magnitude Variation Vs Temperature izl TA izl ICP Vs Ty 15 lt i TA 15 19 Taz 25 C x 100 TA 25 C Te 2596 20043865 www national com NELECXINT NCLECXIN TUN LLE XIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Serial Data Input Timing DATA MSB LS
13. MX2313U selecting a 8 9 prescaler provides a minimum continuous divider range from 56 to 65535 N P x NB_CNTR NA_CNTR Definitions Phase Detector Comparison Frequency Pp Presealer vave O 1 0 Functional Description continued 1 5 PHASE FREQUENCY DETECTORS The phase frequency detector is driven from the N and R COUNTER outputs The maximum frequency at the phase detector inputs is 10 MHz The phase detector outputs con trol the charge pump The polarity of the pump up or pump down control signals are programmed using the PD_POL control bit depending on whether the RF VCO tuning char acteristics are positive or negative see programming de scription in Section 3 2 2 The phase frequency detector has a detection range of 2z to 27 Phase Comparator and Internal Charge Pump Characteristics Note 13 Note 14 Note 15 Note 16 Note 17 The diagram assumes that PD_POL 1 fr is the phase comparator input from the R Divider fp is the phase comparator input from the N Divider CP is charge pump output 1 6 CHARGE PUMP The charge pumps directs charge into or out of an external loop filter The loop filter converts the charge into a stable control voltage which is applied to the tuning input of a VCO The charge pump steers the VCO control voltage towards Vp during pump up events and towards GND during pump down events When locked CP is primarily ina TRI STATE condition with small corrections occurring a
14. NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U 1 0 Functional Description continued No START Lock LOW Not Locked No Phase Error lt 15 ns Phase Error lt 15 ns Phase Error lt 15 ns Yes No Phase Errorx 15 ns Phase Error lt 15 ns Yes Lock HIGH Locked State Phase Error gt 30 ns 1 9 Fastlock OUTPUT The FL pin can be used as the Fastlock output The FL pin can also be programmed as constant low constant high referenced to Vcc or constant high impedance selectable through the T register When the device is configured in Fastlock mode the charge pump current can be increased 4x while maintaining loop stability by synchronously switch ing a parallel loop filter resistor to ground with the FL pin resulting in a 2x increase in loop bandwidth The loop bandwidth the zero gain crossover point of the open loop gain is effectively shifted up in frequency by a factor of the square root of 4 2 during Fastlock mode For w 2 o the phase margin during Fastlock also will remain constant The user calculates the loop filter component values for the normal steady state considerations The device configura tion ensures that as long as a second resistor equal to the primary resistor value is wired in appropriately the loop will lock faster without any additional stability considerations www national com 24 20043805 The PLL can be configured to b
15. ammed to support divide ratios from 2 to 32 767 Divide ratios of less than 2 are prohibited Divider Value R CNTR 14 0 3 2 2 PD POL Phase Detector Polarity R 17 The PD POL control bit is used to set the polarity of the phase detector based on the VCO tuning characteristic i 2 z Li Function Control Bit Register Location Description CO 7 PD POL R 17 Phase Detector Polarity Negative VCO Tuning Characteristic Positive VCO Tuning Characteristic VCO Characteristics PD_POL 1 VCO OUTPUT FREQUENCY PD_POL 0 VCO INPUT VOLTAGE 20043809 3 2 3 CPo_4X Charge Pump Output Current R 18 The CPo_4X control bit allows the charge pump output current magnitude to be switched from 1 mA to 4 mA This happens asynchronously or immediately with the change in CPo_4X bit R 18 Charge Pump Output Current Magnitude 3 2 4 CPo_TRI Charge Pump TRI STATE R 19 The CPo_TRI control bit allows the charge pump to be switched between a normal operating mode and a high impedance output state This happens asynchronously or immediately with the change in CPo_TRI bit Function Control Bit 4X Current aoo a Control Bit Register Location Description 7 CPo_TRI R 19 Charge Pump TRI STATE Sa ENP Pump Operates Normal Charge Pump Output in High Impedance State www national com 26 3 0 Programming Description Continued 3 2 5 FoLD2 1 0 FoLD Output Truth Table T 14 R 21 R 20 The FoLD2 FoLD1 and FoLDO are used to select which
16. bled The OSC CPo Fin Fing LD pins are all forced to a high impedance state The reference divider and feedback divider circuits are disabled and held at 3 0 Programming Description 3 1 MICROWIRE INTERFACE the load point during power down When the device is pro grammed to normal operation the oscillator buffer RF pres caler phase detector and charge pump circuits are all pow ered on The feedback divider and the reference divider are held at the load point This allows the RF prescaler feedback divider reference oscillator the reference divider and pres caler circuitry to reach proper bias levels After a 1 5 us delay the feedback and reference divider are enabled and they resume counting in close alignment The maximum error is one prescaler cycle The MICROWIRE control reg ister remains active and capable of loading and latching in data while in the power down mode The synchronous power down function is gated by the charge pump When the device is configured for synchro nous power down the device will enter the power down mode upon the completion of the next charge pump pulse event The asynchronous power down function is NOT gated by the completion of a charge pump pulse event When the device is configured for asynchronous power down the part will go into power down mode immediately NELECXINT NCLECXIN UN LLE XIN T NOLECXINT The MICROWIRE interface is comprised of a 22 bit shift register and three co
17. caler value Prescaler Value Prescaler Value PA eet cea aaa a 27 www national com NELESXINTUNTZLESXIN TUN LLESXIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U 3 0 Programming Description Continued 3 3 3 B CNTR 12 0 B COUNTER N 19 7 The NB CNTR control word is used to program the B counter The B counter is a 13 bit binary counter used in the programmable feedback divider The B counter can be programmed to values ranging from 3 to 8 191 See Section 1 4 for details on how the value of the B counter should be selected Divider Value B CNTR 12 0 8 191 1 1 1 1 1 1 1 1 1 NOTE B counter divide ratio must be gt 3 3 3 4 A CNTR 4 0 A Counter N 6 2 The NA CNTR control word is used to program the A counter The A counter is a 5 bit swallow counter used in the programmable feedback divider The A counter can be programmed to values ranging from O to 31 See Section 1 4 for details on how the value of the A counter should be selected HIVIGE A CNTR 4 0 NOTES A counter divide ratio must be lt P and A counter divide ratio must be lt B counter divide ratio 3 4 T REGISTER The T register contains the TO CNTR control word and FoLD2 control bit The detailed descriptions and programming information for each control word is discussed in the following sections Register Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 21 20 19 18 17 16 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 Jo
18. cification is the composite average of 3 measurements made at frequency offsets of 2 0 kHz 2 5 kHz and 3 0 kHz Typical Performance Characteristics lee VS Vee LMX2310U lee VS Vee LMX2311U lt lt UN a 5 8 m 20043838 20043839 3 00 2 50 z z 2 00 O O O O 1 50 1 00 2 5 20043840 20043841 ICP TRI pA CP VOLTAGE V 20043843 www national com 8 Typical Performance Characteristics Continued LMX231xU Charge Pump Sweeps Vp b CP _4X Bit 1 Ha o _4X Bit 0 i ps ON ba _4X Bits 1 AA AGA CP 4X Bits 1 CP Voltage V 20043842 9 www national com NELESXINTUNTLESXIN TUN LLE XIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Typical Performance Characteristics Continued Charge Pump Current Variation See formula under Sink Vs Source Mismatch See formula under Charge Charge Pump Current Specification Definitions Pump Current Specification Definitions Variation Mismatch Voltage Offset da CP Voltage V g o g 20043866 LMX2310U F Sensitivity vs Frequency at 3 0V aa m Ty 409C a INPUT POWER dBm ET LA 0 900 1000 1500 2000 2500 3000 5500 20043846 www national com 10 20043867 Typical Performance Characteristics Continued LMX2310U F Sensitivity vs Frequency at 5 5V INPUT POWER dBm I o l Bo O 30 20 l I N O INPUT POWER dBm 30 40 11 20043847 2
19. e in either the Fastlock mode continuously or in the Fastlock mode that uses a timeout counter to switch it back to the normal mode In the Fastlock mode the charge pump current is set to 4 mA and the FL pin is set low If the user sets the PLL to be in the Fastlock mode continuously he can send the R register with CPo_4X set low R 18 0 and sets TO CNTR 11 0 to 1 The user can set the PLL to normal mode 1 mA mode and set the FL pin to TRI STATE mode by programming TO CNTR 11 0 to O If the user elects to use the timeout counter he can program the timeout counter from 4 to 4095 The timeout counter will count down the programmed number of phase detector ref erence cycles After the programmed number of phase de tector reference cycles is reached it will automatically set the charge pump current to the 1 mA mode and set the FL pin to TRI STATE mode A complete programming descrip tion is in Section 3 4 2 2 0 Power Down The LMX2310 1 2 3U are power controlled through logical control of the CE pin in conjunction with programming of the PDWN and CPo_TRI bits A truth table is provided that describes how the state of the CE pin the PDWN bit and CPo_TRI bit set the operating mode of the device A com plete programming description of Power Down is provided in Section 3 3 1 KE X Don t Care When the device enters the power down mode the oscillator buffer RF prescaler phase detector and charge pump cir cuits are all disa
20. ed as an oscillator with a crystal resonator with proper components connected between OSC and OSC pins to generate a reference frequency 1 2 REFERENCE DIVIDER R COUNTER The reference divider is comprised of a 15 bit CMOS binary counter that supports a continuous integer divide range from 2 to 32 767 The divide ratio should be chosen such that the maximum phase comparison frequency of 10 MHz is not exceeded The reference divider circuit is clocked by the output of the reference buffer circuit The output of the reference divider circuit feeds the reference input of the phase detector circuit The frequency of the reference input to the phase detector also referred to as the comparison frequency is equal to reference oscillator frequency divided by the reference divider ratio Refer to Section 3 2 1 for details on programming the R COUNTER 1 3 PRESCALERS The LMX2310 1 2U contains a selectable dual modulus 32 33 and 16 17 prescaler The LMX2313U contains a se lectable dual modulus 16 17 and 8 9 prescaler PLL PLL Input Part Numbers Allowable Prescaler Values Frequency Fin gt 1 2 GHz LMX2310 1U 32 33 www national com 22 dividing the VCO frequency down by way of the feedback counter The phase frequency detector measures the phase error between the f and f signals and outputs control sig nals that are directly proportional to the phase error The charge pump then pumps charge into or out of the l
21. ievel Input Volage We 172Vi055V High level Output Voltage lo 500 pA Vuc 0 4 Pin 7 FoLD High level Output Voltage lo 500 pA V 04 Pin 15 FL Low level Output Voltage lo 1 0 mA Note 9 ma MICROWIRE TIMING Data Clock LE CE cs tou towH tow tes tew www national com Data to Clock Hold Time Note 10 Clock Pulse width High Note 10 Clock Pulse Width Low Note 10 Clock to Load Enable Set 50 Up Time Load Enable Pulse Width Note 10 Note 10 Typ Max ejs CT zy e EE Electrical Characteristics Continued Voc Vp Nye 3 0V 40 C lt Ta lt 85 C unless specified otherwise Symbol Parameter PHASE NOISE CHARACTERISTICS Normalized Single Side Band Phase Noise Single Side Band Phase Noise F 200 kHz Fosc 10 MHz Vosc 1 0 Vpp ICP 4 mA 159 dBc Hz Tas 250 Note 11 LMX2310U Fin 2450 MHz F 200 kHz e 78 dBo Hz Vosc 1 0 Vpp ICP 4 mA Tas25 Note 12 LMX2311U Fin 1960 MHz F 200 kHz Fosc 10 MHz Vosc 1 0 Vpp ICP 4 mA Ta 25 6 Note 12 LMX2312U Fin 902 MHz F 200 kHz Fosc 10 MHz Vosc 1 0 Vpp ICP 4 mA Tg 25G Note 12 LMX2313U Fin 450 MHz dBc Hz F 50 kHz Fosc 10 MHz Vosc 1 0 Vpp ICP 4 mA Ta 250 Note 12 dBc Hz Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indica
22. lalalalalalalalala www national com 28 Physical Dimensions inches millimeters unless otherwise noted 20X R mmm Lo OOO o O 20X ooJ O IS LI 16X 0 5 5 ij KN O il o DIMENSIONS ARE IN MILLIMETERS RECOMMENDED LAND PATTERN 1 1 RATIO WITH PACKAGE SOLDER PADS 20X 0 45 PAD 0 2 MAX PIN 1 INDEX AREA ro 0 52051 18 PIN 1 1D 20 Pin Thin Chip Scale Package Order Number LMX2310U LMX2311U LMX2312U or LMX2313U NS Package Number SLD20A For Tape and Reel 2500 Units Per Reel Order Numbers LMX2310USLDX LMX2311USLDX LMX2312USLDX LMX2313USLDX 20X 0 310 05 SLD20A Rev A m 2X LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reasonably expected to result in a significant injury to
23. ntrol registers The shift register consists of a 20 bit DATA field and a 2 bit address ADDR field as shown below Data is loaded into the shift register on the rising edges of the CLOCK signal MSB first When Latch Enable transitions HIGH data stored in the shift register is loaded into either the R N or T register depending on the state of the ADDR bit The DATA field assignments for the R N and T registers are shown in Section 3 1 1 MSB LSB DATA ADDRESS 21 2 0 3 1 1 Register Map Register Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 121 20 19 18 17 1615 14 15 12 11 10 9 8 7 6 5 4 3 2 1 o0 Address Data Field Field CPo CPO PD aoe eme ff N fewn e _ BCNTANZO aeneo fo 4 T 0 o o o o 0 o0 Folb2 TOR st 0 25 www national com LMX2310U LMX2311U LMX2312U LMX2313U 3 0 Programming Description Continued 3 2 R REGISTER The R register contains the R CNTR control word and PD POL CPo 4X CP TRI FoLDO FoLD1 control bits The detailed descriptions and programming information for each control word is discussed in the following sections Register Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Address Data Fiel Aerea Field FoLD1 FoLDO CP CPo PD R CNTR 14 0 TRI 4X POL 3 2 1 R CNTR 14 0 Reference Divider R COUNTER R 16 2 The reference divider can be progr
24. oop filter based on the magnitude and direction of the phase error The loop filter converts the charge into a stable control voltage for the VCO The phase frequency detector s func tion is to adjust the voltage presented to the VCO until the feedback signal s frequency and phase match that of the reference signal When this phase locked condition exists the RF VCO frequency will be N times that of the comparison frequency where N is the feedback divider ratio Q fout 20043829 PLL Part Numbers Allowable Prescaler Values Input Frequency Fin lt 1 2 GHz LMX2310 1 2U 16 17 or 32 33 Fin lt 600 LMX2313U 8 9 or MHz 16 17 The complimentary Fin and Fiyp input pins drive the input of a bipolar differential pair amplifier The output of the bipolar differential pair amplifier drives a chain of ECL D type flip flops in a dual modulus configuration The output of the prescaler is used to clock the subsequent programmable feedback divider Refer to Section 3 3 2 for details on pro gramming the Prescaler Value 1 4 FEEDBACK DIVIDER N COUNTER The N COUNTER is clocked by the output of the prescaler The N COUNTER is composed of a 13 bit programmable integer divider The 5 bit swallow counter is part of the prescaler Selecting a 32 33 prescaler provides a minimum continuous divider range from 992 to 262 143 while selecting a 16 17 prescaler value allows for continuous divider values from 240 to 131 071 In the L
25. p to V if unused The Chip Enable is internally referenced to Vuc Power supply for MICROWIRE circuitry Must be lt Vcc Typically connected to same supply level as microprocessor or baseband controller to enable programming at low voltages Power supply voltage input Input may range from 2 7V to 5 5V Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane Fastlock mode output In Fastlock mode this pin is at logic low When not in Fastlock mode this pin is in TRI STATE mode This pin can also be forced to TRI STATE forced low or forced high by the programming of the first two bits of the Timeout Counter 20 rm FH Power supply for charge pump Must be 3 Voc www national com 4 Absolute Maximum Ratings Notes 1 Lead Temp solder 4 sec T 260 C 2 If Military Aerospace specified devices are required Recommended Operating please contact the National Semiconductor Sales Office Conditions Note 1 Distributors for availability and specifications Power Supply Voltage Min Max Unit Vcc Vp Vic 0 3V to 6 5V Power Supply Voltage Voltage on any pin with GND 0V Voc 27 55 V CP FL Fin OSC OSCour Mi 0 3V to Vec 0 3V Vp Vee 5 5 V Data Clock LE CE FoLD V 0 3V to Vic 0 3V Vic 1 72 Veo V Storage Temperature Range Ts 65 C to 150 C Operating Temperature Ta 40 85 C Electrical Characteristics Voc Vp Vuc
26. t the phase com parison rate The charge pump output current magnitude can be selected as 1 0 mA or 4 0 mA by programming the ICPo 4X bits When TO_CNTR 11 0 1 the charge pump output current magnitude is set to 4 0 mA Refer to Section 3 2 3 and 3 4 2 for details on programming the charge pump output current magnitude 1 7 MICROWIRE SERIAL INTERFACE The programmable register set is accessed through the MICROWIRE serial interface The interface is comprised of three signal pins CLOCK DATA and LE Latch Enable The MICROWIRE circuitry is referenced to V c which allows the circuitry to operate down to a 1 72V source Serial data is clocked into a 22 bit shift register from DATA on the rising edge of CLOCK The serial data is clocked in MSB first The last two bits decode the internal register address On the rising edge of LE the data stored in the shift register is loaded into one of the three latches based on the address bits The synthesizer can be programmed even in the power down state A complete programming description is in Sec tion 3 0 1 8 MULTI FUNCTION OUTPUTS The LMX2310 1 2 3U FoLD output pin is a multi function output that can be configured as an analog lock detect a digital lock detect and a monitor of the output of the refer 23 20043804 The minimum width of the pump up and pump down current pulses occur at the CP pin when the loop is phase locked ence divider and the feedback divider circuits The FoL
27. te conditions for which the device is intended to be functional but do not guarantee specific performance limits For guaranteed specifications and conditions see the Electrical Characteristics The guaranteed specifications apply only for the conditions listed Note 2 This device is a high performance RF integrated circuit with an ESD rating lt 2 kV Handling and assembly of this device should only be done at ESD free workstations Note 3 Typical Conditions are at a Ta of 25 C Note 4 Icc current is measured with Clock Data and LE pins connected to GND OSCin and Fin pins are connected to Vcc PWDN bit is program to 0 Icc current is the current into Vcc pin Note 5 Note 6 Note 7 Note 8 Note 9 See F y Sensitivity Test Setup See OSC Sensitivity Test Setup Charge Pump Magnitude is controlled by CPo_4X bit R18 See Charge Pump Measurement Definition for detail on how these measurements are made Note 10 See Serial Input Data Timing Note 11 Normalized Single Side Band Phase Noise is defined as Ly f L f 20 log Fin Fo where L f is defined as the Single Side Band Phase Noise Analog Lock Detect open drain output pin only can be pulled up to Vex that will not exceed 6 5V 7 www national com NELECXINT NCLECXINV NLLECXIN T NOLECXINT LMX2310U LMX2311U LMX2312U LMX2313U Note 12 Phase Noise is measured using a reference evaluation board with a loop bandwidth of approximately 12 kHz The phase noise spe
28. the user BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification CSP 9 111C2 and the Banned Substances and Materials of Interest Specification CSP 9 111S2 and contain no Banned Substances as defined in CSP 9 111S2 National Semiconductor National Semiconductor National Semiconductor National Semiconductor Americas Customer Europe Customer Support Center Asia Pacific Customer Japan Customer Support Center Support Center Fax 49 0 180 530 85 86 Support Center Fax 81 3 5639 7507 Email new feedback nsc com Email europe support nsc com Email ap support nsc com Email jon feedback nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 Tel 81 3 5639 7560 English Tel 44 0 870 24 0 2171 www national com Fran ais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications SUONEJIUNWWO9 EUOSJ9d JH 10J y u4g Aouanba14 JaMmod MOT LIUN LUNUNET ld NE LEZXNT NZ LEZXN UN LLEZXIN NO LEZXINT J9Z1S9
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National LMX2310U/LMX2311U/LMX2312U/LMX2313U handbook